Semiconductor device and manufacturing method

Abstract

Provided is a semiconductor device in which doping concentration peaks in a buffer region each have an apex at which the doping concentration shows a maximum, a lower tail in which the doping concentration monotonously decreases from the apex toward a lower surface, and an upper tail in which the doping concentration monotonously decreases from the apex toward an upper surface. At least one of the doping concentration peaks in the buffer region is a gradual concentration peak of which a slope ratio calculated by dividing the absolute value of the slope of the upper tail by the absolute value of the slope of the lower tail is 0.1 to 3 inclusive.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

Background Art

[0002] Conventionally, in a semiconductor device such as an IGBT, a configuration in which a high-concentration buffer region is provided between a drift region and a collector region is known (see, for example, Patent Document 1). [Prior Art Document] [Patent Document] [Patent Document 1] WO2020-100995 Problems to be Solved

[0003] In a semiconductor device, it is preferable to reduce a turn-off surge. General Disclosure

[0004] In order to solve the above problems, in a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and a drift region of a first conductivity type provided therein. The semiconductor device may include a buffer region provided between the drift region and the lower surface in the semiconductor substrate, the buffer region including one or more doping concentration peaks of the first conductivity type having a higher doping concentration than the drift region. The doping concentration peak may have a vertex at which the doping concentration exhibits a maximum value, a lower skirt in which the doping concentration monotonically decreases from the vertex toward the lower surface, and an upper skirt in which the doping concentration monotonically decreases from the vertex toward the upper surface. At least one of the doping concentration peaks of the buffer region may be a slow concentration peak in which a slope ratio obtained by dividing the absolute value of the slope of the lower skirt by the absolute value of the slope of the upper skirt is 0.1 or more and 3 or less.

[0005] The buffer region may include two or more of the doping concentration peaks.

[0006] The buffer region may include two or more of the slow concentration peaks.

[0007] The buffer region may contain hydrogen.

[0008] The buffer region is provided between the two doping concentration peaks and may have a minimum portion where the doping concentration exhibits a minimum value. The distance in the depth direction of the semiconductor substrate between the apex of the gentle concentration peak and the minimum portion disposed on the upper surface side of the gentle concentration peak may be 3 μm or more and 5 μm or less.

[0009] At least one of the doping concentration peaks of the buffer region may be a steep concentration peak where the slope ratio obtained by dividing the absolute value of the slope of the lower skirt by the absolute value of the slope of the upper skirt is greater than 3.

[0010] At least one of the doping concentration peaks of the buffer region may be a steep concentration peak where the distance in the depth direction of the semiconductor substrate between the apex of the doping concentration peak and the minimum portion disposed on the upper surface side of the doping concentration peak is less than 3 μm.

[0011] Among the doping concentration peaks of the buffer region, the doping concentration peak having the maximum distance from the lower surface may be the steep concentration peak.

[0012] Among the doping concentration peaks of the buffer region, the doping concentration peak having the minimum distance from the lower surface may be the steep concentration peak.

[0013] At least one of the doping concentration peaks disposed on the upper surface side of the gentle concentration peak may be the steep concentration peak.

[0014] The doping concentration peak having the second smallest distance from the lower surface may be the gentle concentration peak.

[0015] Among the doping concentration peaks other than the doping concentration peak having the smallest distance from the lower surface, the doping concentration peak having the maximum doping concentration may be the gentle concentration peak.

[0016] The buffer region may have three or more of the doping concentration peaks. At least one of the doping concentration peaks other than the doping concentration peak having the smallest distance from the lower surface and the doping concentration peak having the largest distance from the lower surface may be the gentle concentration peak.

[0017] The buffer region may have two or more of the gentle concentration peaks arranged adjacent to each other in the depth direction of the semiconductor substrate.

[0018] Of the doping concentration peaks arranged on the upper surface side of the critical depth position where the integrated concentration obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface becomes the critical integrated concentration of the semiconductor substrate, the doping concentration peak having the maximum doping concentration may be the gentle concentration peak.

[0019] All of the doping concentration peaks arranged on the upper surface side of the critical depth position may be the gentle concentration peaks.

[0020] At least one of the doping concentration peaks having a maximum value of the doping concentration that is 10 times or more the bulk donor concentration of the semiconductor substrate may be the gentle concentration peak.

[0021] In a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, and a buffer region provided between the drift region and the lower surface in the semiconductor substrate and including one or more doping concentration peaks of the first conductivity type having a higher doping concentration than the drift region. In the manufacturing method, when forming the buffer region by implanting dopant ions of the first conductivity type at one or more depth positions from the lower surface of the semiconductor substrate, the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate may be set to ±3° or less for at least one of the depth positions.

[0022] When forming the buffer region, for at least one of the depth positions, the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate may be made greater than ±3°.

[0023] Note that the above summary of the invention does not list all of the necessary features of the present invention. Also, sub-combinations of these feature groups may also be inventions.

Brief Description of the Drawings

[0024]

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Mode for Carrying Out the Invention

[0025] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0026] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0027] In this specification, technical matters may be described using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without indicating positive or negative, it means the directions parallel to the +Z-axis and -Z-axis.

[0028] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Further, in this specification, a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction.

[0029] Also, a region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate may sometimes be referred to as the upper surface side. Similarly, a region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate may sometimes be referred to as the lower surface side.

[0030] When referred to as "identical" or "equal" in this specification, it may include cases having errors due to manufacturing variations or the like. Such errors are, for example, within 10%.

[0031] In this specification, the conductivity type of a doped region doped with impurities is described as P-type or N-type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be described as dopants. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor having an N-type conductivity type or a semiconductor having a P-type conductivity type.

[0032] In this specification, doping concentration means the concentration of donors or acceptors in thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charges. As an example, if the donor concentration is N D and the acceptor concentration is N A , then the net doping concentration at any position is N D -N A . In this specification, the net doping concentration may sometimes be simply described as the doping concentration.

[0033] The donor has a function of supplying electrons to the semiconductor. The acceptor has a function of receiving electrons from the semiconductor. The donor and acceptor are not limited to the impurities themselves. For example, a VOH defect formed by the combination of a hole (V), oxygen (O), and hydrogen (H) present in the semiconductor functions as a donor that supplies electrons. In this specification, the VOH defect may be referred to as a hydrogen donor.

[0034] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donor is a donor by a dopant that was contained substantially uniformly in the ingot during the production of the ingot from which the semiconductor substrate is derived. The bulk donor in this example is an element other than hydrogen. The dopant of the bulk donor is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donor is also included in the P-type region. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 . A higher oxygen concentration tends to more easily generate hydrogen donors. The bulk donor concentration may use the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain a dopant such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3The following applies. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or higher. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or lower. In addition, each concentration in the present invention may be a value at room temperature. As an example, the value at room temperature may be a value at 300 K (Kelvin) (about 26.9 °C).

[0035] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. Although the unit of length may be expressed in cm, various calculations may be performed after converting to meters (m).

[0036] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the electrically activated state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by the voltage-capacitance measurement method (CV method). Also, the carrier concentration measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method may be a value in the thermal equilibrium state. Also, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in the region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0037] In addition, when the concentration distribution of donors, acceptors, or net doping has a peak, the peak value may be used as the concentration of donors, acceptors, or net doping in the region. In cases where the concentration of donors, acceptors, or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors, or net doping in the region may be used as the concentration of donors, acceptors, or net doping. In this specification, for the concentration representation per unit volume, atoms / cm 3 , or, / cm 3 is used. This unit is used for the donor or acceptor concentration in the semiconductor substrate, or the chemical concentration. The atoms notation may be omitted.

[0038] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility is caused by the scattering of carriers due to the disorder of the crystal structure (disorder) such as lattice defects.

[0039] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donors or acceptors. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic that acts as a donor, or the acceptor concentration of boron (boron) that acts as an acceptor, is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen that acts as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0040] FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. In FIG. 1, the positions where each member is projected onto the upper surface of the semiconductor substrate 10 are shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.

[0041] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has a side edge 162 in a top view. When simply referred to as a top view in this specification, it means looking from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of side edges 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to any one of the side edges 162. Also, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0042] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160 but is omitted in FIG. 1. The active portion 160 may refer to a region overlapping with the emitter electrode in a top view. Also, a region sandwiched by the active portion 160 in a top view may also be included in the active portion 160.

[0043] A transistor portion 70 including transistor elements such as IGBTs (Insulated Gate Bipolar Transistors) is provided in the active portion 160. A diode portion 80 including diode elements such as freewheeling diodes (FWDs) may be further provided in the active portion 160. In the example of FIG. 1, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0044] In FIG. 1, the region where the transistor portion 70 is disposed is marked with the symbol "I", and the region where the diode portion 80 is disposed is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in the top view may be referred to as the extending direction (the Y-axis direction in FIG. 1). The transistor portion 70 and the diode portion 80 may each have a longitudinal direction in the extending direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.

[0045] The diode portion 80 has an N+-type cathode region in the region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the region that overlaps the cathode region in the top view. On the lower surface of the semiconductor substrate 10, a P+-type collector region may be provided in the region other than the cathode region. In this specification, the extended region 81 obtained by extending the diode portion 80 in the Y-axis direction up to the gate wiring described later may also be included in the diode portion 80. A collector region is provided on the lower surface of the extended region 81.

[0046] The transistor portion 70 has a P+-type collector region in the region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor portion 70, a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the upper surface side of the semiconductor substrate 10.

[0047] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 in this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed in the vicinity of the end side 162. The vicinity of the end side 162 refers to the region between the end side 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

[0048] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0049] The gate wiring in this example has an outer peripheral gate wiring 130 and an active side gate wiring 131. The outer peripheral gate wiring 130 is disposed between the active portion 160 and the end side 162 of the semiconductor substrate 10 in a top view. The outer peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the outer peripheral gate wiring 130 in a top view may be regarded as the active portion 160. Also, a well region is formed below the gate wiring. The well region is a P-type region having a higher concentration than the base region described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be regarded as the active portion 160.

[0050] The outer peripheral gate wiring 130 is connected to the gate pad 164. The outer peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0051] The active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, it is possible to reduce the variation in the wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0052] The outer peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer peripheral gate wiring 130 and the active-side gate wiring 131 are disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 and the active-side gate wiring 131 may be wirings formed of a semiconductor such as polysilicon doped with impurities.

[0053] The active-side gate wiring 131 may be connected to the outer peripheral gate wiring 130. The active-side gate wiring 131 in this example is provided to extend in the X-axis direction so as to cross the active portion 160 at substantially the center in the Y-axis direction from one outer peripheral gate wiring 130 sandwiching the active portion 160 to the other outer peripheral gate wiring 130. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction in each divided region.

[0054] Further, the semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) for simulating the operation of the transistor portions provided in the active portion 160.

[0055] The semiconductor device 100 in this example includes an edge termination structure portion 90 between the active portion 160 and the end side 162 in a top view. The edge termination structure portion 90 in this example is disposed between the outer peripheral gate wiring 130 and the end side 162. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and RESURF provided annularly surrounding the active portion 160.

[0056] Figure 2 is an enlarged view of region D in Figure 1. Region D is a region including the transistor portion 70, the diode portion 80, and the active side gate wiring 131. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0057] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is omitted in Figure 2. Contact holes 54 are provided through the interlayer insulating film of this example. In Figure 2, each contact hole 54 is hatched with oblique lines.

[0058] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

[0059] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0060] The emitter electrode 52 is formed of a material containing metal. In FIG. 2, the range where the emitter electrode 52 is provided is shown. For example, at least a part of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy like AlSi, AlSiCu, etc. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, etc. under the region formed of aluminum or the like. Further, in the contact hole, a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like may be provided.

[0061] The well region 11 is provided overlapping the active side gate wiring 131. The well region 11 is also provided extending with a predetermined width in a range not overlapping the active side gate wiring 131. The well region 11 of this example is provided away from the active side gate wiring 131 side from the Y-axis direction end of the contact hole 54. The well region 11 is a region of the second conductivity type with a higher doping concentration than the base region 14. The base region 14 of this example is P-type, and the well region 11 is P+-type.

[0062] Each of the transistor portion 70 and the diode portion 80 has a plurality of trench portions arranged in the array direction. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the array direction. In the diode portion 80 of this example, a plurality of dummy trench portions 30 are provided along the array direction. The diode portion 80 of this example is not provided with a gate trench portion 40.

[0063] The gate trench portion 40 of this example may have two straight portions 39 (portions of the trench that are linear along the extending direction) extending along the extending direction perpendicular to the array direction, and a tip portion 41 connecting the two straight portions 39. The extending direction in FIG. 2 is the Y-axis direction.

[0064] At least a part of the tip portion 41 is preferably provided in a curved shape in a top view. By connecting the ends of the two linear portions 39 in the Y-axis direction with the tip portion 41, the electric field concentration at the ends of the linear portions 39 can be alleviated.

[0065] In the transistor portion 70, the dummy trench portion 30 is provided between the respective linear portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the respective linear portions 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a linear shape extending in the extending direction, and may have a linear portion 29 and a tip portion 31 similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 2 includes both a linear dummy trench portion 30 without a tip portion 31 and a dummy trench portion 30 with a tip portion 31.

[0066] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a top view. That is, at the ends of each trench portion in the Y-axis direction, the bottom in the depth direction of each trench portion is covered by the well region 11. Thereby, the electric field concentration at the bottom of each trench portion can be alleviated.

[0067] A mesa portion is provided between the respective trench portions in the array direction. The mesa portion refers to a region sandwiched by the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion in this example is provided to extend in the extending direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10. In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. When simply referred to as a mesa portion in this specification, it refers to each of the mesa portion 60 and the mesa portion 61.

[0068] A base region 14 is provided in each mesa portion. Among the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active side gate wiring 131 is defined as the base region 14-e. In FIG. 2, the base region 14-e disposed at one end in the extending direction of each mesa portion is shown, but the base region 14-e is also disposed at the other end of each mesa portion. In each mesa portion, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided in a region sandwiched by the base regions 14-e in a top view. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0069] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. A contact region 15 exposed on the upper surface of the semiconductor substrate 10 may be provided in the mesa portion 60 in contact with the gate trench portion 40.

[0070] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the extending direction (Y-axis direction) of the trench portion.

[0071] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched by the emitter regions 12.

[0072] The mesa portion 61 of the diode section 80 is not provided with the emitter region 12. The base region 14 and the contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched by the base regions 14-e on the upper surface of the mesa portion 61, the contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched by the contact regions 15 on the upper surface of the mesa portion 61, the base region 14 may be provided. The base region 14 may be disposed over the entire region sandwiched by the contact regions 15.

[0073] Above each mesa portion, a contact hole 54 is provided. The contact hole 54 is disposed in the region sandwiched by the base regions 14-e. The contact hole 54 in this example is provided above each of the regions of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the regions corresponding to the base regions 14-e and the well region 11. The contact hole 54 may be disposed at the center in the arrangement direction (X-axis direction) of the mesa portions 60.

[0074] In the diode section 80, an N+-type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. On the lower surface of the semiconductor substrate 10, a P+-type collector region 22 may be provided in the region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0075] The cathode region 82 is arranged away from the well region 11 in the Y-axis direction. Thereby, a distance between the P-type region (well region 11) that has a relatively high doping concentration and is formed to a deep position and the cathode region 82 is ensured, and the breakdown voltage can be improved. An end portion of the cathode region 82 in the Y-axis direction in this example is arranged away from the well region 11 more than an end portion of the contact hole 54 in the Y-axis direction. In another example, the end portion of the cathode region 82 in the Y-axis direction may be arranged between the well region 11 and the contact hole 54.

[0076] FIG. 3 is a diagram showing an example of an e-e cross section in FIG. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 in this example has, in the cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0077] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as a silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The contact hole 54 described in FIG. 2 is provided in the interlayer insulating film 38.

[0078] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-type or N- type drift region 18. The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80.

[0080] In the mesa portion 60 of the transistor portion 70, an N+-type emitter region 12 and a P-type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+-type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0081] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0082] The base region 14 is provided below the emitter region 12. The base region 14 in this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0083] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+-type region having a higher doping concentration than the drift region 18. That is, the donor concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0084] In the mesa portion 61 of the diode portion 80, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0085] In each of the transistor section 70 and the diode section 80, an N+-type buffer region 20 may be provided under the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Also, the doping concentration of the drift region 18 may be the average value of the doping concentrations in a region where the doping concentration distribution is substantially flat.

[0086] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be provided at the same depth positions as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 in this example contains hydrogen as a hydrogen donor. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+-type collector region 22 and the N+-type cathode region 82.

[0087] In the transistor section 70, a P+-type collector region 22 is provided under the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0088] In the diode section 80, an N+-type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements serving as donors and acceptors in each region are not limited to the above-described examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0089] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion is provided from the upper surface 21 of the semiconductor substrate 10, through the base region 14, to below the base region 14. In a region where at least any one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doping regions. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed after the doping region is formed. Even in the case where the doping region is formed between the trench portions after the trench portions are formed, it is included in the case where the trench portion penetrates the doping region.

[0090] As described above, the transistor section 70 is provided with the gate trench portion 40 and the dummy trench portion 30. The diode section 80 is provided with the dummy trench portion 30 and is not provided with the gate trench portion 40. In this example, the boundary in the X-axis direction between the diode section 80 and the transistor section 70 is the boundary between the cathode region 82 and the collector region 22.

[0091] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0092] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0093] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0094] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a convex curved shape (curved shape in cross section) downward. In this specification, the depth position of the lower end of the gate trench portion 40 is denoted as Zt.

[0095] FIG. 4 is a diagram showing an example of the doping concentration distribution on the f-f line in FIG. 3. The f-f line is a line parallel to the Z axis passing through a part of the buffer region 20 and the drift region 18. The horizontal axis in FIG. 4 indicates the distance (μm) in the Z-axis direction from the lower end of the buffer region 20. The lower end of the buffer region 20 is, for example, the boundary position between the collector region 22 and the buffer region 20. Also, the distance in the Z-axis direction from the lower end of the buffer region 20 indicates the position in the Z-axis direction when the lower end of the buffer region 20 is set as the reference position 0. The vertical axis in FIG. 4 is a logarithmic axis showing the doping concentration per unit volume ( / cm 3 ).

[0096] The buffer region 20 has one or more doping concentration peaks 202. The buffer region 20 may include two or more doping concentration peaks 202. In the example of FIG. 4, the buffer region 20 has four doping concentration peaks 202. In this specification, the plurality of doping concentration peaks 202 are sequentially referred to as the first doping concentration peak 202-1, the second doping concentration peak 202-2, the third doping concentration peak 202-3, the fourth doping concentration peak 202-4, ··· from the one closest to the lower end of the buffer region 20 (or the one closest to the lower surface 23 of the semiconductor substrate 10). Also in this specification, among the plurality of doping concentration peaks 202, the one closest to the lower end of the buffer region 20 (or the one closest to the lower surface 23 of the semiconductor substrate 10) may be referred to as the shallowest concentration peak, and the one farthest from the lower end of the buffer region 20 (or the one farthest from the lower surface 23 of the semiconductor substrate 10) may be referred to as the deepest concentration peak. The plurality of doping concentration peaks 202 are arranged on the lower surface 23 side of the semiconductor substrate 10. Some of the doping concentration peaks 202 may be arranged on the upper surface 21 side of the semiconductor substrate 10.

[0097] Each doping concentration peak 202 has a vertex 203, a lower skirt 204, and an upper skirt 205. The vertex 203 is a point where the doping concentration shows a maximum value. The lower skirt 204 is a portion where the doping concentration monotonically decreases from the vertex 203 toward the lower surface 23. Monotonically decreasing means that there is no portion where the doping concentration increases. That is, in the lower skirt 204, as approaching the lower surface 23 from the vertex 203, the doping concentration decreases or is maintained. The upper skirt 205 is a portion where the doping concentration monotonically decreases from the vertex 203 toward the upper surface 21. In the above-described method for measuring the doping concentration, due to noise, measurement errors, etc., the values of adjacent measurement points may repeat minute decreases or increases. In such cases, it may be determined whether the measured values increase or decrease monotonically after averaging the measured values, such as using the average value over three or more measurement points or using the value fitted over three or more measurement points.

[0098] The lower skirt 204 and the upper skirt 205 have a doping concentration higher than the doping concentration D of the drift region 18. The doping concentration D of the drift region 18 d may be the average value of the doping concentration of the drift region 18, or may be the doping concentration of the drift region 18 at the center in the thickness direction of the semiconductor substrate 10. The doping concentration D of the drift region 18 d may coincide with the bulk donor concentration D of the semiconductor substrate 10, or may be higher than the bulk donor concentration D d and may be higher than the bulk donor concentration D b and may be higher than the bulk donor concentration D b as well.

[0099] The buffer region 20 in this example is provided between two doping concentration peaks 202 and has a minimum portion 210 where the doping concentration shows a minimum value. In the example of FIG. 4, a minimum portion 210 is provided between each doping concentration peak 202. The region from the vertex 203 to the minimum portion 210 may be the lower skirt 204 or the upper skirt 205. However, the boundary position on the upper surface 21 side of the upper skirt 205 of the deepest concentration peak (the fourth doping concentration peak 202-4 in this example) is the position where the doping concentration becomes the doping concentration D of the drift region 18 d Also, the boundary position on the lower surface 23 side of the lower skirt 204 of the shallowest concentration peak (the first doping concentration peak 202-1 in this example) may be the position of the PN junction with the collector region 22. In the case of the diode portion 80, the boundary position on the lower surface 23 side of the lower skirt 204 of the shallowest concentration peak (the first doping concentration peak 202-1 in this example) may be the position of the minimum portion between the cathode region 82 and the buffer region 20. In FIG. 4, the doping concentration distribution in the vicinity of the PN junction between the collector region 22 and the buffer region 20 is omitted.

[0100] At least one of the doping concentration peaks 202 in the buffer region 20 is a gentle concentration peak where the slope of the upper skirt 205 is relatively gentle. Specifically, for the gentle concentration peak, the slope ratio c = a / b obtained by dividing the absolute value b of the slope of the lower skirt 204 by the absolute value a of the slope of the upper skirt 205 is 0.1 or more and 3 or less. The method for calculating the slope of each skirt will be described later. In this specification, the "absolute value of the slope" may be simply referred to as the "slope". In the example of FIG. 4, the second doping concentration peak 202-2 where the distance from the lower surface 23 is the second smallest is the gentle concentration peak. The other doping concentration peaks 202 may or may not be gentle concentration peaks.

[0101] When the transistor section 70 is transitioned from the on state to the off state, a depletion layer (also referred to as a space charge region) spreads from the PN junction between the base region 14 and the drift region 18 (or the accumulation region 16) toward the lower surface 23 side. By providing the high-concentration buffer region 20, it is possible to prevent the depletion layer from reaching the collector region 22 and maintain the breakdown voltage of the semiconductor device 100.

[0102] On the other hand, when the depletion layer spreading from the upper surface 21 side reaches the upper skirt 205 with a steep concentration gradient, an additional turn-off surge is generated in the voltage waveform, and the voltage peak may increase or the voltage increase rate (dV / dt) may increase. In this example, by setting at least one of the doping concentration peaks 202 as a gentle concentration peak, an increase in the voltage peak in the turn-off surge can be suppressed. Further, by adjusting the gradient of the doping concentration peak 202, an increase in the voltage peak in the turn-off surge can be suppressed without changing the integrated value (dose amount) of the doping concentration in the buffer region 20.

[0103] FIG. 5 is a diagram showing an example of a method for calculating the slope b of the lower skirt 204 and the slope a of the upper skirt 205 of the doping concentration peak 202. In this example, the second doping concentration peak 202-2 will be described as an example, but the same applies to the other doping concentration peaks 202. The doping concentration at the apex 203 of the second doping concentration peak 202-2 is D H and the doping concentration at the first minimum portion 210-1 is DL1 Let the doping concentration of the second minimum portion 210-2 be D. L2 The first minimum portion 210-1 is disposed on the lower surface 23 side of the lower skirt 204 of the second doping concentration peak 202-2 and is connected to the lower skirt 204. The second minimum portion 210-2 is disposed on the upper surface 21 side of the upper skirt 205 of the second doping concentration peak 202-2 and is connected to the upper skirt 205.

[0104] Also, let the straight line approximating the lower skirt 204 be the lower straight line 221 and the straight line approximating the upper skirt 205 be the upper straight line 222. The slope of the lower straight line 221 may be the slope b of the lower skirt 204. The slope of the upper straight line 222 may be the slope a of the upper skirt 205.

[0105] As an example, the slope b of the lower skirt 204 and the slope a of the upper skirt 205 are given by the following equations. b = |log 10 (α H ×D H ) - log 10 (α L ×D L1 )| / (Z D2 - Z D1 ) a = |log 10 (α L ×D L2 ) - log 10 (α H ×D H )| / (Z U2 - Z U1 ) Note that α H and α L are coefficients between 0 and 1. Also, Z D2 is the depth position where the doping concentration is α H ×D H at the lower skirt 204, Z D1 is the depth position where the doping concentration is α L ×D L1 at the lower skirt 204, Z U2 is the depth position where the doping concentration is α L ×D L2 at the upper skirt 205, and Z U1is the depth position at which the doping concentration is α H ×D H in the upper hem 205. When there are a plurality of measurement points between Z D2 and Z D1 , or between Z U2 and Z U1 , the depth position may be set as x, the common logarithm of the doping concentration may be set as y, and the slope a or b may be obtained by fitting a linear function.

[0106] In the example of FIG. 5, α H is 0.7 , and α L is 0.3 . In this case, the slope b of the lower hem 204 is the point at which the doping concentration is 0.7 ×D H in the lower hem 204 (depth position Z D2 ), and the point at which the doping concentration is 0.3 ×D L1 in the lower hem 204 (depth position Z D1 ), and is given by the slope of the lower straight line 221 connecting the two points. The slope a of the upper hem 205 is the point at which the doping concentration is 0.7 ×D H in the upper hem 205 (depth position Z U1 ), and the point at which the doping concentration is 0.3 ×D L2 in the upper hem 205 (depth position Z U2 ), and is given by the slope of the upper straight line 222 connecting the two points. α H may be 0.8 or 0.9 . α L may be 0.4 or 0.5.

[0107] Note that the lower hem 204 of the first doping concentration peak 202-1 forms a PN junction with the collector region 22, and the PN junction portion corresponds to the minimum portion 210. In this case, it may be difficult to determine the doping concentration of the minimum portion 210. The lower straight line 221 approximating the lower hem 204 of the first doping concentration peak 202-1 has a doping concentration of α H ×DH and the point where it becomes, and β L ×D H It may be a straight line connecting the point where it becomes. β L is 0 or more and α H is a coefficient smaller than. β L is α H It may be 0.1 times that of, or may be 0.01 times that of.

[0108] As described above, at least one of the doping concentration peaks 202 in the buffer region 20 is a gentle concentration peak where the slope ratio c obtained by dividing the slope a of the lower skirt 204 by the slope b of the upper skirt 205 is 0.1 or more and 3 or less. The slope ratio c of the gentle concentration peak may be 2.8 or less, may be 2.5 or less, may be 2 or less, may be 1.5 or less, may be 1 or less, may be less than 1, or may be 0.8 or less. The smaller the slope ratio c, the gentler the concentration gradient of the upper skirt 205 becomes, and it becomes easier to reduce the turn-off noise. Also, the slope ratio c of the gentle concentration peak may be 0.2 or more, may be 0.4 or more, or may be 0.5 or more.

[0109] Also, at least one of the plurality of doping concentration peaks 202 in the buffer region 20 may be a steep concentration peak where the slope ratio c obtained by dividing the slope b of the lower skirt 204 by the slope a of the upper skirt 205 is greater than 3. In the example of FIG. 4, the doping concentration peaks 202 other than the second doping concentration peak 202-2 are steep concentration peaks. The slope ratio c of the steep concentration peak may be 4 or more, or may be 5 or more.

[0110] Since the steep concentration peak has a steep concentration gradient of the upper skirt 205, it is easy to control the depth position of the upper skirt 205. Also, since the variation in the degree of diffusion of the dopant is small, it becomes easy to control the doping concentration at the vertex 203.

[0111] As an example, among the doping concentration peaks 202 in the buffer region 20, the deepest concentration peak with the maximum distance from the bottom surface 23 (in the example of FIG. 4, the fourth doping concentration peak 202-4) may be a steep concentration peak. Thereby, the position and doping concentration of the doping concentration peak 202 first reached by the space charge region can be controlled with high precision, and it becomes easier to control the turn-off characteristics of the semiconductor device 100.

[0112] Also, among the doping concentration peaks 202 in the buffer region 20, the shallowest concentration peak with the minimum distance from the bottom surface 23 (in the example of FIG. 4, the first doping concentration peak 202-1) may be a steep concentration peak. The shallowest concentration peak may be the doping concentration peak 202 with the highest doping concentration among the plurality of doping concentration peaks 202. By accurately controlling the position and doping concentration of the shallowest concentration peak, the influence on the doping concentration distribution in the collector region 22 can be suppressed.

[0113] Also, there are four or more doping concentration peaks 202 in the buffer region 20, and among the doping concentration peaks 202 in the buffer region 20, the shallowest concentration peak with the minimum distance from the bottom surface 23 (in the example of FIG. 4, the first doping concentration peak 202-1) is a steep concentration peak, and the doping concentration peaks 202 other than the shallowest concentration peak may be gentle concentration peaks. The shallowest concentration peak may be the doping concentration peak 202 with the highest doping concentration among the plurality of doping concentration peaks 202. By setting the peaks other than the shallowest concentration peak as gentle concentration peaks, an increase in the voltage peak in the turn-off surge can be suppressed at the doping concentration peak 202 where the turn-off surge tends to be large.

[0114] Also, among the doping concentration peaks 202 other than the first doping concentration peak 202-1 with the smallest distance from the bottom surface 23, the doping concentration peak 202 with the highest doping concentration (in the example of FIG. 4, the second doping concentration peak 202-2) may be a gentle concentration peak. Thereby, the turn-off surge can be suppressed at the doping concentration peak 202 where the turn-off surge tends to be large.

[0115] Also, at least one of the doping concentration peaks 202 disposed closer to the upper surface 21 than the gentle concentration peak (in the example of FIG. 4, the second doping concentration peak 202-2) may be a steep concentration peak. In the example of FIG. 4, all the doping concentration peaks 202 disposed closer to the upper surface 21 than the gentle concentration peak are steep concentration peaks.

[0116] Also, when the buffer region 20 has three or more doping concentration peaks 202, at least one of the doping concentration peaks 202 other than the shallowest concentration peak (in the example of FIG. 4, the first doping concentration peak 202-1) and the deepest concentration peak (in the example of FIG. 4, the fourth doping concentration peak 202-4) may be a gentle concentration peak. As described above, by setting the shallowest concentration peak as a steep concentration peak, the influence on the doping concentration of the collector region 22 can be reduced, and by setting the deepest concentration peak as a steep concentration peak, the turn-off characteristics of the semiconductor device 100 can be accurately controlled. Also, by providing a gentle concentration peak, the turn-off surge can be suppressed. In the example of FIG. 4, the doping concentration peaks 202 other than the shallowest concentration peak and the deepest concentration peak include gentle concentration peaks and steep concentration peaks. In other examples, all the doping concentration peaks 202 other than the shallowest concentration peak and the deepest concentration peak may be gentle concentration peaks.

[0117] FIG. 6 is a diagram showing an example of a method for calculating the inclination a of the upper skirt 205 of the fourth doping concentration peak 202-4. The method for calculating the inclination b of the lower skirt 204 is the same as the example of FIG. 5. The fourth doping concentration peak 202-4 in this example is the deepest concentration peak closest to the drift region 18.

[0118] The upper skirt 205 of the fourth doping concentration peak 202-4 is connected to the drift region 18. For this reason, in the buffer region 20 on the upper surface 21 side of the upper skirt 205, there may be no minimum portion 210 where the doping concentration shows a minimum value. In this example, instead of the doping concentration of the minimum portion 210, the doping concentration D of the drift region 18 d is the concentration D L2Let it be so. Even in this case, the slope a of the upper straight line 222 is given by the following formula. a = |log 10 (α L × D L2 ) - log 10 (α H × D H )| / (Z U2 - Z U1 ) Other points are the same as the example described in FIG. 5.

[0119] FIG. 7 is an enlarged view of the doping concentration distribution in the vicinity of the second doping concentration peak 202-2 and the third doping concentration peak 202-3. In this example, the second doping concentration peak 202-2 is a gentle concentration peak, and the third doping concentration peak 202-3 is a steep concentration peak.

[0120] Between the second doping concentration peak 202-2 and the third doping concentration peak 202-3, a second minimum portion 210-2 where the doping concentration shows a minimum value is arranged. Also, a third minimum portion 210-3 is arranged on the upper surface 21 side of the third doping concentration peak 202-3. Let the depth position of the apex 203 of the second doping concentration peak 202-2 be Z P2 , the depth position of the second minimum portion 210-2 be Z V2 , the depth position of the apex 203 of the third doping concentration peak 202-3 be Z P3 , and the depth position of the third minimum portion 210-3 be Z V3 . Also, let the distance between the depth positions Z P2 and Z V2 be Z 2 , the distance between the depth positions Z P3 and Z V3 be Z 3 , and the distance between the depth positions Z P2 and Z P3 be Z 23 .

[0121] Since the second doping concentration peak 202-2 is a gentle concentration peak, the distance Z in the depth direction between the apex 203 of the second doping concentration peak 202-2 and the second minimum portion 210-22 becomes relatively large. Also, since the third doping concentration peak 202-3 is a sharp concentration peak, the distance Z in the depth direction between the apex 203 of the third doping concentration peak 202-3 and the third minimum portion 210-3 3 becomes relatively small.

[0122] Distance Z 2 is the distance Z 3 may be larger. The distance Z 2 is the distance Z 3 may be 1.5 times or more, or even 2 times or more of the distance Z. The distance Z in this example 2 is 3 μm or more and 5 μm or less. The distance Z 2 may be 3.5 μm or more, or even 4 μm or more. Regardless of the slope ratio c, the doping concentration peak where the apex 203 and the minimum portion 210 are separated by the distance Z 2 may be regarded as a gentle concentration peak. The distance Z in this example 3 is less than 3 μm. Regardless of the slope ratio c, the doping concentration peak where the apex 203 and the minimum portion 210 are separated by the distance Z 3 may be regarded as a sharp concentration peak. The distance Z 3 may be 2.5 μm or less, or even 2 μm or less.

[0123] Also, the second minimum portion 210-2 may be arranged near the center between the apex 203 of the second doping concentration peak 202-2 and the apex 203 of the third doping concentration peak 202-3. For example, the distance Z 2 is 0.7×Z 23 or more and 1.3×Z 23 or less. The distance Z 2 may be 0.8×Z 23 or more. The distance Z 2 may be 1.2×Z 23 or less.

[0124] FIG. 8 is a diagram for explaining an example of a manufacturing process for forming the doping concentration peak 202 in the buffer region 20. In this example, the doping concentration peak 202 is formed by implanting dopant ions such as protons, phosphorus, arsenic, or antimony into the implantation surface 109 of the semiconductor wafer 110. The semiconductor wafer 110 includes a plurality of semiconductor substrates 10. A plurality of semiconductor chips are formed by singulating and cutting out each semiconductor substrate 10 from the semiconductor wafer 110. Instead of the semiconductor wafer 110, dopant ions may be implanted into the singulated semiconductor substrate 10. The implantation surface 109 corresponds to the lower surface 23 of the semiconductor substrate 10.

[0125] In this example, let the incident angle of the dopant ions with respect to the implantation surface 109 of the semiconductor wafer 110 (that is, a plurality of semiconductor substrates 10) be θ. The incident angle θ is the angle formed by the irradiation direction of the dopant ions and the implantation surface 109. The dopant ions are implanted into the implantation surface 109 as an ion beam by an acceleration energy such as an acceleration voltage. The irradiation direction of the dopant ions may be the direction to which an acceleration energy such as an acceleration voltage is applied. The incident angle θ is also referred to as the tilt angle. Also, let the rotation angle of the implantation surface 109 with respect to the irradiation direction of the dopant ions be γ. The rotation angle γ is the angle by which the implantation surface 109 rotates along the circumferential direction. The rotation angle γ may be the rotation angle between a reference position such as the notch 108 and the position 106. The position 106 is the position where the projection line 107 obtained by projecting the ion beam irradiated to the center of the implantation surface 109 onto the implantation surface 109 intersects the end of the implantation surface 109. The rotation angle γ is also referred to as the twist angle.

[0126] FIG. 9 shows an example of the arrangement of silicon atoms 111 in the semiconductor wafer 110 as seen from the irradiation direction of the dopant ions when the incident angle θ is 0° and the rotation angle γ is 0°. As an example, the implantation surface 109 is a (100) plane.

[0127] Although there are a plurality of silicon atoms 111 along the depth direction (Z-axis direction), in this example, since it is viewed from the direction of θ = 0° and γ = 0°, the silicon atoms 111 arranged in the depth direction are completely overlapped. Therefore, the possibility that the dopant ions irradiated on the implantation surface 109 collide with the silicon atoms 111 becomes relatively small, and the dopant ions are more likely to reach a deeper position. For this reason, the slope of the upper skirt 205 of the doping concentration peak 202 becomes gentle, and a gentle concentration peak can be formed.

[0128] FIG. 10 shows an example of the arrangement of silicon atoms of the semiconductor wafer 110 viewed from the irradiation direction of dopant ions when the incident angle θ is 2° and the rotation angle γ is 0°. In this example, since θ is not 0°, the silicon atoms 111 arranged in the depth direction appear to be slightly shifted. Therefore, although the possibility that the dopant ions irradiated on the implantation surface 109 collide with the silicon atoms 111 becomes slightly higher, a gentle concentration peak can be formed.

[0129] FIG. 11 shows an example of the arrangement of silicon atoms of the semiconductor wafer 110 viewed from the irradiation direction of dopant ions when the incident angle θ is 4° and the rotation angle γ is 0°. In this example, since θ is even larger, the silicon atoms 111 arranged in the depth direction appear to be relatively largely shifted. Therefore, the possibility that the dopant ions irradiated on the implantation surface 109 collide with the silicon atoms 111 becomes high, and a gentle concentration peak cannot be formed. If the incident angle θ is ±3° or less, a gentle concentration peak could be formed. When forming a gentle concentration peak, the incident angle θ may be ±3° or less, may be ±2° or less, may be ±1° or less, or may be 0°.

[0130] On the other hand, when the incident angle θ is greater than ±3°, a sharp concentration peak was formed. When forming a sharp concentration peak, the incident angle θ may be greater than ±3°, may be ±4° or more, may be ±5° or more, may be ±6° or more, and may even be ±7° or more. Further, by adjusting the incident angle θ for each doping concentration peak 202, a buffer region 20 in which a gentle concentration peak and a sharp concentration peak are mixed can be formed. The second doping concentration peak 202-2 in FIG. 4 is formed by setting the incident angle θ to 3°. Doping concentration peaks 202 other than the second doping concentration peak 202-2 in FIG. 4 are formed by setting the incident angle θ to 7°.

[0131] FIG. 12 shows an example of the arrangement of silicon atoms of the semiconductor wafer 110 as viewed from the irradiation direction of dopant ions when the incident angle θ is 7° and the rotation angle γ is 23°. In this example, since θ is even larger, the silicon atoms 111 arranged in the depth direction appear to be even more displaced. For this reason, the dopant ions irradiated onto the implantation surface 109 are likely to collide with the silicon atoms 111, and a gentle concentration peak cannot be formed. Further, since the rotation angle γ is greater than 0°, the silicon atoms 111 arranged in the depth direction appear to be displaced obliquely. However, even when the rotation angle γ was changed, the inclination a of the upper skirt 205 of the doping concentration peak 202 did not change much. The rotation angle γ may be made different for the gentle concentration peak and the sharp concentration peak, or may be the same.

[0132] FIG. 13 is a diagram showing another example of the doping concentration distribution in the buffer region 20. The buffer region 20 in this example includes two or more gentle concentration peaks. Two doping concentration peaks 202 (the second doping concentration peak 202-2 and the third doping concentration peak 202-3 in the example of FIG. 13) arranged adjacent to each other in the depth direction may be gentle concentration peaks.

[0133] By using two adjacent doping concentration peaks 202 as gentle concentration peaks, the doping concentration at the minimum 210-2 between the concentration peaks becomes relatively high. Therefore, when the space charge region reaches the vicinity of these doping concentration peaks 202, it becomes easier to suppress the turn-off surge. The doping concentrations of two or more gentle concentration peaks may decrease as they move away from the lower surface 23.

[0134] FIG. 14 is a diagram showing another example of the doping concentration distribution in the buffer region 20. In the buffer region 20 of this example, the second doping concentration peak 202-2, the third doping concentration peak 202-3, and the fourth doping concentration peak 202-4 may be gentle concentration peaks. That is, doping concentration peaks other than the first doping concentration peak 202-1, which is a steep concentration peak, may be gentle concentration peaks. In this specification, the integrated value obtained by integrating the doping concentration from the upper end of the drift region 18 toward the lower surface 23 is referred to as the integrated concentration. The upper end of the drift region 18 may use the boundary with the accumulation region 16, or may use the boundary with the base region 14 when the accumulation region 16 does not exist. Also, the lower end position Z t of the gate trench portion 40 may be used as the upper end position of the drift region 18.

[0135] The semiconductor substrate 10 has a critical depth position Z r at which the integrated concentration reaches the critical integrated concentration. The critical integrated concentration nc is expressed, for example, by the following formula. nc = εs × Ec / q However, εs is the dielectric constant of the material forming the semiconductor substrate 10, q is the elementary charge amount, and Ec is the breakdown electric field strength of the semiconductor substrate 10. For example, when the semiconductor substrate 10 is a silicon substrate, Ec is 1.8×10 5 ~2.5×10 5 (V / cm), and nc is 1.2×10 12 ~1.6×10 12 ( / cm 2 ).

[0136] Also, when a forward bias is applied between the collector electrode 24 and the emitter electrode 52 and avalanche breakdown occurs when the maximum value of the electric field strength reaches the breakdown electric field strength of the semiconductor substrate 10, if the region up to a specific position in the drift region 18 is depleted (space-charge-region formed), the value obtained by integrating the donor concentration from the upper end of the drift region 18 to the specific position corresponds to the critical integral concentration. The space-charge region (depletion layer) may reach up to the critical depth position Z r at most.

[0137] The critical depth position Z r Of the doping concentration peaks 202 disposed closer to the upper surface 21 than the critical depth position Z, the doping concentration peak 202 having the maximum doping concentration at the apex 203 may be a gentle concentration peak. The critical depth position Z r Of the doping concentration peaks 202 disposed closer to the upper surface 21 than the critical depth position Z, two or more doping concentration peaks 202 may be gentle concentration peaks. As shown in FIG. 14, all of the doping concentration peaks 202 disposed closer to the upper surface 21 than the critical depth position Z r may be gentle concentration peaks. Even with such a configuration, the turn-off surge can be suppressed.

[0138] In the examples described with reference to FIGS. 1 to 14, the buffer region 20 may contain hydrogen. Of the doping concentration peaks 202 of the buffer region 20, at least one may be a concentration peak of a hydrogen donor formed by implanting hydrogen ions such as protons. The gentle concentration peak may be a concentration peak of a hydrogen donor. The steep concentration peak may be a concentration peak of a donor other than a hydrogen donor such as phosphorus, or may be a concentration peak of a hydrogen donor.

[0139] Also, of the doping concentration peaks 202 of the buffer region 20, at least one doping concentration peak 202 whose maximum value of the doping concentration (the doping concentration at the apex 203) is 10 times or more the bulk donor concentration D b of the semiconductor substrate 10 may be a gentle concentration peak. The doping concentration at the apex 203 of the gentle concentration peak is the bulk donor concentration D bIt may be 100 times or more.

[0140] FIG. 15 is a diagram for explaining a process of forming a buffer region 20 in a method of manufacturing a semiconductor device 100. Structures other than the buffer region 20 may be formed by known processes. The manufacturing method of this example has a slow concentration peak formation step S301 and a steep concentration peak formation step S302. Either the slow concentration peak formation step S301 or the steep concentration peak formation step S302 may be performed first.

[0141] In the slow concentration peak formation step S301, as described with reference to FIGS. 8 to 12, a slow concentration peak is formed by adjusting the incident angle θ of dopant ions. Also, in the steep concentration peak formation step S302, as described with reference to FIGS. 8 to 12, a steep concentration peak is formed by adjusting the incident angle θ of dopant ions.

[0142] Specifically, in the case of forming the buffer region 20 by implanting dopant ions of a first conductivity type at one or more depth positions from the lower surface 23 of the semiconductor substrate 10, for at least one depth position, the incident angle θ of the dopant ions with respect to the lower surface 23 of the semiconductor substrate 10 is set to ±3° or less. Thereby, a slow concentration peak can be formed at the depth position. Also, in the case of forming the buffer region 20, for at least one depth position, the incident angle θ of the dopant ions with respect to the lower surface 23 of the semiconductor substrate 10 is made larger than ±3°. Thereby, a steep concentration peak can be formed at the depth position. Note that the dopant is activated by heat-treating the semiconductor substrate 10 after implanting dopant ions at each depth position. Heat treatment may be performed in each of the slow concentration peak formation step S301 and the steep concentration peak formation step S302, or heat treatment may be performed collectively after performing both the slow concentration peak formation step S301 and the steep concentration peak formation step S302.

[0143] As described above, the present invention has been described using embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0144] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the specification, and the drawings is not explicitly stated as "earlier" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described for convenience using "first," "next," etc., it does not mean that it is essential to implement in this order.

Explanation of Reference Signs

[0145] 10 ··· semiconductor substrate, 11 ··· well region, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· storage region, 18 ··· drift region, 20 ··· buffer region, 21 ··· upper surface, 22 ··· collector region, 23 ··· lower surface, 24 ··· collector electrode, 29 ··· straight portion, 30 ··· dummy trench portion, 31 ··· tip portion, 32 ··· dummy insulating film, 34 ··· dummy conductive portion, 38 ··· interlayer insulating film, 39 ··· straight portion, 40 ··· gate trench portion, 41 ··· tip portion, 42 ··· gate insulating film, 44 ··· gate conductive portion, 52 ··· emitter electrode, 54 ··· contact hole, 60, 61 ··· mesa portion, 70 ··· transistor portion, 80 ··· diode portion, 81 ··· extension region, 82 ··· cathode region, 90 ··· edge termination structure portion, 100 ··· semiconductor device, 106 ··· position, 107 ··· projection line, 108 ··· notch, 109 ··· implantation surface, 110 ··· semiconductor wafer, 111 ··· silicon atom, 130 ··· outer peripheral gate wiring, 131 ··· active side gate wiring, 160 ··· active portion, 162 ··· end side, 164 ··· gate pad, 202 ··· doping concentration peak, 203 ··· vertex, 204 ··· lower skirt, 205 ··· upper skirt, 210 ··· minimum portion, 221 ··· lower straight line, 222 ··· upper straight line

Claims

1. A semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type; A buffer region provided between the drift region and the lower surface in the semiconductor substrate, and including three or more doping concentration peaks of the first conductivity type having a higher doping concentration than the drift region; Comprising; The doping concentration peak has a vertex where the doping concentration exhibits a maximum value, a lower skirt where the doping concentration monotonically decreases from the vertex toward the lower surface, and an upper skirt where the doping concentration monotonically decreases from the vertex toward the upper surface; At least one of the doping concentration peaks in the buffer region is a gentle concentration peak having a slope ratio obtained by dividing the absolute value of the slope of the upper skirt by the absolute value of the slope of the lower skirt of 0.1 or more and 3 or less, when a linear axis indicating the distance in the depth direction is used as the horizontal axis and a logarithmic axis indicating the doping concentration is used as the vertical axis; The doping concentration peak is; A first doping concentration peak having the minimum distance from the lower surface; A second doping concentration peak located on the upper surface side of the first doping concentration peak; A third doping concentration peak located on the upper surface side of the second doping concentration peak; Comprising; The buffer region has a minimum portion provided between two of the doping concentration peaks, where the doping concentration exhibits a minimum value; The second doping concentration peak is the gentle concentration peak; The absolute value of the slope of the upper skirt of the third doping concentration peak is larger than the absolute value of the slope of the upper skirt of the second doping concentration peak; The distance between the position of the second doping concentration peak and the position of the minimum portion closest to the second doping concentration peak among the minimum portions of the doping concentration provided on the upper surface side of the second doping concentration peak is defined as a first distance; The distance between the position of the third doping concentration peak and the position of the minimum portion closest to the third doping concentration peak among the minimum portions of the doping concentration provided on the upper surface side of the third doping concentration peak is defined as a second distance; The first distance is larger than the second distance; A semiconductor device.

2. The buffer region contains hydrogen; The semiconductor device according to claim 1.

3. The distance in the depth direction of the semiconductor substrate between the vertex of the gentle concentration peak and the minimum portion disposed on the upper surface side of the gentle concentration peak is 3 μm or more and 5 μm or less. The semiconductor device according to claim 1.

4. At least one of the doping concentration peaks in the buffer region is a steep concentration peak where the distance in the depth direction of the semiconductor substrate between the apex of the doping concentration peak and the minimum portion disposed on the upper surface side of the doping concentration peak is less than 3 μm. The semiconductor device according to claim 3.

5. The third doping concentration peak is a steep concentration peak having a slope ratio greater than 3. The semiconductor device according to claim 1.

6. Among the doping concentration peaks in the buffer region, the doping concentration peak having the maximum distance from the lower surface is the steep concentration peak. The semiconductor device according to claim 5.

7. Among the doping concentration peaks in the buffer region, the doping concentration peak having the minimum distance from the lower surface is the steep concentration peak. The semiconductor device according to claim 5.

8. The doping concentration peak having the second smallest distance from the lower surface is the gentle concentration peak. The semiconductor device according to any one of claims 1 to 7.

9. Among the doping concentration peaks other than the doping concentration peak having the smallest distance from the lower surface, the doping concentration peak having the maximum doping concentration is the gentle concentration peak. The semiconductor device according to any one of claims 1 to 7.

10. The depth position at which the integrated concentration obtained by integrating the doping concentration from the upper end of the drift region toward the lower surface becomes the critical integrated concentration of the semiconductor substrate is defined as the critical depth position. Among the doping concentration peaks disposed on the upper surface side of the critical depth position, the doping concentration peak having the maximum maximum value of the doping concentration of the doping concentration peak is defined as the maximum doping concentration peak. The maximum doping concentration peak is the gentle concentration peak. The semiconductor device according to any one of claims 1 to 7.

11. At least one of the doping concentration peaks among which the maximum value of the doping concentration is 10 times or more the bulk donor concentration of the semiconductor substrate is the gentle concentration peak. The semiconductor device according to any one of claims 1 to 6.

12. Among the doping concentration peaks in the buffer region, the first doping concentration peak is the steep concentration peak. The semiconductor device according to claim 6.

13. At least two of the doping concentration peaks in the buffer region are the steep concentration peaks, the gentle concentration peak is located between the steep concentration peaks in the depth direction of the semiconductor substrate, the gentle concentration peak and the steep concentration peaks are arranged adjacent to each other in the depth direction The semiconductor device according to claim 5.

14. Among the doping concentration peaks in the buffer region, the steep concentration peaks are included in the doping concentration peaks other than the first doping concentration peak and the doping concentration peak having the maximum distance from the upper surface. The semiconductor device according to claim 5.

15. At least one of the doping concentration peaks, in which the maximum value of the doping concentration is 10 times or more the bulk donor concentration of the semiconductor substrate, is the gentle concentration peak. The semiconductor device according to claim 7.

16. The slope ratio of the gentle concentration peak is 0.1 or more and less than 1. The semiconductor device according to claim 1.

17. The absolute value of the slope of the upper skirt is greater than the absolute value of the slope of the lower skirt. The semiconductor device according to claim 1.

18. A semiconductor device manufacturing method according to claim 1, comprising a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type, and a buffer region provided between the drift region and the lower surface in the semiconductor substrate and including three or more doping concentration peaks of the first conductivity type having a higher doping concentration than the drift region. When forming the buffer region by implanting dopant ions of the first conductivity type at three or more depth positions from the lower surface of the semiconductor substrate, a manufacturing method in which the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate is set to ±3° or less for at least one of the depth positions. When forming the buffer region, for at least one of the depth positions, the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate is made greater than ±3°.

19. After implanting the dopant ions of the first conductivity type with the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate made greater than ±3°, the dopant ions of the first conductivity type are implanted with the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate set to ±3° or less. The manufacturing method according to claim 18.

20. The manufacturing method according to claim 19. The manufacturing method according to claim 19.

21. The peak position of the dopant ions of the first conductivity type, which are implanted with the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate being made greater than ±3°, from the lower surface is deeper than the peak position of the dopant ions of the first conductivity type, which are implanted with the incident angle of the dopant ions with respect to the lower surface of the semiconductor substrate being made ±3° or less, from the lower surface The manufacturing method according to claim 19

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