Multilayer ceramic capacitor

Abstract

This multilayer ceramic capacitor includes a capacitor body 1 in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked, first via conductors 5 provided inside the capacitor body 1 and electrically connected to the plurality of first internal electrodes, second via conductors 6 provided inside the capacitor body 1 and electrically connected to the plurality of second internal electrodes, a first external electrode provided on the surface of the capacitor body 1 and electrically connected to the first via conductors 5, and a second external electrode provided on the surface of the capacitor body 1 and electrically connected to the second via conductors 6. When the capacitor body 1 is viewed in the stacking direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, with respect to a reference arrangement in which m × n (m and n are natural numbers of 3 or more) virtual lattice points are set and the via conductors including the first via conductors 5 and the second via conductors 6 are arranged at all virtual lattice points, the first via conductors 5 and the second via conductors 6 are not arranged at the number of virtual lattice points of 1 or more and (m - 2) × (n - 2) or less that are located on the inside with respect to the virtual lattice points located on the outermost periphery.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] There are known multilayer capacitors with reduced ESL (equivalent series inductance) by thickening the current flow path, shortening the current flow path, canceling out the magnetic fields generated by currents with different polarities, etc. Patent Document 1 discloses an example of a multilayer capacitor with reduced ESL.

[0003] The multilayer capacitor 200 disclosed in Patent Document 1 includes a capacitor body 210 in which a plurality of dielectric layers 201, a plurality of first internal electrodes 202, and a plurality of second internal electrodes 203 are laminated, as shown in FIGS. 10(a) and 10(b). The capacitor body 210 includes a plurality of first via conductors 204 that are electrically connected to the plurality of first internal electrodes 202 and extend to one main surface of the capacitor body 210, and a plurality of second via conductors 205 that are electrically connected to the plurality of second internal electrodes 203 and extend to one main surface of the capacitor body 210. On one main surface of the capacitor body 210, a plurality of first external electrodes 211 that are electrically connected to the plurality of first via conductors 204 respectively, and a plurality of second external electrodes 212 that are electrically connected to the plurality of second via conductors 205 respectively are formed. The plurality of first external electrodes 211 and the plurality of second external electrodes 212 are arranged in a grid pattern as shown in FIG. 10(a). Similarly, the plurality of first via conductors 204 and the plurality of second via conductors 205 are also arranged in a grid pattern.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a configuration in which a plurality of via conductors 204 and 205 are provided in a lattice pattern like the multilayer capacitor 200 disclosed in Patent Document 1, the effective area where the first internal electrode 202 and the second internal electrode 203 face each other is reduced, and the capacitance decreases.

[0006] The present invention solves the above problems, and an object thereof is to provide a multilayer ceramic capacitor capable of increasing the capacitance as compared with a conventional multilayer ceramic capacitor in which via conductors are arranged in a lattice pattern.

Means for Solving the Problems

[0007] The multilayer ceramic capacitor of the present invention includes a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated, a first via conductor provided inside the capacitor body and electrically connected to the plurality of first internal electrodes, a second via conductor provided inside the capacitor body and electrically connected to the plurality of second internal electrodes, a first external electrode provided on the surface of the capacitor body and electrically connected to the first via conductor, a second external electrode provided on the surface of the capacitor body and electrically connected to the second via conductor, and is characterized in that when the capacitor body is viewed in the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, m×n (m and n are natural numbers of 3 or more respectively) virtual lattice points are set, and the via conductors including the first via conductor and the second via conductor are not arranged at one or more virtual lattice points located inside the virtual lattice points located on the outermost periphery and less than or equal to (m - 2)×(n - 2) with respect to the reference arrangement in which they are arranged at all the virtual lattice points.

Advantages of the Invention

[0008] According to the multilayer ceramic capacitor of the present invention, among the m×n virtual lattice points, since the first via conductor and the second via conductor are not arranged at one or more virtual lattice points located inside the virtual lattice points located on the outermost periphery and less than or equal to (m - 2)×(n - 2), the capacitance can be increased as compared with the configuration in which via conductors are arranged at all of the m×n virtual lattice points.

Brief Description of the Drawings

[0009]

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Figure 10

Embodiments for Carrying Out the Invention

[0010] Embodiments of the present invention are shown below to specifically explain the features of the present invention.

[0011] FIG. 1 is a plan view schematically showing a multilayer ceramic capacitor 100 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing the structure when the multilayer ceramic capacitor 100 shown in FIG. 1 is cut along the II-II line. FIG. 3 is a cross-sectional view schematically showing the structure when the multilayer ceramic capacitor 100 shown in FIG. 1 is cut along the III-III line.

[0012] The multilayer ceramic capacitor 100 includes a capacitor body 1, a first via conductor 5, a second via conductor 6, a first external electrode 11, and a second external electrode 12.

[0013] The capacitor body 1 has a structure in which a plurality of dielectric layers 2, a plurality of first internal electrodes 3, and a plurality of second internal electrodes 4 are laminated. More specifically, the capacitor body 1 has a structure in which a plurality of first internal electrodes 3 and second internal electrodes 4 are alternately laminated via the dielectric layer 2.

[0014] The material of the dielectric layer 2 is arbitrary. For example, BaTiO 3 , CaTiO 3 , SrTiO 3 , SrZrO 3 , or CaZrO 3It is made of a ceramic material mainly composed of etc. Sub-components with a content less than that of the main components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. may be added to these main components.

[0015] The shape of the capacitor body 1 is arbitrary. In the present embodiment, the capacitor body 1 has a rectangular parallelepiped shape as a whole. The shape of a rectangular parallelepiped as a whole means, for example, a shape in which the corners and edges of the rectangular parallelepiped are rounded, or a shape in which there are irregularities on the surface of the rectangular parallelepiped. It is not a perfect rectangular parallelepiped shape, but it has six surfaces and can be regarded as a rectangular parallelepiped as a whole. Therefore, the capacitor body 1 includes a first main surface 1a, a second main surface 1b, a first side surface 1c, a second side surface 1d, a third side surface 1e, and a fourth side surface 1f.

[0016] The first main surface 1a and the second main surface 1b of the capacitor body 1 are surfaces that face each other in the stacking direction T of the dielectric layer 2, the first internal electrode 3, and the second internal electrode 4. In the present embodiment, the first main surface 1a and the second main surface 1b have a rectangular shape, more specifically, a square shape. However, the shapes of the first main surface 1a and the second main surface 1b are not limited to rectangles. The first side surface 1c to the fourth side surface 1f of the capacitor body 1 are the surfaces of the capacitor body 1 other than the first main surface 1a and the second main surface 1b. The first side surface 1c to the fourth side surface 1f of the capacitor body 1 are orthogonal to the first main surface 1a and the second main surface 1b, but they do not have to be orthogonal.

[0017] The dimensions of the capacitor body 1 are arbitrary, but for example, the longitudinal dimension in the plane view can be 0.3 mm or more and 3.0 mm or less, the transverse dimension can be 0.3 mm or more and 3.0 mm or less, and the dimension in the stacking direction T can be 50 μm or more and 200 μm or less. The dimension of the capacitor body 1 in the stacking direction T is the thickness of the capacitor body 1.

[0018] The materials of the first internal electrode 3 and the second internal electrode 4 are arbitrary. For example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals can be used. The first internal electrode 3 and the second internal electrode 4 may contain the same ceramic material as the dielectric ceramic contained in the dielectric layer 2 as a common material. In that case, the proportion of the common material contained in the first internal electrode 3 and the second internal electrode 4 is, for example, 20 vol% or less.

[0019] The thicknesses of the first internal electrode 3 and the second internal electrode 4 are arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode 3 and the second internal electrode 4 is arbitrary, but the two together can be, for example, about 10 layers or more and 150 layers or less.

[0020] As shown in FIG. 2, a plurality of first through-holes 3a are formed in the first internal electrode 3 to allow a plurality of second via conductors 6, which will be described later, to pass through. A plurality of second through-holes 4a are formed in the second internal electrode 4 to allow a plurality of first via conductors 5, which will be described later, to pass through.

[0021] In the multilayer ceramic capacitor 100, capacitance is formed by the first internal electrode 3 and the second internal electrode 4 facing each other with the dielectric layer 2 interposed therebetween.

[0022] The first via conductor 5 is provided inside the capacitor body 1 and is electrically connected to a plurality of first internal electrodes 3. More specifically, the first via conductor 5 is provided inside the capacitor body 1 in a manner extending in the stacking direction T from the first main surface 1a to the second main surface 1b of the capacitor body 1. The first via conductor 5 passes through the second through-hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4.

[0023] The second via conductor 6 is provided inside the capacitor body 1 and is electrically connected to a plurality of second internal electrodes 4. More specifically, the second via conductor 6 is provided inside the capacitor body 1 in a manner extending in the stacking direction T from the first main surface 1a to the second main surface 1b of the capacitor body 1. The second via conductor 6 passes through the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0024] As shown in FIG. 2, the first via conductor 5 and the second via conductor 6 are each exposed on the second main surface 1b of the capacitor body 1, but they do not have to be exposed.

[0025] The materials of the first via conductor 5 and the second via conductor 6 are arbitrary. For example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals can be used.

[0026] The shapes of the first via conductor 5 and the second via conductor 6 are arbitrary. For example, they can be cylindrical. In that case, the diameters of the first via conductor 5 and the second via conductor 6 are, for example, about 30 μm or more and 150 μm or less. Also, the distance between adjacent first via conductor 5 and second via conductor 6, more specifically, the distance L1 (see FIG. 2) between the center of the first via conductor 5 and the center of the second via conductor 6 is, for example, about 50 μm or more and 500 μm or less.

[0027] The first external electrode 11 is provided on the surface of the capacitor body 1 and is electrically connected to the first via conductor 5. In the present embodiment, the first external electrode 11 is provided only on one of the first main surface 1a and the second main surface 1b that face each other in the stacking direction T of the capacitor body 1. In FIG. 2, a configuration in which the first external electrode 11 is provided only on the first main surface 1a of the capacitor body 1 is shown. The number of the first external electrodes 11 is the same as the number of the first via conductors 5. As described above, since the first via conductor 5 is electrically connected to a plurality of first internal electrodes 3, the first external electrode 11 is electrically connected to a plurality of first internal electrodes 3.

[0028] The second external electrode 12 is provided on the surface of the capacitor body 1 and is electrically connected to the second via conductor 6. In the present embodiment, the second external electrode 12 is provided only on one of the first main surface 1a and the second main surface 1b of the capacitor body 1. In FIG. 2, a configuration in which the second external electrode 12 is provided only on the first main surface 1a of the capacitor body 1 is shown. The number of the second external electrodes 12 is the same as the number of the second via conductors 6. As described above, since the second via conductor 6 is electrically connected to a plurality of second internal electrodes 4, the second external electrode 12 is electrically connected to a plurality of second internal electrodes 4.

[0029] The materials of the first external electrode 11 and the second external electrode 12 are arbitrary. In the present embodiment, the first external electrode 11 and the second external electrode 12 are plating electrodes formed by plating. Examples of the material constituting the plating electrode include Cu, Ni, Sn, etc. The plating electrode may be composed of a single layer or a plurality of layers.

[0030] As shown in FIG. 1, in the present embodiment, the shapes of the first external electrode 11 and the second external electrode 12 when viewed in the stacking direction T are circular. However, the shapes of the first external electrode 11 and the second external electrode 12 when viewed in the stacking direction T are not limited to circular.

[0031] The present invention is characterized by the arrangement positions of the first via conductor 5 and the second via conductor 6. The arrangement positions of the first via conductor 5 and the second via conductor 6 of the multilayer ceramic capacitor 100 in the present embodiment will be described below.

[0032] As shown in FIG. 4, when the capacitor body 1 is viewed in the stacking direction T, m×n (m and n are natural numbers of 3 or more respectively) virtual lattice points T1 to Tx (x = m×n) are set, and a reference arrangement is a configuration in which via conductors 7 including the first via conductor 5 and the second via conductor 6 are arranged at all the virtual lattice points T1 to Tx. The m×n virtual lattice points are lattice points arranged in a lattice pattern of m rows and n columns. However, as is clear from the fact that they are called "virtual lattice points", lattice points are not provided on the capacitor body 1 in a visible form. In FIG. 4, m = 5 and n = 5, and an example in which 25 virtual lattice points T1 to T25 are set is shown. However, m and n are not limited to 5, and can each take any natural number of 3 or more.

[0033] In the multilayer ceramic capacitor 100 in the present embodiment, as shown in FIG. 5, with respect to the reference arrangement shown in FIG. 4, the first via conductor 5 and the second via conductor 6 are not arranged at one or more virtual lattice points located inside the virtual lattice points located on the outermost periphery and less than or equal to (m - 2)×(n - 2). In the example shown in FIG. 5, the first via conductor 5 and the second via conductor 6 are not arranged at all the virtual lattice points T7 to T9, T12 to T14, T17 to T19 located inside the virtual lattice points located on the outermost periphery of the reference arrangement shown in FIG. 4. That is, the via conductors including the first via conductor 5 and the second via conductor 6 are arranged only at the outermost virtual lattice points T1 to T6, T10, T11, T15, T16, T20 to 25. In the present embodiment, as shown in FIG. 5, in each of the lattice-like row direction and column direction, the first via conductor 5 and the second via conductor 6 are alternately arranged.

[0034] In this way, by adopting a configuration in which the first via conductor 5 and the second via conductor 6 are not arranged at some of the virtual lattice points T1 to Tx with respect to the reference arrangement (see FIG. 4) in which the via conductors 7 are arranged at all the virtual lattice points, the effective area where the first internal electrode 3 and the second internal electrode 4 face each other in the stacking direction T via the dielectric layer 2 increases, so that the capacitance increases.

[0035] In particular, as shown in FIG. 5, by adopting a configuration in which the first via conductor 5 and the second via conductor 6 are not arranged at all the virtual lattice points located inside the virtual lattice points located on the outermost periphery of the reference arrangement, the capacitance can be further increased.

[0036] Note that by adopting a configuration in which via conductors are not arranged at some of the virtual lattice points of the reference arrangement, the ESR (equivalent series resistance) and the ESL (equivalent series inductance) increase as compared with the stacked ceramic capacitor of the reference arrangement. However, due to the increase in the ESR, as shown in FIG. 6, when the stacked ceramic capacitor 100 in the present embodiment is connected in parallel to the power supply line with another stacked ceramic capacitor 110 having a different capacitance, the magnitude of the anti-resonance generated between the two stacked ceramic capacitors can be reduced. Note that FIG. 6 shows the equivalent circuits of the stacked ceramic capacitor 100 and the stacked ceramic capacitor 110 including a capacitance component (C), a resistance component (R), and an inductance component (L).

[0037] Here, among the virtual lattice points located inside the outermost periphery of the reference arrangement where the first via conductor 5 and the second via conductor 6 are not arranged, it is preferable that the virtual lattice points correspond to via conductors through which the current flowing when a voltage is applied between the first external electrode 11 and the second external electrode 12 in the reference arrangement is small. That is, when a voltage is applied between the first external electrode 11 and the second external electrode 12 in the reference arrangement, the magnitude of the current flowing through the first via conductor 5 and the second via conductor 6 differs depending on the positions of the virtual lattice points T1 to Tx. By adopting a configuration in which the first via conductor 5 and the second via conductor 6 are not arranged at the virtual lattice points corresponding to the via conductors through which the current flowing during voltage application is small, an increase in ESL can be suppressed.

[0038] That is, among the virtual lattice points located inside the outermost periphery of the reference arrangement, by adopting a configuration in which the first via conductor 5 and the second via conductor 6 are not arranged at the virtual lattice points corresponding to the via conductors through which the current flowing when a voltage is applied between the first external electrode 11 and the second external electrode 12 in the reference arrangement is small, it is possible to achieve both an increase in capacitance and suppression of an increase in ESL.

[0039] Here, when a voltage is applied between the first external electrode 11 and the second external electrode 12 in the reference arrangement shown in FIG. 4, if the current flowing through the via conductor 7 at the positions of the virtual lattice points T1 to T5 is large and the current flowing through the via conductor 7 at the positions of the virtual lattice points T21 to T25 is small, it may be considered to adopt a configuration in which the via conductor 7 is not arranged at the outermost virtual lattice points T21 to T25 through which the current flowing is small. However, when mounting such a multilayer ceramic capacitor on a substrate or the like, if the orientations of the virtual lattice point T1 to T5 side and the virtual lattice point T21 to T25 side are reversed during mounting, an increase in ESL cannot be suppressed, and conversely, the ESL will increase.

[0040] However, in the multilayer ceramic capacitor 100 according to the present embodiment, since the first via conductor 5 and the second via conductor 6 are not arranged at virtual lattice points located inside the virtual lattice points located on the outermost periphery with respect to the reference arrangement, it is less affected by the increase in ESL due to the orientation during mounting of the multilayer ceramic capacitor 100 as described above. For example, when a plurality of virtual lattice points where the first via conductor 5 and the second via conductor 6 are arranged are symmetrically arranged such as line symmetry or point symmetry, it is preferable because it is not affected by the increase in ESL due to the orientation during mounting of the multilayer ceramic capacitor 100. In particular, as shown in FIG. 5, when a plurality of virtual lattice points where the first via conductor 5 and the second via conductor 6 are arranged are point-symmetrically arranged, it is more preferable because it is not affected by the increase in ESL due to the orientation during mounting of the multilayer ceramic capacitor 100.

[0041] In the present embodiment, the difference between the number of the first via conductors 5 and the number of the second via conductors 6 is one or less. If the difference between the number of the first via conductors 5 and the number of the second via conductors 6 is large, the bias between the current distribution flowing through the first via conductor 5 and the current distribution flowing through the second via conductor 6 becomes large, and the ESL increases. However, by setting the difference between the number of the first via conductors 5 and the number of the second via conductors 6 to one or less, the above-described increase in ESL can be suppressed. In particular, in the case of a configuration where the difference between the number of the first via conductors 5 and the number of the second via conductors 6 is 0, the bias between the current distribution flowing through the first via conductor 5 and the current distribution flowing through the second via conductor 6 can be further suppressed, and the above-described increase in ESL can be further suppressed, which is preferable.

[0042] Figs. 7(a) and 7(b) are diagrams each showing another configuration example in which m = n (= 5), and the first via conductor 5 and the second via conductor 6 are not arranged at one or more and (m - 2)×(n - 2) or less virtual lattice points located inside the virtual lattice points located on the outermost periphery with respect to the reference arrangement. In the example shown in Fig. 7(a), the number of the first via conductors 5 and the number of the second via conductors 6 are the same. In the example shown in Fig. 7(b), the difference between the number of the first via conductors 5 and the number of the second via conductors 6 is one. As shown in Figs. 7(a) and 7(b), with respect to the reference arrangement, among the virtual lattice points located inside the virtual lattice points located on the outermost periphery, the first via conductor 5 and the second via conductor 6 may not be arranged at any virtual lattice point, but as described above, it is preferable to adopt a configuration in which the first via conductor 5 and the second via conductor 6 are not arranged at the virtual lattice points corresponding to the via conductors through which the current flowing during voltage application is small.

[0043] Figs. 8(a) and 8(b) are diagrams each showing a configuration example in which m ≠ n, and the first via conductor 5 and the second via conductor 6 are not arranged at one or more and (m - 2)×(n - 2) or less virtual lattice points located inside the virtual lattice points located on the outermost periphery with respect to the reference arrangement. In Fig. 8, an example in which m = 4 and n = 6 is shown, but as described above, m and n can take any natural numbers. As shown in Figs. 8(a) and 8(b), the first main surface 1a and the second main surface 1b opposite to the first main surface 1a each have a rectangular shape.

[0044] In the examples shown in Figs. 8(a) and 8(b), the number of the first via conductors 5 and the number of the second via conductors 6 are the same. Further, in the example shown in Fig. 8(b), since the plurality of virtual lattice points at which the first via conductor 5 and the second via conductor 6 are arranged are in a point-symmetrical arrangement, even when the orientation changes by 180° during the mounting of the multilayer ceramic capacitor 100, it is not affected by the increase in ESL.

[0045] FIG. 9 is a diagram showing the results of measuring the electrical characteristics of the multilayer ceramic capacitor 100 according to the present embodiment, the multilayer ceramic capacitor in the reference arrangement shown in FIG. 4 (hereinafter referred to as the multilayer ceramic capacitor of Comparative Example 1), and the multilayer ceramic capacitor in which the first via conductor 5 and the second via conductor 6 are not arranged at a part of the outermost virtual lattice points T1 to T6, T11, T16, and T21 with respect to the reference arrangement shown in FIG. 4 (hereinafter referred to as the multilayer ceramic capacitor of Comparative Example 2). Each multilayer ceramic capacitor includes a capacitance component, a resistance component, and an inductance component as shown in FIG. 6. FIG. 9(a) shows the capacitance, FIG. 9(b) shows the ESR, and FIG. 9(c) shows the ESL.

[0046] As shown in FIG. 9(a), the multilayer ceramic capacitor 100 according to the present embodiment has an increased capacitance as compared with the multilayer ceramic capacitor of Comparative Example 1. On the other hand, as shown in FIGS. 9(b) and 9(c), the ESR of the multilayer ceramic capacitor 100 according to the present embodiment is higher than the ESR of the multilayer ceramic capacitor of Comparative Example 1 but lower than the ESR of the multilayer ceramic capacitor of Comparative Example 2. Also, the ESL of the multilayer ceramic capacitor 100 according to the present embodiment is higher than the ESL of the multilayer ceramic capacitor of Comparative Example 1 but lower than the ESL of the multilayer ceramic capacitor of Comparative Example 2.

[0047] That is, the multilayer ceramic capacitor 100 according to the present embodiment has a larger capacitance than the multilayer ceramic capacitor of Comparative Example 1 in which via conductors are arranged at all virtual lattice points, and has a lower ESR and ESL than the multilayer ceramic capacitor of Comparative Example 2 in which via conductors are not arranged at a part of the outermost virtual lattice points with respect to the standard arrangement.

[0048] The present invention is not limited to the above-described embodiments, and various applications and modifications can be made within the scope of the present invention. For example, although the first external electrode 11 and the second external electrode 12 have been described as being provided only on one of the first main surface 1a and the second main surface 1b that face each other in the stacking direction T on the surface of the capacitor body 1, they may be provided on both the first main surface 1a and the second main surface 1b.

Explanation of Reference Numerals

[0049] 1 Capacitor body 2 Dielectric layer 3 First internal electrode 4 Second internal electrode 5 First via conductor 6 Second via conductor 7 Via conductor 11 First external electrode 12 Second external electrode 100 Multilayer ceramic capacitor T1~T25 Virtual lattice points

Claims

1. A capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; A first via conductor provided inside the capacitor body and electrically connected to the plurality of first internal electrodes; A second via conductor provided inside the capacitor body and electrically connected to the plurality of second internal electrodes; A first external electrode provided on the surface of the capacitor body and electrically connected to the first via conductor; A second external electrode provided on the surface of the capacitor body and electrically connected to the second via conductor; Comprising: When the capacitor body is viewed in the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, m×n (m and n are natural numbers of 4 or more respectively) virtual lattice points are set, and with respect to a reference arrangement in which via conductors including the first via conductor and the second via conductor are arranged at all the virtual lattice points, the first via conductor and the second via conductor are not arranged at one or more virtual lattice points located inside the virtual lattice points located on the outermost periphery and less than or equal to (m−2)×(n−2) (however, the case where the first via conductor and the second via conductor are not arranged at all the virtual lattice points located inside the virtual lattice points located on the outermost periphery of the reference arrangement is excluded). A multilayer ceramic capacitor characterized by this.

2. The multilayer ceramic capacitor according to claim 1, wherein the difference between the number of the first via conductors and the number of the second via conductors is one or less.

3. The virtual lattice points where the first via conductor and the second via conductor are not arranged are the virtual lattice points corresponding to the via conductors where the current flowing when a voltage is applied between the first external electrode and the second external electrode in the reference arrangement is small among the virtual lattice points located inside the virtual lattice points located on the outermost periphery of the reference arrangement. The multilayer ceramic capacitor according to claim 1, characterized by this.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the plurality of virtual lattice points where the first via conductor and the second via conductor are arranged are arranged symmetrically.

5. The first external electrode and the second external electrode are provided only on one of the first main surface and the second main surface that face each other in the stacking direction among the surfaces of the capacitor body, according to any one of claims 1 to 3, for the multilayer ceramic capacitor.

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