Optical Switch

Abstract

To provide a large-scale optical switch which includes a smaller number of element SW circuits while securing a non-blocking function in order to address the limited number of element SW circuits which can be installed on one wafer in a process of manufacturing the optical switch.SOLUTION: There are provided circuit topology and an implementation configuration for realizing a non-blocking type large-scale optical switch with a smaller number of element SW circuits than optical switches using conventional techniques. In terms of the circuit topology, a three-stage Clos type optical switch has sub-switches of different constitution mixed in first-stage and third-stage blocks. In terms of the implementation, all element switch circuits of the optical switch are fabricated on one wafer, and a plurality of switch regions and a plurality of waveguide regions are arranged in a zigzag-like manner. Electric wiring of the respective SW circuits arranged toward a heater is concentrated on a plurality of surface-mounted type connectors arranged on an inner side on a wafer surface. Wafer use efficiency is thus improved to reduce manufacturing costs.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to an optical switch for use in an optical communication network. [Background technology]

[0002] Optical switches are key devices in optical communication networks. In order to process the rapidly increasing communication traffic in recent years, larger-scale optical switches are required. An important performance index of an optical switch is the number of inputs and outputs that can be controlled by one switch, i.e., the number of input ports and output ports. A large-scale optical switch with a large number of ports makes it possible to switch the paths of many optical signals at the same time.

[0003] In order to increase the scale of optical switches, a multi-input, multi-output optical switch using a waveguide is considered to be promising. An optical switch is composed of many element switch circuits (hereinafter referred to as element SW circuits) with two inputs and two outputs (2 × 2). 2 Since the propagation loss of optical signals is small in silica-based waveguides, optical switches using silica-based waveguides can obtain good characteristics even when the signal light passes through many element switch circuits (Non-Patent Document 1).

[0004] One of the important functions required for optical switches is to maintain a non-blocking state even when they become large-scale and have multiple inputs and multiple outputs. Non-blocking means that when signal light from an arbitrary input port is switched to an unused output port, there is no effect on the path between the already connected input port and output port or on the optical signals passing through this path.

[0005] In the actual manufacturing process of optical switches, there is a limit to the number of elemental SW circuits that can be placed on one wafer. In order to realize larger-scale optical switches, it is important to develop new circuit topologies and implementation configurations that realize larger-scale multi-input multi-output optical switches with fewer elemental SW circuits while maintaining the above-mentioned non-blocking function. [Prior art documents]

Non-licensed literature

[0006] [Non-licensed document 1] Takashi Goh, Mitsuho Yasu, Kuninori Hattori, Akira Himeno, Masayuki Okuno, and Yasuji Ohmori, “Low Loss and High Extinction Ratio Strictly Nonblocking 16×16 Thermooptic Matrix Switch on 6-in Wafer Using Silica-Based Planar Lightwave Circuit Technology,” IEEE J. Lightwave Technol., vol. 19, no. 3, pp.371-379, 2001 [Non-licensed document 2] S. Sohma, T. Watanabe, N. Ooba, M. Itoh, T. Shibata and H. Takahashi, “Silica-based PLC Type 32x32 Optical Matrix Switch,” 2006 European Conference on Optical Communications, 2006, pp. 1-2, doi: 10.1109 / ECOC.2006.4801113 [Non-licensed document 3] C. Clos, “A study of non-blocking switching networks,” in The Bell System Technical Journal, vol. 32, no. 2, pp. 406-424, March 1953, doi: 10.1002 / j.1538-7305.1953.tb01433.x

Non-licensed Document 4

[0007] The present invention provides a circuit topology and implementation that realizes a non-blocking, large-scale optical switch with an efficient manufacturing process while reducing the number of elemental SW circuits in a wafer. [Means for solving the problem]

[0008] One embodiment of the present invention is a three-stage Clos-type optical switch having M input ports and N output ports, comprising: a first stage consisting of a plurality of sub-switches, the first stage including a sub-switch of a first configuration having m input ports and a sub-switch of a second configuration having a number of input ports different from m; a second stage including a plurality of sub-switches to which output ports of the plurality of sub-switches in the first stage are connected; and a third stage consisting of a plurality of sub-switches to which output ports of the plurality of sub-switches in the second stage are connected, the third stage including a sub-switch of a third configuration having n output ports and a sub-switch of a fourth configuration having a number of output ports different from n, each of the sub-switches including a plurality of element switch circuits, the element switch circuits being cascaded. an optical switch including two or more connected Mach-Zunder interferometers and a heater formed on one arm waveguide of each Mach-Zunder interferometer, all of the sub-switches in the first, second and third stages being arranged on a single wafer, the element switch circuit being formed in each stage as being divided into one or more switch regions, waveguide regions consisting only of waveguides connecting adjacent switch regions being arranged alternately with the switch regions, the switch regions and the waveguide regions being arranged in a zigzag pattern from the input side of the optical switch toward the output side in the order of the first stage, the second stage and the third stage, and a connector that collects electrical wiring that drives the heaters and connects them to the outside being arranged across the switch regions in different stages. Effect of the Invention

[0009] By reducing the number of element switch circuits within a wafer, a non-blocking, large-scale optical switch can be efficiently realized. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a three-stage Clos-type optical switch according to the prior art. [Diagram 2]13 is a graph showing the relationship between the number of ports of a sub-SW and the number S of required element SW circuits. [Diagram 3] This figure compares S by changing the number of ports n of the sub-SW in a 64x64 configuration. [Figure 4] FIG. 11 is a diagram showing an example of a configuration in which sub-SWs with different configurations are mixed in the first and third stages. [Diagram 5] FIG. 13 is a diagram showing another example in which sub-SWs of different configurations are mixed in a symmetrical configuration. [Figure 6] FIG. 13 is a diagram showing another example in which sub-SWs of different configurations are mixed in an asymmetric configuration. [Figure 7] FIG. 1 is a diagram showing a circuit configuration of an optical switch in which different sub-SWs according to the present disclosure are mixed. [Figure 8] 1 is a diagram illustrating the layout of element SW circuits on a wafer of an optical switch according to the present disclosure. [Figure 9] 2 is an enlarged view showing the configuration of a waveguide region of an optical switch according to the present disclosure; FIG. [Figure 10] 1 is a diagram illustrating the electrical connector arrangement on a wafer of the disclosed optical switch. [Figure 11] 2 is a diagram showing a configuration of an element SW circuit in an optical switch according to the present disclosure. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The optical switch disclosed herein provides a circuit topology and implementation form that realizes a large-scale non-blocking optical switch with fewer element SW circuits compared to conventional optical switches. In terms of circuit topology, sub-switches (sub-SWs) with different configurations are mixed in the first and third stage blocks of a three-stage Clos-type optical switch. In terms of implementation form, all element SW circuits of the optical switch are fabricated on one wafer, multiple switch regions and multiple waveguide regions are alternately arranged in a zigzag pattern, and electrical wiring to the heaters of each element SW circuit is concentrated to a connector arranged on the inner side of the wafer surface. It is also possible to increase the utilization efficiency of the wafer and reduce manufacturing costs. Below, the configuration of the optical switch disclosed herein will be explained in comparison with the optical switch of the conventional technology.

[0012] As already mentioned, excellent optical characteristics can be obtained with a waveguide device using a quartz substrate. On the other hand, it is difficult to miniaturize the element switch circuit compared to a waveguide device using Si photonics that forms a waveguide on a Si substrate. When the element switch circuit described later is created using a Mach-Zehnder Interferometer (MZI), as described in Non-Patent Document 2, the maximum switch size on a quartz substrate is about 32 x 32 per chip.

[0013] Non-Patent Document 3 reports that by making the optical switch a three-stage Clos type, it is possible to reduce the number of element switch circuits that make up a large-scale switch. In this three-stage Clos type optical switch, a large-scale multi-input multi-output optical switch is divided into smaller multi-input multi-output optical switches. The small-scale multi-input multi-output switch that is the smallest unit that makes up a large-scale optical switch is called a sub-switch (hereinafter, sub-SW).

[0014] Fig. 1 is a diagram showing the circuit configuration of a three-stage Clos-type optical switch of the prior art. The optical switch 100 has M input ports and N output ports, and is composed of a first-stage block 101, a second-stage block 102, and a third-stage block 103. In the optical switch 100 of Fig. 1, the first-stage block 101 is composed of p sub-SWs 104-1 of m×k size, the second-stage block 102 is composed of k sub-SWs 104-2 of p×q size, and the third-stage block 103 is composed of q sub-SWs 104-3 of k×n size. It is known that the condition for the three-stage Clos-type optical switch 100 of Fig. 1 to become non-blocking is expressed by the following formula. k≧m+n+1 Equation (1)

[0015] A sub-SW includes element SW circuits whose number is (number of input ports) x (number of output ports). The relationship between the number of ports M, N of the optical switch, the number of sub-SWs in each stage p, k, q, and the number of ports m, n of the sub-SW, and the required number of element SW circuits S is calculated using the following formula:

[0016]

number

[0017] Here, if the number of input ports and output ports of the optical switch is the same, that is, M=N, and further, m=n and p=q, the number of element SW circuits S is given by the following equation.

[0018]

number

[0019] For example, in silica-based waveguides, MZIs are often used as element SW circuits, and a double-gate configuration is also used to improve the crosstalk characteristics in optical switches. In the double-gate configuration, one element SW circuit is composed of two 2×2SWs (or 1×2SWs, 2×1SWs), and the number of element SW circuits required is 2S, which is obtained by further doubling S in equation (3).

[0020] Figure 2 is a graph showing the relationship between the number of ports of the sub-SW in a 3-stage Clos-type optical switch and the required number of element SW circuits S. Consider the case where the number of input ports and output ports are equal and the optical switch has a symmetrical structure, i.e., M=N, m=n, p=q, in the 3-stage Clos-type optical switch shown in Figure 1. The required number of element SW circuits S is as shown in formula (2).

[0021] FIG. 2(a) shows the relationship between the number of ports n of the sub-SW and the number of element SW circuits S when the number of ports n of the sub-SW is a divisor of the number of ports N of the optical switch. FIG. 2(b) shows the relationship between the number of ports n of the sub-SW and the index S / N 2 In both cases, the overall scale of the optical switch is shown as a parameter (N×N, N=16, 32, 64, 128). 2 represents the ratio of the number of element SW circuits S to the square of the number of ports N of the entire optical switch, and corresponds to the ratio of the number of element SW circuits to the entire scale of the optical switch. 2If the S / N ratio is small, an optical switch can be efficiently constructed with a relatively smaller number of element SW circuits. In a typical PILOSS-type optical switch, rather than a Clos-type switch that divides the optical switch into multiple blocks, the S / N ratio is 2 will be 1.

[0022] Referring to Fig. 2(a), when the number of ports N of the optical switch is fixed, the required number of element SW circuits S is minimized at a certain value for the number of ports n of the sub-SW. For example, in a 128 x 128 optical switch configuration, the number of ports n of the sub-SW is minimal at 8. In a 16 x 16 optical switch, the number of element switch circuits S does not decrease even when a 3-stage Clos type configuration is adopted, and even in a 32 x 32 optical switch, the effect of reducing the number of element SW circuits S is limited.

[0023] Also, referring to FIG. 2(b), the indicator S / N 2 The reduction in S / N ratio can be seen in optical switches with a scale larger than 32 × 32. In order to use a three-stage Clos-type configuration instead of the usual PILOSS configuration, the S / N ratio must be increased. 2 must be at least less than 1. In order to accommodate a large-scale optical switch circuit, the larger the wafer diameter, the better, for example, 6 inches or more is desirable. As an example of a wafer with such a large diameter and a realistic manufacturing process for optical integrated circuits, the case of accommodating all the elemental switch circuits of the 64 × 64 scale 3-stage Clos-type optical switch shown in Figure 1 will be described below.

[0024] Figure 3 shows a table comparing the breakdown of the number of element SW circuits S in a 64 x 64 size optical switch by changing the number of ports n of the sub-SW. In Figure 1, the number of input and output ports is equal (M = N = 64) and the optical switch has a symmetrical structure, and shows the number of element SW circuits in each stage when the number of ports n of the sub-SW (2, 4, 8, 16, 32) is changed. The configurations shown in the table in Figure 3 correspond to the plot points on the 64 x 64 curve shown in Figure 2. When n = 4, N 2 S / N = 4096 2=0.6563, which has the effect of reducing the number of element switch circuits by about 35% compared to an optical switch with a PILOSS configuration.

[0025] The inventors have investigated an optical switch configuration that further reduces the number of element switch circuits, compared to the PILOSS configuration, by reducing the number of element switch circuits by 35% through the above optimization of the 64 x 64 optical switch. By combining this with a new implementation configuration, a large-scale optical switch can be realized with an efficient manufacturing process. The inventors focused on, first, improving the number of element switch circuits in the circuit topology, and, second, improving the area occupied by electrical wiring in the implementation.

[0026] In the optimization of the 3-stage Clos-type optical switch shown in Figures 1 to 3 above, the optical switch configuration was limited to an N x N symmetrical structure with the same number of ports on the input and output sides. In addition, the number of ports n of the sub-SWs in the first and third stage blocks was set as a divisor of the number of ports N of the optical switch, and all sub-SWs were given the same configuration. In the table in Figure 3, the number of element SW circuits and the index S / N 2 Even when n=4, which is the smallest, the total number of element switch circuits is 2688. As will be described later, each of the many element switch circuits requires electrical wiring to control its respective heater. To efficiently connect the heaters to a control signal source external to the optical switch chip, a multi-pin connector is required to collect the many electrical wirings for the element switch circuits. If it is possible to reduce the number of connectors while simultaneously reducing the number of element switch circuits, the manufacturing cost of the optical switch can also be reduced.

[0027] Therefore, we investigated a 64x64 optical switch in which sub-SWs with a port number n of 4 and sub-SWs with a port number n' other than 4 are mixed in the first and third stage blocks. We compared the combination of sub-SWs with different configurations in the first and third stage blocks with the configuration of the conventional technology in which sub-SWs with the same configuration are used in each stage shown in Figure 3. For simplicity, we considered that the sub-SWs in the first and third stage blocks have symmetrical optical switch circuit topologies. For example, if the first stage sub-SW has an nxp configuration, the corresponding third stage sub-SW has a pxn configuration.

[0028] Figure 4 shows an example of an optical switch configuration in which sub-SWs of different configurations are mixed in the first and third stage blocks. When the number of input ports M and output ports N are 64, the first stage block of a three-stage Clos type mixes one sub-SW with an input port number n=4 (first configuration) and 12 sub-SWs with an input port number n´=5 (second configuration). The third stage block of a three-stage Clos type mixes one sub-SW with an output port number n=4 (third configuration) and 12 sub-SWs with an output port number n´=5 (fourth configuration).

[0029] In an optical switch that has a mixture of a sub-SW with n ports and a sub-SW with n' ports of a different configuration, the condition for non-blocking is given by the following formula, where MAX(n) is the larger of n and n'. k≧n+MAX(n)-1 Equation (4)

[0030] 1, the number of ports of the sub-SW is the number of ports on the optical switch input side for the sub-SW in the first stage block 101 (corresponding to m in FIG. 1), and the number of ports on the optical switch output side for the sub-SW 103 in the third stage block (corresponding to n in FIG. 1). The sub-SW in the first stage block and the sub-SW in the third stage block have a symmetrical structure.

[0031] As shown in Fig. 4, by mixing sub-SWs with different configurations in the first and third stage blocks, the total number of element SW circuits is S = 2640. Compared to the case where all sub-SWs in the first and third stage blocks have the same configuration with port number n = 4 (4 × 7, 7 × 4) as shown in the table in Fig. 3, the total number of element SW circuits can be reduced by 48. The effect of mixing sub-SWs with different configurations in the first and third stage blocks can also be confirmed in other configuration patterns where sub-SWs are mixed.

[0032] FIG. 5 shows another example of a configuration pattern of an optical switch in which sub-SWs with different configurations are mixed in the first and third stage blocks in the case of a symmetrical configuration of M=N=64. Each parameter in the table of FIG. 5 is as defined in FIG. 8 described later, where M=N. In the table shown in FIG. 5, 1 ×k 1 , m 2 ×k 2 The two types of sub-SWs are mixed, and in the third block, 1 ×n 1 , k 2 ×n 2 The figure shows the configuration patterns when two types of sub-SWs are mixed. The number of element SW circuits is compared with the case in Fig. 3 where only sub-SWs of the same configuration (4x7, 7x4) with m=n=4 and k=7 are equipped. It can be seen that there are various configuration patterns in which sub-SWs of different configurations are mixed, which can reduce the total number of element SW circuits.

[0033] FIG. 6 shows an example of an optical switch configuration pattern in which sub-SWs of different configurations are mixed in the first and third stage blocks in an asymmetric configuration with M=64 and N=128. The parameters in the table in the figure are as defined in FIG. 8, which will be described later. The above-mentioned FIG. 4 and FIG. 5 show the effect of mixing sub-SWs in an optical switch with a symmetric structure where M=N=64 and the same number of input ports and output ports. In FIG. 6, p 1 m 1 ×k 1 , p 2 m 2 ×k2 The two types of sub-SWs are mixed (however, 1 >m 2 ) In the third block with output ports N=128, q 1 k 1 ×n 1 , q 2 k 2 ×n 2 There are two types of sub-SWs with the above configurations (however, 1 >n 2 ) Even in an asymmetric optical switch with different numbers of input and output ports, it is clear that there are various configuration patterns in which sub-SWs of different configurations are mixed together, which can reduce the total number of element SW circuits.

[0034] FIG. 7 is a diagram showing the circuit configuration of a three-stage Clos-type optical switch according to the present disclosure, in which sub-SWs of different configurations are mixed. The optical switch 10 has M input ports and N output ports, and is composed of a first-stage block 11, a second-stage block 12, and a third-stage block 13. The difference in configuration from the conventional optical switch shown in FIG. 1 is that sub-SWs of different configurations are mixed in each of the first and third stages. In the first-stage block, m 1 ×k 1 The configuration of the sub SW11-1 and m 2 ×k 2 The third block 13 includes two types of sub-SW11-2 with the configuration of k 1 ×n 1 The configuration of the sub SW13-1 and k 2 ×n 2 The number of input ports M is m 1 ×p 1 +m 2 ×p 2 The number of output ports N is n 1 ×q 1 +n 2 ×q 2 The number of ports of the sub-SW is k 1 , k 2 is the number of ports m 1 , m 2 , n 1 , n 2The following formula shall be satisfied between

[0035]

number

[0036] The second stage block 12 also includes sub-switches with different configurations in order to conform to a configuration in which sub-switches with different configurations in the first stage and third stage are mixed.

[0037] It will be understood that the reduction in the number of element SW circuits in the optical switches of each configuration shown in Figures 4 to 6, combined with the features of the implementation of the optical switch of the present disclosure described below, has the effect of increasing the scale of the optical switch and reducing the manufacturing cost. Below, various features of the implementation of the optical switch of the present disclosure in which sub-SWs of different structures are mixed, as shown in Figure 7, will be described.

[0038] 8 is a diagram showing the layout configuration of the optical switch of the present disclosure on a wafer. As an example, the rough layout of the element SW circuits of the optical switch on a wafer 200 made of a quartz substrate is shown. The optical switch of the present disclosure differs from the conventional three-stage Clos type optical switch 100 shown in FIG. 1 only in that sub-SWs of different configurations are mixed in each of the first stage block 101 and the third stage block 103. There is no difference in the rough layout of the three-stage blocks of the three-stage Clos type optical switch.

[0039] In the optical switch of the present disclosure, all element SW circuits of the 64×64 optical switch are arranged in a zigzag shape (zigzag shape) with multiple regions connected between the input point 221-1 indicated by the arrow at the top of FIG. 8 and the output point 221-2 indicated at the bottom. In the six switch (SW) regions 211-1, 211-2, 212-1, 212-2, 213-1, and 213-2 hatched with diagonal lines, multiple element SW circuits constituting sub-SWs are arranged in a matrix shape. The details will be described later with reference to FIG. 11, but the element SW circuits include at least MZIs, waveguides connecting between MZIs, and heaters. The seven waveguide regions 214a to 214g including bent portions on the input side or output side of each SW region are composed only of waveguides connecting between element SW circuits at the respective ends of adjacent SW regions. Therefore, in the optical switch of the present disclosure, the element SW circuit of the Clos-type optical switch is divided into a plurality of SW regions in the order of the constituent stages (first stage, second stage, third stage). Waveguide regions consisting only of waveguides connecting adjacent SW regions are arranged alternately with the SW regions, and these SW regions and waveguide regions are arranged in a zigzag pattern from the input side to the output side.

[0040] Referring again to FIG. 8, the zigzag arrangement is described in detail. In the two SW regions 211-1 and 211-2 sandwiching the U-shaped waveguide region 214b, sub-SWs with different configurations of the first stage block of the three-stage Clos type optical switch are arranged. Following the SW region 211-2, a waveguide region 214c is arranged in a U-shaped folded shape to connect the first stage block and the second stage block. Similarly, in the two SW regions 212-1 and 212-2 sandwiching the waveguide region 214d, sub-SWs of the second stage block are arranged. Following the SW region 212-2, a waveguide region 214e is arranged in a U-shaped folded shape to connect the second stage block and the third stage block. Similarly, in the two SW regions 213-1 and 213-2 sandwiching the waveguide region 214f, sub-SWs with different configurations of the third stage block are arranged.

[0041] In the on-wafer configuration of Fig. 8, the sub-SWs in each stage are arranged in two separate SW regions, but this is one example of an optical circuit arrangement, and the division of the SW regions is not limited to that shown in Fig. 8. The number of SW regions in each stage may be one or three or more, and the number of SW regions may differ depending on the stage.

[0042] The optical switch disclosed in this disclosure can realize a configuration that suppresses signal crosstalk by further including a waveguide region with a folded structure that connects between SW regions arranged in a zigzag pattern. In the configuration of a three-stage Clos type optical switch, as shown in FIG. 1, paths cross between each stage. If this path crossing is realized by a two-dimensional waveguide on the wafer surface, the waveguides will cross, and crosstalk will occur due to signal light leaking between the paths. In order to suppress crosstalk at the crossing, it is necessary to make the crossing angle of the two waveguides as large as possible (Non-Patent Document 6).

[0043] FIG. 9 is a diagram showing an enlarged configuration of the waveguide region of the optical switch of the present disclosure. Only a part of the wafer 200 shown in FIG. 8 is shown, and the waveguide region 231 connecting the two SW regions 230-1 and 230-2 is shown enlarged on the right side. All of the multiple waveguides connecting the two SW regions have a U-shaped folded structure. In general, in order to propagate an optical signal with low loss in an optical waveguide, it is necessary to provide a bending radius of a predetermined value or more, and in order to make the crossing angle large, the area in the wafer used for the crossing becomes wide. According to the arrangement of the optical switch of the present disclosure, the necessary large bending angle can be realized by the folding back that the waveguide region 231 inherently has. And, by arranging the crossing portion 232 in the waveguide region 231, the crossing angle can be maximized without increasing the circuit area for crosstalk reduction. As is clear from the enlarged view of FIG. 9, it is possible to arrange the two waveguides so that they are orthogonal at 90 degrees at all crossing portions, and the optical switch of the present disclosure hardly generates crosstalk of the signal light between the paths.

[0044] Furthermore, the optical switch of the present disclosure also has features in the electrical wiring and its extraction configuration. Referring again to Fig. 8, the wafer 200 including the optical switch is cut at the dicing lines 223-1 and 223-2, and mounted on another substrate of the device. On the device, a bundle of 64 optical fibers is connected at the end faces cut by the dicing lines at the input point 221-1 and the output point 221-2. Although not shown in Fig. 8, electrical wiring for control is configured for the heaters of each element SW circuit on a layer separate from the waveguides of the MZI of the element SW circuit on the wafer.

[0045] In an optical switch, each element switch circuit needs to be controlled independently. To achieve this, each element switch circuit needs to be electrically connected to a control device that sends out a control signal via electrical wiring on the wafer and a cable or flexible printed circuit board (FPC), etc. A common method for connecting to electrical wiring on the wafer is to use wire bonding to pads provided on the periphery of the chip. However, this method requires that electrical wiring be extended from each element switch circuit to the periphery of the chip, and a large area on the chip is used for electrical wiring. If the optical switch becomes larger and the number S of element switch circuits increases, the area used only for electrical wiring also increases (Non-Patent Document 4). Electrical wiring reduces the utilization efficiency of the wafer and increases the chip size and wafer diameter. It also increases the cost of the wafer and the cost of the manufacturing process.

[0046] In the optical switch of the present disclosure shown in Fig. 8, surface mount (SMT) type electrical connectors are mounted on the six SW regions 211-1, 211-2, 212-1, 212-2, 213-1, and 213-2 in which element SW circuits are fabricated, and each element switch circuit is electrically connected to an external control device, etc. via the electrical connectors. This mounting method can eliminate or reduce the increase in chip size and wafer diameter due to electrical wiring, and the waste in wafer utilization efficiency. FIG. 10 is a diagram for explaining the arrangement of electrical connectors on a wafer of an optical switch of the present disclosure. The six SW regions and seven waveguide regions on the wafer 220 are the same as those shown in FIG. 8. In order to collect electrical wiring to each element SW circuit, an SMT type connector is arranged on the surface of the wafer, and the outer shape of the connector is shown by nine dotted line regions 2301- to 230-9. The connector is mounted by carrying out a process such as reflow soldering on the wafer 200. The electrode pads formed on the wafer surface and the connector pins are soldered near the dotted lines showing the outer shape of the connector in FIG. 10. When the SMT type connector is arranged as in FIG. 10, a connector that can be inserted and removed from the connector on the mating FPC cable side perpendicular to the wafer surface can be used. If the connector shape on the FPC cable side is L-shaped, it may be inserted and removed parallel to the wafer surface.

[0047] In the optical switch of the present disclosure, all element SW circuits of the optical switch are mounted on one wafer, and the element SW circuits in one stage are arranged in a plurality of SW regions. As described in FIG. 8, the plurality of SW regions 211-1 to 213-2 are arranged in a zigzag pattern alternately with the waveguide regions 214a to 214g, so that one SW region is arranged close to another SW region in the same stage or in an adjacent stage. All element SW circuits of the three-stage Clos-type optical switch are arranged together in the wafer surface. By arranging a plurality of SMT connectors on the inner side of the wafer surface across the SW regions of adjacent stages, it is possible to realize concentrated electrical wiring. By arranging each of the plurality of SMT connectors so as to cross at least two SW regions, it is possible to share the connector within the same stage or across different stages.

[0048] Compared to the conventional technology where connectors are arranged around the periphery of the wafer, electrical wiring can be arranged more compactly. There is no need to route electrical wiring around the periphery of the wafer, and no need to provide an area for electrical wiring. The area of ​​the circular wafer can be used without waste, resulting in extremely high wafer utilization. There is no need to increase the diameter of the wafer, and small-diameter wafers can be used, making it possible to use a process that is sufficiently stable and proven in terms of the manufacturing process of optical integrated circuits. By mixing sub-SWs with different configurations in the first and third stage blocks to reduce the number of element SW circuits and adopting the connector arrangement described above, the manufacturing cost of the entire optical switch can be reduced.

[0049] Fig. 11 is a diagram showing the configuration of an element SW circuit in an optical switch of the present disclosure. Fig. 11 shows an element SW circuit when a three-stage Clos-type optical switch is configured with a matrix switch. To obtain a high extinction ratio as an optical switch, it is necessary to increase the extinction ratio in the element SW circuits corresponding to each intersection of the matrix switch. An element SW circuit that achieves a high extinction ratio can be realized by connecting multiple MZIs in parallel or in cascade (Non-Patent Document 5). (a) and (b) in Fig. 11 both show element SW circuits with a double gate configuration using two MZIs connected in cascade.

[0050] Referring to FIG. 11, each of the double-gate element SW circuits 300a and 300b includes two MZIs 301 and 302. One MZI 301 is composed of an input coupler 307a, two arm waveguides, and an output coupler 307b. Heaters 304-1 and 304-2 are formed on one arm waveguide of each MZI. (a) and (b) of FIG. 11 show different examples of electrical wiring to two heaters of the element SW circuit. (a) of FIG. 11 shows electrical wiring 305-1 and 305-2 that drive the heaters in parallel connection, and (b) shows electrical wiring 306 that drives the heaters in direct connection. In either case of electrical wiring, the output port can be switched by applying a control voltage 303 to both ends of the electrical wiring to change the optical path length of one of the waveguides using the heater. Multiple MZIs connected in series are always turned ON / OFF simultaneously. By electrically connecting the heaters in series, it is possible to reduce the number of electrodes required per element switch circuit. This type of electrical connection reduces the area that the electrical wiring occupies on the wafer, and contributes to miniaturizing the optical switch chip.

[0051] Two electrical wirings are required to control the element switch circuit shown in Fig. 11, but if one terminal is grounded to drive the heater, only one electrical wiring is required per element switch circuit. In the 64 x 64 optical switch shown in Fig. 8, when sub-SWs with different configurations are combined in the first and third stages, the total number of element switch circuits S is 2640 as shown in Fig. 4. Here, if an SMT connector with 80 pins is used, and one of the electrical wirings of the heater is grounded and one pin of each SMT connector is used for grounding, the total number of connectors is 34. This can also reduce the number of connectors compared to the total number of 35 when the first and third stages of sub-SWs are configured with the same configuration as in the conventional technology configuration shown in Fig. 3.

[0052] In the above description of the implementation form, a three-stage Clos-type optical switch has been taken as an example, but in a Clos-type optical switch with a different number of stages other than three, sub-SWs with different configurations may be mixed in the first stage (input side) and the final stage (output side). The effect of reducing the number of element switch circuits may also be achieved by mixing sub-SWs with different configurations only on either the input side or the output side. In addition, the above-mentioned implementation structure example of the three-stage Clos-type optical switch has been described in the case where the input ports M and the output ports N are the same number, but it can also be applied to an asymmetric optical switch with different M and N configurations as described in FIG. 6.

[0053] As described above in detail, the optical switch disclosed herein provides a circuit topology and implementation form that realizes a non-blocking, large-scale optical switch with fewer element switch circuits than conventional techniques. [Industrial Applicability]

[0054] The present invention can be applied to an optical switch used in optical communications.

Claims

1. A three-stage Clos-type optical switch having M input ports and N output ports, a first stage of sub-switches, the first stage including a first configuration of sub-switches having m input ports and a second configuration of sub-switches having a number of input ports different from m; a second stage including a plurality of sub-switches to which output ports of the plurality of sub-switches of the first stage are connected; a third stage comprising a plurality of sub-switches to which output ports of the plurality of sub-switches of the second stage are connected, the third stage including a sub-switch of a third configuration having n output ports and a sub-switch of a fourth configuration having a number of output ports different from n; Equipped with Each of the sub-switches includes a plurality of element switch circuits, and the element switch circuits include two or more cascaded Mach-Zehnder interferometers and a heater formed on one arm waveguide of each of the Mach-Zehnder interferometers; all of the sub-switches in the first stage, the second stage and the third stage are disposed on a single wafer; the element switch circuits are divided into one or more switch regions in each stage, and waveguide regions each consisting of only a waveguide connecting adjacent switch regions are arranged alternately with the switch regions, and the switch regions and the waveguide regions are arranged in a zigzag pattern from the input side of the optical switch toward the output side in the order of the first stage, the second stage, and the third stage, A connector for collecting the electric wiring for driving the heater and connecting it to the outside is arranged across the switch areas in different stages.

1. An optical switch comprising:

2. the number of input ports M and the number of output ports N are equal; The optical switch described in claim 1, characterized in that the number m of input ports of the sub-switch of the first configuration is equal to the number n of output ports of the sub-switch of the third configuration, and the number of input ports of the sub-switch of the second configuration is equal to the number of output ports of the sub-switch of the fourth configuration.

3. M=N=64, the first stage includes one 4×8 switch and twelve 5×9 switches; the second stage includes eight 13×13 switches and one 12×12 switch; The optical switch of claim 2, wherein the third stage includes one 8x4 switch and twelve 9x5 switches.

4. The material of the wafer is quartz (SiO 2 4. The optical switch according to claim 1, wherein

5. 4. The optical switch according to claim 1, wherein in the waveguide region between two adjacent switch regions, different waveguides cross at a crossing angle of 90 degrees.

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