Semiconductor Module and Electronic Device

Abstract

To provide a semiconductor module in which the bond strength between a chip component and a solder is sufficient.SOLUTION: A semiconductor module includes a semiconductor device including a first land, a second land, and a third land, a wiring board including a substrate and a fourth land, a fifth land, and a sixth land disposed on a main surface of the substrate, a chip component including a first electrode and a second electrode disposed apart from each other in a longitudinal direction and disposed between the wiring board and the semiconductor device, a first solder bonding the first land and the fourth land, and the first electrode, a second solder bonding the second land and the fifth land, and the second electrode, and a third solder bonding the third land and the sixth land. The volume of the first solder and the volume of the second solder are larger than the volume of the third solder.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module and an electronic device.

Background Art

[0002] An electronic device such as a mobile device includes a semiconductor module including a semiconductor device that communicates with another semiconductor device such as a memory, and a wiring board on which the semiconductor device is mounted. In electronic devices, the communication speed of semiconductor devices is increasing and the voltage is decreasing, and it is required to reduce the noise generated in the semiconductor devices.

[0003] As one means for reducing noise, it is known to connect a bypass capacitor between the power supply terminal and the ground terminal of a semiconductor device. Patent Document 1 discloses a technique of mounting a bypass capacitor, which is a chip component, on a wiring board with solder between a semiconductor device and the wiring board.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the prior art, the bonding strength between the chip component and the solder was insufficient.

Means for Solving the Problems

[0006] A semiconductor module for solving the above problems includes a semiconductor device having a first land, a second land, and a third land, a substrate, a fourth land disposed on a main surface of the substrate, a wiring board having a fifth land and a sixth land, a chip component having a first electrode and a second electrode disposed at intervals in a longitudinal direction and disposed between the wiring board and the semiconductor device, a first solder joining the first land, the fourth land, and the first electrode, a second solder joining the second land, the fifth land, and the second electrode, and a third solder joining the third land and the sixth land, and volumes of the first solder and the second solder are larger than that of the third solder. The volume of the first solder and the volume of the second solder are 1.2 times or more the volume of the third solder. It is characterized by this.

Effect of the Invention

[0007] According to the present disclosure, a semiconductor module having sufficient bonding strength between a chip component and solder can be provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0010] [First Embodiment] FIG. 1 is an explanatory diagram of a digital camera 600 which is an imaging device as an example of an electronic device according to the first embodiment. The digital camera 600 which is an imaging device is an interchangeable-lens digital camera and includes a camera body 601. A lens unit (lens barrel) 602 including a lens is detachable from the camera body 601. The camera body 601 includes a housing 611, and a processing module 300 which is a printed circuit board and a sensor module 900 disposed inside the housing 611. The processing module 300 is an example of a semiconductor module. The processing module 300 and the sensor module 900 are electrically connected by a cable 950.

[0011] The sensor module 900 has an image sensor 700 which is an imaging element and a printed wiring board 800. The image sensor 700 is mounted on the printed wiring board 800. The image sensor 700 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 700 has a function of converting light incident through the lens unit 602 into an electrical signal.

[0012] The processing module 300 includes a semiconductor device 100 and a printed wiring board 200 which is a first wiring board. The semiconductor device 100 is mounted on the printed wiring board 200. The printed wiring board 200 is a rigid board. The semiconductor device 100 is, for example, a digital signal processor, and has a function of acquiring an electrical signal from an image sensor 700, performing a process of correcting the acquired electrical signal, and generating image data.

[0013] Hereinafter, the processing module 300 will be described with reference to FIGS. 2 to 4.

[0014] The semiconductor device 100 is an area array semiconductor package, and in the first embodiment, it is a BGA (Ball Grid Array) semiconductor package. The semiconductor device 100 includes a semiconductor element and a package substrate 102 which is a second printed wiring board. The package substrate 102 is a rigid board.

[0015] The semiconductor element 101 is mounted on the package substrate 102. The package substrate 102 has an insulating substrate 120. The insulating substrate 120 has a main surface 121 and a main surface 122 opposite to the main surface 121. The material of the insulating substrate 120 is, for example, a ceramic such as alumina. The semiconductor element 101 is, for example, a semiconductor chip, and is mounted on the main surface 121 of the insulating substrate 120 in a face-down manner in the first embodiment.

[0016] The semiconductor element 101 has a plurality of power terminals, a plurality of ground terminals, and a plurality of signal terminals, and each terminal is joined to the package substrate 102 by wire bonding or flip chip bonding (not shown). FIGS. 2(b), 3(a), and (b) show a power terminal 111E which is one of the plurality of power terminals and a ground terminal 111G which is one of the plurality of ground terminals. That is, the semiconductor element 101 has the power terminal 111E and the ground terminal 111G.

[0017] On the main surface 121 of the insulating substrate 120, a sealing resin 106 for sealing the semiconductor element 101 is provided. The package substrate 102 has a plurality of lands 130 disposed on the main surface 122 of the insulating substrate 120.

[0018] The plurality of lands 130 are arranged at a pitch with a minimum interval of 0.7 mm or less between each land. From the viewpoint of arranging the lands at high density, it is preferable that the minimum interval between each land is a pitch of 0.4 mm or less. However, the arrangement pattern may be a grid pattern, that is, a matrix pattern, or a staggered pattern. The land 130 is a terminal formed of a conductive metal material, such as copper or gold, and is, for example, a signal terminal, a power supply terminal, a ground terminal, or a dummy terminal. The plurality of lands 130 include a land 130E serving as a power supply terminal, a land 130G serving as a ground terminal, and lands 130S other than the lands 130E and 130G. The land 130S is a land that serves as a signal terminal, a power supply terminal, a ground terminal, or a dummy terminal. The land 130E is the first land, the land 130G is the second land, and the lands 130S are a plurality of third lands. The land 130E that is the first land and the land 130G that is the second land are adjacent to each other. The land 130S that is the third land is adjacent to the land 130E that is the first land and the land 130G that is the second land. The land 130E is electrically connected to the power supply terminal 111E of the semiconductor element 101 via a via conductor 112E formed in the insulating substrate 120. The land 130G is electrically connected to the ground terminal 111G of the semiconductor element 101 via a via conductor 112G formed in the insulating substrate 120.

[0019] On the main surface 122, a solder resist 108 is provided. The solder resist 108 is a film made of a solder resist material. Each of the plurality of lands 130 is exposed by a plurality of openings formed in the solder resist 108. The land 130 may be either an SMD (solder mask defined) or an NSMD (non-solder mask defined) land, but in the first embodiment, it is an SMD land. Note that each of the lands 130 may be formed independently without the solder resist 108. Although not shown, a heat sink may be disposed on the upper surface of the semiconductor element 101.

[0020] The printed wiring board 200, which is a wiring board, has an insulating substrate 220. The insulating substrate 220 has a main surface 221 and a main surface 222 opposite to the main surface 221. The printed wiring board 200 has a plurality of lands 230 disposed on the main surface 221 of the insulating substrate 220. The material of the insulating substrate 220 is an insulating material such as an epoxy resin. However, the wiring board is not limited to a printed wiring board and may be a semiconductor substrate such as an Si substrate.

[0021] The plurality of lands 230 are terminals formed of a conductive metal material, such as copper or gold, and are, for example, signal terminals, power supply terminals, ground terminals, or dummy terminals. The material of the insulating substrate 220 is an insulating material such as an epoxy resin. The plurality of lands 230 include a land 230E serving as a power supply terminal, a land 230G serving as a ground terminal, and lands 230S other than the lands 230E and 230G. The land 230S is a land that serves as a signal terminal, a power supply terminal, a ground terminal, or a dummy terminal. The land 230E is the fourth land, the land 230G is the fifth land, and the lands 230S are a plurality of sixth lands. The land 230E that is the fourth land and the land 230G that is the fifth land are adjacent to each other. The land 230S that is the sixth land is adjacent to the land 230E that is the fourth land and the land 230G that is the fifth land. The land 230E is electrically connected to a via conductor 212E formed in the insulating substrate 220. The land 230G is electrically connected to a via conductor 212G formed in the insulating substrate 220. A power supply IC (not shown) electrically connected to the via conductors 212E and 212G shown in FIG. 3 is mounted on the printed wiring board 200. The power supply IC can supply power to the semiconductor element 101 of the semiconductor device 100 via solder joints 191 and 192. Note that the power supply IC (not shown) of the printed wiring board 200 may be electrically connected without passing through the via conductors 212E and 212G. The land 230S may be electrically connected to a signal wiring (not shown). The 4 land 230E that is a 5 land, the land 230G that is a 6 land, and the lands 230S that are lands have substantially the same size. Specifically, the area of the land with the largest area is 1.1 times or less the area of the land with the smallest area.

[0022] The printed wiring board 200 has a solder resist 208. The solder resist 208 is a film made of a solder resist material. The solder resist 208 is provided on the main surface 221. Each of the plurality of lands 230 is exposed by a plurality of openings formed in the solder resist 208. The land 230 may be either an SMD or an NSMD land, but in the first embodiment, it is an SMD land. Also, the solder resist 208 may have a plurality of guiding portions 208E and 208G that cover the first conductor pattern 250E and the second conductor pattern 250G, which will be described later. The functions of the guiding portions 208E and 208G will be described later. Note that the printed wiring board 200 may not have the solder resist 208. In that case, each of the plurality of lands 230 may be independently formed on the main surface 221 of the insulating substrate 220. Also, the openings in the solder resist 208 may expose not only the lands 230S, 230E, and 230G but also the region where the capacitor 400 is disposed.

[0023] In the first embodiment, the land 230E of the printed wiring board 200 is joined to the land 130E via a first solder joint 191 formed of solder. Also, the land 230G is joined to the land 130G via a second solder joint 192 formed of solder. Also, the land 230S is joined to the land 130S via a third solder joint 193 formed of solder. Note that each solder joint may also be referred to as "solder".

[0024] The processing module 300 includes a capacitor 400, which is an example of an electronic component. The capacitor 400 is a passive component and a chip component. The size of the chip component in plan view is preferably 0402 size, which is 0.4 mm × 0.2 mm, or 0201 size, which is 0.25 mm × 0.125 mm, etc., that is, 0402 size or less. Note that the notations such as 0402 size and 0201 size conform to the size notation method (mm standard) of electronic components in the Japanese Industrial Standards.

[0025] The capacitor 400 has a substantially rectangular parallelepiped-shaped element body 401 extending in the longitudinal direction, and a pair of electrodes 410 and 420 spaced apart from each other on both sides of the element body 401 in the longitudinal direction. The pair of electrodes 410 and 420 are fixed to the element body 401 with a space therebetween in the longitudinal direction. In FIGS. 2(b) to 4, the longitudinal direction of the capacitor 400, that is, the element body 401, is the X direction. The short-side direction of the capacitor 400, that is, the element body 401, is the Y direction. The Y direction is the width direction orthogonal to the X direction. The vertical direction of the capacitor 400, that is, the element body 401, is the Z direction. The Z direction is the direction orthogonal to the X direction and the Y direction. The Z direction is also the direction perpendicular to the main surfaces 121, 122, 221, and 222.

[0026] One of the pair of electrodes 410 and 420, i.e., the electrode 410, is the first electrode, and the other electrode 420 is the second electrode. Each of the electrodes 410 and 420 includes a base and an outer film covering the base. The material of the outer film of the electrodes 410 and 420 is a metal material having conductivity such as tin.

[0027] The capacitor 400 is a bypass capacitor. The electrode 410 of the capacitor 400 is connected to the solder joint 191. That is, the electrode 410 of the capacitor 400 is electrically connected to the lands 130E and 230E via the solder joint 191. The electrode 420 of the capacitor 400 is connected to the solder joint 192. That is, the electrode 420 of the capacitor 400 is electrically connected to the lands 130G and 230G via the solder joint 192.

[0028] As shown in FIG. 4, the electrode 410 has three side surfaces 411, 412, 413, an upper surface 414, and a lower surface 415, which are the electrode surfaces. The side surfaces 411, 412, 413, the upper surface 414, and the lower surface 415 are rectangular when viewed from a direction perpendicular to each surface. Among the three side surfaces 411, 412, 413, two side surfaces 412, 413 are opposed to each other with a space therebetween in the Y direction. The upper surface 414 and the lower surface 415 are opposed to each other with a space therebetween in the Z direction. The side surface 411 is adjacent to the side surfaces 412, 413, the upper surface 414, and the lower surface 415 at right angles. The electrode 420 has three side surfaces 421, 422, 423, an upper surface 424, and a lower surface 425, which are the electrode surfaces. The side surfaces 421, 422, 423, the upper surface 424, and the lower surface 425 are rectangular when viewed from a direction perpendicular to each surface. Among the three side surfaces 421, 422, 423, two side surfaces 422, 423 are opposed to each other with a space therebetween in the Y direction. The upper surface 424 and the lower surface 425 are opposed to each other with a space therebetween in the Z direction. The side surface 421 is adjacent to the side surfaces 422, 423, the upper surface 424, and the lower surface 425 at right angles. The side surface 411 of the electrode 410 and the side surface 421 of the electrode 420 are arranged to be opposed to each other with a space therebetween in the X direction. The upper surface 414 of the electrode 410 faces the land 130E of the semiconductor device 100, and the lower surface 415 of the electrode 410 faces the land 230E of the printed wiring board 200. The upper surface 424 of the electrode 420 faces the land 130G of the semiconductor device 100, and the lower surface 425 of the electrode 420 faces the land 230G of the printed wiring board 200.

[0029] Power noise is generated due to the inductance of the wiring between the electrode 410 of the capacitor 400 and the power supply terminal 111E, and the inductance of the wiring between the electrode 420 of the capacitor 400 and the ground terminal 111G. Power noise refers to the voltage fluctuation of the power line generated when the semiconductor device 100 operates. This voltage fluctuation is generated by the change in the power current due to the inductance and resistance parasitic on the power line. In order to reduce the inductance of the wiring and thus reduce the power noise, the capacitor 400 is preferably arranged such that the wiring between the power supply terminal 111E and the ground terminal 111G of the semiconductor device 100 is the shortest. In the present disclosure, since the electrode 410 of the capacitor 400 is electrically connected to the land 130E of the semiconductor device 100 at the solder joint 191, the inductance of the wiring between the electrode 410 of the capacitor 400 and the land 130E can be reduced. Also, since the electrode 420 of the capacitor 400 is electrically connected to the land 130G of the semiconductor device 100 at the solder joint 192, the inductance of the wiring between the electrode 420 of the capacitor 400 and the land 130G can be reduced. Since the inductance of the wiring is reduced, the generated power noise is reduced, and high-speed communication in the semiconductor device 100 can be realized.

[0030] Incidentally, in Patent Document 1 as well, a capacitor, which is a chip component, is mounted between a semiconductor device and a wiring board with solder. However, as a result of intensive studies by the inventor of the present application, it has been found that the bonding strength between the chip component and the solder is insufficient in the technology disclosed in the above document. Specifically, in the above document, solder balls of the semiconductor device are not formed at the positions where the chip components are connected. Therefore, the volume of the solder joint connecting the electrode of the chip component is smaller than the volume of the solder joint connecting the semiconductor device and the wiring board. In the technology disclosed in the above document, the chip component may be peeled off from the solder joint when a strong impact such as a drop test is applied.

[0031] Therefore, the present disclosure adopts a configuration in which the volume of the first solder joint 191 and the volume of the second solder joint 192 are larger than the volume of the third solder joint 193. By adopting such a configuration, it has been found that the bonding strength between the solder joints 191 and 192 and the capacitor 400 can be made higher than in the prior art. When a strong impact such as a thermal shock is applied to the processing module 300, stress concentrates near the edges of the electrodes 410 and 420 of the capacitor 400. If the volume of the solder joints 191 and 192 is smaller than the volume of the solder joint 193, at least one of the electrodes 410 and 420 of the capacitor 400 will contact the land 130 or the land 230. In this state, when stress concentrates near the edges of the electrodes 410 and 420 of the capacitor 400, cracks are likely to occur from near the edges of the electrodes 410 and 420. When cracks occur, the bonding reliability of the solder joints 191 and 192 to which the capacitor 400 is bonded decreases. On the other hand, when the volume of the first solder joint 191 and the volume of the second solder joint 192 are larger than the volume of the third solder joint 193, the stress applied to the edges of the electrodes 410 and 420 of the capacitor 400 can be dispersed. Therefore, the possibility of the above-mentioned cracks occurring is reduced, and the bonding reliability is improved.

[0032] More preferably, the volume of the first solder joint 191 and the volume of the second solder joint 192 are 1.2 times or more the volume of the third solder joint 193. Also, it is preferable that the volume of the first solder joint 191 and the volume of the second solder joint 192 are less than 4 times the volume of the third solder joint 193. If the volume of the first solder joint 191 and the volume of the second solder joint 192 are 4 times or more the volume of the third solder joint 193, it may become impossible to arrange the solder joints at a narrow pitch, and there is a possibility that the semiconductor device 100 cannot be made small.

[0033] The capacitor 400 is preferably arranged with a gap from the semiconductor device 100 and the printed wiring board 200, respectively. More specifically, the difference between the first distance between the capacitor 400 and the semiconductor device 100 and the second distance between the capacitor 400 and the printed wiring board 200 is preferably smaller than the first distance and the second distance and close to zero. That is, the capacitor 400 is preferably arranged at the center of the solder joints 191 and 192. When the capacitor 400 is arranged at the center of the solder joints 191 and 192, the stress applied to the edges of the electrodes 410 and 420 of the capacitor 400 can be dispersed. Therefore, the impact on the capacitor 400 can be reduced, and the bonding reliability can be further improved.

[0034] However, as shown in FIG. 3(a), the maximum length R191 in the X direction of the solder joint 191 is longer than the maximum length R193 in the X direction of the solder joint 193. However, if the maximum length in the X direction of the solder joint 191 is too long, there is a possibility of contacting the solder joint 193 and causing a short circuit. Therefore, the maximum length in the X direction of the solder joint 191 is preferably not more than twice the maximum length in the X direction of the solder joint 193.

[0035] The processing module 300 preferably has a first chip component lead 260E and a second chip component lead 260G. The first chip component lead 260E and the second chip component lead 260G serve to guide the capacitor 400 to the solder joints 191 and 192 when manufacturing the processing module 300.

[0036] The first chip component lead path 260E, which is the first component lead path, includes a first conductor pattern 250E and an induction portion 208E of a solder resist that covers the first conductor pattern 250E. The first conductor pattern 250E extends in a first direction intersecting the longitudinal direction of the capacitor 400 from a land 230E disposed on the main surface 221 of the insulating substrate 220. The length in the Y direction is longer than half of the length in the short-side direction of the capacitor 400 and shorter than the shortest distance between the land 230E, which is the third land, and the land 230S, which is the fifth land. The first conductor pattern 250E is not in contact with the land 230G and the land 230S. Also, the first conductor pattern 250E is not directly connected to wiring (not shown).

[0037] The second chip component lead path 260G, which is the second component lead path, includes a second conductor pattern 250G and an induction portion 208G of a solder resist that covers the second conductor pattern 250G. The second conductor pattern 250G extends in a second direction intersecting the longitudinal direction of the capacitor 400 from a land 230G disposed on the main surface 221 of the insulating substrate 220. The length in the Y direction is longer than half of the length in the short-side direction of the capacitor 400 and shorter than the shortest distance between the land 230G, which is the fourth land, and the land 230S, which is the fifth land. The second conductor pattern 250G is not in contact with the land 230E and the land 230S. Also, the second conductor pattern 250G is not directly connected to wiring (not shown).

[0038] The first conductor pattern 250E extends in a direction approaching the second conductor pattern 250G as it extends from the land 230E, but the first conductor pattern 250E and the second conductor pattern 250G may extend in parallel. That is, the first direction and the second direction may be the same direction. The first conductor pattern 250E and the second conductor pattern 250G are formed of a conductive metal material, such as copper or gold. The first conductor pattern 250E and the second conductor pattern 250G are rectangular when viewed in the Z direction, but are not limited thereto. When viewed in the Z direction, they may have any shape, such as a polygonal shape, a circular shape, or an elliptical shape.

[0039] The first chip component guiding path 260E and the second chip component guiding path 260G play a role of guiding the capacitor 400, which is a chip component, to the joining location when joining the capacitor 400 to the first solder joint 191 and the second solder joint 192. Solder paste is placed on the guiding portions 208E and 208G, and the capacitor is placed on the solder paste. When the solder paste is heated and melted, the capacitor 400 is guided to the joining location.

[0040] Each of the first chip component guiding path 260E and the second chip component guiding path 260G is covered by the guiding portions 208E and 208G of the solder resist for the first conductor pattern 250E and the second conductor pattern 250G, respectively. By adopting such a configuration, since there is no step until the capacitor 400 is guided from the first chip component guiding path 260E and the second chip component guiding path 260G to the joining location, it is possible to horizontally move while maintaining the placed posture. As a result, as shown in FIG. 3(c), it becomes easier to join so that the center line connecting the centers of the solder joints 191 and 192 and the longitudinal center line of the capacitor 400 are on the same line.

[0041] Also, it is preferable that the lengths of the first conductor pattern 250E and the second conductor pattern 250G are greater than half of the length of the capacitor 400 in the short side direction. This is because a sufficient amount of solder paste can be placed and it can be stably guided. The first conductor pattern 250E is preferably extended in a direction approaching the second conductor pattern 250G as it extends from the land 230E. By arranging the first conductor pattern 250E and the second conductor pattern 250G in this way, they can be arranged longer. Also, the widths of the first conductor pattern 250E and the second conductor pattern 250G are preferably equal to or greater than the width of the electrodes of the capacitor 400. This is to prevent the capacitor from falling off the guiding path during movement and to move it stably. Note that the width of the electrodes of the capacitor refers to the length in the X direction of the lower surface 415 or the lower surface 425 of the electrodes of the capacitor in FIG. 4.

[0042] When the process of heating and melting the above-described solder paste is performed, flux F1 remains in the induction part 208E. Also, flux F2 remains in the induction part 208G. It is preferable that the fluxes F1 and F2 are provided only in the induction parts 208E and 208G. This is to prevent the phenomenon of ion migration that occurs when the fluxes remaining on the induction path come into contact with each other or with the surrounding fluxes.

[0043] As described above, in the processing module 300, the volumes of the solder joints 191 and 192 that join the capacitors are larger than the volume of the solder joint 193 that joins the semiconductor device and the wiring board. Therefore, it is possible to provide a semiconductor module in which the bonding strength between the solder and the capacitor is sufficient compared to the prior art.

[0044] (Manufacturing Method of Processing Module 1) Next, a method for manufacturing the processing module 300 will be described. FIGS. 5 and 6 are explanatory views of a method for manufacturing the processing module 300 according to the first embodiment. In each step, a side view and a top view are shown.

[0045] First, as shown in FIG. 5(a), a printed wiring board 200 is prepared (step S1). The printed wiring board 200 has lands 230E, 230G, 230S, a first conductor pattern 250E, a second conductor pattern 250G, and a solder resist 208 on the main surface 221. The solder resist 208 has induction parts 208E and 208G and a plurality of openings. The lands 230E, 230G, and 230S are exposed through the openings of the solder resist 208, respectively. In step S1, the semiconductor device 100 and the capacitor 400 are also prepared.

[0046] Next, as shown in FIG. 5(b), a solder paste P1 which is a first solder paste, a solder paste P2 which is a second solder paste, and a solder paste P3 which is a third solder paste are supplied onto the printed wiring board 200 at intervals from each other (step S2). The solder paste P1 is supplied onto the land 230E which is the third land and onto the guiding portion 208E. The solder paste P2 is supplied onto the land 230G which is the fourth land and onto the guiding portion 208G. The solder paste P3 is supplied onto the land 230S which is the fifth land.

[0047] The solder pastes P1, P2 and P3 contain solder powder and a flux component necessary for soldering. In the present disclosure, the solder pastes P1, P2 and P3 are all made of the same material, but may not be made of the same material as long as they have similar melting points. In step S2, the solder pastes P1, P2 and P3 are supplied to the printed wiring board 200 by screen printing using a metal mask 23. Note that the supply method of the solder pastes P1, P2 and P3 is not limited thereto. For example, a dispenser may be used.

[0048] Next, as shown in FIG. 5(c), the capacitor 400 is placed such that the electrode 410 contacts the solder paste P1 on the guiding portion 208E and the electrode 420 contacts the solder paste P2 on the guiding portion 208G. More specifically, in the solder pastes P1, P2 provided on the guiding portions 208E, 208G, the capacitor 400 is placed near the tip in the direction away from the lands 230E, 230G (S3). Thereby, the lower surface 415 of the electrode 410 contacts the solder paste P1, and the lower surface 425 of the electrode 420 contacts the solder paste P2. In step S3, the capacitor 400 is placed on the solder pastes P1, P2 using a mounter (not shown).

[0049] Next, as shown in FIG. 5(d), the semiconductor device 100 is placed on the printed wiring board 200 such that the land 130E faces the land 230E and the land 130G faces the land 230G (S4). In step S4, the semiconductor device 100 is placed on the printed wiring board 200 using a mounter (not shown). At this time, the placement position of the semiconductor device 100 is adjusted so that the land 130E faces the land 230E, the land 130G faces the land 230G, and the land 130S faces the land 230S. Solder balls B1, B2, and B3 are provided on the lands 130E, 130G, and 130S of the semiconductor device 100, respectively. Therefore, the semiconductor device 100 is placed on the printed wiring board 200 such that the solder ball B1 faces the land 230E, the solder ball B2 faces the land 230G, and the solder ball B3 faces the land 230S. In step S4, by placing the semiconductor device 100 on the printed wiring board 200, the solder balls B1, B2, and B3 come into contact with the solder pastes P1, P2, and P3, respectively. In this step S4, the positional relationship among the printed wiring board 200, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in FIG. 5(d). Each of the lands 130E, 130G, and 130S of the semiconductor device 100 partially or entirely overlaps with each of the lands 230E, 230G, and 230S of the printed wiring board 200 when viewed from the Z direction. When the semiconductor device 100 is mounted, the capacitor 400 is placed at a position where it does not contact the solder balls B1 and B2. Note that in the top view of FIG. 5(d), only the solder balls B1, B2, and B3 among the components of the semiconductor module 100 are shown.

[0050] Next, with the semiconductor device 100 and the capacitor 400 placed on the printed wiring board 200, they are conveyed to a reflow furnace (not shown). Then, in step S5 shown in FIG. 6(a), the temperature of the atmosphere in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder powder to heat and melt the solder pastes P1, P2, P3 and the solder balls B1, B2, B3. When the solder paste P1 and the solder ball B1 are melted, a molten solder M1 with fluidity is formed. When the solder paste P2 and the solder ball B2 are melted, a molten solder M2 with fluidity is formed. When the solder paste P3 and the solder ball B3 are melted, a molten solder M3 with fluidity is formed.

[0051] Subsequent to step S5, in step S6 shown in FIG. 6(b), heating is continued to cause the molten solders M1, M2 to flow. The molten solders M1, M2 on the induction portions 208E, 208G aggregate on the lands 230E, 230G. As a result, the capacitor 400 placed on the induction portions 208E, 208G reaches the lands 230E, 230G due to the aggregation of the molten solders M1, M2. Further, when the capacitor 400 reaches the lands 230E and 230G, it is pushed upward in the direction approaching the semiconductor device 100 by the force received from the molten solders M1, M2. As a result, the distance between the upper surface 414 of the electrode 410 and the land 130E is reduced, and the distance between the upper surface 424 of the electrode 420 and the land 130G is reduced. That is, the body 401 of the capacitor 400 is arranged with a gap from the semiconductor device 100 and the printed wiring board 200, respectively. Then, the fluxes F1, F2 contained in the solder pastes P1, P2 remain on the chip component induction paths 260E, 260G, respectively.

[0052] Thereafter, the molten solders M1, M2, and M3 are cooled and solidified. As shown in FIG. 6(c), a solder joint 191, which is the first solder joint joining the lands 130E, 230E and the electrode 410 with solder, is formed. Also, a solder joint 192, which is the second solder joint joining the lands 130G, 230G and the electrode 420 with solder, is formed. Further, a solder joint 193, which is the third solder joint joining the lands 130S and 230S with solder, is formed. At this time, the volumes of the solder joints 191 and 192 are larger than the volume of the solder joint 193. This is because, although the sizes of the solder balls B1, B2, and B3 are constant, the solder paste P1 placed on the guiding portion 208E adheres to the solder ball B1 and the solder paste P2 placed on the guiding portion 208G adheres to the solder ball B2 and solidifies respectively. That is, the volumes of the solder joints 191 and 192 can be controlled by the amounts of the solder pastes P1 and P2 placed on the guiding portions 208E and 208G. As described above, the processing module 300 shown in FIG. 3 is manufactured.

[0053] Thereafter, by housing the processing module 300 in the housing 611 shown in FIG. 1, the camera body 601, that is, the digital camera 600 is manufactured.

[0054] According to the manufacturing method of the present disclosure, a processing module 300 can be manufactured in which the volumes of the solder joints 191 and 192 joining the capacitors are larger than the volume of the solder joint 193 joining the semiconductor device and the wiring board. Therefore, a semiconductor module having sufficient joining strength between the solder and the capacitor can be provided as compared with the prior art.

[0055] (Manufacturing method of processing module 2) Next, a second manufacturing method of the processing module, which is a modification of the above-described manufacturing method, will be described. FIGS. 7 and 8 are explanatory views of the manufacturing method of the processing module 300A. The processing module 300A is different from the processing module 300 in that the printed wiring board 200A does not have the first chip component guiding path 260E and the second chip component guiding path 260G.

[0056] First, as shown in FIG. 7(a), a printed wiring board 200 is prepared (step S11). The printed wiring board 200A has lands 230EA, 230GA, 230SA on the main surface 221A, and a solder resist 208 having a plurality of openings. The lands 230E, 230G, and 230S are each exposed by the openings of the solder resist 208. In step S11, the semiconductor device 100 and the capacitor 400 are also prepared. In advance, solder balls B1, which are ball terminals, are attached to the land 130E, solder balls B2 are attached to the land 130G, and solder balls B3 are attached to the land 130S of the semiconductor device 100. They are attached so that the centers of the respective solder balls coincide with the centers of the lands 230. In the present embodiment, it is preferable that the solder balls B1, B2, and B3 are all the same size and material, but they are not limited to the same size and material as long as they have a melting point close to each other.

[0057] Next, as shown in FIG. 7(b), a solder paste P1, which is a first solder paste, a solder paste P2, which is a second solder paste, and a solder paste P3, which is a third solder paste, are supplied to the printed wiring board 200 at intervals from each other (step S12). The solder paste P1 extends from the land 230E, which is the fourth land, and is also supplied onto the solder resist 208. The solder paste P2 extends from the land 230GA, which is the fifth land, and is also supplied onto the solder resist 208. The solder paste P3 is supplied onto the land 230A, which is the sixth land.

[0058] The solder pastes P1, P2, and P3 contain solder powder and a flux component necessary for soldering. In the present disclosure, the solder pastes P1, P2, and P3 are all made of the same material, but they do not have to be made of the same material as long as they have a melting point close to each other. In step S2, the solder pastes P1, P2, and P3 are supplied to the printed wiring board 200 by screen printing using a metal mask 23. Note that the supply method of the solder pastes P1, P2, and P3 is not limited to this. For example, a dispenser may be used.

[0059] Depending on the amounts of the solder pastes P1 and P2, the volumes of the solder joints 191 and 192 can be controlled.

[0060] Next, as shown in FIG. 7(c), the capacitor 400 is placed (S13) so that the electrode 410 contacts the solder paste P1 and the electrode 420 contacts the solder paste P2. Thereby, the lower surface 415 of the electrode 410 contacts the solder paste P1, and the lower surface 425 of the electrode 420 contacts the solder paste P2. In step S13, the capacitor 400 is placed on the solder pastes P1 and P2 using a mounter (not shown).

[0061] Next, as shown in FIG. 7(d), the semiconductor device 100 is placed on the printed wiring board 200 such that the lands 130S and 230SA, the lands 130E and 230EA, and the lands 130G and 230GA face each other (S14). In step S14, the semiconductor device 100 is placed on the printed wiring board 200 using a mounter (not shown). At this time, the mounting position of the semiconductor device 100 is adjusted such that the lands 130E and 230EA face each other, the lands 130G and 230GA face each other, and the lands 130S and 230SA face each other. Solder balls B1, B2, and B3 are provided on the lands 130E, 130G, and 130S of the semiconductor device 100, respectively. Therefore, the semiconductor device 100 is placed on the printed wiring board 200A such that the solder ball B1 and the land 230EA, the solder ball B2 and the land 230GA, and the solder ball B3 and the land 230SA face each other. By placing the semiconductor device 100 on the printed wiring board 200A in step S14, the solder balls B1, B2, and B3 come into contact with the solder pastes P1, P2, and P3, respectively. In this step S14, the positional relationship among the printed wiring board 200A, the capacitor 400, and the semiconductor device 100 when viewed from the Z direction is as shown in FIG. 7(d). Each of the lands 130E, 130G, and 130S of the semiconductor device 100 partially or entirely overlaps with each of the lands 230EA, 230GA, and 230SA of the printed wiring board 200 when viewed from the Z direction. When the semiconductor device 100 is mounted, the capacitor 400 is placed at a position where it does not contact the solder balls B1 and B2.

[0062] Next, with the semiconductor device 100 and the capacitor 400 placed on the printed wiring board 200A, they are transported to a reflow furnace (not shown). Then, in the process S15 shown in FIG. 8(a), the temperature of the atmosphere in the reflow furnace is adjusted to a temperature equal to or higher than the melting point of the solder powder to heat and melt the solder pastes P1, P2, P3 and the solder balls B1, B2, B3. When the solder paste P1 and the solder ball B1 are melted, they aggregate to form a single fluid molten solder M191. When the solder paste P2 and the solder ball B2 are melted, they aggregate to form a single fluid molten solder M192. When the solder paste P3 and the solder ball B3 are melted, they become a fluid molten solder M193.

[0063] Here, when the wettability of the solder on the lands 230EA and 230G of the printed wiring board 200A is W1 and the wettability of the solder on the solder resist 208 of the printed wiring board 200A is W2, the relationship is W1 > W2. Therefore, the solder paste P1 on the solder resist 208 aggregates toward the solder paste P1 and the solder ball B1 between the land 111E and the 230EA, which have the best solder wettability, and integrates as the molten solder M191. Also, the solder paste P2 on the solder resist 208 aggregates toward the solder paste P2 between the land 111G and the 230E, which have the best solder wettability, and integrates as the molten solder M192.

[0064] Also, when the wettability of the solder on the electrode surfaces 411, 412, 413, 414, 415, and 421, 422, 423, 424, 425 of the capacitor 400 is W3, the relationship is W3 > W2. Therefore, the molten solder paste wets the five surfaces of the electrode surfaces 411, 412, 413, 414, 415, and 421, 422, 423, 424, 425 of the capacitor 400 and is covered with solder. Since the electrodes 410 and 420 of the capacitor 400 are covered with solder, as the solder pastes P1 and P2 flow, the capacitor 400 moves in the Y1 direction of the lands 230EA and 230GA. Then, the electrodes 410 and 420 of the capacitor 400 are incorporated into the molten solders M191 and M192.

[0065] The volumes of the molten solders M191 and M192 are each larger than the volume of the molten solder M193 by the amount of the aggregation of the solder pastes P1 and P2.

[0066] Subsequent to step S15, in step S16 shown in FIG. 8(b), when heating is continued, the molten solders M191, M192, and M193 further flow and become spherical. When the molten solder becomes spherical, the electrodes 410 and 420 of the capacitor 400 are attracted with substantially equal forces in the X1 direction at the solder joint 191 and in the X2 direction at the solder joint 192, respectively. Therefore, the capacitor 400 is self-aligned near the center between the solder joint 191 and the solder joint 192 in the X and Y directions. Also in the Z direction, while being attracted with substantially equal forces in the X1 direction at the solder joint 191 and in the X2 direction at the solder joint 192, the capacitor 400 is attracted with substantially equal forces in the Z1 and Z2 directions at the solder joints 191 and 192, respectively. Therefore, gaps are formed between the capacitor 400 and the semiconductor device 100 and between the capacitor 400 and the printed wiring board 200A, respectively.

[0067] When the solder volume is large and the shape is closer to a perfect sphere, the difference between the first distance between the capacitor 400 and the semiconductor device 100 and the second distance between the capacitor 400 and the printed wiring board 200A becomes smaller than the first distance and the second distance and approaches zero. That is, the capacitor 400 can be disposed at the center of the solder joints 191 and 192.

[0068] Thereafter, the molten solders M191, M192, and M193 are cooled and solidified. As shown in FIG. 8(c), a solder joint 191 is formed by soldering the land 130E, the electrode 410, and the land 230EA, and a solder joint 192 is formed by soldering the land 130G, the electrode 420, and the land 230GA. Also, a solder joint 193 is formed by soldering the land 130S and the land 230SA. Thus, the processing module 300A is manufactured.

[0069] Thereafter, by housing the processing module 300A in the housing 611 shown in FIG. 1, the camera body 601, that is, the digital camera 600 is manufactured.

[0070] According to the manufacturing method of the present disclosure, a processing module 300 can be manufactured in which the volumes of the solder joints 191 and 192 for joining the capacitors are larger than the volume of the solder joint 193 for joining the semiconductor device and the wiring board. Therefore, a semiconductor module with sufficient bonding strength between the solder and the capacitor can be provided as compared with the prior art.

[0071] (Example 1) In the semiconductor device 100 shown in FIG. 8(c), the minimum pitch of the solder balls B, which are two adjacent pre-bonding ball terminals, was 0.4 [mm]. The solder ball B had a diameter of Φ0.25 [mm]. The material of the land 130 was Cu. The material of the solder ball B was Sn-3.0%Ag0.5%Cu. The area of the capacitor 400 as viewed from the Z direction was 0.2 [mm] × 0.1 [mm]. The capacitor 400 was a 0201 chip component.

[0072] The sizes of the lands 130E and 130G in the semiconductor device 100 as viewed from the Z direction were Φ0.22 [mm]. The sizes of the lands 230E and 230G in the printed wiring board 200 as viewed from the Z direction were made the same as those of the lands 130E and 130G, i.e., Φ0.22 [mm]. The pitch of the lands 230 was 0.4 [mm].

[0073] In the process S12 shown in FIG. 7(b), the solder pastes P1 and P2 each had a width of 0.22 [mm] and extended from the solder paste on the lands 230E and 230G to a length of 0.25 [mm]. The thickness of the metal mask 23 was made 0.08 [mm] based on the minimum pitch of the solder balls B, which are two adjacent pre-bonding ball terminals in the semiconductor device 100, and the size of the capacitor 400.

[0074] The solder pastes P1, P2, and P3 used materials containing solder powder of Sn-3.0%Ag0.5%Cu and flux components.

[0075] In steps S15 and S16 shown in FIGS. 8(a) and 6(b), the peak temperature of the atmosphere in the reflow furnace was set to 230° C. or higher to melt the solder balls B1, B2, B3 and the solder pastes P1, P2, P3. Thereafter, the molten solders M191, M192, M193 were cooled and solidified. It was confirmed that the capacitor 400 was joined to the semiconductor device 100 by spherical solder joints 191, 192.

[0076] In the fabricated processing module, the volumes of the solder joints 191 and 192 were 1.2 times the solder volume of the joint 193. The maximum widths of the solder joints 191 and 192 were 7% larger than the maximum width of the joint 193. Also, voids were formed between the capacitor 400 and the semiconductor device 100, and between the capacitor 400 and the printed wiring board 200. Further, flux marks were confirmed on the solder resist 208 at the screen-printed locations of the solder pastes P1 and P2.

[0077] Note that the present invention is not limited to the embodiments described above, and many modifications are possible within the technical idea of the present invention. Also, the effects described in the embodiments are merely an enumeration of the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

[0078] In the above-described embodiment, the case where the electronic component is the capacitor 400 has been described, but the present invention is not limited thereto. The electronic component may be a passive component such as a resistor or an inductor.

[0079] In the above-described embodiment, the preparation of the semiconductor device 100 in which the solder ball B3 is provided on the land 230S in advance has been described, but the present invention is not limited thereto. That is, in the step of preparing the semiconductor device 100, the solder ball B3 may be provided on the land 230S.

Explanation of Reference Numerals

[0080] 100 Semiconductor device 101 Semiconductor element 102 Package substrate 106 Encapsulating resin 108 Solder resist 120 Insulating substrate 121 Main surface 122 Main surface 130E Land (first land) 130G Land (second land) 130S Land (third land) 191 / 191A Solder joint (first solder) 192 / 192A Solder joint (second solder) 193 / 193A Solder joint (third solder) 200 / 200A Printed wiring board 208 / 208A Solder resist 208E Inductive part 208G Inductive part 220 / 220A Insulating substrate 221 / 221A Main surface 222 / 222A Main surface 230E / 230EA Land (the 4 land) 230G / 230GA Land (the 5 land) 230S / 230SA Land (sixth land) 250E First conductor pattern 250G Second conductor pattern 260E First chip component lead 260G Second chip component lead 300 / 300A Processing module (semiconductor module) 400 Capacitor (chip component) 410 Electrode (first electrode) 420 Electrode (second electrode) 600 Digital camera (electronic device) 611 Housing F1 / F2 Flux

Claims

1. A semiconductor device having a first land, a second land, and a third land; A wiring board having a substrate, a fourth land disposed on a main surface of the substrate, a fifth land, and a sixth land; A chip component having a first electrode and a second electrode disposed at intervals in a longitudinal direction and disposed between the wiring board and the semiconductor device; A first solder that joins the first land, the fourth land, and the first electrode; A second solder that joins the second land, the fifth land, and the second electrode; A third solder that joins the third land and the sixth land; And having The volume of the first solder and the volume of the second solder are larger than the volume of the third solder, A semiconductor module, wherein the volume of the first solder and the volume of the second solder are 1.2 times or more the volume of the third solder.

2. The semiconductor module according to claim 1, wherein the volume of the first solder and the volume of the second solder are less than 4 times the volume of the third solder.

3. The semiconductor module according to claim 1 or 2, wherein the area of the largest land among the fourth land, the fifth land, and the sixth land is 1.1 times or less the area of the land with the smallest area.

4. The semiconductor module according to any one of claims 1 to 3, wherein the chip component is disposed with a gap between the semiconductor device and the wiring board, respectively.

5. The semiconductor module according to claim 4, wherein the difference between the first distance between the chip component and the semiconductor device and the second distance between the chip component and the wiring board is smaller than the first distance and the second distance.

6. The first solder and the third solder are adjacent to each other in a first direction, The semiconductor module according to any one of claims 1 to 5, wherein the length of the first solder in the first direction is longer than the length of the third solder in the first direction.

7. The wiring board is a printed wiring board, A solder resist having a plurality of openings and a plurality of guiding portions is provided on the main surface of the substrate, The fourth land, the fifth land, and the sixth land are exposed by the openings, A first conductor pattern disposed on the main surface of the substrate and extending in a first direction intersecting the longitudinal direction of the chip component from the fourth land A second conductor pattern disposed on the main surface of the substrate and extending in a second direction intersecting the longitudinal direction of the chip component from the fifth land. The semiconductor module according to any one of claims 1 to 6, wherein each of the first conductor pattern and the second conductor pattern is covered by the guiding portion of the solder resist, and a component guiding path for guiding the chip component to the first solder and the second solder is formed.

8. The length of the first conductor pattern in the first direction is longer than half of the length of the chip component in the short-side direction. The semiconductor module according to claim 7, wherein the length of the second conductor pattern in the second direction is longer than half of the length of the chip component in the short-side direction.

9. The length of the first conductor pattern in the first direction is shorter than the shortest distance between the fourth land and the sixth land. The semiconductor module according to claim 8, wherein the length of the second conductor pattern in the second direction is shorter than the shortest distance between the fifth land and the sixth land.

10. The semiconductor module according to any one of claims 7 to 9, wherein a flux is disposed on the guiding portion of the solder resist.

11. The semiconductor module according to claim 10, wherein the flux is disposed only on the guiding portion on the solder resist.

12. The semiconductor module according to any one of claims 7 to 11, wherein the first conductor pattern and the second conductor pattern are not connected to a wiring.

13. The width of the first conductor pattern is equal to or greater than the length of the first electrode of the chip component in the longitudinal direction. The semiconductor module according to any one of claims 7 to 12, wherein the width of the second conductor pattern is equal to or greater than the length of the second electrode of the chip component in the longitudinal direction.

14. The semiconductor module according to any one of claims 7 to 13, wherein the first conductor pattern extends in a direction approaching the second conductor pattern as it extends from the fourth land.

15. The semiconductor module according to any one of claims 1 to 14, wherein the first land is a power terminal and the second land is a ground terminal.

16. The semiconductor module according to any one of claims 1 to 15, wherein the chip component is a chip component having a size of 0402 or less.

17. The semiconductor module according to any one of claims 1 to 16, wherein the chip component is a capacitor.

18. The semiconductor module according to any one of claims 1 to 17, wherein the semiconductor device is a semiconductor package of BGA in which the interval between each land is 0.4 mm or less.

19. A housing, An electronic device comprising: the semiconductor module according to any one of claims 1 to 18, disposed inside the housing.

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