Semiconductor module

Abstract

To provide a semiconductor module capable of appropriately detecting an overcurrent state due to a load short-circuit and the like.SOLUTION: There is provided a semiconductor module comprising: a first switching element which is connected to a first line applied with a power voltage; a terminal which is connected to the first switching element and generates a first voltage according to a first current flowing through the first switching element; a second switching element which is connected to the first line and through which a second current according to the first current flows; a voltage generation circuit which applies a second voltage lowered by a prescribed voltage from the power voltage to a second line; a resistor which is connected between the second switching element and the terminal and generates a third voltage according to the second current; a reference voltage current which is connected to the terminal and generates a prescribed fourth voltage; and a comparison circuit which is connected between the first line and the second line and determines whether or not the first switching element is in an overcurrent state on the basis of comparison between the third voltage and the fourth voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor module.

Background Art

[0002] An intelligent power switch (IPS) having an overcurrent detection function is known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an IPS, generally, a comparison circuit is provided to detect whether a switching element is in an overcurrent state. By the way, for example, when the switching element is in an overcurrent state due to a short circuit of a load or the like, the voltage input to the comparison circuit may go out of the common-phase input range, and the comparison circuit may not be able to detect the overcurrent state.

[0005] The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor module capable of appropriately detecting an overcurrent state due to a short circuit of a load or the like.

Means for Solving the Problems

[0006] To solve the above problems, in the present invention, a first switching element connected to a first line to which a power supply voltage is applied, a terminal that is connected to the first switching element and generates a first voltage corresponding to a first current flowing through the first switching element when the first switching element is on, a second switching element that is connected to the first line and through which a second current corresponding to the first current flows, a voltage generation circuit that applies a second voltage obtained by reducing the power supply voltage by a predetermined voltage to a second line, a resistor that is connected between the second switching element and the terminal and generates a third voltage corresponding to the second current, a reference voltage circuit that is connected to the terminal and generates a predetermined fourth voltage, and a comparison circuit that is connected between the first line and the second line and determines whether the first switching element is in an overcurrent state based on a comparison between the third voltage and the fourth voltage are provided, and a semiconductor module is provided.

Advantages of the Invention

[0007] It is possible to provide a semiconductor module that can appropriately detect an overcurrent state due to a short circuit or the like of a load.

[0008] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9A

Figure 9B

Embodiments for Carrying Out the Invention

[0010] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0011] In this specification, the term "connection" is used, and unless otherwise specified, "connection" means "electrically connected". In this specification, for a voltage or a signal, when the logic level is at the low (Lo) level, it is referred to as the Lo level, and when the logic level is at the high (Hi) level, it is referred to as the Hi level.

[0012] In this specification, one side in the direction parallel to the depth direction of the semiconductor module is referred to as the "front", and the other side is referred to as the "back". Here, directions such as "front" or "back" are not limited to the direction of gravity or the direction of attachment of each member to the substrate or the like when the semiconductor module is mounted.

[0013] In this specification, the ground potential is the reference potential formed by the entire system including the semiconductor module and is 0V.

[0014] ===Example 1=== <<Overview of Semiconductor Module 10>> FIG. 1 shows an outline of the configuration of the semiconductor module 10. The semiconductor module 10 is an IPS that drives a load 12 based on a signal Sin from a microcomputer 11 by a power supply 13 that supplies a power supply voltage Vdd. The semiconductor module 10 is provided on the side closer to the power supply 13, that is, the high side, with respect to the load 12.

[0015] The microcomputer 11 is connected to the terminal SIN of the semiconductor module 10 and inputs a signal S1. As an example, the microcomputer 11 is a device included in an electric control unit (ECU) of an automobile.

[0016] The load 12 is, as an example, a solenoid valve used in a transmission system of an automobile with an automatic transmission. The solenoid valve includes a solenoid that constitutes an electromagnet and a valve (not shown). When the solenoid is conductive, the valve closes, and when the solenoid becomes non-conductive, the valve opens. Here, the load 12 includes an inductor 51 and a resistor 52.

[0017] The inductor 51 is, as an example, the solenoid in the solenoid valve. The resistor 52 adjusts the voltage applied to the inductor 51. The resistor 52 is provided between the inductor 51 and the ground.

[0018] The power supply 13 applies the power supply voltage Vdd to the terminal VDD. The terminal VDD is connected to the line L1, and the power supply voltage Vdd is applied to the line L1. As an example, the power supply 13 is an automobile battery.

[0019] <<Configuration Example of Semiconductor Module 10>> Here, the semiconductor module 10 includes a voltage generation circuit 21, a drive circuit 22, switching elements 23 and 24, a resistor 25, a reference voltage circuit 26, and a comparison circuit 27.

[0020] <<Regarding the voltage generation circuit 21>> The voltage generation circuit 21 generates a voltage Vgnd which is the voltage on the ground side of a control circuit 41 etc. to be described later, and applies the voltage Vgnd to line L2. The voltage Vgnd is a voltage that has decreased by a predetermined voltage (for example, 5V) with respect to the power supply voltage Vdd. The voltage generation circuit 21 is provided between line L1 to which the power supply voltage Vdd is applied and a terminal VG that is grounded.

[0021] <<Overview of the drive circuit 22>> The drive circuit 22 turns on and off the switching element 23 according to a signal S1 input from a microcomputer. Specifically, the drive circuit 22 turns on the switching element 23 connected to line L3 by applying a voltage Vdrv to line L3. On the other hand, the drive circuit 22 turns off the switching element 23 by turning on a cutoff element 33.

[0022] In particular, as will be described later, when the comparison circuit 27 determines that the switching element 23 is in an overcurrent state, the drive circuit 22 performs an operation to protect the switching element 23. When the comparison circuit 27 of the present embodiment determines that the switching element 23 is in an overcurrent state, the drive circuit 22 turns off the switching element 23.

[0023] <<Details of the drive circuit 22>> Here, the drive circuit 22 includes a control signal output circuit 31, a boost circuit 32, and a cutoff element 33.

[0024] ==Control signal output circuit 31== The control signal output circuit 31 outputs a signal S2, which is a control signal, to the boost circuit 32 based on the signal S1 from the microcomputer 11 and the voltage Vcmp from the comparison circuit 27. The control signal output circuit 31 of the present embodiment includes a control circuit 41 and a filter circuit 42.

[0025] ===Control Circuit 41=== Based on the signal S1 input from the microcomputer 11 via the terminal SIN and the voltage Vflt input from the filter circuit 42, the control circuit 41 outputs a signal S2.

[0026] In the present embodiment, when the voltage Vflt input from the filter circuit 42 is at the Hi level and the signal S1 is at the Lo level, the control circuit 41 outputs a signal S2 at the Hi level. On the other hand, when the voltage Vflt input from the filter circuit 42 is at the Hi level and the signal S1 is at the Hi level, the control circuit 41 outputs a signal S2 at the Lo level.

[0027] Also, when the voltage Vflt input from the filter circuit is at the Lo level, the control circuit 41 of the present embodiment outputs a signal S2 at the Hi level.

[0028] ===Filter Circuit 42=== The filter circuit 42 sets a mask for the operation of the control circuit 41 during a predetermined period Tflt (for example, 10 μs) when the switching element 23 is on. Here, the "predetermined period Tflt when the switching element 23 is on" refers to the period from when the signal S1 for turning on the switching element 23 is input to the filter circuit 42 until the period Tflt elapses.

[0029] Specifically, before the period Tflt, the filter circuit 42 outputs a Hi-level voltage Vflt to the control circuit 41 in response to the input Lo-level signal S1. Also, during the period Tflt, regardless of the comparison result of the comparison circuit 27 described later, the filter circuit 42 outputs a Hi-level voltage Vflt to the control circuit 41. In this case, the control circuit 41 outputs the signal S2 according to the signal S1. On the other hand, after the elapse of the period Tflt, the control circuit 41 outputs the signal S2 based on the signal S1 and the comparison result of the comparison circuit 27 described later.

[0030] Incidentally, although details will be described later, the comparison circuit 27 may instantaneously indicate a logical level indicating an overcurrent state of the switching element 23 during the period (e.g., several microseconds) from when the signal S1 is input to the control circuit 41 until each circuit in the semiconductor module 10 stabilizes. The filter circuit 42 can stably drive the circuit by setting a mask on the comparison result of the comparison circuit 27.

[0031] Also, the filter circuit 42 of the present embodiment is connected to the terminal SIN. Thereby, the signal S1 is input to the filter circuit 42, and the filter circuit 42 can detect the timing when the control circuit 41 enters the operation of turning on the switching element 23.

[0032] ==Boost circuit 32== When the switching element 23 is turned on and the signal S2 input from the control circuit 41 is at the Lo level, the boost circuit 32 boosts the input power supply voltage Vdd to generate the drive voltage Vdrv. Further, the boost circuit 32 applies the drive voltage Vdrv to the control electrode of the switching element 23. The switching element 23 is turned on by the drive voltage Vdrv.

[0033] On the other hand, when the signal S2 is at the Hi level, the boost circuit 32 stops generating the drive voltage Vdrv. The boost circuit 32 is, as an example, a charge pump circuit.

[0034] ==Cut-off element 33== The cut-off element 33 turns off the switching element 23 in response to the signal S2 from the control circuit 41. The cut-off element 33 of the present embodiment is a MOS transistor. However, the cut-off element 33 may be another switching element.

[0035] In this embodiment, first, the control circuit 41 to which a Lo-level signal S1 for turning off the switching element 23 is input from the microcomputer 11 outputs a Hi-level signal S2. In response to the Hi-level signal S2, the boost circuit 32 stops generating the drive voltage Vdrv, and the cutoff element 33 turns on. As a result, the cutoff element 33 reduces the voltage applied to the control electrode of the switching element 23 via the line L3, turning off the switching element 23.

[0036] On the other hand, the control circuit 41 to which a Hi-level signal S1 for turning on the switching element 23 is input from the microcomputer 11 outputs a Lo-level signal S2. In response to the Lo-level signal S2, the boost circuit 32 starts generating the drive voltage Vdrv, and the cutoff element 33 turns off. As a result, the cutoff element 33 stops stepping down the line L3, the voltage applied to the control electrode of the switching element 23 increases, and the switching element 23 turns on.

[0037] <<Details of the switching element 23>> The switching element 23 switches the voltage applied from the power supply 13 to the load 12. The switching element 23 is, for example, a high-breakdown-voltage switching element.

[0038] The switching element 23 of this embodiment is an N-type MOS transistor (VMOS transistor) having a vertical trench structure in which a drain electrode is formed on the back surface of the substrate and a source electrode is formed on the front surface. The switching element 23 of this embodiment is a power semiconductor element having a breakdown voltage of several tens of V (for example, having an on-resistance of 100 mΩ).

[0039] However, the switching element 23 is not limited to a VMOS transistor, may be a planar-type MOS transistor, or may be a bipolar element such as an IGBT (Insulated Gate Bipolar Transistor).

[0040] The control electrode of the switching element 23 is connected to the line L3. As an example, when the switching element 23 is a MOS transistor or an IGBT, the control electrode becomes the gate electrode, and when the switching element 23 is a bipolar transistor, the control electrode becomes the base terminal.

[0041] The drain electrode of the switching element 23 is connected to the line L1, and the source electrode is connected to the terminal VO. When the switching element 23 is an IGBT or a bipolar transistor, the collector electrode and the emitter electrode correspond to the drain electrode and the source electrode, respectively.

[0042] The terminal VO is the terminal to which the load 12 is connected and across which the voltage Vout applied to the load 12 is generated. The voltage Vout generated at the terminal VO is a voltage corresponding to the on-resistance of the switching element 23 and the current Ids flowing through the switching element 23 when the switching element 23 is on.

[0043] <<Regarding the switching element 24>> The switching element 24 is an element through which a current Isns corresponding to the current Ids flowing through the switching element 23 flows. The switching element 24 has a similar structure to the switching element 23. As an example, the switching element 24 is provided by a power semiconductor element having lower conductivity than the switching element 23 (for example, 0.25% of the current Isns flows with respect to the current Ids).

[0044] For example, when the switching element 23 is a MOS transistor, the switching element 24 becomes a sense MOS transistor, and when the switching element 24 is an IGBT, it becomes a sense IGBT.

[0045] The gate electrode of the switching element 24 is connected in parallel with the gate electrode of the switching element 23 with respect to the line L3. The drain-source electrodes of the switching element 24 are connected to the line L1 and the resistor 25, respectively.

[0046] <<Regarding Resistance 25>> Resistance 25 is a resistor (e.g., 20 Ω) for detecting the overcurrent state of switching element 23. A voltage Vsns corresponding to current Isns is generated across resistance 25. Resistance 25 is connected between switching element 24 and terminal VO.

[0047] <<Regarding Reference Voltage Circuit 26>> Reference voltage circuit 26 generates a predetermined reference voltage Vref that serves as a reference for comparator circuit 27 to detect overcurrent, and applies it to line Inp connected to the non-inverting input terminal of comparator circuit 27. The reference voltage circuit 26 of the present embodiment is connected to line L3 to which the voltage Vdrv boosted by boost circuit 32 is applied and line L4 connected to terminal VO.

[0048] The reference voltage Vref is set as a voltage with a constant potential difference (e.g., 100 mV) with respect to the voltage VO generated at terminal VO. For example, when resistance 25 is 20 Ω and the current Ids flowing through switching element 23 is 2 A and overcurrent detection is performed, and in this case the current Isns is 5 mA, the reference voltage Vref = 20×0.005 (V) = 100 (mV) is set.

[0049] <<Regarding Comparator Circuit 27>> Comparator circuit 27 compares the voltage Vsns generated across resistance 25 with the reference voltage Vref generated by reference voltage circuit 26, and determines whether switching element 23 is in an overcurrent state. Comparator circuit 27 outputs a voltage Vcmp with different logic levels according to the determination result.

[0050] In the present embodiment, voltage Vcmp is input to filter circuit 42. In the present embodiment, according to voltage Vcmp, filter circuit 42 supplies voltage Vflt to control circuit 41.

[0051] Specifically, the voltage Vflt becomes a logic level indicating that the switching element 23 is not in an overcurrent state regardless of the voltage Vcmp in the period before the period Tflt elapses after the signal S1 indicates the Hi level, and becomes a logic level equal to the voltage Vcmp input from the comparison circuit 27 after the elapse of the period Tflt.

[0052] In the present embodiment, since the comparison circuit 27 is connected to the control circuit 41 via the filter circuit 42, when the control circuit 41 operates based on the voltage Vflt, without connecting the comparison circuit 27 to the control circuit 41, the control circuit 41 can operate indirectly based on the voltage Vcmp as well.

[0053] A reference voltage Vref is applied to the line Inp connected to the non-inverting input terminal of the comparison circuit 27, and a voltage Vsns is applied to the line Inm connected to the inverting input terminal of the comparison circuit 27. In the period before the switching elements 23 and 24 are turned on and during which the signal S1 indicates the Lo level, the voltages applied to the lines Inp and Inm are both low. In this case, the comparison circuit 27 of the present embodiment outputs a Lo-level voltage Vcmp to the filter circuit 42. Further, the comparison circuit 27 is connected to the lines L1 and L2, and thereby the voltage difference between the power supply voltage Vdd and the voltage Vgnd is used as a bias voltage.

[0054] =====Form with Changed Connection Relationship of Comparison Circuit 27===== In another embodiment of the semiconductor module 10, the comparison circuit 27 is connected to the control circuit 41 without passing through the filter circuit 42. In particular, in an embodiment where the control circuit 41 is connected to the filter circuit 42 separately from the comparison circuit 27, the control circuit 41 preferentially applies the Hi-level voltage Vflt output from the filter circuit 42 over the voltage Vcmp output by the comparison circuit 27, and when the voltage flt is at the Hi level, outputs the signal S2 based on the signal S1 regardless of the logic level of the voltage Vcmp.

[0055] In the semiconductor module 10, line L1 corresponds to the "first line". Also, the switching element 23 corresponds to the "first switching element". The current Ids flowing through the switching element 23 corresponds to the "first current", and the voltage Vout corresponds to the "first voltage".

[0056] The switching element 24 corresponds to the "second switching element", and the current Isns corresponds to the "second current".

[0057] The voltage Vgnd corresponds to the "second voltage", and line L2 corresponds to the "second line".

[0058] The signal S1 corresponds to the "input signal". The voltage Vsns corresponds to the "third voltage", and the reference voltage Vref corresponds to the "fourth voltage".

[0059] <<Configuration of the reference voltage circuit 26>> FIG. 2 shows an example of the configuration of the reference voltage circuit 26. The reference voltage circuit 26 includes a depletion-type MOS transistor 61, a MOS transistor 62, and resistors 63 and 64.

[0060] The gate electrode and the source electrode of the depletion-type MOS transistor 61 are connected, and the gate electrode and the drain electrode of the MOS transistor 62 are connected. Also, the depletion-type MOS transistor 61 and the MOS transistor 62 are N-type MOS transistors.

[0061] The depletion-type MOS transistor 61 is a high-voltage withstand MOS transistor. Therefore, the depletion-type MOS transistor 61 can operate stably even when the voltage Vdrv output from the boost circuit 32 fluctuates. The drain electrode of the depletion-type MOS transistor 61 is connected to the line L3 to which the voltage Vdrv is applied by the boost circuit 32.

[0062] A MOS transistor 62 and a resistor 63 are connected to the source electrode of the depletion-type MOS transistor 61. The current supplied from the depletion-type MOS transistor 61 depends on the threshold voltage of the MOS transistor 62. Therefore, a predetermined bias voltage depending on the threshold voltage of the MOS transistor 62 is supplied to the resistors 63 and 64.

[0063] The MOS transistor 62 functions as a bias voltage source for generating a bias voltage. The MOS transistor 62 is provided between the depletion-type MOS transistor 61 and the line L4 to which the voltage Vout is applied.

[0064] The resistor 63, together with the resistor 64, divides the bias voltage supplied from the depletion-type MOS transistor 61 to supply a reference voltage Vref which serves as a reference voltage for detecting an overcurrent. One end of the resistor 63 is connected to the drain electrode of the MOS transistor 62. The resistor 64 is connected to the other end of the resistor 63, and the voltage generated between the resistor 64 and the line L4 is supplied as the reference voltage Vref.

[0065] The resistor 64 is provided between the resistor 63 and the line L4. One end of the resistor 64 is connected to the resistor 63, and the other end is connected to the line L4.

[0066] <<Configuration of the comparison circuit 27>> FIG. 3A shows an example of the configuration of the comparison circuit 27. The comparison circuit 27 includes a depletion-type MOS transistor 71 and MOS transistors 72 to 79. The MOS transistors 76, 77, 78 are P-type MOS transistors, and the MOS transistors 72 to 75, 79 are N-type MOS transistors. Also, the depletion-type MOS transistor 71 is N-type.

[0067] The depletion-type MOS transistor 71 and the MOS transistor 72 constitute a bias current source when operating the MOS transistors 73, 79.

[0068] The gate electrode of MOS transistor 72 is connected to the drain electrode of MOS transistor 72. Further, the gate electrodes of MOS transistor 73 and MOS transistor 79 are connected in parallel to the gate electrode of MOS transistor 72. Therefore, MOS transistors 72, 73, and 79 form a current mirror circuit.

[0069] Since MOS transistor 73 forms a current mirror circuit with MOS transistor 72, MOS transistor 73 functions as a current source that conducts a drain-source current corresponding to the bias current formed by depletion-type MOS transistor 71 and MOS transistor 72.

[0070] MOS transistors 74 and 75 form a differential pair with the drain-source current of MOS transistor 73 as the tail current.

[0071] Since each of MOS transistors 74 and 75 is an N-type transistor, comparison circuit 27 operates accurately when the voltages input to lines Inp and Inm are close to voltage Vdd. On the other hand, when the voltages input to lines Inp and Inm are less than the threshold voltages of MOS transistors 74 and 75, comparison circuit 27 may stop operating.

[0072] MOS transistors 76 and 77 form a current mirror circuit. Thereby, the current flowing from MOS transistors 76 and 77 to MOS transistors 74 and 75 is adjusted.

[0073] Since the currents flowing through MOS transistors 74 and 75 differ according to the voltage applied to the differential pair, the voltage applied to MOS transistor 78 changes.

[0074] MOS transistors 78 and 79 form the output stage of comparison circuit 27. Since MOS transistor 79 forms a current mirror circuit with MOS transistors 72 and 73, the current flowing through MOS transistor 79 is equal to that of MOS transistors 72 and 73.

[0075] The voltage applied to the gate electrode of the MOS transistor 78 changes according to the voltage applied to the gate electrodes of the differential pair. As a result, the voltage Vcmp changes and the comparison circuit 27 functions.

[0076] <<Input voltage to the comparison circuit 27>> FIG. 3B shows an example of the variation range of the input voltage to the comparison circuit 27 and the in-phase input range.

[0077] Since the MOS transistors 74 and 75 constituting the differential pair connected to the input lines Inp and Inm of the comparison circuit 27 are N-type MOS transistors, the comparison circuit 27 does not operate as a comparison circuit when the input voltage becomes equal to or lower than a predetermined voltage V1.

[0078] The resistor 25 in FIG. 1 is connected to the terminal VO, and the reference voltage circuit 26 is provided between the line L3 and the line L4. That is, both the resistor 25 and the reference voltage circuit 26 are connected to the terminal VO.

[0079] Therefore, when the voltage Vout generated at the terminal VO becomes lower than the voltage Vgnd, both the voltage Vsns and the reference voltage Vref become lower. In this case, the voltages input to the comparison circuit 27 through the lines Inp and Inm both become small.

[0080] In the range where the voltage V1 < voltage Vout < power supply voltage Vdd, the comparison circuit 27 has an in-phase input range. In this case, the comparison circuit 27 can output a voltage Vcmp having a logic level corresponding to the voltage applied to the lines Inp and Inm. On the other hand, when the voltage Vout < voltage V1, it becomes a non-in-phase input range, and the comparison circuit 27 may stop operating.

[0081] As cases where the load 12 is in an overcurrent state, (i) an overcurrent flows through the load 12, and (ii) a path parallel to the load 12 may short-circuit between the terminal VO and the ground due to a circuit defect, dirt, etc., and an overcurrent may flow in the grounding direction through a path different from the load 12.

[0082] (i) In this case, there is no decrease in the voltage Vout applied to the terminal VO, and the comparison circuit 27 operates within the common-mode input range. Therefore, when it is detected that the voltage Vsns exceeds the reference voltage Vref, a voltage Vcmp at a logic level indicating an overcurrent state is output. As a result, the drive circuit 22 can perform operations such as shutting off the switching element 23, and the circuit is appropriately protected from overcurrent.

[0083] On the other hand, in case (ii), the voltage Vout may become less than the voltage V1, and the comparison circuit 27 may stop operating. In the comparison circuit of the present embodiment, since it is connected to output a voltage Vcmp at a logic level as described later with reference to FIG. 6B and the like, even in such a case, it is possible to determine that the switching element 23 is in an overcurrent state.

[0084] Also, the comparison circuit 27 of the present embodiment does not include a differential pair using P-type MOS transistors. That is, in the semiconductor module 10, even in case (ii), it is possible to determine overcurrent without using an element with a large circuit area such as a rail-to-rail input type comparator. Therefore, the semiconductor module 10 of the present embodiment also contributes to reducing the circuit area.

[0085] In this way, in the semiconductor module 10, by inputting the voltage Vsns and the voltage Vref to the comparison circuit 27, even without inputting the voltage Vout to the comparison circuit 27, the circuit can be protected from the overcurrent state of the switching element 23 when the voltage Vout drops below the voltage Vgnd.

[0086] <<Timing diagram during normal operation>> FIG. 4 shows an example of a schematic of the time variation of the voltage and signals within the semiconductor module 10 during normal operation. In this specification, the "normal operation" of the semiconductor module 10 refers to the case where the switching element 23 is not in an overcurrent state and the semiconductor module 10 operates within the range of the voltage Vout and the voltage Vgnd.

[0087] In the figure, a schematic of the voltage and signal is shown, where Lo represents the case when the logic level is at the low (Lo) level, and Hi represents the case when the logic level is at the high (Hi) level.

[0088] At time t1, in order to drive the switching element 23, the microcomputer 11 raises the signal S1 input to the terminal SIN from the Lo level to the Hi level. Also, in order to continue driving the switching element 23, the microcomputer 11 maintains the signal S1, which has risen to the Hi level, at the Hi level.

[0089] When the switching element 23 turns on, the switching element 24 also turns on. As a result, the drain-source current Isns of the switching element 24 increases. As the drain-source current Isns of the switching element 24 increases, the voltage Vsns generated across the resistor 25 also rises.

[0090] Furthermore, at time t3, the voltage Vsns shows a steady value. In this embodiment, since the semiconductor module 10 operates normally, the voltage Vsns does not reach the reference voltage Vref at which the switching element 23 enters an overcurrent state.

[0091] The voltage Vsns is input to the line Inm of the comparison circuit 27, and the voltage Vref is input from the reference voltage circuit 26 to the line Inp. In this embodiment, after the switching element 23 turns on and the semiconductor module 10 is operating normally, the comparison circuit 27 outputs a high-level voltage Vcmp.

[0092] Note that since the comparison circuit 27 is provided between the lines L1 and L2, the fact that the voltage Vcmp output from the comparison circuit 27 is at the high level means that the voltage Vcmp is at the power supply voltage Vdd. On the other hand, the fact that the voltage Vcmp is at the low level means that the voltage Vcmp is at the voltage Vgnd.

[0093] Also, regarding the voltage Vcmp, the low-level voltage Vcmp corresponds to "the fifth voltage of the first logic level", and the high-level voltage Vcmp corresponds to "the fifth voltage of the second logic level".

[0094] In the filter circuit 42 of the present embodiment, the signal S1 is input by being connected to the terminal SIN. Further, the voltage Vcmp is input to the filter circuit 42.

[0095] In the period before the time t1, the voltage in the line Inm input from the reference voltage circuit 26 to the comparison circuit 27 becomes a low value. Also, in this period, since the switching element 24 is not turned on either, the voltage generated across the resistor 25 also becomes a low value, and the voltage Vsns input to the line Inp of the comparison circuit 27 also becomes a low value. In this case, the comparison circuit 27 of the present embodiment outputs a Lo-level voltage Vcmp.

[0096] On the other hand, in the period after the time t1, the voltage Vref is applied from the reference voltage circuit 26 to the line Inp of the comparison circuit 27. Since the semiconductor module 10 of the present embodiment performs normal operation and the voltage Vout generated at the terminal does not reach the voltage Vref, in the period after the time t1, the comparison circuit 27 outputs a Hi-level voltage Vcmp.

[0097] At the time t1, in response to the signal S1 switching from the Lo level to the Hi level, between the time t1 and the time t2 after the elapse of the period Tflt from the time t1, the filter circuit 42 sets a mask for the voltage Vcmp output from the comparison circuit 27.

[0098] Specifically, between the time t1 and the time t2, the filter circuit 42 outputs a Hi-level voltage Vflt to the control circuit 41 regardless of the logic level of the voltage Vcmp. Thereby, between the time t1 and the time t2, the logic level of the voltage Vcmp is masked for the control circuit 41. In the period after the time t2, the filter circuit 42 outputs a voltage flt having the same logic level as the voltage Vcmp. Also, the filter circuit 42 outputs a Hi-level voltage Vflt in response to the Lo-level signal S1 in the period before the time t1.

[0099] Note that the overcurrent detection of the semiconductor module 10 is performed using the voltage Vsns corresponding to the current Isns flowing through the switching element 24 that rises earlier than the switching element 23. Therefore, the period Tflt is set to a short time (for example, 10 μs).

[0100] A signal S1 is input to the control circuit 41 from the microcomputer 11 via the terminal SIN. In the period before the time t1, a signal S1 of Lo level is input to the control circuit 41 to turn off the switching element 23. In response to the signal S1 of Lo level, the control circuit 41 outputs a signal S2 of Hi level. While the signal S2 is at Hi level, the boost circuit 32 does not boost the power supply voltage Vdd, and the cutoff element 33 is in the on state.

[0101] At the time t1, when the signal S1 input to the control circuit 41 to turn on the switching element 23 becomes Hi level, the control circuit 41 outputs a signal S2 that has dropped from Hi level to Lo level. When the signal S2 becomes Lo level, the boost circuit 32 boosts the power supply voltage Vdd and starts generating the drive voltage Vdrv, which is applied to the switching element 23. Further, the cutoff element 33 becomes the off state.

[0102] In this embodiment, the semiconductor module 10 performs normal operation, and an overcurrent state is not detected. Therefore, in the period after the time t1, the control circuit 41 continues to output a signal S2 of Lo level to maintain the on state of the switching element 23.

[0103] <<Timing diagram at the time of overcurrent detection>> FIG. 5 shows an example of a schematic of the time change of the voltage and signals in the semiconductor module 10 at the time of overcurrent detection.

[0104] At the time t4, as in the normal operation, the microcomputer 11 raises the signal S1 from Lo level to Hi level to drive the switching element 23. Also, to continue driving the switching element 23, the microcomputer 11 maintains the signal S1 that has risen to Hi level at Hi level.

[0105] At time t4, the switching elements 23 and 24 turn on. The current Isns of the switching elements 23 and 24 increases. In this embodiment, as the current Vsns increases, the voltage Vsns rises, and when it reaches the reference voltage Vref at time t6, the comparison circuit 27 determines that the switching element 23 is in an overcurrent state.

[0106] When the comparison circuit 27 detects the overcurrent state of the switching element 23, the drive circuit 22 turns off the switching element 23. In this case, as the switching element 23 turns off, the switching element 24 also turns off. Therefore, the voltage Vsns generated across the resistor 25 decreases after reaching the reference voltage Vref.

[0107] In this embodiment, in order to protect the switching element 23 from the overcurrent state, the drive circuit 22 turns off the switching element 23 for a predetermined period from time t6. Accordingly, the switching element 24 also turns off, and the voltage Vsns generated across the resistor 25 is maintained at the value after it has decreased to the voltage Vout.

[0108] In the period before time t4, both the voltage supplied from the reference voltage circuit 26 to line Inp and the voltage supplied to line Inm are low values. In this case, the comparison circuit 27 outputs a Lo-level voltage Vcmp.

[0109] In the period from time t4 to time t6, the voltage Vref is supplied from the reference voltage circuit to line Inp, and the voltage Vsns generated across the resistor 25 is supplied to line Inm, and the voltage Vsns is lower than the reference voltage Vref. In this case, the comparison circuit 27 outputs a Hi-level voltage Vcmp to the filter circuit 42.

[0110] On the other hand, at time t6, the voltage Vsns reaches the reference voltage Vref, and the comparison circuit 27 determines that the switching element 23 is in an overcurrent state. As a result, the comparison circuit 27 outputs a voltage Vcmp of Lo level to the filter circuit 42. Further, the comparison circuit 27 continues to output a voltage Vcmp of Lo level for a predetermined period from time t4.

[0111] Also, in the period before time t4, in response to the input Lo-level signal S1, the filter circuit 42 outputs a voltage Vflt of Hi level.

[0112] The filter circuit 42 outputs a voltage Vflt of Hi level during the period Tflt from time t4 to time t5 regardless of the logic level of the voltage Vcmp. Thereby, the logic level of the voltage Vcmp is masked for the control circuit 41.

[0113] In the present embodiment, during the period Tflt from time t4 to time t5, the comparison circuit 27 outputs a voltage Vcmp of Hi level. From time t4 to time t5, even if the circuit operation in the semiconductor module 10 is not stable and the comparison circuit 27 outputs a voltage Vcmp of Lo level, the filter circuit 42 outputs a voltage Vflt of Hi level during this period.

[0114] On the other hand, after time t5, the filter circuit 42 outputs a voltage Vflt having the same logic level as the voltage Vcmp to the control circuit 41.

[0115] Therefore, in the present embodiment, the filter circuit 42 outputs a voltage Vflt of Hi level in the period before time t4 and in the period from time t4 to t6. In a predetermined period after time t6, the filter circuit 42 outputs a voltage flt of Lo level.

[0116] Prior to time t4, a signal S1 at the Lo level is input to the control circuit 41 to turn off the switching element 23. In response to the signal S1 at the Lo level, the control circuit 41 outputs a signal S2 at the Hi level. While the signal S2 is at the Hi level, the boost circuit 32 does not boost the power supply voltage Vdd, and the cutoff element 33 is in the on state.

[0117] At time t4, when the signal S1 becomes Hi level to turn on the switching element 23, the control circuit 41 outputs a signal S2 that has dropped from the Hi level to the Lo level. When the signal S2 becomes Lo level, the boost circuit 32 starts boosting the power supply voltage Vdd to generate the drive voltage Vdrv and applies it to the switching element 23. Further, the cutoff element 33 becomes off.

[0118] On the other hand, at time t6, a voltage Vflt at the Lo level is input to the control circuit 41 from the filter circuit 42. Thereby, it is shown to the control circuit 41 that the switching element 23 is in an overcurrent state due to the voltage Vflt at the Lo level.

[0119] Therefore, in the period after time t6, in response to the voltage Vflt at the Lo level input from the filter circuit 42, the control circuit 41 outputs a signal S2 at the Hi level. In response to the logical level of the signal S2 becoming Hi level, the boost circuit 32 stops boosting the power supply voltage Vdd, the cutoff element 33 turns on, and the switching element 23 turns off.

[0120] <<Relationship between voltage and current in the period after the period Tflt of Example 1>> FIG. 6A shows an example of a schematic of the voltage Vout, current Ids, and voltage Vcmp output from the comparison circuit 27 at the terminal VO. A graph in which the signal S1 is switched from the Lo level to the HI level and the switching element 23 is in the on state in the period after the period Tflt has elapsed is shown.

[0121] The relationship between the voltage Vout and the current Ids is shown. When the switching element 23 is in the on state and the semiconductor module 10 is operating normally, the voltage Vout applied to the terminal VO indicates the power supply voltage Vdd.

[0122] When the drain-source current Ids of the switching element 23 reaches the current Ioc (for example, 2 A) indicating an overcurrent state, a graph is shown in which the voltage Vout applied to the terminal VO reaches the voltage Voc indicating an overcurrent.

[0123] In this embodiment, when the voltage Vout applied to the terminal VO reaches the voltage Voc, the voltage Vsns generated in the resistor 25 reaches the reference voltage Vref output by the reference voltage circuit 26. That is, in the range where the voltage Vout applied to the terminal VO is greater than the voltage Voc and less than or equal to the power supply voltage Vdd, the semiconductor module 10 operates normally.

[0124] In the range where the voltage Vout is higher than the voltage Voc and lower than the power supply voltage Vdd, that is, in the range where the voltage Vsns is lower than the reference voltage Vref, the comparison circuit 27 outputs a high-level voltage Vcmp. On the other hand, in the range where the voltage Vout is lower than the voltage Voc, that is, in the range where the voltage Vsns is higher than the reference voltage Vref, the comparison circuit 27 outputs a low-level voltage Vcmp.

[0125] The voltage flt indicates the same logic level as the voltage Vcmp.

[0126] <<Voltage Logic Level of Example 1>> FIG. 6B shows an example of the voltage Vcmp output from the comparison circuit 27 in each operating state of the comparison circuit 27. A table in the period after the signal S1 is switched from the low level to the high level and after the period Tflt has elapsed is shown.

[0127] When the semiconductor module 10 is operating normally, the comparison circuit 27 outputs a high-level voltage Vcmp. That is, when the voltage Vsns is lower than the reference voltage Vref, the comparison circuit 27 outputs a high-level voltage Vcmp.

[0128] On the other hand, when the voltage Vsns is higher than the reference voltage Vref, the comparison circuit 27 determines that the switching element 23 is in an overcurrent state. That is, when the voltage Vsns is higher than the reference voltage Vref, the comparison circuit 27 outputs a Lo-level voltage Vcmp.

[0129] The comparison circuit 27 may stop operating outside the common-mode input range. In such a case, in the comparison circuit 27 of the present embodiment, the reference voltage circuit 26 is connected to the line Inp and the node between the switching element 24 and the resistor 25 is connected to the line Inm so that a Lo-level voltage Vcmp is output.

[0130] Therefore, when the voltage Vout is lower than the voltage Vgnd, the comparison circuit 27 outputs a Lo-level voltage Vcmp. That is, when the voltage Vout is lower than the voltage Vgnd, the comparison circuit 27 determines that the switching element 23 is in an overcurrent state. The drive circuit 22 drives the switching element 23 based on the voltage Vcmp input from the comparison circuit 27.

[0131] ===Embodiment 2=== <<Configuration of Semiconductor Module 20>> FIG. 7 shows an example of the configuration of the semiconductor module 20. Hereinafter, mainly, the differences from the semiconductor module 10 in the configuration of the semiconductor module 20 will be described. In the semiconductor module 20, elements denoted by the same reference numerals as those in the semiconductor module 10 have the same configuration.

[0132] In the semiconductor module 20, the connection relationship between the reference voltage circuit 26 and the comparison circuit 27 is different from that of the semiconductor module 10. Further, the semiconductor module 20 includes a logic circuit 28 connected to the reference voltage circuit 26, the comparison circuit 27, and the filter circuit 42.

[0133] In the semiconductor module 20, the voltage Vref supplied from the reference voltage circuit 26 is input to the line Inm to which the inverting input terminal of the comparison circuit 27 is connected. On the other hand, the voltage Vsns generated at the node between the switching element 24 and the resistor 25 is input to the line Inp to which the non-inverting input terminal of the comparison circuit 27 is connected.

[0134] That is, the inputs to the lines Inp and Inm of the semiconductor module 20 are opposite to the inputs to the lines Inp and Inm of the semiconductor module 10. As a result, the logic level of the voltage Vcmp output from the comparison circuit 27 is different between the semiconductor module 10 and the semiconductor module 20.

[0135] <<Logic circuit 28>> The logic circuit 28 outputs the voltage Vlg to the filter circuit 42. In the present embodiment, according to the voltage Vlg, the filter circuit 42 supplies the voltage Vflt to the control circuit 41.

[0136] The voltage Vflt becomes a logic level of Lo level according to the signal S1 of Lo level. Also, the voltage Vflt becomes a logic level (Lo level) indicating that the switching element 23 is not in an overcurrent state regardless of the voltage Vlg before the period Tflt elapses after the signal S1 indicates the Hi level. Further, the voltage Vflt becomes a logic level equal to the voltage Vcmp input from the comparison circuit 27 after the period Tflt elapses after the signal S1 indicates the Hi level. Note that in the semiconductor module 20, unlike the semiconductor module 10, the logic level of the voltage Vflt indicating that the switching element 23 is not in an overcurrent state is the Lo level.

[0137] In the present embodiment, since the logic circuit 28 is connected to the control circuit 41 via the filter circuit 42, when the control circuit 41 operates based on the voltage Vflt, without connecting the logic circuit 28 to the control circuit 41, the control circuit 41 can also operate indirectly based on the voltage Vlg.

[0138] ====A form in which the connection relationship of the logic circuit 28 is partially changed==== In another embodiment of the semiconductor module 20, the logic circuit 28 is connected to the control circuit 41 without passing through the filter circuit 42. In particular, in an embodiment where the control circuit 41 is connected to the filter circuit 42 separately from the logic circuit 28, the control circuit 41 preferentially applies the Hi-level voltage Vflt output from the filter circuit 42 over the voltage Vlg output from the logic circuit 28. When the voltage flt is at the Hi level, the control circuit outputs the signal S2 based on the signal S1 regardless of the logic level of the voltage Vlg.

[0139] ===Control Circuit 41 in Semiconductor Module 20=== Also in the semiconductor module 20, the control circuit 41 outputs the signal S2 based on the signal S1 and the voltage Vflt from the microcomputer 11. However, the logic level of the voltage Vflt input to the control circuit 41 is different when the switching element 23 is determined to be in an overcurrent state by the comparison circuit 27 in the embodiment of the semiconductor module 10.

[0140] Therefore, in this embodiment, when the voltage Vflt input from the filter circuit 42 is at the Lo level and the signal S1 is at the Lo level, the control circuit 41 outputs a Hi-level signal S2 in response to the Lo-level signal S1. On the other hand, when the voltage Vflt input from the filter circuit 42 is at the Lo level and the signal S1 is at the Hi level, the control circuit 41 outputs a Lo-level signal S2.

[0141] Also, when the voltage Vflt input from the filter circuit is at the Hi level, the control circuit 41 of this embodiment outputs a Hi-level signal S2.

[0142] Note that in the semiconductor module 20, the voltage Vlg corresponds to the "sixth voltage".

[0143] <<Configuration of Logic Circuit 28>> FIG. 8 shows the configuration of the logic circuit 28 and the relationship between the logic circuit 28 and the filter circuit 34. The logic circuit 28 includes an inverter circuit 81 and an OR circuit 82.

[0144] The inversion circuit 81 outputs voltages Vinv of different logic levels according to whether the reference voltage Vref input from the reference voltage circuit 26 is greater than a predetermined threshold voltage. When the voltage Vout drops below the voltage Vgnd, the reference voltage Vref also drops.

[0145] The inversion circuit 81 of this embodiment outputs a high-level voltage Vinv when the voltage Vref drops below the predetermined threshold voltage. On the other hand, the inversion circuit 81 of this embodiment outputs a low-level voltage Vinv when the voltage Vref is higher than the predetermined threshold voltage.

[0146] Note that the threshold voltage for the voltage Vref at which the inversion circuit 81 switches the logic level of the voltage Vinv from the low level to the high level is set to at least a voltage equal to or higher than the voltage at which the voltage Vout drops to the voltage Vgnd. That is, the inversion circuit 81 is designed to output a high-level voltage Vinv at least in the range where the voltage Vout drops below the voltage Vgnd.

[0147] The inversion circuit 81 is connected to the reference voltage circuit 26. Also, the inversion circuit 81 is connected to lines L1 and L2 and operates with the power supply voltage Vdd applied to line L1 and the voltage Vgnd applied to line L2 as bias voltages.

[0148] The OR circuit 82 outputs a high-level voltage Vlg when either the input voltage Vcmp or the voltage Vinv has a high-level logic level. On the other hand, the OR circuit 82 outputs a low-level voltage Vlg when both the voltage Vcmp and the voltage Vinv are at the low level.

[0149] The OR circuit 82 is connected to the comparison circuit 27 and the inversion circuit 81. Also, the OR circuit 82 is connected to lines L1 and L2 and operates with the power supply voltage Vdd applied to line L1 and the voltage Vgnd applied to line L2 as bias voltages.

[0150] The voltage Vlg output from the OR circuit 82 is input to the drive circuit 22. The voltage Vlg is used for the drive circuit 22 to control the drive of the switching element 23. In the present embodiment, the voltage Vlg is input to the filter circuit 42.

[0151] However, the circuit to which the voltage Vlg is input is not limited to the filter circuit 42. When the voltage Vlg indicates a Hi level, control for an overcurrent state may be performed. Therefore, in another embodiment of the semiconductor module 20, the voltage Vlg may be input to the control circuit 41 without passing through the filter circuit 42.

[0152] Also, for the voltage Vlg, the Hi-level voltage Vlg corresponds to "the sixth voltage of the first logic level", and the Lo-level voltage Vlg corresponds to "the sixth voltage of the second logic level".

[0153] <<Relationship between voltage and current during the period after the elapse of the period Tflt in Example 2>> FIG. 9A shows an example of a schematic of the voltage Vout, current Ids, and voltage Vcmp output from the comparison circuit 27 at the terminal VO. In the semiconductor module 20, a graph of the current and voltage corresponding to FIG. 6A is shown. The signal S1 is switched to the Hi level, and a graph in which the switching element 23 is in the on state during the period after the elapse of the period Tflt is shown.

[0154] The relationship between the voltage Vout and the current Ids is shown. When the switching element 23 is in the on state and the semiconductor module 10 is operating normally, the voltage Vout applied to the terminal VO indicates the power supply voltage Vdd.

[0155] When the drain-source current Ids of the switching element 23 reaches the current Ioc (for example, 2 A) indicating an overcurrent state, a graph is shown in which the voltage Vout applied to the terminal VO reaches the voltage Voc indicating an overcurrent.

[0156] In this embodiment, when the voltage Vout applied to the terminal VO reaches the voltage Voc, the voltage Vsns generated in the resistor 25 reaches the reference voltage Vref. That is, in the range where the voltage Vout applied to the terminal VO is greater than the voltage Voc and less than or equal to the power supply voltage Vdd, the semiconductor module 20 operates normally.

[0157] In the semiconductor module 20, different from the semiconductor module 10, in the range where the voltage Vout is greater than the voltage Voc and less than the power supply voltage Vdd, that is, in the range where the voltage Vsns is less than the reference voltage Vref, the comparison circuit 27 outputs a Lo-level voltage Vcmp. On the other hand, in the range where the voltage Vout is less than the voltage Voc, that is, in the range where the voltage Vsns is greater than the reference voltage Vref, a Hi-level voltage Vcmp is output.

[0158] Also, in this embodiment, when the voltage Vout decreases, both the reference voltage Vref and the voltage Vsns decrease, and when the voltage input to the comparison circuit 27 is outside the common-mode input range, the comparison circuit 27 may output a Lo-level logic level.

[0159] In the semiconductor module 20, the inverter circuit 81 outputs a Hi-level voltage Vinv when the voltage Vout is less than the voltage Vgnd. Therefore, at a voltage where the comparison circuit 27 reaches or exceeds the voltage outside the common-mode input range and the voltage Vout is lower than the voltage Vout reaching the voltage Voc, the inverter circuit 81 switches the logic level of the output voltage Vinv from the Lo level to the Hi level.

[0160] Actually, the inverter circuit 81 compares the reference voltage Vref with a predetermined threshold voltage, and when the reference voltage Vref becomes lower than this threshold voltage, switches the logic level of the voltage Vinv. That is, the threshold voltage is set so as to correspond to the case where the inverter circuit 81 switches the logic level of the voltage Vinv from the Lo level to the Hi level when the voltage Vout is any voltage in the range greater than the voltage Vgnd and less than the voltage Voc.

[0161] As a result, when the voltage Vout is lower than the voltage Voc, either the voltage Vcmp output by the comparison circuit 27 or the voltage Vinv output by the inverter circuit 81 becomes a Hi level. Since the voltage Vcmp and the voltage Vinv are input to the OR circuit 82, when the voltage Vout is lower than the voltage Voc, the OR circuit 82 outputs a Hi-level voltage Vlg.

[0162] Also, when the signal S1 is switched from the Lo level to the HI level, in the period after the elapse of the period Tflt, the filter circuit 42 outputs a voltage Vflt having the same logic level as the voltage Vlg. Therefore, the filter circuit 42 outputs a Hi-level voltage Vflt when the voltage Vout is lower than the voltage Voc.

[0163] <<Logic Levels of Voltages in Embodiment 2>> FIG. 9B shows an example of the voltage Vcmp output from the comparison circuit 27 and the voltage Vlg output from the logic circuit 28 in each operating state of the comparison circuit 27. A table in the period after the signal S1 is switched from the Lo level to the HI level and after the elapse of the period Tflt is shown.

[0164] During normal operation of the semiconductor module 10, in contrast to the comparison circuit 27 of the semiconductor module 10 outputting a Hi-level voltage Vcmp, during normal operation of the semiconductor module 20, the comparison circuit 27 of the semiconductor module 20 outputs a Lo-level voltage Vcmp. This is because the voltages applied to the lines Inp and Inm input to the comparison circuit 27 are different between the semiconductor module 10 and the semiconductor module 20.

[0165] The comparison circuit 27 outputs a Hi-level voltage Vcmp to the logic circuit 28 when the voltage Vsns is higher than the reference voltage Vref. On the other hand, the comparison circuit 27 outputs a Lo-level voltage Vcmp to the logic circuit 28 when the voltage Vsns is lower than the reference voltage Vref. Also, the comparison circuit 27 outputs a Lo-level voltage Vcmp to the logic circuit 28 when the voltage Vout is lower than Vgnd.

[0166] When the voltage Vout is lower than the voltage Vgnd, the inversion circuit 81 outputs a high-level voltage Vinv. Therefore, when the voltage Vout is lower than the voltage Vgnd or the voltage Vsns is higher than the reference voltage Vref, the OR circuit 82 outputs a high-level voltage Vlg. In this case, the drive circuit 22 drives the switching element 23 based on the voltage Vlg.

[0167] In this way, in the semiconductor module 20, by inputting the voltage Vsns or the voltage Vref to the comparison circuit 27 or the logic circuit 28, the circuit can be protected from the overcurrent state of the switching element 23 when the voltage Vout drops below the voltage Vgnd without inputting the voltage Vout to the comparison circuit 27 or the logic circuit 28.

[0168] ===Summary=== The semiconductor modules 10 and 20 of the present embodiment have been described above.

[0169] In the present embodiment, a switching element 23 connected to a line L1 to which a power supply voltage Vdd is applied, a terminal VO to which a voltage Vout corresponding to a current Ids flowing through the switching element 23 when the switching element 23 is on is generated while being connected to the switching element 23, a switching element 24 connected to the line L1 and through which a current Isns corresponding to the current Ids flows, a voltage generation circuit 21 that applies a voltage Vgnd that has dropped by a predetermined voltage from the power supply voltage Vdd to the line L2, a resistor 25 that is connected between the switching element 24 and the terminal VO and generates a voltage Vsns corresponding to the current Isns, a reference voltage circuit 26 that is connected to the terminal Vout and generates a reference voltage Vref, and a comparison circuit 27 that is connected between the line L1 and the line L2 and determines whether or not the switching element 23 is in an overcurrent state based on a comparison between the voltage Vsns and the reference voltage Vref, are provided.

[0170] As a result, the semiconductor modules 10 and 20 of the present embodiment can appropriately protect the circuit from overcurrent in both cases: (i) when an overcurrent flows through the load 12; and (ii) when a path parallel to the load 12 is short-circuited between the terminal VO and the ground due to a circuit defect, dirt, etc., and an overcurrent flows in the grounding direction through a path different from the load 12.

[0171] In addition, the semiconductor modules 10 and 20 include a drive circuit 22 that turns on and off the switching element 23 in response to the input signal S1. When the comparison circuit 27 determines that the switching element is in an overcurrent state, the drive circuit 22 turns off the switching element 23.

[0172] As a result, in the case of an overcurrent state, the switching element 23 is turned off, and the semiconductor modules 10 and 20 and the system connected to the semiconductor modules 10 and 20 can be protected from the overcurrent state.

[0173] In addition, the comparison circuit 27 of Example 1 determines that the switching element 23 is in an overcurrent state when the voltage Vout is lower than the voltage Vgnd.

[0174] That is, in the comparison circuit 27 of Example 1, when the voltage Vout is lower than the voltage Vgnd, the comparison circuit 27 outputs the same logic as when the switching element 23 reaches an overcurrent state. As a result, the semiconductor module 10 can also protect the system from overcurrent when a path parallel to the load 12 is short-circuited between the terminal VO and the ground due to a circuit defect, dirt, etc., and an overcurrent flows in the grounding direction through a path different from the load 12.

[0175] Furthermore, in the comparison circuit 27 of the present embodiment, an overcurrent state can be detected without using an element with a large circuit area such as a rail-to-rail input type comparator. Therefore, the configuration of the semiconductor module 10 also contributes to reducing the circuit area.

[0176] Further, when the voltage Vsns is lower than the reference voltage Vref, the comparison circuit 27 outputs a high-level voltage Vcmp. When the voltage Vout is lower than the voltage Vgnd, or when the voltage Vsns is higher than the reference voltage Vref, the comparison circuit 27 outputs a low-level voltage Vcmp. The drive circuit 22 drives the switching element 23 based on the voltage Vcmp.

[0177] As described above, the comparison circuit 27 specifically shows what logic level to output according to the input voltage. Further, in the semiconductor module 10, since the comparison circuit 27 outputs such a logic level, by inputting the voltage Vsns and the voltage Vref, even without inputting the voltage Vout to the comparison circuit 27, when the voltage Vout drops below the voltage Vgnd, the circuit can be protected from the overcurrent state of the switching element 23.

[0178] The semiconductor module 20 of the second embodiment includes a logic circuit 28 connected to the comparison circuit 27. When the voltage Vsns is higher than the reference voltage Vref, the comparison circuit 27 outputs a high-level voltage Vcmp to the logic circuit 28. When the voltage Vsns is lower than the reference voltage Vref, the comparison circuit 27 outputs a low-level voltage Vcmp. When the voltage Vout is lower than the voltage Vgnd, or when the voltage Vsns is higher than the voltage gnd, the logic circuit 28 outputs a high-level voltage Vlg. The drive circuit 22 drives the switching element 23 based on the voltage Vlg.

[0179] Thereby, in the semiconductor module 20, even when a path parallel to the load 12 is short-circuited between the terminal VO and the ground due to a circuit defect, dirt, etc., and an overcurrent flows in the grounding direction through a path different from the load 12, the system can be protected from the overcurrent.

[0180] Further, the logic circuit 28 is connected to the reference voltage circuit 26 and the comparison circuit 27.

[0181] As a result, in the semiconductor module 20, by inputting the voltage Vsns or the voltage Vref to the comparison circuit 27 or the logic circuit 28, even without inputting the voltage Vout to the comparison circuit 27 or the logic circuit 28, the circuit can be protected from the overcurrent state of the switching element 23 when the voltage Vout drops below the voltage Vgnd.

[0182] Further, the logic circuit 28 includes an inverter circuit 81 connected to the reference voltage circuit 26 and an OR circuit 82 connected to the comparison circuit 27 and the inverter circuit 81.

[0183] As a result, the logic circuit 28 becomes a circuit that outputs a high-level voltage Vlg when the voltage Vout is lower than the voltage Vgnd or when the voltage Vsns is higher than the voltage gnd.

[0184] Also, in the semiconductor modules 10 and 20, the drive circuit 22 outputs a signal S2 based on an input signal S1 for controlling the on / off of the switching element 23 regardless of the comparison result of the comparison circuit 27 during a predetermined period Tflt when the switching element 23 turns on, and outputs a signal S2 based on the input signal S1 and the comparison result after the predetermined period Tflt has elapsed. A control signal output circuit 31, a booster circuit 32 that applies a drive voltage Vdrv to the control electrode of the switching element 23 based on the signal S2 when the switching element turns on, and a cutoff element 33 that turns off the switching element 23 in response to the signal S2 for turning off the switching element 23.

[0185] As a result, an IPS having a function of appropriately protecting the circuit from overcurrent can be configured for both (i) the case where an overcurrent flows through the load 12 and (ii) the case where a path parallel to the load 12 is short-circuited between the terminal VO and the ground due to a circuit defect, dirt, etc., and an overcurrent flows in the grounding direction through a path different from the load 12.

[0186] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements are made to the above embodiments. It will be apparent to those skilled in the art that this is possible. It is clear from the description of the claims that the technical scope of the present invention may also include forms in which such modifications or improvements are added without departing from the spirit thereof, and equivalents thereof.

[0187] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly indicated as "earlier" or "preceding" etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if "first," "next," etc. are used for convenience of explanation, it does not mean that it is essential to implement in this order.

Description of Reference Numerals

[0188] 10, 20 Semiconductor module 11 Microcomputer 12 Load 13 Power supply 21 Voltage generation circuit 22 Drive circuit 23, 24 Switching element 25 Resistor 26 Reference voltage circuit 27 Comparison circuit 28 Logic circuit 31 Control signal output circuit 32 Boost circuit 33 Cut-off element 41 Control circuit 42 Filter circuit 51 Inductor 52 Resistor 61 Depletion-type MOS transistor 62 MOS transistor 63, 64 Resistors 71 Depletion-type MOS transistor 72 - 79 MOS transistors 81 Inversion circuit 82 OR circuit

Claims

1. A first switching element connected to a first line to which a power supply voltage is applied; A terminal that is connected to the first switching element and generates a first voltage corresponding to a first current flowing through the first switching element when the first switching element is on; A second switching element that is connected to the first line and through which a second current corresponding to the first current flows; A voltage generation circuit that applies a second voltage, which has been reduced by a predetermined voltage from the power supply voltage, to a second line; A resistor that is connected between the second switching element and the terminal and generates a third voltage corresponding to the second current; A reference voltage circuit that is connected to the terminal and generates a predetermined fourth voltage; A comparison circuit that is connected between the first line and the second line and determines whether the first switching element is in an overcurrent state based on a comparison between the third voltage and the fourth voltage; A semiconductor module comprising the above.

2. The semiconductor module according to Claim 1, further comprising: A drive circuit that turns the first switching element on and off in response to an input signal; The drive circuit turns off the first switching element when the comparison circuit determines that the first switching element is in an overcurrent state. A semiconductor module.

3. The semiconductor module according to Claim 2, wherein: The comparison circuit determines that the first switching element is in an overcurrent state when the first voltage is lower than the second voltage. A semiconductor module.

4. The semiconductor module according to Claim 3, wherein: The comparison circuit outputs a fifth voltage of a first logic level when the third voltage is lower than the fourth voltage, and outputs a fifth voltage of a second logic level when the first voltage is lower than the second voltage or the third voltage is higher than the fourth voltage; The drive circuit drives the first switching element based on the fifth voltage. A semiconductor module.

5. The semiconductor module according to Claim 2, further comprising: A logic circuit connected to the comparison circuit; The comparison circuit outputs a fifth voltage of a first logic level to the logic circuit when the third voltage is higher than the fourth voltage, and outputs a fifth voltage of a second logic level when the third voltage is lower than the fourth voltage. When the first voltage is lower than the second voltage, or when the third voltage is higher than the fourth voltage, the logic circuit outputs a sixth voltage of the first logic level. Based on the sixth voltage, the drive circuit drives the first switching element. Semiconductor module.

6. The semiconductor module according to claim 5, wherein the logic circuit is connected to the reference voltage circuit and the comparison circuit. Semiconductor module.

7. The semiconductor module according to claim 5, wherein the logic circuit includes an inverter circuit connected to the reference voltage circuit, and an OR circuit connected to the comparison circuit and the inverter circuit. Semiconductor module.

8. The semiconductor module according to any one of claims 2 to 7, wherein the drive circuit outputs a control signal based on an input signal for controlling the on / off of the first switching element regardless of the comparison result of the comparison circuit during a predetermined period when the first switching element is turned on, and outputs the control signal based on the input signal and the comparison result after the elapse of the predetermined period; a control signal output circuit; a booster circuit that applies a drive voltage to the control electrode of the first switching element based on the control signal when the first switching element is turned on; a cutoff element that turns off the first switching element in response to the control signal for turning off the first switching element; including Semiconductor module.

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