Transmitting device, receiving device, and transmission system

Abstract

This transmission device comprises: a transmission unit that includes, in a payload, pixel data in the amount of one line constituting an image of one frame, the transmission unit being capable of outputting, to a transmittal path, a plurality of packets in which a header is added to the payload; and an insertion rate calculation unit that can calculate the insertion rate of a padding code inserted into the payload in order to fill in the difference between the transmittal rate of the pixel data inputted to the transmission unit and the transmittal rate of pixel data outputted from the transmission unit to the transmittal path.

Description

Technical Field

[0001] The present disclosure relates to a transmission device that transmits image data, a reception device that receives image data, and a transmission system that transmits and receives image data.

Background Art

[0002] Some transmission systems transmit and receive image data including pixel data for a plurality of lines output from an imaging unit between a transmission unit and a reception unit. Patent Document 1 discloses a transmission system that generates a packet having a header including control information and a payload including pixel data for one line, and uses this packet to transmit and receive image data. In the technique described in Patent Document 1, in order to bridge the difference in transmission bandwidth between the transmission rate of pixel data input to the transmission unit (pixel data bandwidth) and the transmission rate of pixel data transmitted from the transmission unit and input to the reception unit (PHY transmission bandwidth), it is possible to insert a group of symbols called padding codes into the payload data.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] In the technique described in Patent Document 1, on the reception unit side, it is difficult to know the insertion rate of the above-described padding codes, so it may be difficult to perform optimal data processing.

[0005] It is desirable to provide a transmission device, a reception device, and a transmission system capable of performing optimal data processing.

[0006] A transmission device according to an embodiment of the present disclosure includes a transmission unit that can output a plurality of packets including pixel data for one line constituting one frame of an image in a payload and adding a header to the payload to a transmission path, and a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path, and an insertion rate calculation unit that can calculate an insertion rate of padding codes inserted into the payload to fill the difference. The transmission device according to one embodiment may further include a header generation unit capable of adding data indicating the insertion rate of the padding code calculated by the insertion rate calculation unit to the header. Alternatively, the transmission device according to one embodiment may further include a register capable of storing data indicating the insertion rate of the padding code calculated by the insertion rate calculation unit, and the register may be capable of outputting data indicating the insertion rate of the padding code to a receiving device capable of receiving a packet via a transmission path through a path different from the transmission path of the packet. Alternatively, the transmission device according to one embodiment may further include a packet generation unit capable of generating a packet including a dummy area in the payload instead of pixel data, and adding data indicating the insertion rate of the padding code to the dummy area.

[0007] A receiving device according to an embodiment of the present disclosure includes a receiving unit that can receive a plurality of packets including pixel data for one line constituting one frame of an image in a payload and adding a header to the payload from a transmission unit of a transmission device via a transmission path, and data on an insertion rate of padding codes inserted into the payload to fill the difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path can be received from the transmission device.

[0008] A transmission system according to an embodiment of the present disclosure includes a transmission device and a receiving device. The transmission device includes a transmission unit that can output a plurality of packets including pixel data for one line constituting one frame of an image in a payload and adding a header to the payload to a transmission path, and a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path, and an insertion rate calculation unit that can calculate an insertion rate of padding codes inserted into the payload to fill the difference. The receiving device includes a receiving unit capable of receiving a plurality of packets from the transmitting unit of the transmitting device via a transmission path, and may be capable of receiving data on the insertion rate of the padding code from the transmitting device.

[0009] In the transmission device, receiving device, or transmission system according to an embodiment of the present disclosure, it is possible to know the insertion rate of the padding code.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. One embodiment 1.1 Configuration and operation of a transmission system according to one embodiment (Figs. 1 to 11) 1.2 Improvement examples of a transmission system according to one embodiment (Figs. 12 to 15) 1.3 Effects 2. Other embodiments

[0012] <1. One embodiment> [1.1 Configuration and operation of a transmission system according to one embodiment] [Configuration example of a transmission system] Fig. 1 shows a first configuration example of a transmission system 1 according to one embodiment of the present disclosure.

[0013] The transmission system 1 shown in Fig. 1 includes a sensor module 11 and a DSP (Digital Signal Processor) 12. The sensor module 11 and the DSP 12 are each constituted by, for example, different LSIs (Large Scale Integrated Circuits) and are provided in the same imaging device having an imaging function, such as a digital camera or a mobile phone.

[0014] The sensor module 11 has an imaging unit 21 and a transmission unit 22. The sensor module 11 also has a system control unit 51 and a register 53. The sensor module 11 also has a frame data input unit 52 (Fig. 6) described later. The system control unit 51 and the register 53 are connected to the imaging unit 21 and the transmission unit 22.

[0015] The DSP 12 has a reception unit 31 and an image processing unit 32. The DSP 12 also has a register 142 and a system control unit 143. The DSP 12 also has a frame data output unit 141 (Fig. 7) described later. The register 142 and the system control unit 143 are connected to the reception unit 31 and the image processing unit 32.

[0016] The system control unit 51 and the register 53 in the sensor module 11 and the register 142 and the system control unit 143 in the DSP 12 are connected to each other by the control line 13, and communication such as control data is possible between the sensor module 11 and the DSP 12.

[0017] The imaging unit 21 has an image sensor such as a CMOS (Complementary Metal Oxide Semiconductor), and performs photoelectric conversion of the light received through the lens. Further, the imaging unit 21 performs A / D conversion of the signal obtained by the photoelectric conversion, and outputs the pixel data constituting one frame of the image to the transmission unit 22 one pixel data at a time in order.

[0018] The transmission unit 22 assigns the data of each pixel supplied from the imaging unit 21 to a plurality of transmission paths, for example, in the order supplied from the imaging unit 21, and transmits the data to the DSP 12 in parallel via the plurality of transmission paths. In the example of FIG. 1, the pixel data is transmitted using eight transmission paths. The transmission path between the sensor module 11 and the DSP 12 may be a wired transmission path or a wireless transmission path. Hereinafter, the transmission path between the sensor module 11 and the DSP 12 is appropriately referred to as a lane.

[0019] The receiving unit 31 of the DSP 12 receives the pixel data transmitted from the transmission unit 22 via eight lanes, and outputs the data of each pixel to the image processing unit 32 in order.

[0020] The image processing unit 32 generates an image of one frame based on the pixel data supplied from the receiving unit 31, and performs various image processes using the generated image. The image data transmitted from the sensor module 11 to the DSP 12 is RAW data, and in the image processing unit 32, various processes such as compression of the image data, display of the image, and recording of the image data on a recording medium are performed.

[0021] FIG. 2 shows a second configuration example of the transmission system 1 according to an embodiment.

[0022] The imaging unit 21 may be configured to output a plurality of pixel data of different types for the same pixel. For example, as shown in FIG. 2, two pixel data of different types (first pixel data DATA1 and second pixel data DATA2) may be output as the data of the same pixel. For example, for the same pixel, two pixel data with different gains may be output. In this case, between the transmission unit 22 and the reception unit 31, for example, two pixel data may be configured to be transmitted in parallel. For example, among Lane0 to 7, Lane0 to 3 may be assigned as a first divided transmission path (LINK0) for transmitting the first pixel data DATA1, and Lane4 to 7 may be assigned as a second divided transmission path (LINK1) for transmitting the second pixel data DATA2. In this way, in order to transmit pixel data of different types in parallel between the transmission unit 22 and the reception unit 31, a plurality of lanes may be divided into a plurality of divided transmission paths (LINK) for each type of pixel data.

[0023] In the transmission system 1, a plurality of transmission units 22 and a plurality of reception units 31 may be provided respectively. In this case, for example, the image data of one frame or a plurality of frames captured by one imaging unit 21 may be divided and input in parallel to a plurality of transmission units, and the image data of one frame or a plurality of frames input in parallel may be transmitted in parallel to a plurality of reception units 31. Then, the image data of one frame or a plurality of frames from the plurality of reception units 31 received in parallel may be output to the DSP12 in parallel.

[0024] As described above, in the sensor module 11 of the transmission system 1, it is possible to provide one or a plurality of transmission units 22 for transmitting the image data of one frame or a plurality of frames captured. On the other hand, in the DSP12, corresponding to the transmission unit 22 of the sensor module 11, it is possible to provide one or a plurality of reception units 31 for receiving the image data of one frame or a plurality of frames transmitted from the sensor module 11.

[0025] The following describes the data transmission in the transmission system 1 of FIG. 1, where one transmission unit 22 is provided in the sensor module 11 and one reception unit 31 is provided in the DSP 12. Data transmission is similarly performed between each of the plurality of transmission units 22 and each of the plurality of reception units 31.

[0026] [Frame Format] FIG. 3 shows an example of a frame format used for transmitting one frame of image data between the sensor module 11 and the DSP 12.

[0027] The effective pixel region A1 is the region of effective pixels of one frame of the image captured by the imaging unit 21. A margin region A2 having the same number of vertical pixels as the number of vertical pixels in the effective pixel region A1 is set on the left side of the effective pixel region A1.

[0028] A pre-dummy region A3 having the same number of horizontal pixels as the total number of horizontal pixels in the effective pixel region A1 and the margin region A2 is set above the effective pixel region A1. In the example of FIG. 3, Embedded Data is inserted into the pre-dummy region A3. Embedded Data includes information on setting values related to imaging by the imaging unit 21, such as the shutter speed, aperture value, and gain. Embedded Data may also be inserted into the post-dummy region A4.

[0029] A post-dummy region A4 having the same number of horizontal pixels as the total number of horizontal pixels in the effective pixel region A1 and the margin region A2 is set below the effective pixel region A1.

[0030] The image data region A11 is composed of the effective pixel region A1, the margin region A2, the pre-dummy region A3, and the post-dummy region A4.

[0031] A header is added before each line that constitutes the image data area A11, and a Start Code is added before the header. Also, a footer is optionally added after each line that constitutes the image data area A11, and a control code such as an End Code described later is added after the footer. When the footer is not added, a control code such as an End Code is added after each line that constitutes the image data area A11.

[0032] Every time an image of one frame captured by the imaging unit 21 is transmitted from the sensor module 11 to the DSP 12, the entire data in the format shown in FIG. 3 is transmitted as transmission data.

[0033] The upper band in FIG. 3 shows the structure of the packet used for the transmission of the transmission data shown below. Assuming that the horizontal arrangement of pixels is a line, the pixel data constituting one line of the image data area A11 is stored in the payload of the packet. The transmission of the entire image data of one frame is performed using a number of packets equal to or greater than the number of pixels in the vertical direction of the image data area A11.

[0034] A header and a footer are added to the payload storing the pixel data for one line, thereby constituting one packet. As will be described in detail later, the header contains additional information of the pixel data stored in the payload, such as Frame Start, Frame End, Line Valid, Line Number, Reserved, ECC, etc. Also, as surrounded by the thick line L11, the header contains Embedded Line and Data ID. At least a Start Code and an End Code, which are control codes, are added to each packet.

[0035] By adopting a format in which the pixel data constituting one frame of the image is transmitted line by line in this way, it becomes possible to transmit additional information such as headers and control codes such as Start Code and End Code during the blanking period for each line.

[0036] Figure 4 shows an example of the header structure of one packet of the frame format shown in Figure 3. Figure 5 shows an example of the content of the header information in the header structure shown in Figure 4.

[0037] As described above, one packet includes a header and payload data which is pixel data for one line. A footer may be added to the packet. The header includes header information and Header ECC. A Start Code is added at the beginning of each packet, and an End Code is added at the end.

[0038] The header information includes Frame Start, Frame End, Line Valid, Line Number, and Reserved. The header information further includes Embedded Line as line information and Data ID as data identification. The content and amount of information of each are shown in Figure 5.

[0039] Frame Start is 1-bit information indicating the start of a frame. A value of 1 is set for Frame Start of the header of the packet used for transmitting the pixel data of the first line of the image data area A11 in Figure 3, and a value of 0 is set for Frame Start of the header of the packets used for transmitting the pixel data of other lines.

[0040] Frame End is 1-bit information indicating the end of a frame. A value of 1 is set for Frame End of the header of the packet including the pixel data of the last line of the valid pixel area A1 in the payload, and a value of 0 is set for Frame End of the headers of the packets used for transmitting the pixel data of other lines.

[0041] Frame Start and Frame End become frame information which is information regarding the frame.

[0042] Line Valid is 1-bit information indicating whether the line of pixel data stored in the payload is a line of valid pixels. A value of 1 is set for Line Valid in the header of the packet used for transmitting the pixel data of the lines within the valid pixel region A1, and a value of 0 is set for Line Valid in the header of the packet used for transmitting the pixel data of other lines.

[0043] Line Number is 13-bit information representing the line number of the line composed of the pixel data stored in the payload.

[0044] Line Valid and Line Number become line information, which is information regarding the line.

[0045] Embedded Line is 1-bit information indicating whether the packet is used for transmitting the line in which Embedded Data is inserted. For example, a value of 1 is set for Embedded Line in the header of the packet used for transmitting the line including Embedded Data, and a value of 0 is set for Embedded Line in the header of the packet used for transmitting other lines. As described above, the information of the setting values related to imaging is inserted as Embedded Data into predetermined lines of the pre-dummy region A3 and the post-dummy region A4.

[0046] Data ID is P-bit information indicating the number of the pixel data stored in the payload. The P bits represent a predetermined number of bits of 1 bit or more.

[0047] Reserved is a 31 - P-bit region for extension. The total data amount of the header information is 6 bytes.

[0048] As shown in FIG. 4, the Header ECC arranged following the header information includes a CRC (Cyclic Redundancy Check) code, which is a 2-byte error detection code calculated based on the 6-byte header information. Further, the Header ECC includes, following the CRC code, two pieces of the same information as the 8-byte information that is a combination of the header information and the CRC code.

[0049] That is, the header of one packet includes three combinations of the same header information and CRC code. The total data amount of the entire header is 24 bytes in total, which is the sum of 8 bytes of the first combination of the header information and CRC code, 8 bytes of the second combination of the header information and CRC code, and 8 bytes of the third combination of the header information and CRC code.

[0050] [Configuration of Transmission Unit 22 and Reception Unit 31] FIG. 6 shows a configuration example of the transmission unit 22 in the transmission system 1. FIG. 7 shows a configuration example of the reception unit 31 in the transmission system 1.

[0051] The transmission unit 22 and the reception unit 31 each consist of a link layer configuration and a physical layer configuration. In FIGS. 6 and 7, the configuration shown above the solid line L2 is the link layer configuration, and the configuration shown below the solid line L2 is the physical layer configuration.

[0052] Note that the configuration shown above the solid line L1 is the application layer configuration. The application layer includes a system control unit 51, a frame data input unit 52, and a register 53, and a frame data output unit 141, a register 142, and a system control unit 143. The frame data input unit 52 is provided, for example, in the imaging unit 21. The frame data output unit 141 is provided, for example, in the image processing unit 32.

[0053] The system control unit 51 communicates with the LINK-TX protocol management unit 61 of the transmission unit 22 and controls the transmission of image data by providing information regarding the frame format and the like.

[0054] The frame data input unit 52 performs imaging according to an instruction from the user or the like, and supplies the data of each pixel constituting the image obtained by performing the imaging to the Pixel to Byte conversion unit 62 of the transmission unit 22.

[0055] The register 53 stores information such as the number of bits and the number of lanes of Pixel to Byte conversion. The transmission process of the image data is performed according to the information stored in the register 53.

[0056] The frame data output unit 141 generates and outputs an image of one frame based on the pixel data of each line supplied from the reception unit 31. Various processes are performed using the image output from the frame data output unit 141.

[0057] The register 142 stores various setting values related to the reception of image data, such as the number of bits and the number of lanes of Byte to Pixel conversion. The reception process of the image data is performed according to the information stored in the register 142.

[0058] The system control unit 143 communicates with the LINK-RX protocol management unit 121 and controls sequences such as mode change.

[0059] [Configuration of the Link Layer of the Transmission Unit 22] As shown in FIG. 6, the transmission unit 22 is provided with a LINK-TX protocol management unit 61, a Pixel to Byte conversion unit 62, a payload ECC insertion unit 63, a packet generation unit 64, and a lane distribution unit 65 as the configuration of the link layer. The LINK-TX protocol management unit 61 includes a state control unit 71, a header generation unit 72, a data insertion unit 73, and a footer generation unit 74.

[0060] The state control unit 71 of the LINK-TX protocol management unit 61 manages the state of the link layer of the transmission unit 22.

[0061] The header generation unit 72 generates a header to be added to the payload storing pixel data for one line, as shown in FIG. 4 for example, and outputs it to the packet generation unit 64.

[0062] The header generation unit 72 generates header information according to the control by the system control unit 51. For example, information representing the line number of the pixel data output by the frame data input unit 52 and information representing the start and end of the frame are supplied from the system control unit 51 to the header generation unit 72.

[0063] Also, the header generation unit 72 applies the header information to a generation polynomial to calculate a CRC code. The generation polynomial of the CRC code added to the header information is represented by, for example, the following formula (1). CRC16 = X 16 + X 15 + X 2 + 1 ……(1)

[0064] The header generation unit 72 generates a pair of the header information and the CRC code by adding the CRC code to the header information, and generates a header by repeatedly arranging three pairs of the same header information and CRC code. The header generation unit 72 outputs the generated header to the packet generation unit 64.

[0065] The data insertion unit 73 generates data used for stuffing, and outputs it to the Pixel to Byte conversion unit 62 and the lane distribution unit 65. The payload stuffing data, which is the stuffing data supplied to the Pixel to Byte conversion unit 62, is added to the pixel data after Pixel to Byte conversion and is used for adjusting the data amount of the pixel data stored in the payload. Also, the lane stuffing data, which is the stuffing data supplied to the lane distribution unit 65, is added to the data after lane assignment and is used for adjusting the data amount between lanes.

[0066] The footer generation unit 74 calculates a 32-bit CRC code by appropriately applying the payload data to a generation polynomial according to the control by the system control unit 51, and outputs the calculated CRC code as a footer to the packet generation unit 64. The generation polynomial of the CRC code added as a footer is represented by, for example, the following formula (2). CRC32 = X 32 + X 31 + X 4 + X 3 + X + 1 ……(2)

[0067] The Pixel to Byte conversion unit 62 acquires the pixel data supplied from the frame data input unit 52, and performs Pixel to Byte conversion to convert the data of each pixel into data in units of 1 byte. For example, the pixel value (RGB) of each pixel of the image captured by the imaging unit 21 is represented by any number of bits among 8 bits, 10 bits, 12 bits, 14 bits, and 16 bits.

[0068] The Pixel to Byte conversion unit 62 performs Pixel to Byte conversion on each pixel in order, for example, from the pixel at the left end of the line. Further, the Pixel to Byte conversion unit 62 generates payload data by adding the payload stuffing data supplied from the data insertion unit 73 to the pixel data in units of bytes obtained by Pixel to Byte conversion, and outputs it to the payload ECC insertion unit 63.

[0069] The pixel data after Pixel to Byte conversion is grouped into a predetermined number of groups in the order obtained by the conversion. In the link layer of the transmission unit 22, after grouping is performed in this way, processing is performed in parallel on the pixel data at the same position in each group for each period defined by the clock signal. For example, when the pixel data is assigned to 16 groups, the processing of the pixel data is advanced so that the 16 pixel data arranged in each column are processed within the same period.

[0070] As described above, the payload of one packet contains one line of pixel data. Here, the processing of the pixel data in the valid pixel region A1 of FIG. 3 is described, but the pixel data in other regions such as the margin region A2 is also processed together with the pixel data in the valid pixel region A1.

[0071] After the pixel data for one line is grouped, payload stuffing data is added so that the data length of each group becomes the same length. The payload stuffing data is 1-byte data.

[0072] The payload data having such a configuration is supplied from the Pixel to Byte conversion unit 62 to the payload ECC insertion unit 63.

[0073] The payload ECC insertion unit 63 calculates an error correction code used for error correction of the payload data based on the payload data supplied from the Pixel to Byte conversion unit 62, and inserts the parity, which is the error correction code obtained by the calculation, into the payload data. For example, a Reed-Solomon code is used as the error correction code. Note that the insertion of the error correction code is optional. For example, it is possible to perform only one of the insertion of parity by the payload ECC insertion unit 63 and the addition of a footer by the footer generation unit 74.

[0074] In the payload ECC insertion unit 63, basically, for example, 2 bytes of parity are generated based on 224 pixel data, and are inserted following the 224 pixel data.

[0075] The payload ECC insertion unit 63 outputs the payload data with the parity inserted to the packet generation unit 64. When the parity is not inserted, the payload data supplied from the Pixel to Byte conversion unit 62 to the payload ECC insertion unit 63 is output to the packet generation unit 64 as it is.

[0076] The packet generation unit 64 generates a packet by adding the header generated by the header generation unit 72 to the payload data supplied from the payload ECC insertion unit 63. When the footer generation unit 74 generates a footer, the packet generation unit 64 also adds the footer to the payload data.

[0077] The packet generation unit 64 outputs the packet data, which is the data constituting one generated packet, to the lane distribution unit 65. The lane distribution unit 65 is supplied with packet data consisting of header data and payload data, packet data consisting of header data, payload data, and footer data, or packet data consisting of header data and payload data with parity inserted. The packet structure in FIG. 4 is logical, and in the link layer and physical layer, the data of the packet having the structure in FIG. 4 is processed in byte units.

[0078] The lane distribution unit 65 allocates the packet data supplied from the packet generation unit 64 to each lane used for data transmission among Lane0 to Lane7 in order from the head data.

[0079] The lane distribution unit 65 outputs the packet data allocated to each lane to the physical layer. Hereinafter, the case of transmitting data using 8 lanes of Lane0 to Lane7 will be mainly described, but the same processing is performed even when the number of lanes used for data transmission is other numbers.

[0080] [Configuration of the Physical Layer of the Transmission Unit 22] As shown in FIG. 6, the transmission unit 22 is provided with a PHY-TX state control unit 81, a clock generation unit 82, and signal processing units 83-0 to 83-N as the configuration of the physical layer. The signal processing unit 83-0 includes a control code insertion unit 91, an 8B10B symbol encoder 92, a synchronization unit 93, and a transmission unit 94. The packet data assigned to Lane0 output from the lane distribution unit 65 is input to the signal processing unit 83-0, and the packet data assigned to Lane1 is input to the signal processing unit 83-1. Also, the packet data assigned to LaneN is input to the signal processing unit 83-N.

[0081] In this way, the physical layer of the transmission unit 22 is provided with the same number of signal processing units 83-0 to 83-N as the number of lanes, and the processing of the packet data transmitted using each lane is performed in parallel in each of the signal processing units 83-0 to 83-N. The configuration of the signal processing unit 83-0 will be described, but the signal processing units 83-1 to 83-N also have the same configuration.

[0082] The PHY-TX state control unit 81 controls each unit of the signal processing units 83-0 to 83-N. For example, the timing of each process performed by the signal processing units 83-0 to 83-N is controlled by the PHY-TX state control unit 81.

[0083] The clock generation unit 82 generates a clock signal and outputs it to the synchronization units 93 of the signal processing units 83-0 to 83-N respectively.

[0084] The control code insertion unit 91 of the signal processing unit 83-0 adds a control code to the packet data supplied from the lane distribution unit 65. The control code is a code represented by one symbol selected from a plurality of types of symbols prepared in advance or a combination of a plurality of types of symbols. Each symbol inserted by the control code insertion unit 91 is 8-bit data. By performing 8B10B conversion in the subsequent circuit, one symbol inserted by the control code insertion unit 91 becomes 10-bit data. On the other hand, in the receiving unit 31, 10B8B conversion is performed on the received data as described later, but each symbol before 10B8B conversion included in the received data is 10-bit data, and each symbol after 10B8B conversion becomes 8-bit data.

[0085] The control code includes a Start Code, an End Code, etc. shown in FIG. 4. The control code also includes an Idle Code, a Pad Code, a Sync Code, a Deskew Code, and a Standby Code.

[0086] FIG. 8 shows an example of the control code added by the control code insertion unit 91.

[0087] The Idle Code is a group of symbols repeatedly transmitted during periods other than the transmission of packet data. The Idle Code is represented by D00.0 (00000000) of the D Character which is an 8B10B Code.

[0088] The Start Code is a group of symbols indicating the start of a packet. As described above, the Start Code is added before the packet. The Start Code is represented by four symbols, K28.5, K27.7, K28.2, and K27.7, which is a combination of three types of K Characters. An example of the value of each K Character is shown in FIG. 9.

[0089] The End Code is a group of symbols indicating the end of a packet. As described above, the End Code is added at the end of the packet. The End Code is represented by four symbols, K28.5, K29.7, K30.7, and K29.7, which are combinations of three types of K Characters.

[0090] The Pad Code is a group of symbols called padding codes that are inserted into the payload data to fill the difference between the pixel data bandwidth and the PHY transmission bandwidth. The pixel data bandwidth is the transmission rate of pixel data output from the imaging unit 21 and input to the transmission unit 22, and the PHY transmission bandwidth is the transmission rate of pixel data transmitted from the transmission unit 22 and input to the reception unit 31. The Pad Code is represented by four symbols, K23.7, K28.4, K28.6, and K28.7, which are combinations of four types of K Characters.

[0091] Figure 10 shows an example of Pad Code insertion.

[0092] The upper part of Figure 10 shows the payload data assigned to each lane before Pad Code insertion, and the lower part shows the payload data after Pad Code insertion. In the example of Figure 10, Pad Codes are inserted between the third and fourth pixel data from the beginning, between the sixth and seventh pixel data, and between the twelfth and thirteenth pixel data. In this way, the Pad Code is inserted at the same position in the payload data of each lane from Lane0 to Lane7.

[0093] The insertion of the Pad Code for the payload data assigned to Lane0 is performed by the control code insertion unit 91 of the signal processing unit 83-0. Similarly, the insertion of the Pad Code for the payload data assigned to other lanes is performed at the same timing in the signal processing units 83-1 to 83-N, respectively. The number of Pad Codes is determined based on the difference between the pixel data bandwidth and the PHY transmission bandwidth, the frequency of the clock signal generated by the clock generation unit 82, and so on.

[0094] In this way, the Pad Code is inserted to adjust the difference between the two bands when the pixel data band is narrow and the PHY transmission band is wide. For example, by inserting the Pad Code, the difference between the pixel data band and the PHY transmission band is adjusted to fall within a certain range.

[0095] The Sync Code is a group of symbols used to ensure bit synchronization and symbol synchronization between the transmitter 22 and the receiver 31. The Sync Code is represented by two symbols, K28.5 and Any**. Any** indicates that any type of symbol may be used. The Sync Code is repeatedly transmitted, for example, during the training mode before the transmission of packet data starts between the transmitter 22 and the receiver 31.

[0096] The Deskew Code is a group of symbols used to correct the Data Skew between lanes, that is, the shift in the reception timing of the data received by each lane of the receiver 31. The Deskew Code is represented by two symbols, K28.5 and Any**. The correction of the Data Skew between lanes using the Deskew Code will be described later.

[0097] The Standby Code is a group of symbols used to notify the receiver 31 that the output of the transmitter 22 has entered a state such as High-Z (high impedance) and data transmission has stopped. That is, the Standby Code is transmitted to the receiver 31 when the transmission of packet data ends and the Standby state is entered. The Standby Code is represented by two symbols, K28.5 and Any**.

[0098] FIG. 11 shows an example of packet data after control code insertion.

[0099] As shown in FIG. 11, in the signal processing units 83-0 to 83-N, a Start Code is added before the packet data, and a Pad Code is inserted into the payload data, respectively. An End Code is added after the packet data, and a Deskew Code is added after the End Code. In the example of FIG. 11, an Idle Code is added after the Deskew Code.

[0100] The control code insertion unit 91 outputs the packet data with the control code added to the 8B10B symbol encoder 92.

[0101] The 8B10B symbol encoder 92 performs 8B10B conversion on the packet data (packet data with the control code added) supplied from the control code insertion unit 91, and outputs the packet data converted into 10-bit units of data to the synchronization unit 93.

[0102] The synchronization unit 93 outputs each bit of the packet data supplied from the 8B10B symbol encoder 92 to the transmission unit 94 according to the clock signal generated by the clock generation unit 82.

[0103] The transmission unit 94 transmits the packet data supplied from the synchronization unit 93 to the reception unit 31 via the transmission line constituting Lane0. When data transmission is performed using 8 lanes, the packet data is also transmitted to the reception unit 31 using the transmission lines constituting Lane1 to 7.

[0104] [Configuration of the Physical Layer of the Reception Unit 31] As shown in FIG. 7, the receiving unit 31 is provided with a PHY-RX state control unit 101 and signal processing units 102-0 to 102-N as components of the physical layer. The signal processing unit 102-0 includes a receiving unit 111, a clock generation unit 112, a synchronization unit 113, a symbol synchronization unit 114, a 10B8B symbol decoder 115, a skew correction unit 116, and a control code removal unit 117. Packet data transmitted through the transmission line constituting Lane0 is input to the signal processing unit 102-0, and packet data transmitted through the transmission line constituting Lane1 is input to the signal processing unit 102-1. Also, packet data transmitted through the transmission line constituting LaneN is input to the signal processing unit 102-N.

[0105] As described above, the physical layer of the receiving unit 31 is provided with the same number of signal processing units 102-0 to 102-N as the number of lanes, and the processing of the packet data transmitted using each lane is performed in parallel in each of the signal processing units 102-0 to 102-N. The configuration of the signal processing unit 102-0 will be described, but the signal processing units 102-1 to 102-N also have the same configuration.

[0106] The receiving unit 111 receives a signal representing the packet data transmitted from the transmitting unit 22 through the transmission line constituting Lane0 and outputs it to the clock generation unit 112.

[0107] The clock generation unit 112 performs bit synchronization by detecting the edge of the signal supplied from the receiving unit 111 and generates a clock signal based on the edge detection period. The clock generation unit 112 outputs the signal supplied from the receiving unit 111 to the synchronization unit 113 together with the clock signal.

[0108] The synchronization unit 113 samples the signal received in the receiving unit 111 according to the clock signal generated by the clock generation unit 112 and outputs the packet data obtained by the sampling to the symbol synchronization unit 114. The functions of CDR (Clock Data Recovery) are realized by the clock generation unit 112 and the synchronization unit 113.

[0109] The symbol synchronization unit 114 performs symbol synchronization by detecting the control code included in the packet data or by detecting some of the symbols included in the control code. For example, the symbol synchronization unit 114 detects the K28.5 symbols included in the Start Code, End Code, and Deskew Code to perform symbol synchronization. The symbol synchronization unit 114 outputs the packet data in 10-bit units representing each symbol to the 10B8B symbol decoder 115.

[0110] Also, the symbol synchronization unit 114 performs symbol synchronization by detecting the boundaries of the symbols included in the Sync Code repeatedly transmitted from the transmitter 22 during the training mode before the transmission of the packet data starts.

[0111] The 10B8B symbol decoder 115 performs 10B8B conversion on the packet data in 10-bit units supplied from the symbol synchronization unit 114, and outputs the packet data converted into 8-bit units to the skew correction unit 116.

[0112] The skew correction unit 116 detects the Deskew Code from the packet data supplied from the 10B8B symbol decoder 115. Information on the detection timing of the Deskew Code by the skew correction unit 116 is supplied to the PHY-RX state control unit 101.

[0113] Also, the skew correction unit 116 corrects the Data Skew between lanes so that the timing of the Deskew Code matches the timing represented by the information supplied from the PHY-RX state control unit 101. Information representing the latest timing among the detection timings of the Deskew Code detected in each of the signal processing units 102-0 to 102-N is supplied from the PHY-RX state control unit 101.

[0114] The skew correction unit 116 outputs the packet data with corrected data skew to the control code removal unit 117.

[0115] The control code removal unit 117 removes the control code added to the packet data and outputs the data between the start code and the end code as packet data to the link layer.

[0116] The PHY-RX state control unit 101 controls each of the signal processing units 102-0 to 102-N to correct data skew between lanes. Also, when a transmission error occurs in a predetermined lane and the control code is lost, the PHY-RX state control unit 101 performs error correction of the control code by adding the control code transmitted on another lane in place of the lost control code.

[0117] [Configuration of the link layer of the receiving unit 31] As shown in FIG. 7, the receiving unit 31 is provided with a LINK-RX protocol management unit 121, a lane integration unit 122, a packet separation unit 123, a payload error correction unit 124, and a byte to pixel conversion unit 125 as the configuration of the link layer. The LINK-RX protocol management unit 121 includes a state control unit 131, a header error correction unit 132, a data removal unit 133, and a footer error detection unit 134.

[0118] The lane integration unit 122 integrates the packet data supplied from the signal processing units 102-0 to 102-N of the physical layer by rearranging it in the reverse order of the distribution order to each lane by the lane distribution unit 65 of the transmitting unit 22.

[0119] When integrating the packet data of each lane, the lane stuffing data is removed by the lane integration unit 122 according to the control by the data removal unit 133. The lane integration unit 122 outputs the integrated packet data to the packet separation unit 123.

[0120] The packet separation unit 123 separates the packet data for one packet integrated by the lane integration unit 122 into packet data constituting header data and packet data constituting payload data. The packet separation unit 123 outputs the header data to the header error correction unit 132 and outputs the payload data to the payload error correction unit 124.

[0121] Also, when the packet includes a footer, the packet separation unit 123 separates the data for one packet into packet data constituting header data, packet data constituting payload data, and packet data constituting footer data. The packet separation unit 123 outputs the header data to the header error correction unit 132 and outputs the payload data to the payload error correction unit 124. Further, the packet separation unit 123 outputs the footer data to the footer error detection unit 134.

[0122] When parity is inserted into the payload data supplied from the packet separation unit 124, the payload error correction unit 124 detects an error in the payload data by performing an error correction operation based on the parity and corrects the detected error.

[0123] The payload error correction unit 124 outputs the pixel data after error correction obtained by performing error correction on each Basic Block and Extra Block to the Byte to Pixel conversion unit 125. When parity is not inserted into the payload data supplied from the packet separation unit 123, the payload data supplied from the packet separation unit 123 is directly output to the Byte to Pixel conversion unit 125.

[0124] The Byte to Pixel conversion unit 125 removes the payload stuffing data included in the payload data supplied from the payload error correction unit 124 according to the control by the data removal unit 133.

[0125] Also, the Byte to Pixel conversion unit 125 performs Byte to Pixel conversion that converts the data of each pixel in byte units obtained by removing the payload stuffing data into pixel data in units of, for example, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits. In the Byte to Pixel conversion unit 125, conversion reverse to the Pixel to Byte conversion by the Pixel to Byte conversion unit 62 of the transmission unit 22 is performed.

[0126] The Byte to Pixel conversion unit 125 outputs the pixel data in units of, for example, 8 bits, 10 bits, 12 bits, 14 bits, or 16 bits obtained by the Byte to Pixel conversion to the frame data output unit 141. In the frame data output unit 141, for example, each line of valid pixels specified by Line Valid of the header information is generated based on the pixel data obtained by the Byte to Pixel conversion unit 125, and an image of one frame is generated by arranging each line according to the Line Number of the header information.

[0127] The state control unit 131 of the LINK-RX protocol management unit 121 manages the state of the link layer of the reception unit 31.

[0128] The header error correction unit 132 acquires three sets of a combination of header information and a CRC code based on the header data supplied from the packet separation unit 123. The header error correction unit 132 performs an error detection calculation, which is an operation for detecting an error in the header information, on each set of the combination of the header information and the CRC code using the CRC code of the same set as the header information.

[0129] Further, the header error correction unit 132 infers correct header information based on at least one of the error detection result of each set of header information and the comparison result of the data obtained by the error detection calculation, and outputs the header information inferred to be correct and the decoding result. The data obtained by the error detection calculation is a value obtained by applying the CRC generation polynomial to the header information. Further, the decoding result is information indicating decoding success or decoding failure.

[0130] Let the three sets of header information and CRC codes be set 1, set 2, and set 3, respectively. In this case, the header error correction unit 132 obtains, by the error detection calculation for set 1, whether there is an error in the header information of set 1 (error detection result) and data 1 which is the data obtained by the error detection calculation. Further, the header error correction unit 132 obtains, by the error detection calculation for set 2, whether there is an error in the header information of set 2 and data 2 which is the data obtained by the error detection calculation. The header error correction unit 132 obtains, by the error detection calculation for set 3, whether there is an error in the header information of set 3 and data 3 which is the data obtained by the error detection calculation.

[0131] Further, the header error correction unit 132 determines whether data 1 and data 2 match, whether data 2 and data 3 match, and whether data 3 and data 1 match, respectively.

[0132] For example, when no error is detected by any of the error detection calculations for sets 1, 2, and 3 and all the comparison results of the data obtained by the error detection calculation match, the header error correction unit 132 selects, as the decoding result, information indicating decoding success. Further, the header error correction unit 132 infers that all the header information is correct and selects any one of the header information of set 1, the header information of set 2, and the header information of set 3 as the output information.

[0133] On the other hand, if no error is detected only in the error detection calculation for Group 1, the header error correction unit 132 selects information indicating successful decoding as the decoding result, presumes that the header information of Group 1 is correct, and selects the header information of Group 1 as the output information.

[0134] Also, if no error is detected only in the error detection calculation for Group 2, the header error correction unit 132 selects information indicating successful decoding as the decoding result, presumes that the header information of Group 2 is correct, and selects the header information of Group 2 as the output information.

[0135] If no error is detected only in the error detection calculation for Group 3, the header error correction unit 132 selects information indicating successful decoding as the decoding result, presumes that the header information of Group 3 is correct, and selects the header information of Group 3 as the output information.

[0136] The header error correction unit 132 outputs and stores the decoding result and the output information selected as described above in the register 142. In this way, the error correction of the header information by the header error correction unit 132 is performed by detecting the error-free header information from among a plurality of header information using the CRC code and outputting the detected header information.

[0137] The data removal unit 133 controls the lane integration unit 122 to remove the lane stuffing data and controls the Byte to Pixel conversion unit 125 to remove the payload stuffing data.

[0138] The footer error detection unit 134 acquires the CRC code stored in the footer based on the footer data supplied from the packet separation unit 123. The footer error detection unit 134 performs an error detection calculation using the acquired CRC code and detects an error in the payload data. The footer error detection unit 134 outputs the error detection result and stores it in the register 142.

[0139] [Overview of the Operations of the Sensor Module 11 and the DSP 12] Next, an overview of the operations of the sensor module 11 and the DSP 12 will be described. The operation of the imaging device having the transmission system 1 will be described as an example.

[0140] In the imaging unit 21 of the sensor module 11, for example, imaging is performed when an instruction to start imaging is given, such as when a shutter button provided on the imaging device is pressed. The frame data input unit 52 (FIG. 6) of the imaging unit 21 outputs the pixel data constituting one frame of the image obtained by imaging to the transmission unit 22 one pixel data at a time in order.

[0141] By the data transmission process performed by the transmission unit 22, a packet in which pixel data for one line is stored in the payload is generated, and the packet data constituting the packet is transmitted to the reception unit 31.

[0142] In the reception unit 31, data reception processing is performed. By the data reception processing, the packet data transmitted from the transmission unit 22 is received, and the pixel data stored in the payload is output to the image processing unit 32.

[0143] The data transmission process performed by the transmission unit 22 and the data reception process performed by the reception unit 31 are alternately performed for the pixel data for one line. That is, when the pixel data for a certain line is transmitted by the data transmission process, the data reception process is performed, and when the pixel data for one line is received by the data reception process, the data transmission process is performed for the pixel data for the next line. The data transmission process performed by the transmission unit 22 and the data reception process performed by the reception unit 31 may be performed in parallel in time as appropriate.

[0144] When the transmission and reception of the pixel data for all the lines constituting one frame of the image are completed, the frame data output unit 141 of the image processing unit 32 generates one frame of the image based on the pixel data supplied from the reception unit 31.

[0145] [1.3 Improvement Example of the Transmission System 1 According to an Embodiment] As described with reference to FIGS. 8 to 11, in the transmission system 1 according to one embodiment, in order to fill the difference in the transmission bandwidth between the transmission rate of the pixel data (pixel data bandwidth) input from the imaging unit 21 to the transmission unit 22 and the transmission rate of the pixel data (PHY transmission bandwidth) transmitted from the transmission unit 22 and input to the reception unit 31, it is possible to insert a Pad Code into the payload data. The insertion rate of the Pad Code is determined by the operation of the sensor module 11 on the transmission side. However, on the reception side, the DSP 12 does not have a means to know the insertion rate of the Pad Code, and it is necessary to adopt a configuration that can receive any inserted Pad Code.

[0146] Therefore, hereinafter, as an improvement example of the transmission system 1 according to one embodiment, a technique that enables the reception side to know the insertion rate of the Pad Code will be described.

[0147] Note that the Pad Code is inserted into the payload when the PHY transmission bandwidth is larger than the pixel data bandwidth and a predetermined condition is satisfied. The Pad Code is inserted, for example, when the following conditional expression (A) is satisfied. CIS_Bandwidth×(57 / 56)×(5 / 4)<PHY_Bandwidth ……(A)

[0148] Here, in the conditional expression (A), CIS_Bandwidth corresponds to the pixel data bandwidth input from the imaging unit 21 to the transmission unit 22 and is represented by the following conditional expression (B). CIS_Bandwidth=pixel_clock_rate*PIXEL_BIT ……(B) However, pixel_clock_rate: Pixel input rate [Mpix / sec] PINXEL_BIT: Number of bits per pixel Let it be so.

[0149] In the conditional expression (A), PHY_Bandwidth corresponds to the PHY transmission bandwidth of the pixel data transmitted from the transmission unit 22 and input to the reception unit 31, and is represented by the following conditional expression (C). PHY_Bandwidth = output_bit_rate * Lane_NUM ……(C) However, Output_bit_rate: Output bit rate [bit / sec] Lane_NUM: Number of output lanes shall be as such.

[0150] In the conditional expression (A), (57 / 56) is the data transmission efficiency when 4-bit parity bits are added, and is calculated as follows. (224 + 4) / 224 = 57 / 56

[0151] In the conditional expression (A), (5 / 4) is the transmission efficiency of the data subjected to 8B10B conversion, and is calculated as follows. 10 / 8 = 5 / 4

[0152] FIG. 12 shows a first example of an improvement example of the transmission unit 22 in the transmission system 1 according to an embodiment.

[0153] In the first example shown in FIG. 12, with respect to the configuration shown in FIG. 6, an insertion rate calculation unit 75 for calculating the insertion rate of the Pad Code is added in the LINK-TX protocol management unit 61 of the transmission unit 22.

[0154] Note that the insertion rate of the Pad Code indicates the ratio of the Pad Code length to the payload length. As described above, the Pad Code is inserted by the control code insertion unit 91 after the data is lane-allocated.

[0155] FIG. 13 shows an example in which data indicating the insertion rate of the Pad Code is added to the header.

[0156] Data indicating the insertion rate of the Pad Code calculated by the insertion rate calculation unit 75 can be added to the Reserved area in the header, as shown in FIG. 13, for example. The header generation unit 72 generates a header with data indicating the insertion rate of the Pad Code added to the Reserved area, for example.

[0157] In this case, the receiving unit 31 can receive a packet including data indicating the insertion rate of the Pad Code in the header via the lane. As a result, on the receiving side, it becomes possible to know the insertion rate of the Pad Code in, for example, the frame data output unit 141 and the system control unit 143.

[0158] FIG. 14 shows a second example of an improvement example of the transmission unit 22 in the transmission system 1 according to an embodiment.

[0159] Data indicating the insertion rate of the Pad Code calculated by the insertion rate calculation unit 75 may be stored in the register 53 on the transmission side, as shown in FIG. 14, for example. The register 53 can output data indicating the insertion rate of the Pad Code to the receiving side via a path different from the lane that is the transmission path of the packet. The path different from the lane may be, for example, the control line 13 shown in FIGS. 1 and 2. On the receiving side, data indicating the insertion rate of the Pad Code may be received via a path different from the transmission path of the packet and stored in the register 142 on the receiving side. As a result, on the receiving side, it becomes possible to know the insertion rate of the Pad Code in, for example, the frame data output unit 141 and the system control unit 143. Note that the data storing the insertion rate of the Pad Code may be other than the register 142. For example, the frame data output unit 141 or the system control unit 143 may store the data indicating the insertion rate.

[0160] FIG. 15 shows a third example of an improvement example of the transmission unit 22 in the transmission system 1 according to an embodiment.

[0161] Also, data indicating the insertion rate of the Pad Code calculated by the insertion rate calculation unit 75 can be added to the Embedded Data area, for example, as shown in FIG. 15. Note that FIG. 15 shows an example where the Embedded Data area is in the pre-dummy area A3, but the Embedded Data area may be inserted in the post-dummy area A4. The packet generation unit 64 generates, for example, a packet with data indicating the insertion rate of the Pad Code added to the Embedded Data area.

[0162] In this case, the receiving unit 31 can receive, via the lane, a packet including data indicating the insertion rate of the Pad Code in the dummy area. As a result, on the receiving side, for example, in the frame data output unit 141 and the system control unit 143, it becomes possible to know the insertion rate of the Pad Code.

[0163] [1.3 Effects] As described above, according to the improvement example of the transmission system 1 according to an embodiment, since it is configured to be able to know the insertion rate of the Pad Code, it becomes possible to perform optimal data processing. On the receiving side, for example, in the frame data output unit 141 and the system control unit 143, it becomes possible to know the insertion rate of the Pad Code and the payload length.

[0164] Note that the effects described in this specification are merely examples and are not limiting, and there may be other effects. The same applies to the effects of other embodiments hereinafter.

[0165] <2. Other Embodiments> The technology according to the present disclosure is not limited to the description of the above embodiment, and various modifications can be made.

[0166] For example, the present technology can also have the following configuration. According to the present technology with the following configuration, since it is configured to be able to know the insertion rate of the padding code, it becomes possible to perform optimal data processing.

[0167] (1) A transmission unit that can output a plurality of packets including pixel data for one line constituting an image of one frame in a payload and adding a header to the payload to a transmission path, An insertion rate calculation unit that can calculate an insertion rate of padding codes inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path comprising transmission device. (2) A header generation unit that can add data indicating the insertion rate of the padding code calculated by the insertion rate calculation unit to the header, further comprising the transmission device according to (1) above. (3) A register that can store data indicating the insertion rate of the padding code calculated by the insertion rate calculation unit, further comprising the transmission device according to (1) above. (4) The register can output data indicating the insertion rate of the padding code to a receiving device that can receive the packet via the transmission path through a path different from the transmission path of the packet the transmission device according to (3) above. (5) A packet generation unit that can generate a packet including a dummy area in the payload instead of the pixel data and add data indicating the insertion rate of the padding code to the dummy area, further comprising the transmission device according to (1) above. (6) The padding code is inserted into the payload when the transmission rate of the pixel data output from the transmission unit to the transmission path is greater than the transmission rate of the pixel data input to the transmission unit and satisfies a predetermined condition The transmission device according to any one of (1) to (5) above. (7) A receiving unit capable of receiving, via a transmission path, a plurality of packets including pixel data for one line constituting one frame of an image in a payload and having a header added to the payload and data on an insertion rate of padding codes inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path is receivable from the transmission device Receiving device. (8) The receiving unit is capable of receiving, via the transmission path, a packet including data on an insertion rate of the padding code The receiving device according to (7) above. (9) Data indicating an insertion rate of the padding code can be received via a path different from a transmission path of the packet The receiving device according to (7) above. (10) A transmission device and a receiving device and The transmission device includes a transmission unit capable of outputting, to a transmission path, a plurality of packets including pixel data for one line constituting one frame of an image in a payload and having a header added to the payload, and an insertion rate calculation unit capable of calculating an insertion rate of padding codes inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path and is provided with (11) The receiving device includes a receiving unit capable of receiving, via the transmission path, the plurality of packets from the transmission unit of the transmission device and Data on the insertion rate of the padding code can be received from the transmitting device. The transmission system according to (10) above.

[0168] This application claims priority based on Japanese Patent Application No. 2019-209580, filed with the Japan Patent Office on November 20, 2019, and incorporates by reference all of the contents of this application.

[0169] Those skilled in the art can conceive of various modifications, combinations, sub - combinations, and changes according to design requirements and other factors, and it is understood that they are included within the scope of the appended claims and their equivalents.

Claims

1. A transmission unit that can output a plurality of packets including pixel data for one line constituting an image of one frame in a payload and adding a header to the payload to a transmission path; An insertion rate calculation unit that can calculate an insertion rate of padding codes inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path; A header generation unit that can add data indicating the insertion rate of the padding codes calculated by the insertion rate calculation unit to the header Comprising A transmission device.

2. A transmission unit that can output a plurality of packets including pixel data for one line constituting an image of one frame in a payload and adding a header to the payload to a transmission path; An insertion rate calculation unit that can calculate an insertion rate of padding codes inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path; A register that can store data indicating the insertion rate of the padding codes calculated by the insertion rate calculation unit Comprising The register can output data indicating the insertion rate of the padding codes to a receiving device that can receive the packets via the transmission path through a path different from the transmission path of the packets A transmission device.

3. A transmission unit that can output a plurality of packets including pixel data for one line constituting an image of one frame in a payload and adding a header to the payload to a transmission path; An insertion rate calculation unit that can calculate an insertion rate of padding codes inserted into the payload to fill a difference between a transmission rate of the pixel data input to the transmission unit and a transmission rate of the pixel data output from the transmission unit to the transmission path; A packet generation unit that can generate a packet including a dummy area in the payload instead of the pixel data and add data indicating the insertion rate of the padding codes to the dummy area Comprising A transmission device.

4. The padding codes are inserted into the payload when the transmission rate of the pixel data output from the transmission unit to the transmission path is greater than the transmission rate of the pixel data input to the transmission unit and satisfies a predetermined condition The transmission device according to any one of Claims 1 to 3.

5. A plurality of packets including pixel data for one line constituting an image of one frame in a payload and having a header added to the payload are receivable by a receiving unit from a transmitting unit of a transmitting device via a transmission path. The receiving unit is provided. Data on the insertion rate of padding codes inserted into the payload to fill the difference between the transmission rate of the pixel data input to the transmitting unit and the transmission rate of the pixel data output from the transmitting unit to the transmission path is receivable from the transmitting device. A receiving device. **Claim 6** The receiving unit can receive a packet including data on the insertion rate of the padding code via the transmission path. The receiving device according to claim 5. **Claim 7** Data indicating the insertion rate of the padding code can be received via a path different from the transmission path of the packet. The receiving device according to claim 5. **Claim 8** A transmitting device and a receiving device are included. The transmitting device includes: a transmitting unit capable of outputting a plurality of packets including pixel data for one line constituting an image of one frame in a payload and having a header added to the payload to a transmission path; and an insertion rate calculation unit capable of calculating the insertion rate of padding codes inserted into the payload to fill the difference between the transmission rate of the pixel data input to the transmitting unit and the transmission rate of the pixel data output from the transmitting unit to the transmission path. The transmitting device is provided. The receiving device includes: a receiving unit capable of receiving the plurality of packets from the transmitting unit of the transmitting device via the transmission path. The receiving device is provided. Data on the insertion rate of the padding code is receivable from the transmitting device. A transmission system.

Images