Reference voltage generator

Abstract

To provide a reference voltage circuit device in which consumption current and an influence of external stress are suppressed.SOLUTION: A reference voltage circuit device includes a current mirror circuit formed of a first transistor 35 and a second transistor 36, a constant current circuit 101 that outputs constant current, a voltage generation circuit 102 that uses the constant current as input current and generates output voltage based on the input current, and a reference voltage output terminal 3 that outputs the output voltage. The constant current circuit 101 has a plurality of depression type MOS transistors D11 to D1n connected in series. Each gate width is the same and the total of the gate lengths is the total gate length of the constant current circuit. The voltage generation circuit 102 has a plurality of enhanced type MOS transistors E1 to E1m connected in series. Each gate width is the same and the total of the gate lengths is the total gate length of the voltage generation circuit. The transistor size of each of the depression type MOS transistors and the enhanced type MOS transistors is determined so that the influence of stress is suppressed.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to a reference voltage Generation device.

Background Art

[0002] A reference voltage circuit widely used in analog processing circuits is required to have a high stability of the output reference voltage and a low current consumption. (Patent Document 1)

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the above Patent Document 1 aims to improve the yield by compensating for temperature characteristics and correcting manufacturing process variations.

[0005] Generally, in order to reduce the current consumption, the channel length of the transistors constituting the reference voltage circuit is increased to suppress the drain current. However, when the channel length is increased, its electrical characteristics are easily affected by external stresses other than the semiconductor chip, such as the shrinkage of the resin in the resin encapsulation forming process in a subsequent process, and there is a problem that the stability of the reference voltage decreases.

Means for Solving the Problems

[0006] In order to solve the above problems, the present invention provides a current mirror circuit configured such that the gates of a first transistor and a second transistor are commonly connected, the drain of the first transistor is connected to the gate, and the sources of the first transistor and the second transistor are connected to a power supply terminal, and A constant current circuit that outputs a constant current with respect to an input voltage, A voltage generation circuit that uses the constant current as an input current and generates an output voltage based on the input current, A reference voltage output terminal that outputs the output voltage, A reference voltage generation device comprising The drain of the first transistor that outputs the input voltage is connected to the constant current circuit, and the drain of the second transistor that outputs the input current is connected to the voltage generation circuit and the reference voltage Output terminal, The constant current circuit includes a depletion-type MOS transistor circuit, The depletion-type MOS transistor circuit has a total gate width and a total gate length of the depletion-type MOS transistor circuit, The depletion-type MOS transistor circuit includes n (n is an integer 2, 3, 4, ···) depletion-type MOS transistors, From the first depletion-type MOS transistor to the nth The nth depletion-type MOS transistors are connected in series, The first depletion-type MOS transistor has a first gate width and a first gate length, and its gate and source are connected to a ground terminal, The nth depletion-type MOS transistor has the first gate width and an nth gate length, and its drain is connected to the drain of the first transistor Of the rain, The voltage generation circuit includes an enhancement-type MOS transistor circuit, The enhancement-type MOS transistor circuit has a total gate width and a total gate length of the enhancement-type MOS transistor circuit, The enhancement-type MOS transistor circuit includes m (m is an integer 2, 3, 4, ···) enhancement-type MOS transistors The included, From the first enhancement-type MOS transistor to the mth The mth enhancement-type MOS transistors are connected in series, The first enhancement-type MOS transistor has the first gate width and a gate length of E1, and the drain and the gate are connected to the second transistor Of the rain and the reference voltage Output terminals, The m-th enhancement-type MOS transistor has the first gate width and a gate length of Em, and the source is connected to the ground terminal. The first gate width is the total gate width of the depletion-type MOS transistor circuit and the total gate width of the enhancement-type MOS transistor circuit. The sum of the first gate length to the n-th gate length is the total gate length of the depletion-type MOS transistor circuit. From the gate length of E1 to the The The sum of the gate lengths of Em is the total gate length of the enhancement-type MOS transistor circuit, and it is a reference voltage generation device.

Effect of the Invention

[0007] A reference voltage device that suppresses the influence of the consumption current and external stress is provided. Generation is provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The drawings used in the following description may be partially omitted for easy understanding of the features of the present invention, and may be different from the actual ones. In each drawing, the same components are denoted by the same reference numerals, and detailed descriptions of overlapping parts are omitted.

[0010] FIG. 10 is a circuit diagram showing a reference voltage generator 100 according to an embodiment of the present invention.

[0011] In an analog processing circuit, output characteristics such as the output voltage and current are affected by the electrical characteristics of the transistors that make up the analog processing circuit. For example, the reference voltage generator 100 includes a depletion-type NMOS transistor 101 that outputs a constant current and an enhancement-type NMOS transistor that outputs a voltage corresponding to the constant current value. The reference voltage Vref output by the reference voltage generator is determined by electrical characteristics such as the threshold voltage and mutual conductance of the depletion-type NMOS transistor and the enhancement-type NMOS transistor.

[0012] The analog processing circuit is required to always maintain stable characteristics against various external fluctuations. A typical external fluctuation factor is temperature. For the MOS transistors that make up the analog processing circuit, it is desirable that the electrical fluctuations with respect to temperature are sufficiently small compared to the allowable values. Also, when the temperature fluctuation of the MOS transistor exceeds the allowable value, by means of circuit design, the temperature fluctuations of the individual MOS transistors are offset to suppress the temperature fluctuations as the output characteristics.

[0013] In recent years, in addition to temperature fluctuations, an external factor that has become prominent is the stress applied from the outside. For example, when encapsulating a semiconductor chip including an analog processing circuit with a thermosetting resin, according to the coefficient of linear expansion of the thermosetting resin, a shrinkage stress is applied to the semiconductor chip during curing. The semiconductor chip is formed of a semiconductor material such as silicon, but since their coefficients of linear expansion are different, stress due to the difference in shrinkage occurs between the thermosetting resin and the semiconductor chip. The stress causes strain in the channel within the transistor composed of silicon, and causes characteristic fluctuations of the transistor due to the piezoresistive effect of silicon. Therefore, electrical trimming may be performed to adjust the output characteristics of the analog processing circuit for the semiconductor device completed through the resin encapsulation process.

[0014] The inventor has newly found that when a semiconductor chip is externally stressed, the influence on MOS transistors can be suppressed. Based on this finding, an analog processing circuit with suppressed characteristic variations against stress has been realized. This finding will be described below.

[0015] Characteristic variations of silicon due to stress generally include variations in impurity concentration due to changes in the bandgap and variations in carrier mobility due to changes in the lattice spacing. In many cases, since a large amount of impurities are implanted into silicon during manufacturing, the influence of mobility variations is significant in the electrical characteristics of MOS transistors.

[0016] FIG. 9 shows, for the drain current that is greatly affected by mobility in the electrical characteristics of a MOS transistor, the change rate (ΔId change rate / [−100 Mpa]) of the variation amount (ΔId) of the drain current when a constant stress (100 Mpa) is applied, with the channel length L (horizontal axis) and channel width W (vertical axis) of the MOS transistor as parameters, viewed from above at a gate voltage of 0.6V.

[0017] In FIG. 9, the ○ symbol indicates that the absolute value of the ΔId change rate is │−1.6%│ or less. The ▲ symbol indicates that the absolute value of the ΔId change rate is greater than │−1.6%│ and less than │−3.1%│. The × symbol indicates that the absolute value of the ΔId change rate is greater than -3.1% │.

[0018] More specifically, if the gate width W is 5 μm or less and the gate length is 25 μm or less, the change rate (ΔId change rate / [−100 Mpa]) of the variation amount of the drain current is less than the absolute value │−3.1%│. Furthermore, if the gate width W is 2.5 μm or less and the gate length is 1.5 μm or less, the change rate (ΔId change rate / [−100 Mpa]) of the variation amount of the drain current is │−1.6%│ or less in absolute value. That is, it can be seen that the smaller the channel length L (μm) and channel width W (μm), that is, the smaller the channel size of the MOS transistor, the smaller the variation rate of the drain current amount due to stress.

[0019] Therefore, it can be understood that by combining MOS transistors with a small channel size to form a channel size comparable to that of a transistor with a large channel size, the influence of stress can be greatly reduced.

Embodiment

[0020] Referring to FIGS. 1 to 3, a reference voltage generator according to a first embodiment of the present invention will be described.

[0021] As shown in FIG. 1, the reference voltage generator of this embodiment includes a constant current circuit 101 that outputs a constant current with respect to an input voltage VDD, a voltage generation circuit 102 that is connected in series to the constant current circuit 101, uses the constant current as an input current, and generates an output voltage based on the input current, and a reference voltage output terminal 3 that outputs the output voltage. The reference voltage generator 100 includes a depletion-type NMOS transistor circuit, and the transistor size of the depletion-type NMOS transistor circuit is a total gate width Wd and a total gate length Ld. The constant current circuit 101 serially connects n depletion-type NMOS transistors from depletion-type NMOS transistor D11 to D1n. The gate and source of depletion-type NMOS transistor D11 are connected, and the source is connected to the reference voltage output terminal 3.

[0022] The drain of depletion-type NMOS transistor D1n is connected to the input voltage VDD, and the source is connected to the drain of depletion-type NMOS transistor D1n-1. The gate widths of depletion-type NMOS transistors D11 to D1n are the same gate width Wd1, and the gate lengths are Ld11, Ld12, Ld13 ··· Ld1n, respectively.

[0023] Also, the gates of depletion-type NMOS transistors D11 to D1n are connected to the sources of the respective depletion-type NMOS transistors. Can be .

[0024] The voltage generation circuit 102 includes an enhancement-type NMOS transistor circuit, and the transistor size of the enhancement-type NMOS transistor circuit is the total gate width We and the total gate length Le.

[0025] And the voltage generation circuit 102 has m enhancement-type NMOS transistors E11 to E1m connected in series. The gate and drain of the enhancement-type NMOS transistor E11 are connected, and the drain is connected to the reference voltage output terminal 3. The source of the enhancement-type NMOS transistor E1m is connected to the ground terminal 2, and the drain is connected to the source of the enhancement-type NMOS transistor E1m-1.

[0026] The gate widths of the enhancement-type NMOS transistors E11 to E1m are the same gate width We1, and the gate lengths are Le11, Le12, Le13 ··· Le1m respectively. Also, the gates of the enhancement-type NMOS transistors E11 to E1n are connected to the drains of the respective enhancement-type NMOS transistors. Can be.

[0027] The total gate width Wd of the depletion-type NMOS transistor circuit, the gate width Wd1 of the depletion-type NMOS transistor, the total gate width We of the enhancement-type NMOS transistor circuit, and the gate width We1 of the enhancement-type NMOS transistor are equal (Wd = Wd1 = We = We1).

[0028] The total gate length Ld of the depletion-type NMOS transistor circuit is equal to the sum of the gate lengths (Ld11, Ld12, Ld13 ··· Ld1n) of the depletion-type NMOS transistors (Ld = Ld11 + Ld12 + Ld13 + ··· + Ld1n).

[0029] The total gate length Le of the enhancement-type NMOS transistor circuit is equal to the sum of the gate lengths (Le11, Le12, Le13 ··· Le1m) of the enhancement-type NMOS transistors (Le = Le11 + Le12 + Le13 + ··· + Le1m).

[0030] Then, when the gate width Wd1 of the depletion-type NMOS transistor and the gate width We1 of the enhancement-type NMOS transistor are set to 5 μm or less, and the gate lengths (Ld11, Ld12, Ld13 ··· Ld1n) of the depletion-type NMOS transistor and the gate lengths (Le11, Le12, Le13 ··· Le1m) of the enhancement-type NMOS transistor are set to 25 μm or less, the fluctuation rate of the drain current of each MOS transistor due to the influence of external stress becomes small, so that the power consumption is suppressed and a reference voltage with the influence of external stress suppressed can be provided. Generation An apparatus can be provided.

[0031] Specific reference voltage Generation In the apparatus, when the total gate width Wd of the depletion-type NMOS transistor circuit is 5 μm, the total gate length Ld is 100 μm, the total gate width We of the enhancement-type NMOS transistor circuit is 5 μm, and the total gate length Le is 75 μm, the gate widths Wd = Wd1 = We = We1 = 5 μm. For the depletion-type NMOS transistor circuit, n = 4, the gate lengths Ld11 = Ld12 = Ld13 = Ld14 = 25 μm. For the enhancement-type NMOS transistor circuit, m = 3, and the gate lengths Le11 = Le12 = Le13 = 25 μm, a reference voltage with the power consumption suppressed and the influence of external stress suppressed can be provided. Generation An apparatus can be provided.

[0032] When it is desired to further suppress the influence of external stress, for the gate length, for the depletion-type NMOS transistor circuit, n = 50, the gate lengths Ld11 = Ld12 = Ld13 ··· = Ld150 = 2 μm. For the enhancement-type NMOS transistor circuit, m = 38, and the gate lengths Le11 = Le12 = Le13 ··· = Le137 = 2 μm, Le138 = 1 μm are appropriate.

[0033] FIG. 2 shows, as a modified form of the first embodiment, In Figure 1 a reference voltage device in which the gates of depletion-type NMOS transistors D11 to D1n are commonly connected, and the gates of enhancement-type NMOS transistors E11 to E1m are commonly connected, from a depletion-type NMOS transistor D11. Generation It is a device.

[0034] FIG. 3 shows the In Figure 1 reference voltage device in the case of n = 2 and m = 2 according to the first embodiment. Generation In this case, the gate widths Wd = Wd1 = We = We1 = 5 μm, the gate lengths of the depletion-type NMOS transistors Ld11 = Ld12 = 25 μm, and the gate lengths of the enhancement-type NMOS transistors Le11 = Le12 = 25 μm. The gate length may be even smaller.

Example

[0035] With reference to FIGS. 4 to 8, a reference voltage generator 200 according to a second embodiment of the present invention will be described.

[0036] FIG. 4 shows, in addition to depletion-type NMOS transistors D11 to D1n connected in series to the first column of the constant current circuit 101 having the configuration of FIG. 1, and enhancement-type NMOS transistors E11 to E1m connected in series to the first column of the voltage generation circuit 102, the constant current circuit 101 includes n depletion-type NMOS transistors D11 to D1n connected in series in the first column, and the second column, the third column,..., the pth column (p is an integer of 2 or more) are connected in parallel. The second column is composed of n depletion-type NMOS transistors D21 to D2n connected in series, and the pth column is composed of n depletion-type NMOS transistors Dp1 to Dpn connected in series. The respective depletion-type NMOS transistors D11 to D1n, D21 to D2n,..., Dp1 to Dpn have their gates and sources connected. The sources of the depletion-type NMOS transistors D11, D21,..., Dp1 in the first row are connected to the reference voltage output terminal 3, and the drains of the depletion-type NMOS transistors D1n, D2n,..., Dpn in the nth row are connected to the input voltage VDD.

[0037] The voltage generation circuit 102 connects, in parallel, the m enhancement-mode NMOS transistors E11 to E1m connected in series in the first column, the second column, the third column, ···, the pth column (p is an integer of 2 or more). The second column is composed of m enhancement-mode NMOS transistors E21 to E2m connected in series, and the pth column is composed of m enhancement-mode NMOS transistors Ep1 to Epm connected in series. The respective gates and drains of the enhancement-mode NMOS transistors E11 to E1m, E21 to E2m, ···, Ep1 to Epm are connected. The drains of the enhancement-mode NMOS transistors E11, E21, ···, Ep1 in the first row are connected to the reference voltage output terminal 3, and the sources of the enhancement-mode NMOS transistors E1m, E2m, ···, Epm in the mth row are connected to the ground terminal 2.

[0038] The gate widths of the depletion-mode NMOS transistors Dp1 to Dpn are the same gate width Wdp, and the gate lengths are the same gate lengths corresponding to the depletion-mode NMOS transistors in the first column (Ld11 = Ld21 = ··· = Ldp1, Ld12 = Ld22 = ··· = Ldp2, Ld1n = Ld2n = ··· = Ldpn).

[0039] The gate widths of the enhancement-mode NMOS transistors Ep1 to Epm are the same gate width Wep, and the gate lengths are the same gate lengths corresponding to the enhancement-mode NMOS transistors in the first column (Le11 = Le21 = ··· = Lep1, Le12 = Le22 = ··· = Lep2, Le13 = Le23 = ··· = Lep3 ···, Le1m = Le2m = ··· = Lepm).

[0040] The transistor size of the depletion-mode NMOS transistor circuit is the total gate width Wd and the total gate length Ld, and the transistor size of the enhancement-mode NMOS transistor circuit is the total gate width We and the total gate length Le.

[0041] Let the gate widths Wd1, Wd2, ···, Wdp of the depletion-type NMOS transistors from the first column to the p-th column and the gate widths We1, We2, ···, Wep of the enhancement-type NMOS transistors be such that the total gate width Wd of the depletion-type NMOS transistor circuit is set to the sum of the gate widths Wd1, Wd2, ···, Wdp of the depletion-type NMOS transistors from the first column to the p-th column (Wd = Wd1 + Wd2 + ··· + Wdp).

[0042] The total gate width We of the enhancement-type NMOS transistor circuit is set to the sum of the gate widths We1, We2, ···, Wep of the enhancement-type NMOS transistors from the first column to the p-th column (We = We1 + We2 + ··· + Wep).

[0043] The total gate length Ld of the depletion-type NMOS transistor circuit is set to the sum of the gate lengths of the depletion-type NMOS transistors in the first column.

[0044] Also, the total gate length Le of the enhancement-type NMOS transistor circuit is set to the sum of the gate lengths of the enhancement-type MOS transistors in the first column.

[0045] And when the gate widths (Wd1, Wd2, ···, Wdp) of the depletion-type NMOS transistors and the gate widths (We1, We2, ···, Wep) of the enhancement-type NMOS transistors are 5 μm or less, and the gate lengths (Ld11, Ld12, Ld13, ···, Ld1n)(Ld21, Ld22, Ld23, ···, Ld2n)···(Ldp1, Ldp2, Ldp3, ···, Ldpn) of the depletion-type NMOS transistors and the gate lengths (Le11, Le12, Le13, ···, Le1m)(Le21, Le22, Le23, ···, Le2m)···(Lep1, Lep2, Lep3, ···, Lepm) of the enhancement-type NMOS transistors are 25 μm or less, the rate of variation in the drain current of each MOS transistor due to the influence of external stress is reduced, so that power consumption can be suppressed and a reference voltage device that suppresses the influence of external stress can be provided. Generation An apparatus can be provided.

[0046] Specific reference voltage Generation In the device, when the total gate width Wd of the depletion-type NMOS transistor circuit is 5 μm, the total gate length Ld is 100 μm, the total gate width We of the enhancement-type NMOS transistor circuit is 5 μm, and the total gate length Le is 75 μm, for the depletion-type NMOS transistor circuit, p = 2, n = 4, and the gate width Wd1 = Wd2 = 2.5 μm of the depletion-type NMOS transistor. The total gate width Wd = Wd1 + Wd2 = 5 μm. The gate lengths Ld11 = Ld12 = Ld13 = Ld14 = 25 μm. The total gate length Ld = Ld11 + Ld12 + Ld13 + Ld14 = 100 μm. For the enhancement-type NMOS transistor circuit, p = 2, m = 3, and the gate width We1 = We2 = 2.5 μm. The total gate width We = We1 + We2 = 5 μm. The gate lengths Le11 = Le12 = Le13 = 25 μm. When the total gate length Le = Le11 + Le12 + Le13 = 75 μm, a reference voltage that suppresses power consumption and the influence of external stress can be provided. Generation A device can be provided.

[0047] If it is desired to further suppress the influence of external stress, for the gate length, for the depletion-type NMOS transistor circuit, n = 50, the gate lengths Ld11 = Ld12 = Ld13··· = Ld150 = 2 μm, and for the enhancement-type NMOS transistor circuit, m = 38, the gate lengths Le11 = Le12 = Le13··· = Le137 = 2 μm, Le138 = 1 μm would be appropriate.

[0048] FIG. 5 is a modification of the second embodiment Form As a modification, in the constant current circuit 101 of FIG. 4, for the depletion-type NMOS transistors D11 to D1n in the first column, D21 to D2n in the second column, ···, Dp1 to Dpn in the p-th column, the gates are commonly connected in each column, and in the voltage generation circuit 102 of FIG. 4, for the enhancement-type NMOS transistors E11 to E1m in the first column, E21 to E2m in the second column, ···, Ep1 to Epm in the p-th column, the gates are commonly connected in each column, which is a reference voltage device. Generation It is a device.

[0049] The rest is the same as the second embodiment Of Figure 4 and is the same.

[0050] Figure 6 shows the In Figure 4, reference voltage for the case of n = 2, m = 2, and p = 2 Generation device.

[0051] Other aspects are the same as those of the second embodiment Of Figure 4 and are the same.

[0052] Figure 7 shows the In Figure 4 of reference voltage for n = n, m = m, and p = 2 In the case of device. Generation device.

[0053] Other aspects are the same as those of the second embodiment Of Figure 4 and are the same.

[0054] Figure 8 shows the In Figure 5 of reference voltage for n = n, m = m, and p = In the case of 2 device. Generation device.

[0055] Other aspects are the same as those of the second embodiment Of Figure 5 and are the same.

Example

[0056] With reference to FIG. 12, a reference voltage generation device 300 according to a third embodiment of the present invention will be described.

[0057] In FIG. 12, the gates of the first PMOS transistor 35 and the second PMOS transistor 36 are commonly connected, and their sources are connected to the power supply terminal 1 (input voltage VDD). The commonly connected gates are connected to the drain of the first PMOS transistor 35, forming a current mirror circuit.

[0058] The drain of the first PMOS transistor 35 is connected to the constant current circuit 101, and the drain of the second PMOS transistor 36 is connected to the voltage generation circuit 102 and the reference voltage Output terminal 3.

[0059] The constant current circuit 101 includes a depletion-type NMOS transistor circuit. The depletion-type NMOS transistor circuit connects n depletion-type NMOS transistors from D11 to D1n in series, commonly connects the gates of D11 to D1n, connects the drain of the depletion-type NMOS transistor D1n to the drain of the first PMOS transistor 35, and connects the source of the depletion-type NMOS transistor D11 to the ground terminal 2.

[0060] The voltage generation circuit 102 includes an enhancement-type NMOS transistor circuit. The enhancement-type NMOS transistor circuit connects m enhancement-type NMOS transistors from E11 to E1m in series, commonly connects the gates of E11 to E1m, connects the drain of the enhancement-type NMOS transistor E11 to the drain of the second PMOS transistor 36 and the reference voltage Output terminal 3, and connects the source of the enhancement-type NMOS transistor E1m to the ground terminal 2.

[0061] Then, the current of the depletion-type NMOS transistor circuit of the constant current circuit 101 is transferred to the enhancement-type NMOS transistor circuit of the voltage generation circuit 102 through a current mirror circuit composed of the first PMOS transistor 35 and the second PMOS transistor 36, and the current of the constant current circuit 101 is input to the voltage generation circuit 102 to generate a reference voltage Output at the reference voltage terminal 3. This is , Figures 1 - 3 of the first embodiment and Figures 4 - 8 of the second embodiment the same.

[0062] The rest is the same as that of the first embodiment Of Figures 1 - 3 is the same.

[0063] Also, although not shown, when the depletion-type NMOS transistor circuit of the constant current circuit 101 and the enhancement-type NMOS transistor circuit of the voltage generation circuit 102 are set to n = 1 and m = 1, the source and back gate of the depletion-type NMOS transistor D11 are connected to the ground terminal 2, and the source and back gate of the enhancement-type NMOS transistor E11 are connected to the ground terminal 2, thereby forming a reference voltage generator of the present invention.

Embodiment

[0064] Referring to FIG. 13, a reference voltage generator 400 according to a fourth embodiment of the present invention will be described.

[0065] FIG. 13 shows a reference voltage generator in which the depletion-type NMOS transistor circuit of the constant current circuit 101 and the enhancement-type NMOS transistor circuit of the voltage generation circuit 102 in the reference voltage generator 300 according to the third embodiment of the present invention are respectively constituted by the depletion-type NMOS transistor circuit of the constant current circuit 101 and the enhancement-type NMOS transistor circuit of the voltage generation circuit 102 shown in FIG. 5.

[0066] That is, in the constant current circuit 101 of the reference voltage generator 400 according to the fourth embodiment of the present invention, n depletion-type NMOS transistors D11 to D1n connected in series in the first column are connected in parallel with the second column, the third column, ···, the p-th column (p is an integer of 2 or more). The second column is composed of n depletion-type NMOS transistors D21 to D2n connected in series, and the p-th column is composed of n depletion-type NMOS transistors Dp1 to Dpn connected in series. The depletion-type NMOS transistors D11 to D1n in the first column, D21 to D2n in the second column, ···, Dp1 to Dpn in the p-th column have their gates commonly connected in each column. The voltage generation circuit 102 connects m enhancement-type NMOS transistors E11 to E1m connected in series in the first column in parallel with the second column, the third column, ···, the p-th column (p is an integer of 2 or more). The second column is composed of m enhancement-type NMOS transistors E21 to E2m connected in series, and the p-th column is composed of m enhancement-type NMOS transistors Ep1 to Epm connected in series. The enhancement-type NMOS transistors E11 to E1m, E21 to E2m, ···, Ep1 to Epm have their gates commonly connected in each column, and the reference voltage Generation is generated by the device.

[0067] The rest is the same as the second embodiment Of Figure 5 and is as follows.

[0068] Also, the constant current circuit 101 and the voltage generation circuit 102 of the reference voltage generator 400 can be configured as the reference voltage Figures 1 - 3 of the first embodiment and Figures 4 - 8 of the second embodiment generating device of the present invention with the configuration shown Generation herein.

Explanation of Reference Numerals

[0069] 1 Power supply terminal 2 Ground terminal 3 Reference voltage Output terminal 4 Semiconductor substrate 10 Depletion-type NMOS transistor The 2 0 Enhancement-type NMOS transistor 35 First PMOS transistor 36 Second PMOS transistor 100, 200 Reference voltage generator 101 Constant current circuit (depletion-type NMOS transistor circuit) 102 Voltage generation circuit (enhancement-type NMOS transistor circuit) D 11 、D 12 、D 13 、··、D 1n Depletion-type NMOS transistor D 21 、D 22 、D 23 、··、D 2n Depletion-type NMOS transistor D p1 、D p2 、D p3 、··、D pn Depletion-type NMOS transistor E 11 、E 12 、E 13 、··、E 1m Enhancement-type NMOS transistor E 21 、E 22 、E 23 、··、E 2m Enhancement-type NMOS transistor E p1 、E p2 、E p3 、··、E pm Enhancement-type NMOS transistor Wd, Wd1, ···, Wdp Gate widths of depletion-type NMOS transistors Ld11, Ld12, Ld13, Ld14, ···, Ld1n Gate lengths of depletion-type NMOS transistors Ld21, Ld22, Ld23, Ld24, ···, Ld2n Gate lengths of depletion-type NMOS transistors Ldp1, Ldp2, Ldp3, Ld24, ···, Ldpn Gate lengths of depletion-type NMOS transistors The gate widths of We, We1 ···, Wep enhancement-type MOS transistors The gate lengths of Le11, Le12, Le13, ···, Le1m enhancement-type NMOS transistors The gate lengths of Le21, Le22, Le23, ···, Le2m enhancement-type NMOS transistors The gate lengths of Lep1, Lep2, Lep3, ···, Lepm enhancement-type NMOS transistors

Claims

1. a current mirror circuit in which the gates of a first transistor and a second transistor are commonly connected, the drain and the gate of the first transistor are connected, and the sources of the first transistor and the second transistor are connected to a power supply terminal; A constant current circuit that outputs a constant current in response to an input voltage; a voltage generating circuit that receives the constant current as an input current and generates an output voltage based on the input current; a reference voltage output terminal for outputting the output voltage; A reference voltage generating device comprising: a drain of the first transistor that outputs the input voltage is connected to the constant current circuit, and a drain of the second transistor that outputs the input current is connected to the voltage generating circuit and the reference voltage output terminal; the constant current circuit includes a depletion type MOS transistor circuit, the depletion-type MOS transistor circuit has a depletion-type MOS transistor circuit total gate width and a depletion-type MOS transistor circuit total gate length, the depletion-type MOS transistor circuit includes n (n is an integer 2, 3, 4, . . .) depletion-type MOS transistors, a first depletion type MOS transistor to an n-th depletion type MOS transistor are connected in series; the first depletion type MOS transistor has a first gate width and a first gate length, and a gate and a source are connected to a ground terminal; the nth depletion-type MOS transistor has the first gate width and an nth gate length, and a drain connected to a drain of the first transistor; the voltage generating circuit includes an enhancement type MOS transistor circuit, the enhancement type MOS transistor circuit has an enhancement type MOS transistor circuit total gate width and an enhancement type MOS transistor circuit total gate length, the enhancement type MOS transistor circuit includes m enhancement type MOS transistors (m is an integer 2, 3, 4, . . .); an m-th enhancement type MOS transistor is connected in series from the first enhancement type MOS transistor; the first enhancement type MOS transistor has the first gate width and a gate length of E1, and has a drain and a gate connected to a drain of the second transistor and the reference voltage output terminal; the mth enhancement type MOS transistor has the first gate width and a gate length Em, and has a source connected to a ground terminal; the first gate width is a total gate width of the depletion-type MOS transistor circuit and a total gate width of the enhancement-type MOS transistor circuit, a sum of the first gate length to the nth gate length is a total gate length of the depletion-type MOS transistor circuit, A reference voltage generating device, wherein the sum of the gate lengths of said E1 to Em is the total gate length of said enhancement type MOS transistor circuit.

2. 2. The reference voltage generating device according to claim 1, wherein the first gate width is 5 μm or less, the first gate length and the nth gate length of the depletion type MOS transistor are each 25 μm or less, and the first gate length and the mth gate length of the enhancement type MOS transistor are each 25 μm or less.

3. a current mirror circuit in which the gates of a first transistor and a second transistor are commonly connected, the drain and the gate of the first transistor are connected, and the sources of the first transistor and the second transistor are connected to a power supply terminal; A constant current circuit that outputs a constant current in response to an input voltage; a voltage generating circuit that receives the constant current as an input current and generates an output voltage based on the input current; a reference voltage output terminal for outputting the output voltage; A reference voltage generating device comprising: a drain of the first transistor that outputs the input voltage is connected to the constant current circuit, and a drain of the second transistor that outputs the input current is connected to the voltage generating circuit and the reference voltage output terminal; the constant current circuit includes a depletion type MOS transistor circuit, the depletion type MOS transistor circuit having a depletion type MOS transistor circuit total gate width and a depletion type MOS transistor circuit total gate length; the depletion-type MOS transistor circuit includes n (n is an integer 2, 3, 4, . . .) × p (p is an integer 2, 3, 4, . . .) depletion-type MOS transistors, In a first column, a first depletion type MOS transistor to an n-th depletion type MOS transistor are connected in series; the first depletion type MOS transistor has a first gate width and a first gate length, and a gate and a source are connected to a ground terminal; the nth depletion-type MOS transistor has the first gate width and an nth gate length, and a drain connected to a drain of the first transistor; Further, in a p-th column, n depletion-type MOS transistors from a first depletion-type MOS transistor to an n-th depletion-type MOS transistor are connected in series, and the depletion-type MOS transistors are arranged in parallel from the first column to the p-th column, the first depletion-type MOS transistor in the pth column has a pth gate width and the first gate length, and has a gate and a source connected to a ground terminal; the nth depletion type MOS transistor in the pth column has the pth gate width and the nth gate length, and a drain connected to the drain of the first transistor; the voltage generating circuit includes an enhancement type MOS transistor circuit, the enhancement type MOS transistor circuit having an enhancement type MOS transistor circuit total gate width and an enhancement type MOS transistor circuit total gate length; the enhancement type MOS transistor circuit includes m (m is an integer 2, 3, 4, . . .) × p (p is an integer 2, 3, 4, . . .) enhancement type MOS transistors, In a first column, a first enhancement type MOS transistor to an m-th enhancement type MOS transistor are connected in series; the first enhancement type MOS transistor has the first gate width and a gate length of E1, and has a drain and a gate connected to a drain of the second transistor and the reference voltage output terminal; the mth enhancement type MOS transistor has the first gate width and a gate length Em, and has a source connected to a ground terminal; Further, in the p-th column, m enhancement type MOS transistors from a first enhancement type MOS transistor to an m-th enhancement type MOS transistor are connected in series, and the enhancement type MOS transistors are arranged in parallel from the first column to the p-th column, a first enhancement type MOS transistor in the pth column has a pth gate width and a first gate length, and has a drain and a gate connected to a drain of the second transistor and the reference voltage output terminal; The mth enhancement type MOS transistor in the pth column has a source connected to a ground terminal, a sum of the first gate width to the pth gate width is a total gate width of the depression type MOS transistor circuit and a total gate width of the enhancement type MOS transistor circuit, a sum of the first gate length to the nth gate length is a total gate length of the depletion-type MOS transistor circuit, A reference voltage generating device, wherein the sum of the gate lengths of said E1 through Em is the total gate length of said enhancement type MOS transistor circuit.

4. 4. The reference voltage generating device according to claim 3, wherein the first gate width and the pth gate width are each 5 μm or less, the first gate length and the nth gate length of the depletion type MOS transistor are each 25 μm or less, and the first gate length and the mth gate length of the enhancement type MOS transistor are each 25 μm or less.

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