Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A semiconductor device has a function to compute the sum of products of a weight value set by an analog current signal, and an input value. The analog current signal is outputted by using a digital-to-analog conversion circuit having a circuit in which a plurality of configurations in which a variable resistor and a switch are electrically connected in series are electrically connected in parallel. The semiconductor device uses a ferroelectric element as the variable resistor. The ferroelectric element has an oxide containing one or both of hafnium and zirconium as material having ferroelectricity.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. Further, the technical field of the invention disclosed in this specification and the like relates to an object, a driving method, or a manufacturing method.

[0002] More specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited as an example.

Background Art

[0003] Currently, the development of integrated circuits that mimic the structure of the human brain is actively underway. The integrated circuit has the structure of the brain incorporated as an electronic circuit and has circuits corresponding to the "neurons" and "synapses" of the human brain. Therefore, such an integrated circuit may also be referred to as "neuromorphic", "brainomorphic", or "brain-inspired". The integrated circuit has a non-Neumann architecture and is expected to perform parallel processing with extremely low power consumption compared to the Neumann architecture in which power consumption increases as the processing speed increases.

[0004] A model of information processing that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with human-like or even higher-than-human accuracy. In a neural network, the operation of weighted summation of neuron outputs, that is, the multiplication and summation operation, is the main operation.

[0005] Non-Patent Document 1 proposes a multiply-accumulate circuit using non-volatile memory elements. In this multiply-accumulate circuit, in each memory element, by utilizing the operation in the subthreshold region of a transistor having silicon in the channel formation region, a current corresponding to the multiplication of the data corresponding to the multiplier stored in each memory element and the input data corresponding to the multiplicand is output. Further, data corresponding to the multiply-accumulate operation is obtained by the sum of the currents output from the memory elements in each column. Since the multiply-accumulate circuit has memory elements inside, it can avoid performing data readout and write from an external memory in multiplication and addition. Therefore, the number of data transfer times due to readout and write can be reduced, and it is expected that the power consumption can be lowered.

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] When performing a product-sum operation using a digital circuit, multiplication of digital data (multiplier data) serving as a multiplier and digital data (multiplicand data) serving as a multiplicand is executed by a digital multiplication circuit, addition of the digital data (product data) obtained by the multiplication is executed by a digital addition circuit, and digital data (product-sum data) is acquired as a result of the product-sum operation. The digital multiplication circuit and the digital addition circuit preferably have a specification capable of handling multi-bit operations. However, in this case, since it is necessary to increase the circuit scale of each of the digital multiplication circuit and the digital addition circuit, the circuit area increases and the power consumption may also increase.

[0008] One aspect of the present invention aims to provide a semiconductor device capable of performing a product-sum operation. Or, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a semiconductor device with a reduced circuit area.

Means for Solving the Problems

[0009] One aspect of the present invention is a semiconductor device (artificial neural network) having a function of performing a product-sum operation between a weight value set by an analog current signal and an input value.

[0010] Note that an analog current signal can also be used for writing the input value.

[0011] One aspect of the present invention is a semiconductor device (analog memory) that inputs data using an analog current signal.

[0012] One aspect of the present invention is a current output type digital-to-analog conversion circuit (current output type DAC (Digital to Analog Converter)) that converts a digital signal into an analog current signal.

[0013] One aspect of the present invention is a digital-to-analog conversion circuit having a first circuit in which a transistor and a switch to which a bias potential is input are electrically connected in series, and the first circuit has a second circuit in which a plurality of the first circuits are electrically connected in parallel. The sum of the currents flowing through the second circuit can be output as an analog current signal. In the first circuit, the on-state or off-state of the switch can be controlled by a signal corresponding to each bit of the digital signal. A bias potential for setting the current value of the current flowing through the transistor is input to the gate of the transistor. The magnitude of the current flowing through each transistor can be set to be a weighted current value corresponding to each bit of the digital signal.

[0014] One aspect of the present invention is a digital-to-analog conversion circuit having a first circuit in which a variable resistor element and a switch are electrically connected in series, and the first circuit has a second circuit in which a plurality of the first circuits are electrically connected in parallel. The sum of the currents flowing through the second circuit can be output as an analog current signal. In the first circuit, the on-state or off-state of the switch can be controlled by a signal corresponding to each bit of the digital signal. The magnitude of the current flowing through the variable resistor element can be set to be a weighted current value corresponding to each bit of the digital signal.

[0015] As the variable resistor element, a configuration using a material having ferroelectricity can be adopted.

[0016] For example, an element using a material having ferroelectricity (ferroelectric element) can be used. As an example, an FTJ (ferroelectric tunnel junction) element can be used. As another example, a transistor (FeFET element) including a material having ferroelectricity as a gate insulating layer can be used.

[0017] As the material having ferroelectricity, a configuration using an oxide containing one or both of hafnium and zirconium can be adopted.

[0018] One aspect of the present invention is a digital - analog conversion circuit that uses a ferroelectric element as a variable resistor element.

[0019] Also, the output current of the second circuit can be used as the input current of the current - mirror circuit, and the output current of the current - mirror circuit can be used as an analog current signal.

[0020] The output current of the second circuit can be used as the input current of the current - mirror circuit, and the output current with the amplified current value can be used as an analog current signal. The current amplification factor in the current - mirror circuit can be set in multiple stages according to the digital signal.

[0021] Note that the digital - analog conversion circuit according to one aspect of the present invention is not limited to being used in an artificial neural network or an analog memory. For example, it can be used in various applications such as video signal input of a display device.

Advantages of the Invention

[0022] According to one aspect of the present invention, a semiconductor device with a reduced occupied area can be provided. A semiconductor device corresponding to a multi - bit digital signal can be provided. Or, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Or, according to one aspect of the present invention, a semiconductor device with improved operating speed can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided.

Brief Description of the Drawings

[0023]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0024] (Embodiment 1) The DAC 100 according to one aspect of the present invention will be described with reference to the drawings.

[0025] <Configuration Example of DAC100> FIGS. 1(A) to 1(C) show a configuration example of a DAC 100 that converts an n-bit (where n is a natural number of 2 or more) digital signal into an analog current signal.

[0026] In FIG. 1(A), the DAC 100 may have a circuit 110-k in which a transistor 102-k (where k is a natural number from 1 to n) having a bias potential input to its gate and a switch 101-k are electrically connected in series, and may have a circuit 120 in which circuits 110-1 to 110-n are electrically connected in parallel. Note that the transistor 102-k, the switch 101-k, and the circuit 110-k are not shown in FIG. 1(A). The sum of the currents flowing through the circuit 120 (corresponding to the current Iin) can be output as an analog current signal.

[0027] Note that the current Iin flows between a wiring to which the power supply potential V1 is applied and a wiring to which the power supply potential V2 having a potential difference from the power supply potential V1 is applied. For example, the power supply potential V1 can be set to a potential lower than the power supply potential V2.

[0028] In circuit 110-k, the on-state or off-state of switch 101-k can be controlled by signal wd[k] corresponding to each bit of the digital signal. Signal wd[k] can be a digital voltage signal.

[0029] A bias potential BIAS for setting the current value of the current flowing through transistor 102-k is input to the gate of transistor 102-k. The magnitude of the current flowing through transistor 102-k can be set to be a weighted current value according to the corresponding bit of the digital signal.

[0030] When setting the magnitude of the current flowing through transistor 102-k to be a weighted current value according to the corresponding bit of the digital signal, for example, the channel width of transistor 102-k can be made twice that of transistor 102-1. k-1 Also, transistor 102-k may be configured as two transistors having the same configuration as transistor 102-1 connected in parallel electrically. k-1

[0031] The current Iin output from circuit 120 is used as the input current of current mirror circuit 130, and the output current Iout of current mirror circuit 130 is output as an analog current signal.

[0032] Note that it is also possible to use current Iin as the output current of DAC100.

[0033] FIG. 1(B) is an example in which current mirror circuit 130 is configured using a plurality of transistors in FIG. 1(A). The connection relationship is as shown in the circuit diagram of FIG. 1(B). Note that in FIG. 1(B), current mirror circuit 130 is configured using p-channel type transistors, but it is not limited to this. It may be configured using n-channel type transistors. Also, according to the polarity of the transistors constituting the circuit, the magnitude relationship between power supply potential V1 and power supply potential V2 can be changed.

[0034] ​FIG. 1(C) shows a configuration example of a current mirror circuit 130 different from that in FIG. 1(B). In the configuration of FIG. 1(C), in the current mirror circuit 130, the amplification factor of the output current Iout with respect to the input current Iin can be changed. For example, under the control of digital signals d1 to dm (m is a natural number of 2 or more), the current value of the output current Iout can be selected from the current values ranging from 0 times to 2 m -1 times the current value of Iin and output. For example, when m is 8, it can be selected from the current values of 0 times to 255 times (255 levels of current values) and output.

[0035] In this case, when the current flowing through the switch to which the digital signal d1 is input is Iin, if the transistors in the current mirror circuit 130 are designed such that the current flowing through the switch to which the digital signal dm is input becomes 2 m-1 ×Iin.

[0036] In this way, a circuit corresponding to a more multi-bit digital signal can be provided.

[0037] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0038] (Embodiment 2) The DAC 100 according to one aspect of the present invention will be described with reference to the drawings.

[0039] <Configuration Example of DAC100> FIGS. 2(A) to 2(C) show another configuration example of a DAC 100 that converts an n-bit (n is a natural number of 2 or more) digital signal into an analog current signal. Note that the same parts as those in FIGS. 1(A) to 1(C) are shown with the same configuration, and the description thereof is omitted.

[0040] In FIG. 2(A), the DAC 100 has a circuit 110-k in which a variable resistance element 202-k (k is a natural number from 1 to n) and a switch 101-k are electrically connected in series. Note that the variable resistance element 202-k is not shown in FIG. 2(A).

[0041] The magnitude of the current flowing through the variable resistor element 202-k can be set to a weighted current value according to the corresponding bit of the digital signal.

[0042] FIG. 2(B) is an example in which the current mirror circuit 130 in FIG. 2(A) is configured using a plurality of transistors. For the current mirror circuit 130 in FIG. 2(B), refer to the description of FIG. 1(B) in Embodiment 1.

[0043] FIG. 2(C) shows a configuration example of a current mirror circuit 130 different from that in FIG. 2(B). For the current mirror circuit 130 in FIG. 2(C), refer to the description of FIG. 1(C) in Embodiment 1.

[0044] As the variable resistor element 202-k, an element using a ferroelectric material (ferroelectric element) can be used. As an example, an FTJ (ferroelectric tunnel junction) element can be used. As another example, an FeFET element having a ferroelectric material as a gate insulating layer of a transistor can be used.

[0045] Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, hafnium zirconium oxide (HfZrO X (where X is a real number greater than 0), a material obtained by adding element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, a material obtained by adding element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide, and the like. Also, examples of materials that can have ferroelectricity include lead titanate (PbTiO X(which may be described as), piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used. Further, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the materials listed above can be used. By the way, materials such as hafnium oxide, zirconium oxide, hafnium zirconium oxide, and a material obtained by adding element J1 to hafnium oxide can have their crystal structures (properties) changed not only by film formation conditions but also by various processes. Therefore, in this specification, etc., not only materials that exhibit ferroelectricity are called ferroelectrics, but materials that can have ferroelectricity are called.

[0046] Among them, as a material that can have ferroelectricity, hafnium oxide or a material having hafnium oxide and zirconium oxide is preferable because it can have ferroelectricity even when processed into a thin film of several nm. In this specification, etc., a material having a ferroelectricity in a layered form may be referred to as a ferroelectric layer or a metal oxide film.

[0047] When using hafnium zirconium oxide as a material that can have ferroelectric properties, it is preferable to form a film using the atomic layer deposition (ALD) method, particularly the thermal ALD method. Further, when forming a film of a material that can have ferroelectric properties using the thermal ALD method, it is suitable to use a material that does not contain a hydrocarbon (also referred to as HC) as a precursor. When either one or both of hydrogen and carbon are contained in a material that can have ferroelectric properties, it may inhibit the crystallization of the material that can have ferroelectric properties. Therefore, as described above, by using a precursor that does not contain a hydrocarbon, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material that can have ferroelectric properties. For example, a chlorine-based material can be given as a precursor that does not contain a hydrocarbon. When using a material having hafnium oxide and zirconium oxide (hafnium zirconium oxide) as a material that can have ferroelectric properties, HfCl4 and / or ZrCl4 may be used as a precursor.

[0048] In addition, when forming a film using a material that can have ferroelectric properties, by thoroughly removing at least one or more of impurities in the film, here hydrogen, hydrocarbon, and carbon, a film having high-purity true ferroelectric properties can be formed. Note that the film having high-purity true ferroelectric properties and the high-purity true oxide semiconductor shown in the embodiments described later have very high manufacturing process compatibility. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0049] When using hafnium zirconium oxide as a material that can have ferroelectric properties, it is preferable to alternately form hafnium oxide and zirconium oxide in a composition of 1:1 using the thermal ALD method.

[0050] In addition, when forming a film of a material that may have ferroelectricity using the thermal ALD method, H2O or O3 can be used as the oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, the oxidizing agent for the thermal ALD method may contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0051] In addition, the crystal structure of the material that may have ferroelectricity is not particularly limited. For example, the crystal structure of the material that may have ferroelectricity may be any one or more selected from the cubic system, tetragonal system, orthorhombic system, and monoclinic system. In particular, as a material that may have ferroelectricity, having an orthorhombic crystal structure is preferable because ferroelectricity is exhibited. Alternatively, the material that may have ferroelectricity may have a composite structure having an amorphous structure and a crystal structure.

[0052] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0053] (Embodiment 3) The semiconductor device according to one aspect of the present invention can be used, for example, in an arithmetic circuit of an artificial neural network.

[0054] The arithmetic circuit 350 shown in FIG. 3 has, as an example, an array unit ALP, a circuit ILD, a circuit WLD, a circuit XLD, a circuit AFP, and circuits TW[1] to TW[n] (where n is an integer of 1 or more).

[0055] The circuit ILD and the circuit AFP are electrically connected to the wirings OL[1] to OL[n] and the wirings OLB[1] to OLB[n] via the circuits TW[1] to TW[n].

[0056] Circuits TW[1] to TW[n] function as switching circuits. In each of circuits TW[1] to TW[n], it is possible to switch between the case of inputting the output signals of wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n] to circuit AFP and the case of inputting the output signal of circuit ILD to wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n].

[0057] Circuit WLD is electrically connected to wirings WL[1] to WL[m] (where m is an integer of 1 or more) and wirings WX1L[1] to WX1L[m]. Circuit XLD is electrically connected to wirings WX1L[1] to WX1L[m].

[0058] The arithmetic circuit 350 shown in FIG. 3 has a circuit MP in which an array part ALP is arranged in an m×n matrix. In FIG. 3, the circuit MP located at the i-th row and j-th column (where i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) is denoted as circuit MP[i,j]. However, in FIG. 3, only circuits MP[1,1], MP[1,m], MP[i,j], MP[n,1], and MP[n,m] are illustrated, and the illustration of other circuits MP is omitted.

[0059] Circuit MP[i,j] is electrically connected to wiring WL[i], wiring WXL1[i], wiring OL[j], and wiring OLB[j].

[0060] As an example, circuit MP[i,j] has a function of holding a weight coefficient (also referred to as first data). The weight coefficient may also be referred to as a weight value. Specifically, circuit MP[i,j] holds information corresponding to the weight coefficient input from wirings OL[j] and OLB[j].

[0061] Circuit ILD has a function of outputting information corresponding to the first data, which is a weight coefficient, to wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n].

[0062] As information corresponding to the weight coefficient, for example, a potential, a resistance value, or a current value can be used. When using a current value as information corresponding to the weight coefficient, a current to be input can be generated using the DAC having the configuration described in Embodiment 1 and Embodiment 2. That is, as the circuit ILD, the DAC having the configuration described in Embodiment 1 and Embodiment 2 can be used.

[0063] Further, the circuit MP[i,j] has a function of outputting a product of an input value (also referred to as second data) input from the wiring WX1L[i] and a weight coefficient (first data). As a specific example, when the second data is input from WX1L[i] to the circuit MP[i,j], a current corresponding to the product of the first data and the second data is output to the wiring OL[j] and the wiring OLB[j]. Note that, in FIG. 3, an example in the case where the wiring OL[j] and the wiring OLB[j] are arranged is shown, but one aspect of the present invention is not limited thereto. Only one of the wiring OL[j] and the wiring OLB[j] may be arranged.

[0064] The circuit XLD has a function of supplying second data, which is an input value, to the wirings WXLS[1] to WXLS[m].

[0065] The information corresponding to the input value can be, for example, a potential, a current value, or the like. When using a current value as information corresponding to the input value, a current to be input can be generated using the DAC having the configuration described in Embodiment 1 and Embodiment 2. That is, as the circuit XLD, the DAC having the configuration described in Embodiment 1 and Embodiment 2 can be used.

[0066] Currents corresponding to the products of the first data and the second data output from the circuits MP[1,j] to MP[m,j] are added together and output to the wiring OL[j] and the wiring OLB[j]. In this way, the arithmetic circuit can perform a sum-of-products operation of the weight coefficient and the input value.

[0067] In addition, circuit XLD and circuit WLD have a function of selecting circuit MP which is the destination for writing information according to the first data input from circuit ILD. For example, when writing information to circuits MP[i,1] to MP[i,n] located in the i-th row of array section ALP, circuit XLD supplies, for example, signals for turning on or off writing switching element 1 included in circuits MP[i,1] to MP[i,n] to wiring WXLS[i], and supplies a potential for turning off the writing switching element 1 included in circuits MP other than the i-th row to wiring WXLS. Also, circuit WLD supplies, for example, signals for turning on or off writing switching element 2 included in circuits MP[i,1] to MP[i,n] to wiring WLS[i], and supplies a potential for turning off the writing switching element 2 included in circuits MP other than the i-th row to wiring WLS.

[0068] Circuit AFP has circuits ACTF[1] to ACTF[n]. Circuit ACTF[j] is electrically connected to wiring OL[j] and wiring OLB[j] respectively via circuit TW[j] having a switching function. Circuit ACTF[j] generates a signal according to information (such as potential, current value, etc.) corresponding to the result of the sum-of-products operation input from wiring OL[j] and wiring OLB[j], and can output it as z1 (k) to z n (k) Circuit AFP compares information (such as potential, current value, etc.) corresponding to the result of the sum-of-products operation input from wiring OL[j] and wiring OLB[j], generates a signal according to the comparison result, and can output it as z1 (k) to z n (k) and output it as such.

[0069] <circuit MP> A circuit configuration example applicable to circuit MP[i,j] is shown in FIG. 4. It has transistors M1 to M3 and capacitor C1. Note that, for example, a holding section HC is constituted by transistor M2 and capacitor C1.

[0070] In the circuit MP of FIG. 4, the circuit MCr has substantially the same circuit configuration as the circuit MC. Therefore, in order to distinguish the circuit elements and the like of the circuit MCr from those of the circuit MC, an "r" is attached to the symbols.

[0071] The transistors M1 to M3 illustrated in FIG. 4 are, as an example, n-channel transistors of a multi-gate structure having gates above and below the channel, and each of the transistors M1 to M3 has a first gate and a second gate.

[0072] Also, the semiconductor device according to one aspect of the present invention does not depend on the connection configuration of the back gate of the transistor. In the transistors M1 to M3 illustrated in FIG. 4, a back gate is illustrated, and the connection configuration of the back gate is not illustrated, but the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the back gate of the transistor M2 may be electrically connected. Also, for example, in a transistor having a back gate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring electrically connected to an external circuit or the like is provided, and a potential is applied to the back gate of the transistor by the external circuit or the like. Note that this also applies to the transistors described in other parts of the specification as well as in FIG. 4, or the transistors illustrated in other drawings.

[0073] In addition, the semiconductor device according to one aspect of the present invention is independent of the structure of the transistors included in the semiconductor device. It may be a transistor with a single gate structure. Also, some of the transistors may have a back gate structure, and some other transistors may not have a back gate structure. Note that this also applies not only to the circuit diagram shown in FIG. 4 but also to the transistors described in other parts of the specification or illustrated in other drawings.

[0074] In addition, in this specification and the like, transistors with various structures can be used as the transistors. Therefore, there is no limitation on the type of transistor to be used. As an example of a transistor, a transistor having single-crystalline silicon, or a transistor having an amorphous semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. Alternatively, a thin-film transistor (TFT) obtained by thinning these semiconductors can be used. When using a TFT, there are various advantages. For example, since it can be manufactured at a lower temperature than in the case of single-crystalline silicon, it is possible to reduce the manufacturing cost or the size of the manufacturing equipment.

[0075] Note that as an example of a transistor, a transistor having a compound semiconductor (e.g., SiGe, GaAs, etc.) or an oxide semiconductor (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, In-Sn-O (ITO), Sn-O, Ti-O, Al-Zn-Sn-O (AZTO), In-Sn-Zn-O, etc.) can be used. Alternatively, a thin-film transistor obtained by thinning these compound semiconductors or these oxide semiconductors can be used. These compound semiconductors or oxide semiconductors can be used not only for the channel portion of the transistor but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as wiring, resistance elements, pixel electrodes, or electrodes having translucency. Since it is possible to form them simultaneously with the transistor, the cost can be reduced.

[0076] Note that, as an example of the transistor, a transistor formed using an inkjet method or a printing method can be used. By using these, it is possible to manufacture at room temperature, at a low degree of vacuum, or on a large substrate. Therefore, since it is possible to manufacture without using a mask (reticle), the layout of the transistor can be easily changed. Or, since it is possible to manufacture without using a resist, the material cost can be reduced and the number of processes can be reduced. Or, since it is possible to apply a film only to a necessary portion, the material is not wasted and the cost can be reduced as compared with a manufacturing method of etching after forming a film over the entire surface.

[0077] Note that, as an example of the transistor, a transistor having an organic semiconductor or a carbon nanotube can be used. By using these, a transistor can be formed on a substrate that can be bent. An apparatus using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to shock.

[0078] In the circuit MP of FIG. 4, the first terminal of the transistor M1 is electrically connected to the wiring VE. The second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M3. The gate of the transistor M1 is electrically connected to the first terminal of the capacitor C1 and the first terminal of the transistor M2. The second terminal of the capacitor C1 is electrically connected to the wiring VE. The second terminal of the transistor M2 is electrically connected to the wiring OL. The gate of the transistor M2 is electrically connected to the wiring WL. The second terminal of the transistor M3 is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring WX1L.

[0079] In the circuit M Cr, a connection configuration different from that of the circuit MC will be described. The second terminal of the transistor M3r is electrically connected not to the wiring OL but to the wiring OLB. The first terminal of the transistor M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr.

[0080] In the holding unit HC shown in FIG. 4, the electrical connection point of the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as the node n1.

[0081] The holding unit HC has a function of holding a potential corresponding to the weight coefficient (first data). The holding of the potential in the holding unit HC included in the circuit MC of FIG. 4 can be performed by inputting a current with a predetermined current value from the wiring OL when the transistors M2 and M3 are in the on state, writing it into the capacitor C1, and then turning off the transistor M2. Thereby, the potential of the node n1 can be held as a potential corresponding to the weight coefficient (first data). At this time, a current can be input from the wiring OL, and a potential of a magnitude corresponding to the magnitude of the current can be held in the capacitor C1. Therefore, in the input of the first data, the influence of variations in the current characteristics (such as the threshold voltage) of the transistor M1 can be reduced.

[0082] The current input to the wiring OL can be generated using the DAC having the configuration described in Embodiment 1 or Embodiment 2.

[0083] Also, for the transistor M1, in order to hold the potential of the node n1 for a long time, it is preferable to apply a transistor with a small off-current. As a transistor with a small off-current, for example, an OS transistor can be used. Further, as the transistor M1, a transistor having a back gate may be applied, and a low-level potential may be applied to the back gate to shift the threshold voltage to the positive side to reduce the off-current.

[0084] In this way, a highly reliable arithmetic circuit is provided.

[0085] This embodiment can be freely combined with other embodiments for implementation.

[0086] (Embodiment 4) In this embodiment, another example of a circuit capable of performing a sum-of-products operation, which is a semiconductor device according to one aspect of the present invention, will be described.

[0087] FIG. 5 shows a configuration example of an arithmetic circuit that performs a sum-of-products operation on first data that is positive or “0” and second data that is positive or “0”. The arithmetic circuit MAC1 shown in FIG. 5 is a circuit that performs a sum-of-products operation on first data corresponding to the potential held in each cell and second input data, and performs an operation of an activation function using the result of the sum-of-products operation. Note that the first data and the second data can be, for example, analog data or multi-valued data (discrete data).

[0088] Since this arithmetic circuit also has a function as a memory for holding the first data, it can also be called a memory. In particular, when analog data is used as the first data, it can be called an analog memory.

[0089] The arithmetic circuit MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and conversion circuits ITRZ[1] to ITRZ[n].

[0090] The cell array CA includes cells IM[1,1] to IM[m,n] (where m is an integer of 1 or more and n is an integer of 1 or more here), and cells IMref[1] to IMref[m]. Each of the cells IM[1,1] to IM[m,n] has a function of holding a potential corresponding to a current amount according to the first data, and the cells IMref[1] to IMref[m] have a function of supplying potentials corresponding to the second data necessary for performing a sum-of-products operation with the held potential to signal lines XCL[1] to XCL[m].

[0091] Note that in the cell array CA of FIG. 5, the cells are arranged in a matrix with n + 1 cells in the row direction and m cells in the column direction, but the cell array CA may be configured such that the cells are arranged in a matrix with 2 or more cells in the row direction and 1 or more cells in the column direction.

[0092] Each of cells IM[1,1] to IM[m,n] has, as an example, a transistor F1, a transistor F2, and a capacitor C5, and each of cells IMref[1] to IMref[m] has, as an example, a transistor F1m, a transistor F2m, and a capacitor C5m.

[0093] In particular, it is preferable that the sizes (for example, channel length, channel width, and transistor configuration) of the transistors F1 included in each of cells IM[1,1] to IM[m,n] are equal to each other, and it is preferable that the sizes of the transistors F2 included in each of cells IM[1,1] to IM[m,n] are equal to each other. Also, it is preferable that the sizes of the transistors F1m included in each of cells IMref[1] to IMref[m] are equal to each other, and it is preferable that the sizes of the transistors F2m included in each of cells IMref[1] to IMref[m] are equal to each other. Further, it is preferable that the sizes of the transistor F1 and the transistor F1m are equal to each other, and it is preferable that the sizes of the transistor F2 and the transistor F2m are equal to each other.

[0094] Note that the transistors F1 and F1m are assumed to operate finally in the linear region when in the on state, unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above are assumed to be appropriately biased to voltages within the operating range in the linear region. However, one aspect of the present invention is not limited to this. For example, the transistors F1 and F1m may operate in the saturation region when in the on state, or a combination of operation in the linear region and operation in the saturation region may be possible.

[0095] In addition, unless otherwise specified, the transistors F2 and F2m operate in the subthreshold region (that is, in the transistors F2 or F2m, when the gate-source voltage is lower than the threshold voltage, more preferably, when the drain current increases exponentially with respect to the gate-source voltage). That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above include cases where they are appropriately biased to voltages within the range of operating in the subthreshold region. For this reason, the transistors F2 and F2m include cases where they operate such that an off-current flows between the source and drain.

[0096] In addition, as an example, the transistor F1 and / or the transistor F1m are preferably OS transistors. Additionally, the channel formation region of the transistor F1 and / or the transistor F1m is more preferably an oxide containing at least one of indium, element M (examples of element M include one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.), and zinc.

[0097] By using an OS transistor as the transistor F1 and / or the transistor F1m, the leakage current of the transistor F1 and / or the transistor F1m can be suppressed, so that the power consumption of the arithmetic circuit can be reduced. Specifically, since the leakage current from the holding node to the write word line when the transistor F1 and / or the transistor F1m are in the non-conducting state can be made very small, the refresh operation of the potential of the holding node can be reduced, so that the power consumption of the sum-of-products arithmetic circuit can be reduced. Also, by making the leakage current from the holding node to the write word line very small, the cell can hold the potential of the holding node for a long time, so that the arithmetic accuracy of the arithmetic circuit can be increased.

[0098] Also, for the transistor F2 and / or the transistor F2m, by using an OS transistor, it can operate in a wide current range in the subthreshold region, so that the power consumption can be reduced. Also, for the transistor F2 and / or the transistor F2m, by using an OS transistor, it can be fabricated simultaneously with the transistors F1 and F1m, so the fabrication process of the product-sum operation circuit may be shortened. Also, the transistor F2 and / or the transistor F2m can be a transistor including silicon in the channel formation region (hereinafter referred to as an Si transistor) other than the OS transistor. As the silicon, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single-crystalline silicon, etc. can be used.

[0099] By the way, when a semiconductor device or the like is highly integrated on a chip or the like, heat may be generated in the chip due to the driving of the circuit. Due to this heat generation, the temperature of the transistor rises, and the characteristics of the transistor may change, resulting in a change in the field-effect mobility or a decrease in the operating frequency. Since the OS transistor has higher heat resistance than the Si transistor, the field-effect mobility is less likely to change due to temperature changes, and the operating frequency is also less likely to decrease. Furthermore, the OS transistor is likely to maintain the characteristic that the drain current increases exponentially with respect to the gate-source voltage even when the temperature rises. Therefore, by using the OS transistor, it is easy to perform the product-sum operation described later even in a high-temperature environment. Therefore, when constructing a semiconductor device that is resistant to heat generation due to driving, it is preferable to apply an OS transistor as the transistor.

[0100] In each of the cells IM[1,1] to IM[m,n], the first terminal of the transistor F1 is electrically connected to the gate of the transistor F2. The first terminal of the transistor F2 is electrically connected to the wiring VE. The first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2.

[0101] Also, in each of cells IMref[1] to IMref[m], the first terminal of transistor F1m is electrically connected to the gate of transistor F2m. The first terminal of transistor F2m is electrically connected to wiring VE. The first terminal of capacitor C5m is electrically connected to the gate of transistor F2m.

[0102] Also, the semiconductor device according to one aspect of the present invention is independent of the polarity of the transistors included in the semiconductor device. For example, although transistors F1 and F2 illustrated in FIG. 5 are n-channel transistors, some or all of the transistors may be replaced with p-channel transistors.

[0103] Note that the modification examples regarding the structure and polarity of the transistors are not limited to only transistors F1 and F2. For example, the same applies to transistors F1m, F2m, transistors F3[1] to F3[n] to be described later, transistors F4[1] to F4[n], and further transistors described in other parts of the specification or illustrated in other drawings.

[0104] Wiring VE is a wiring for flowing a current between the first terminal and the second terminal of transistor F2 in each of cells IM[1,1], IM[m,1], IM[1,n], and IM[m,n], and also functions as a wiring for flowing a current between the first terminal and the second terminal of transistor F2 in each of cells IMref[1] and IMref[m]. As an example, wiring VE functions as a wiring for supplying a constant voltage. The constant voltage can be, for example, a low-level potential, a ground potential, or the like.

[0105] In cell IM[1,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 5, in cell IM[1,1], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is designated as node NN[1,1].

[0106] In cell IM[m,1], the second terminal of transistor F1 is electrically connected to wiring WCL[1], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 5, in cell IM[m,1], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is designated as node NN[m,1].

[0107] In cell IM[1,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 5, in cell IM[1,n], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is designated as node NN[1,n].

[0108] In cell IM[m,n], the second terminal of transistor F1 is electrically connected to wiring WCL[n], and the gate of transistor F1 is electrically connected to wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[n], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 5, in cell IM[m,n], the connection point of the first terminal of transistor F1, the gate of transistor F2, and the first terminal of capacitor C5 is defined as node NN[m,n].

[0109] In cell IMref[1], the second terminal of transistor F1m is electrically connected to wiring XCL[1], and the gate of transistor F1m is electrically connected to wiring WSL[1]. The second terminal of transistor F2m is electrically connected to wiring XCL[1], and the second terminal of capacitor C5 is electrically connected to wiring XCL[1]. In FIG. 5, in cell IMref[1], the connection point of the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 is defined as node NNref[1].

[0110] In cell IMref[m], the second terminal of transistor F1m is electrically connected to wiring XCL[m], and the gate of transistor F1m is electrically connected to wiring WSL[m]. The second terminal of transistor F2m is electrically connected to wiring XCL[m], and the second terminal of capacitor C5 is electrically connected to wiring XCL[m]. In FIG. 5, in cell IMref[m], the connection point of the first terminal of transistor F1m, the gate of transistor F2m, and the first terminal of capacitor C5 is defined as node NNref[m].

[0111] The above-mentioned nodes NN[1,1], NN[m,1], NN[1,n], NN[m,n], NNref[1], and NNref[m] function as the holding nodes of their respective cells.

[0112] In cells IM[1,1] to IM[m,n], for example, when transistor F1 is in the on state, transistor F2 has a diode-connected configuration. With the constant voltage provided by wiring VE set to the ground potential (GND), when transistor F1 is in the on state and a current of current amount I flows from wiring WCL to the second terminal of transistor F2, the potential of the gate (node NN) of transistor F2 is determined according to the current amount I. Note that the potential of the second terminal of transistor F2 is ideally equal to the gate (node NN) of transistor F2 because transistor F1 is in the on state. Here, by turning transistor F1 off, the potential of the gate (node NN) of transistor F2 is held. As a result, transistor F2 can pass a current of current amount I corresponding to the ground potential of the first terminal of transistor F2 and the potential of the gate (node NN) of transistor F2 between the source and drain of transistor F2. In this specification and the like, such an operation is referred to as "transistor F2 is programmed to have a current amount I flowing between the source and drain of transistor F2", etc.

[0113] Circuit SWS1, as an example, includes transistors F3[1] to F3[n]. The first terminal of transistor F3[1] is electrically connected to wiring WCL[1], the second terminal of transistor F3[1] is electrically connected to circuit WCS, and the gate of transistor F3[1] is electrically connected to wiring SWL1. The first terminal of transistor F3[n] is electrically connected to wiring WCL[n], the second terminal of transistor F3[n] is electrically connected to circuit WCS, and the gate of transistor F3[n] is electrically connected to wiring SWL1.

[0114] Transistors F3[1] to F3[n] are preferably, for example, OS transistors applicable to transistor F1 and / or transistor F2.

[0115] Circuit SWS1 functions as a circuit that makes the connection between circuit WCS and each of wirings WCL[1] to WCL[n] in a conductive state or a non-conductive state.

[0116] The circuit SWS2 has, as an example, transistors F4[1] to F4[n]. The first terminal of transistor F4[1] is electrically connected to wiring WCL[1], the second terminal of transistor F4[1] is electrically connected to the input terminal of conversion circuit ITRZ[1], and the gate of transistor F4[1] is electrically connected to wiring SWL2. The first terminal of transistor F4[n] is electrically connected to wiring WCL[n], the second terminal of transistor F4[n] is electrically connected to the input terminal of conversion circuit ITRZ[n], and the gate of transistor F4[n] is electrically connected to wiring SWL2.

[0117] The transistors F4[1] to F4[n] are preferably OS transistors applicable to, for example, transistor F1 and / or transistor F2.

[0118] The circuit SWS2 functions as a circuit that makes the connection between wiring WCL[1] and conversion circuit ITRZ[1], and between wiring WCL[n] and conversion circuit ITRZ[n], in a conductive state or a non-conductive state.

[0119] The circuit WCS has a function of supplying data for storage in each cell of the cell array CA.

[0120] The circuit XCS is electrically connected to wirings XCL[1] to XCL[m]. The circuit XCS has a function of passing a current corresponding to reference data, or a current corresponding to second data, through each of cells IMref[1] to IMref[m] of the cell array CA.

[0121] The circuit WSD is electrically connected to wirings WSL[1] to WSL[m]. When writing first data to cells IM[1,1] to IM[m,n], the circuit WSD has a function of selecting the row of the cell array CA that is the write destination of the first data by supplying a predetermined signal to wirings WSL[1] to WSL[m].

[0122] Also, as an example, circuit WSD is electrically connected to wiring SWL1 and wiring SWL2. By supplying a predetermined signal to wiring SWL1, circuit WSD functions to make the connection between circuit WCS and cell array CA conductive or non-conductive. By supplying a predetermined signal to wiring SWL2, circuit WSD functions to make the connection between conversion circuits ITRZ[1] to ITRZ[m] and cell array CA conductive or non-conductive.

[0123] Each of conversion circuits ITRZ[1] to ITRZ[m] has, as an example, an input terminal and an output terminal. For example, the output terminal of conversion circuit ITRZ[1] is electrically connected to wiring OL[1], and the output terminal of conversion circuit ITRZ[n] is electrically connected to wiring OL[n].

[0124] Each of conversion circuits ITRZ[1] to ITRZ[m] has the function of converting the current input to the input terminal into a voltage and outputting it from the output terminal. The voltage can be, for example, an analog voltage, a digital voltage, etc. Also, each of conversion circuits ITRZ[1] to ITRZ[m] may have an arithmetic circuit of a function system. In this case, for example, using the converted voltage, a function may be calculated by the arithmetic circuit and the result of the calculation may be output to wirings OL[1] to OL[n].

[0125] Particularly, when performing calculations of a hierarchical artificial neural network, as the above-described function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. can be used.

[0126] As circuit WCS described in FIG. 5, the DAC described in Embodiment 1 or Embodiment 2 can be used. Also, as XCS described in FIG. 5, the DAC described in Embodiment 1 or Embodiment 2 can be used.

[0127] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0128] (Embodiment 5) In this embodiment, an example of an electronic device having a semiconductor device according to one aspect of the present invention will be described.

[0129] In various electronic devices, for example, DA conversion for converting various digital information such as acoustic information, imaging information, illuminance information, and temperature information into analog information may be performed. By using the semiconductor device according to one aspect of the present invention in an electronic device, DA conversion with suppressed power consumption increase can be performed. That is, by using the semiconductor device according to one aspect of the present invention in an electronic device, power consumption can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, high-precision DA conversion can be realized. Further, by using the semiconductor device according to one aspect of the present invention, high-speed DA conversion can be realized.

[0130] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

Example

[0131] An arithmetic circuit equipped with the DAC described in this specification and the like was actually prototyped, and the operation of the DAC was confirmed. In this example, the actually prototyped DAC and the results of the operation confirmation will be described.

[0132] FIG. 6 is a top view photograph of a die (chip) including the actually fabricated arithmetic circuit. Note that one side of the die is 4 mm. The die shown in FIG. 6 has a configuration in which Si transistors are formed on a semiconductor substrate made of silicon, and OS transistors are formed above them. Specifically, on the semiconductor substrate, a circuit WD, a circuit XD, a circuit RD, and a circuit GD, which will be described later, are formed by the process of Si transistors, and a circuit MCA, which will be described later, is formed by the process of OS transistors.

[0133] Circuit WD corresponds to circuit WCS described in Embodiment 4, circuit XD corresponds to circuit XCS described in Embodiment 4, circuit GD corresponds to circuit WSD described in Embodiment 4, and circuit RD corresponds to conversion circuits ITRZ[1] to ITRZ[n] described in Embodiment 4. Also, circuit MCA corresponds to cell array CA described in Embodiment 4.

[0134] In particular, the DAC is included in each of circuit WD and circuit XD.

[0135] Also, the circuit configuration of the DAC included in the actually prototyped arithmetic circuit is as shown in FIG. 7. The DAC shown in FIG. 7 takes into account the configuration of FIG. 1(B), and in FIG. 1(B), the configuration has n = 8. Also, transistor 102-k has a configuration in which 2 k-1 identical-sized transistors are electrically connected in parallel. That is, transistor 102-2 has a configuration in which 2 transistors are electrically connected in parallel, and transistor 102-8 has a configuration in which 128 transistors are electrically connected in parallel. Note that transistor 102-1 has a configuration in which 1 transistor is included and does not have a configuration in which 2 or more transistors are electrically connected in parallel.

[0136] Here, by inputting digital signals from 0 to 255 to wirings wd[1] to wd[8], the output current Iout obtained from current mirror circuit 130 was measured.

[0137] FIG. 8 is a graph showing the input / output characteristics of the DAC provided in the actually fabricated arithmetic circuit. The input / output characteristics in FIG. 8 show the digital input value (IN(digital)) on the horizontal axis and the output current Iout[nA] on the vertical axis. As shown in FIG. 8, by inputting digital signals from 0 to 255 to wirings wd[1] to wd[8], the output current Iout increased in proportion to the value of the digital signal. As a result, it was confirmed that the DAC included in the actually fabricated arithmetic circuit operates normally.

Description of Symbols

[0138] 100: DAC, 101-k: Switch, 102-k: Transistor, 110-k: Circuit, 110-n: Circuit, 110-1: Circuit, 120: Circuit, 130: Current Mirror Circuit, 202-k: Variable Resistor Element, 350: Arithmetic Circuit

Claims

1. A semiconductor device having a digital-to-analog conversion circuit, the digital-to-analog conversion circuit has a ferroelectric element that functions as a variable resistor element, the digital-to-analog conversion circuit has a function of outputting an analog current signal, having a function of performing a sum-of-products operation on a weighted value set by the analog current signal and an input value, semiconductor device.

2. In Claim 1, the digital-to-analog conversion circuit has a plurality of circuits and a current mirror circuit, each of the plurality of circuits has a switch and the variable resistor element whose first terminal is electrically connected to the first terminal of the switch, the second terminal of the switch included in each of the plurality of circuits is electrically connected to a first wiring to which a first power supply potential is applied, the second terminal of the variable resistor element included in each of the plurality of circuits is electrically connected to the input terminal of the current mirror circuit, the current mirror circuit has a function of outputting the analog current signal, semiconductor device.

3. In Claim 2, the switches included in each of the plurality of circuits correspond one-to-one to each bit of the digital signal input to the digital-to-analog conversion circuit, the switches included in each of the plurality of circuits have their conduction states controlled according to the value of the corresponding bit, the switches included in each of the plurality of circuits have the current value flowing in the conduction state weighted according to the bit, semiconductor device.

4. In any one of Claims 1 to 3, the ferroelectric element has a ferroelectric tunnel junction, semiconductor device.

5. In any one of Claims 1 to 4, the ferroelectric element has an oxide containing either one or both of hafnium and zirconium as a ferroelectric material, semiconductor device.

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