Automated feed-forward and feedback sequences for patterning CD control

Abstract

A method for implementing a feedback sequence for patterning CD control includes performing a series of process steps on a wafer to obtain a plurality of features, the process steps being performed under process conditions. The method includes measuring dimensions of the plurality of features after performing the series of process steps. The method includes determining differences between the measured dimensions and target dimensions for the plurality of features. The method includes modifying the process conditions for the process steps based on the differences and sensitivity factors for the plurality of features related to changes in the dimensions and changes in the process conditions.

Description

Technical Field

[0001] This embodiment relates to the fabrication of semiconductor devices.

Background Art

[0002] Many of the latest semiconductor fabrication processes are carried out in plasma process modules where the substrate is held on a substrate holder when exposed to plasma. These processes are carried out to generate features. Through advanced patterning techniques that include multiple etching and deposition process steps for high-end devices, the size of feature dimensions can continue to be reduced. In particular, smaller features can be obtained using multiple patterning steps with larger dimensions. These advanced patterning techniques also increase the density of features on the substrate. For example, double patterning doubles the density of features such that the density of features becomes twice the original density.

[0003] Multi-patterning schemes enable the continued scaling of state-of-the-art logic and memory devices and require tight critical dimension (CD) and across-wafer uniformity control, as well as wafer-to-wafer uniformity control. As the number of process steps for these applications continues to increase, it becomes increasingly important to minimize variability since each additional step contributes to the overall variation. The critical dimension of features is typically controlled using a manual trial-and-error process. However, this process is inefficient and time-consuming and cannot be used for in-process variations in dimensions and / or process steps. For example, the trial-and-error process is difficult to account for variations in critical dimensions for incoming photolithography substrates and difficult to account for changes to the process. Further, these trial-and-error processes are difficult to account for non-uniformity in feature dimensions across the wafer.

[0004] The background description provided herein is for the purpose of generally presenting the content of the present disclosure. Within the scope described in this background art section, research by the inventors named at the present time, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, are not admitted as prior art against the present disclosure, whether explicitly or implicitly.

[0005] Embodiments of the present disclosure arise in such a situation.

Summary of the Invention

[0006] This embodiment relates to solving one or more problems found in the related art. Specifically, it includes automated feedforward and feedback control for a double patterning process implemented on a substrate in order to manage the variability introduced during each step of the multi-patterning process. For example, the feedforward and / or feedback control can be used for local fine-tuning to minimize fluctuations across the substrate by correcting the variability introduced in the steps of the patterning process, as well as for correcting the non-uniformity of incoming patterns. Some embodiments of the inventions of the present disclosure are described below.

[0007] Embodiments of the present disclosure include a method for establishing a sensitivity coefficient used to control core critical dimensions associated with features formed in a double patterning process. The method includes performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features, the first process step in the series of process steps being performed under a first process condition, and the series of process steps including at least one process step. The method includes performing a series of process steps on a second plurality of test wafers, each of the second plurality of test wafers forming a plurality of features, and the first process step being performed under a second process condition. The method includes measuring a first dimension of a plurality of features located on the first plurality of test wafers. The method includes measuring a second dimension of a plurality of features located on the second plurality of test wafers. The method includes determining a sensitivity coefficient for a plurality of features related to a change in dimension and a change in process condition.

[0008] Other embodiments of the present disclosure include a non-transitory computer-readable medium storing a computer program for implementing a method for establishing a sensitivity coefficient used to control core critical dimensions associated with features formed in a double patterning process. The non-transitory computer-readable medium includes program instructions for performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features, the first process step in the series of process steps being performed under a first process condition, and the series of process steps including at least one process step. The non-transitory computer-readable medium includes program instructions for performing a series of process steps on a second plurality of test wafers, each of the second plurality of test wafers forming a plurality of features, and the first process step being performed under a second process condition. The non-transitory computer-readable medium includes program instructions for measuring a first dimension of a plurality of features located on the first plurality of test wafers. The non-transitory computer-readable medium includes program instructions for measuring a second dimension of a plurality of features located on the second plurality of test wafers. The non-transitory computer-readable medium includes program instructions for determining a sensitivity coefficient for a plurality of features associated with a change in dimension and a change in process condition.

[0009] Still other embodiments of the present disclosure are computer systems including a processor and a memory coupled to the processor and storing instructions that, when executed by the computer system, cause the computer system to execute a method for establishing a sensitivity coefficient used to control core critical dimensions associated with features formed in a double patterning process. The method includes performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features, wherein a first process step in the series of process steps is performed under a first process condition, and the series of process steps includes at least one process step. The method includes performing a series of process steps on a second plurality of test wafers, each of the second plurality of test wafers forming a plurality of features, wherein the first process step is performed under a second process condition. The method includes measuring a first dimension of a plurality of features located on the first plurality of test wafers. The method includes measuring a second dimension of a plurality of features located on the second plurality of test wafers. The method includes determining a sensitivity coefficient for a plurality of features related to a change in dimension and a change in process condition.

[0010] Other embodiments of the present disclosure include a method for performing feedback and controlling core critical dimensions associated with features formed in a double patterning process. The method includes performing a series of process steps on a wafer to obtain a plurality of features, the process steps being performed under process conditions. The method includes measuring dimensions of the plurality of features after performing the series of process steps. The method includes determining a difference between the measured dimensions and target dimensions for the plurality of features. The method includes modifying the process conditions for the process steps based on the differences and sensitivity coefficients for the plurality of features related to changes in dimension and changes in process conditions.

[0011] Other embodiments of the present disclosure include a non-transitory computer-readable medium storing a computer program for implementing a method for implementing feedback and controlling core critical dimensions associated with features formed in a double patterning process. The non-transitory computer-readable medium includes program instructions for performing a series of process steps on a wafer to obtain a plurality of features, the process steps being performed under process conditions. The non-transitory computer-readable medium includes program instructions for measuring the dimensions of the plurality of features after performing the series of process steps. The non-transitory computer-readable medium includes program instructions for determining the difference between the measured dimensions and the target dimensions for the plurality of features. The non-transitory computer-readable medium includes program instructions for modifying the process conditions for the process steps based on the differences and sensitivity coefficients for the plurality of features associated with changes in dimensions and changes in process conditions.

[0012] Still other embodiments of the present disclosure disclose a computer system including a processor and a memory coupled to the processor and storing instructions that, when executed by the computer system, cause the computer system to perform a method for implementing feedback and controlling core critical dimensions associated with features formed in a double patterning process. The method includes performing a series of process steps on a wafer to obtain a plurality of features, the process steps being performed under process conditions. The method includes measuring the dimensions of the plurality of features after performing the series of process steps. The method includes determining the difference between the measured dimensions and the target dimensions for the plurality of features. The method includes modifying the process conditions for the process steps based on the differences and sensitivity coefficients for the plurality of features associated with changes in dimensions and changes in process conditions.

[0013] Other embodiments of the present disclosure include methods for performing feedforward and controlling core critical dimensions associated with features formed in a double patterning process. The method includes measuring the incoming ADI dimension of a mandrel on a wafer. The method includes determining the difference between the incoming ADI dimension of the mandrel and the desired ADI dimension. The method includes performing an etching process step based on the difference in the etching process step and the etching rate and modifying the time to achieve the desired ADT dimension of the core feature based on the incoming ADI dimension, the core feature being formed when performing a first patterning process of a self-aligned double patterning (SADP) process. The method includes receiving a change in a second patterning process of the SADP process. The method includes determining a modified ASD dimension for an oxide layer over the core feature based on the change in the second patterning process. The method includes determining the number of deposition cycles to achieve the modified ASD dimension based on the deposition rate of the ALD process and the desired ADT dimension of the core feature when performing an atomic layer deposition (ALD) process.

[0014] Other embodiments of the present disclosure include a non-transitory computer-readable medium storing a computer program for implementing a method for performing feedforward and controlling core critical dimensions associated with features formed in a double patterning process. The non-transitory computer-readable medium includes program instructions for measuring the incoming ADI dimension of a mandrel on a wafer. The non-transitory computer-readable medium includes program instructions for determining the difference between the incoming ADI dimension of the mandrel and the desired ADI dimension. The non-transitory computer-readable medium includes program instructions for performing an etching process step based on the difference in the etching process steps and the etching rate and modifying the time to achieve the desired ADT dimension of the core feature based on the incoming ADI dimension, where the core feature is formed when performing the first patterning process of a self-aligned double patterning (SADP) process. The non-transitory computer-readable medium includes program instructions for receiving a change in the second patterning process of the SADP process. The non-transitory computer-readable medium includes program instructions for determining a modified ASD dimension for an oxide layer on the core feature based on the change in the second patterning process. The non-transitory computer-readable medium includes program instructions for determining the number of deposition cycles to achieve the modified ASD dimension based on the deposition rate of an atomic layer deposition (ALD) process and the desired ADT dimension of the core feature when performing the ALD process.

[0015] Still other embodiments of the present disclosure are computer systems including a processor and a memory coupled to the processor and storing instructions that, when executed by the computer system, cause the computer system to perform a method for performing feedforward and controlling core critical dimensions associated with features formed in a double patterning process. The method includes measuring an incoming ADI dimension of a mandrel on a wafer. The method includes determining a difference between the incoming ADI dimension of the mandrel and a desired ADI dimension. The method includes performing an etching process step based on a difference in the etching process step and an etching rate and modifying a time to achieve a desired ADT dimension of a core feature based on the incoming ADI dimension, the core feature being formed when performing a first patterning process of a self-aligned double patterning (SADP) process. The method includes receiving a change in a second patterning process of the SADP process. The method includes determining a modified ASD dimension for an oxide layer over the core feature based on the change in the second patterning process. The method includes determining a number of deposition cycles to achieve the modified ASD dimension based on a deposition rate of an atomic layer deposition (ALD) process and the desired ADT dimension of the core feature when performing the ALD process.

[0016] These and other advantages will be understood by those skilled in the art upon reading the specification and claims throughout.

Brief Description of the Drawings

[0017] Embodiments may be best understood by reference to the following description taken in conjunction with the accompanying drawings.

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Best Mode for Carrying Out the Invention

[0032] The following detailed description includes many specific details for illustrative purposes, but those skilled in the art will understand that many variations and modifications to the following details are within the scope of the present disclosure. Accordingly, the aspects of the present disclosure described below are described without loss of generality with respect to the claims that follow this description and without imposing limitations.

[0033] Generally speaking, various embodiments of the present disclosure describe systems and methods that provide automated feedforward and / or feedback control for a double patterning process implemented on a substrate to manage variability introduced during each step of a multi-patterning process. Also, the feedforward and / or feedback control includes a mathematical framework for implementing automation of a control sequence. Further, embodiments of the present disclosure include a transient solver for implementing the mathematical framework. For example, instead of manually performing feedforward and feedback control, the automated feedforward and / or feedback control, in embodiments of the present disclosure, can be used for local fine-tuning to minimize substrate-wide variations by correcting variability introduced in steps of the patterning process, as well as for correcting non-uniformity of incoming patterns. For example, the automated feedforward and / or feedback control is important for accounting for any changes in incoming optical CDs (critical dimensions) or variations in lines for dry etching during the double patterning process. As a result, the automated feedforward and / or feedback control improves the green-to-green time for any changes in pre-steps or post-steps involving the multi-patterning process. As a result of the automation, the feedforward and / or feedback control can be used to minimize variations in CDs and CDNU (critical dimension non-uniformity), save additional costs of iterations, and provide flexibility to make process changes when implementing the patterning process.

[0034] The implementation of automated and / or feedback control is described using the double patterning process throughout the specification, but it is understood that the techniques described herein for automated and / or feedback control can be used in any multi-patterning process such as a quadruple patterning process.

[0035] Embodiments of the present disclosure are used in plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, plasma enhanced chemical vapor deposition (PECVD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, and any other semiconductor processing systems that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers, and relate to plasma process modules including processes such as electroplating, electroetching, electrolytic polishing, electrochemical mechanical polishing, deposition, wet deposition, and processes such as silicon through via (TSV) processes. Further, embodiments of the present disclosure are not limited to the examples provided herein and may be practiced in different plasma processing systems (e.g., inductively coupled systems, capacitively coupled systems, electron cyclotron resonance systems, microwave systems, etc.) using different configurations, geometries, and plasma generation techniques. Examples of plasma processing systems and plasma process modules are disclosed in U.S. Pat. Nos. 8,862,855, 8,847,495, and 8,485,128, and U.S. Patent Application No. 15 / 369,110, all of the above disclosures being incorporated by reference in their entirety. The plasma process module of an embodiment of the present disclosure includes a pedestal configured to support a substrate, with or without an electrostatic chuck (ESC), and the pedestal and / or ESC can include one or more heater zones used to transfer heat to the substrate when performing a process. Generally, the heating assembly can include a showerhead, ESC, support chuck, pedestal, chamber component, or other structure or component that can be implemented in a reactor, chamber, process module, etc. used to process the substrate.

[0036] Throughout the specification, the term "substrate" as used herein refers to a semiconductor wafer in embodiments of the present disclosure. However, in other embodiments, the term substrate can refer to a substrate formed of sapphire, GaN, GaAs, or SiC, or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymer materials, and the like. Also, in various embodiments, the substrates referred to herein can differ in form, shape, and / or size. For example, in some embodiments, the substrate referred to herein can correspond to a 200 mm (millimeter) semiconductor wafer, a 300 mm semiconductor wafer, or a 450 mm semiconductor wafer. Also, in some embodiments, the substrate referred to herein can correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, and can include other shapes.

[0037] With the above general understanding of the various embodiments, exemplary details of the embodiments will now be described with reference to the various drawings. Elements and / or components that are similarly numbered in one or more of the figures are generally intended to have the same configuration and / or function. Further, the figures may not be drawn to scale, but are intended to show and emphasize novel concepts. It will be apparent that the present embodiments can be practiced without some or all of these specific details. In other instances, well-known process operations are not described in detail so as not to unnecessarily obscure the present embodiments.

[0038] Figure 1A shows a reactor system 100 that can be used to deposit a film on a substrate, such as those formed in a multi-patterning process, including wet (e.g., chemical) and dry (e.g., plasma) etching and deposition processes such as atomic layer deposition (ALD) processes. These reactors can utilize one or more heaters and can use a common terminal configuration in this exemplary reactor to control the temperature for uniformity or custom settings. More specifically, Figure 1A shows a substrate processing system 100 used to process a wafer 101. The system includes a chamber 102 having a lower chamber portion 102b and an upper chamber portion 102a. A central column 160 is configured to support a pedestal 140, which is a power supply electrode in one embodiment. The pedestal 140 is electrically coupled to an RF power supply 104 via a matching network 106. The RF power supply 104 is controlled by a control module 110, such as a controller. The control module 110 is configured to operate the substrate processing system 100 by performing process input and control 108. The process input and control 108 can include a process recipe for depositing or forming a film on the wafer 101, such as power levels, timing parameters, process gases, mechanical movement of the wafer 101, etc.

[0039] Embodiments of the present disclosure include a pedestal 140 with or without an electrostatic chuck (ESC) 145 configured to hold the substrate 101 while it is exposed to a plasma processing environment where plasma is generated. The pedestal 140 and / or the ESC 145 can include one or more heater zones that can be individually controlled when performing a processing operation within the reactor system 100, as further described in Figure 1B.

[0040] The central column 160 also includes lift pins (not shown), each of which is actuated by a corresponding lift pin actuating ring 120 controlled by lift pin control 122. The lift pins are used to raise the wafer 101 from the pedestal 140 and lower the wafer 101 after the end effector has lifted and placed the wafer. The substrate processing system 100 further includes a process gas 114, for example, a gas supply manifold 112 connected to the supply of gas chemicals from the facility. Depending on the process being performed, the control module 110 controls the delivery of the process gas 114 via the gas supply manifold 112, chamber pressure, generation of RF power from one or more RF power supplies, exhaust pumps, etc. Next, the selected gas flows into the showerhead 150 and is distributed into the spatial volume defined between the surface of the showerhead 150 facing the wafer 101 and the wafer 101 present on the pedestal 140. In an ALD process, the gas can be a reactant selected for absorption or reaction with the absorbed reactant.

[0041] Furthermore, the gas may or may not be pre-mixed. Appropriate valve regulation and mass flow control mechanisms can be used to ensure that the correct gas is delivered during the deposition and plasma treatment stages of the process. The process gas exits the chamber via an outlet. A vacuum pump (e.g., a single- or two-stage mechanical dry pump and / or a turbomolecular pump) withdraws the process gas and maintains the reactor at an appropriately low pressure by a closed-loop controlled flow restriction device such as a throttle valve or a pendulum valve.

[0042] A carrier ring 175 surrounding the outer region of the pedestal 140 is also shown. The carrier ring 175 is configured to be positioned on a carrier ring support region that is one step lower than the wafer support region at the center of the pedestal 140. The carrier ring includes an outer edge side of its disk structure, e.g., an outer radius, and an inner radius of its disk structure that is closest to the location where the wafer 101 sits, e.g., the wafer edge side. The wafer edge side of the carrier ring includes a plurality of contact support structures configured to lift the wafer 101 when the carrier ring 175 is lifted by the spider fork 180. Thus, the carrier ring 175 can be lifted together with the wafer 101 and rotated, for example, to another station within a multi-station system. In other embodiments, the chamber is a single-station chamber.

[0043] Furthermore, the heater temperature controller 105 is configured to control the temperature of one or more heater zones of the pedestal 140, which may or may not have an ESC 145, and the heater zones can be located within the pedestal and / or the ESC. The heater zones are used to enable accurate control of the surface temperature of the pedestal 140 during substrate processing, regardless of the presence or absence of the ESC 145. The plurality of controllable heater zones can adjust the temperature profile of the pedestal 140 (e.g., a radial profile, an azimuthal profile, etc.), regardless of the presence or absence of the ESC 145, and provide the ability to compensate for the variability introduced during steps of a multi-patterning process. For example, the variability may be caused by changing environmental conditions (e.g., changing heat loss conditions, heat transfer conditions, etc. between different process steps). It is understood that the control of the temperature of one or more heater zones of the pedestal 140, which may or may not have an ESC 145, can be performed by the heater controller 105 and the controller 110, either individually or in combination.

[0044] FIG. 1B shows a pedestal 140A configured as a multi-zone heating system including a plurality of heater zones, each of which is individually controllable to provide heat, according to one embodiment of the present disclosure. The upper surface of the pedestal 140A can include an area configured to support the substrate 101 during processing. In another embodiment, the heater zones can be configured within an ESC that can be the top layer of the pedestal 140, and the ESC can include a base plate, a bonding layer disposed on the base plate, and a ceramic layer disposed on the bonding layer. For the purpose of simplicity and clarity, the heater zones within the pedestal are described below, but it is understood that the heater zones can be located within the pedestal and / or the ESC in various embodiments.

[0045] For purposes of illustration, each heater zone within the pedestal 140A, with or without an ESC, can be heated in one embodiment by one or more heater traces (e.g., resistive elements) controlled by a heater controller 105 and / or a controller 110. For example, each of the heater zones can include a heater trace (e.g., resistive element) electrically coupled to a controller for controlling the power supplied to the corresponding heater trace (e.g., the power supplied through a corresponding heater power source (not shown)). Each of the heater traces can be integrated or embedded within the corresponding heater zone and configured to provide heat to the corresponding heater zone. For example, the heater traces can be fabricated and formed within one of the layers of the pedestal 140A and / or the ESC such that the heater traces are disposed within the layer. Thus, the heat generated by the heater traces can be transferred to the layers of the pedestal 140A and / or the ESC and further transferred to the surface of the pedestal 140A, with or without an ESC.

[0046] The multi-zone heating system of pedestal 140A with or without an ESC shown in FIG. 1B is just an example, and it should be understood that various layout configurations can be supported. For example, the layout configuration of the heater zones (e.g., a grid pattern) can be symmetric, asymmetric, uniformly distributed throughout the grid pattern, non-uniformly distributed throughout the grid pattern, of various shapes that fit within the contour of pedestal 140A with or without an ESC, etc. For example, a heating system having one or more heater zones can be provided, such as a three-heater zone system including an inner zone, an intermediate zone, and an outer zone. The number of heater zones varies between systems and can include, by way of example, heater zones numbered from 1 to 5, or 5 to 10, or 5 to 15, or more than 5 heater zones, or more than 10 heater zones, or more than 20 heater zones, or more than 50 heater zones, or more than 75 heater zones, or more than 100 heater zones, or more than 125 heater zones, or more than 150 heater zones. In yet another example, the heater zones can be grouped into layers, with one set of multiple heater zones in one horizontal layer and at least one other layer including another set of multiple heater zones. In other embodiments, the heater zones can be oriented in various configurations, such as in a pie shape, a circularly oriented heating circle, a grid of individual resistance elements, a zigzag resistance element, a single resistance element, etc. As an example of an embodiment, some layout configurations can provide a continuous circular ring of resistance elements for multiple zones.

[0047] For purely illustrative purposes, pedestal 140A, with or without an ESC, includes ten heater zones numbered from 1 to 10. The heater zones can be defined by radial and / or azimuthal parameters. For example, pedestal 140A can be divided by one or more radii including radius 181, radius 182, radius 183, and radius 184. Additionally, pedestal 140A can be divided by one or more azimuths including azimuths 191 to 198. As shown in FIG. 1B, zone 1 is a radial zone and is located at a radius less than or equal to radius 181. Zone 2 is also a radial zone and is located between radius 181 and radius 182. Zones 3 to 6 are located within the radial zones defined by radius 182 and radius 183 and each lies between different azimuths. For example, within the radial zones defined above, zone 3 is located between azimuths 191 and 192, zone 4 is located between azimuths 192 and 193, zone 5 is located between azimuths 193 and 195, and zone 6 is located between azimuths 191 and 194. Further, zones 7 to 10 are located within the radial zones defined by radius 183 and radius 184 and each lies between different azimuths. For example, within the radial zones defined above, zone 7 is located between azimuths 195 and 198, zone 8 is located between azimuths 197 and 198, zone 9 is located between azimuths 196 and 197, and zone 10 is located between azimuths 195 and 196.

[0048] In one embodiment, a multi-zone heating system is provided in one layer of pedestal 140A with or without an ESC, and the zones are arranged in one or more grid patterns. Each of the elements within the grid is individually controllable to provide heat. The multi-zone heating system provided in one layer of pedestal 140A with or without an ESC can be configured to provide fine-tuning of the heat across pedestal 140A. In another embodiment, the heating system can be distributed across multiple layers of pedestal 140A with or without an ESC. For example, one layer can provide fine-tuning of the heat provided to pedestal 140A. The fine-tuning of the heat can be provided by the grid pattern of heating elements and / or heating zones described above for the multi-zone heating system. The heating system can include another layer of one or more heating zones configured to provide coarse-tuning of the heat applied to pedestal 140A with or without an ESC. For example, the coarse-tuning can be implemented by one or more rings of heating zones that can be provided across pedestal 140A with or without an ESC, such as a dual-heater zone pedestal 140A (e.g., two heater zones), a tri-heater zone pedestal 140A (e.g., three heater zones), or a quad-heater zone pedestal 140A (e.g., four heater zones).

[0049] FIG. 2 shows a top view of a multi-station processing tool or process module 110 provided with four processing stations. This top view is of the lower chamber portion 102b (e.g., the upper chamber portion has been removed for purposes of illustration), and the four stations are accessed by spider forks 226. Each spider fork or fork includes first and second arms, each of which is positioned around a portion of each side of the pedestal 140. In this figure, the spider forks 226 are shown in dashed lines to convey that they are under the carrier ring 200. The spider forks 226 are configured to use the engagement and rotation mechanism 220 to simultaneously lift and raise the carrier ring 200 from the stations (i.e., from the lower surface of the carrier ring 200), and then rotate at least one or more of the stations before lowering the carrier ring 200 (at least one of the carrier rings supports the wafer 101) to the next location, whereby further plasma processing, treatment, and / or film deposition can be performed on each wafer 101.

[0050] FIG. 3 shows a schematic diagram of one embodiment of a multi-station processing tool or process module 110 having an inbound load lock 302 and an outbound load lock 304. The robot 131 is configured to move a substrate from a cassette loaded via the pod 308 at atmospheric pressure to the inbound load lock 302 via the atmospheric port 310. The inbound load lock 302 is coupled to a vacuum source (not shown), and thus can be pumped down when the atmospheric port 310 is closed. The inbound load lock 302 also includes a chamber transfer port 316 that is interlocked with the processing chamber 102b. Thus, when the chamber transfer Port 316 is opened, another robot (such as the robot 312 of the vacuum transfer module 190, not shown) can move the substrate from the inbound load lock 302 to the pedestal 140 of the first processing station for processing.

[0051] The illustrated processing chamber 102b includes four process stations numbered from 1 to 4 in the embodiment shown in FIG. 3. In some embodiments, the processing chamber 102b may be configured to maintain a low pressure environment, whereby the substrate can be transferred between process stations using a carrier 200 without undergoing vacuum breakage and / or air exposure. Each process station illustrated in FIG. 3 includes a process station substrate holder (shown as 318 for station 1) and a process gas feed line inlet.

[0052] FIG. 3 also illustrates a spider fork 226 for transferring a substrate within the processing chamber 102b. The spider fork 226 rotates to enable the transfer of wafers from one station to another. The transfer is performed by enabling the spider fork 226 to lift the carrier 200 from the outer lower surface, whereby the wafer is lifted and the wafer and carrier rotate together to the next station. In one configuration, the spider fork 226 is made of a ceramic material to withstand a high level of heat during processing.

[0053] In the fabrication of a semiconductor wafer (hereinafter, "wafer"), a layer of core material can be deposited on the wafer and patterned for use as a mask when processing one or more underlying materials on / within the wafer. In various embodiments, the wafers can differ in form, shape, and / or size. For example, in some embodiments, the wafers referred to herein can correspond to semiconductor wafers with a diameter of 200 millimeters (mm), semiconductor wafers with a diameter of 300 mm, or semiconductor wafers with a diameter of 450 mm. Also, in some embodiments, the wafers referred to herein can have a non-circular shape, such as a rectangular substrate for a flat panel display, among other shapes.

[0054] The layer of core material is exposed through a reticle to a pattern of light that passes through the photolithography process onto the wafer, whereby the core material can be developed into a predetermined pattern of features, some of the core features having critical dimensions. The critical dimension in this context refers to the minimum dimension that is controlled in a particular fabrication process. The critical dimension of the core features is controlled by the capabilities of the photolithography process used to pattern the layer of core material. For example, there are limits to the extent to which the critical dimension of the core features can be reduced using standard photolithography processes, such as using photolithography based on 193 nanometer light. Attempting to form core features with critical dimensions that are too small can cause problems when patterning the layer of core material using standard photolithography processes. Thus, standard photolithography processes effectively limit the extent to which the critical dimension of the core features can be reduced. However, when core features are formed with the minimum critical dimension that the photolithography process can accurately provide, it is possible to fabricate features with even smaller critical dimensions using the core features by performing a series of etching processes and forming a mask having features based on the core features patterned by photolithography. Such etching processes include self-aligned multiple patterning (SAMP) processes, and can include, among other things, self-aligned double patterning (SADP) processes and self-aligned quadruple patterning (SAQP) processes.

[0055] Figures 4A - 4H show partial vertical cross-sectional views of a wafer 101 undergoing a number of operations in an SADP process, according to some embodiments. Figures 4A - 4C show a first patterning in the SADP process, and Figures 4D - 4H show a second patterning in the SADP process, each of the patterning processes being able to be performed in a different chamber.

[0056] FIG. 4A shows a vertical cross-sectional view of a portion of a wafer 101 on which photolithography is performed to form one or more photoresist (PR) mandrels 403. In particular, the layer of target material 405 to be etched is deposited on top of the wafer 101, i.e., on top of the underlying material 407 of the wafer 101. One or more core material layers, such as core 1 layer 401 and core 2 layer 402, may be formed on top of the underlying material 107.

[0057] The photoresist (PR) layer can be applied to the core 2 layer 402 by a process such as spin coating. The photoresist layer is exposed to light (e.g., ultraviolet light) or other exposure radiation through a photomask, whereby a portion of the photoresist is exposed to the light. Lithography is performed so as to be able to etch the unprotected photoresist. As shown, the photoresist is developed and the exposed photoresist is removed, thereby revealing the pattern of the PR mandrel 403 formed on the core 1 layer 401. In various embodiments, the PR mandrel 403 that defines the feature can be formed of a photoresist material or a carbon material, particularly, spin-on carbon, chemical vapor deposition (CVD) carbon, plasma enhanced chemical vapor deposition (PECVD) carbon, or a flowable carbon mixture, etc. Each of the PR mandrels 403 has a critical dimension ADI measured in a horizontal direction substantially parallel to the bottom surface 412 of the wafer 101. In some scenarios, the patterned PR mandrel 403 can be referred to as a core mandrel or an inflow PR mandrel introduced into the chamber for etching and deposition processes. In some embodiments, the critical dimension ADI of the PR mandrel 403 can be fabricated at the minimum size that the photolithography process can accurately provide.

[0058] Figure 4B shows the transfer of the mask to the underlying core layer 401 using the pattern of the PR mandrel 403. In particular, the etching can be performed such that it can isotropically etch the areas of the core layer 401 that are not protected by the PR mandrel 403. The etching can be performed using wet chemicals (e.g., an acid in a wet etching process). During the etching process, the core layer 401 can also be trimmed laterally to reveal a core 1 feature 401A having a critical dimension ADT measured in a horizontal direction substantially parallel to the bottom surface 412 of the wafer 101. The critical dimension ADT of the core 1 feature 401A can be equal to or smaller than the critical dimension ADI of the PR mandrel 403 (i.e., ADT = ADI or ADT < ADI). Once the etching is complete, the photoresist within the PR mandrel 403 can be stripped, thereby revealing the core 1 feature 401A in the desired mask pattern.

[0059] In Figure 4C, the first patterning in the SADP process is followed by conformal deposition of a mask material (e.g., an oxide material) or a spacer 1 DEP 415 over the core 1 feature 401. In some embodiments, the mask material is deposited using an atomic layer deposition process. The mask material may be selectively etched such that the oxide layer conforms to the core 1 feature 401A as the spacer 1 DEP 415, and some spacing may be left between the core 1 features 401 to remove the mask material to reveal the core 2 layer 402. The conformal spacer 1 DEP 415 is defined by a critical dimension ASD measured in a horizontal direction substantially parallel to the bottom surface 412 of the wafer 101.

[0060] In FIG. 4D, the first patterning process (e.g., in the second patterning process) is a plasma etching process in which the upper part of the spacer 1 DEP 415 is selectively etched to reveal the core 1 feature 401A, followed by etching (e.g., pulling the core 1 layer 401). In some embodiments, the plasma etching process is performed in a separate chamber. The plasma etching process for removing the upper part of the mask material 415 and the core 1 feature 401A can be an isotropic or anisotropic etching process. As shown, the side spacer 415A of the spacer 1 DEP 415 remains on the wafer 101 and is used as a mask for plasma etching features into the core 2 layer 402. In some embodiments, the side spacer 415A is a square spacer.

[0061] FIG. 4E shows the transfer of the mask formed by the pattern of the side spacer 415A (formed of the material of the core 1 layer 401) onto the underlying core 2 layer 402. In particular, the etching can be performed such that the areas of the core 2 layer 402 not protected by the side spacer 415A can be etched isotropically. Also, the core 2 layer can be trimmed laterally during the etching process. In addition, the side spacer 415A can also be selectively etched. The etching can be performed in an anisotropic manner (e.g., top-down etching) using a dry etching process (e.g., in a dry plasma environment). As shown, the core 2 features 402A that can be trimmed remain on the wafer 101.

[0062] FIG. 4F wherein In the second patterning in the SADP process, conformal deposition of the spacer 2 DEP 425 (e.g., an oxide material) onto the core 2 feature 402A follows. In some embodiments, the oxide material deposition layer is deposited using an atomic layer deposition process. The deposition layer may be selectively etched so that the oxide layer conforms to the features 402A of the core 2 as the spacer 2 DEP 425.

[0063] In FIG. 4G, the second patterning process (e.g., in the second patterning process) is a plasma etching process in which the upper part of the spacer 2 DEP425 is selectively etched to reveal the core 2 feature 402A, and can also be etched and trimmed (e.g., pulling the core 2). Spacer 2 DEP The plasma etching process for removing the upper part of 425 and the core 2 feature 402A can be an isotropic or anisotropic etching process defined to remove material. As shown, the side spacer 425A of the spacer 2 DEP425 remains on the wafer 101 and is used as a mask for plasma etching features into the target material 405.

[0064] FIG. 4H shows a vertical cross-sectional view of a part of the wafer 101 after the final plasma etching process for forming the final feature 405A, showing the transfer of the mask formed by the pattern of the side spacer 425A (formed of the material of the core 2 layer 402) to the underlying target material 405. In particular, the etching can be performed such that the areas of the target material 405 not protected by the side spacer 425A can be etched isotropically. Also, the target material 405 can be trimmed laterally during the etching process. In addition, the side spacer 425A can also be selectively etched. The etching can be performed using a dry etching process (e.g., in a dry plasma environment) in an isotropic or anisotropic manner (e.g., top-down etching). As shown, the final feature 405A remains on the wafer 101.

[0065] The critical dimension of the final feature 405A can be defined by the line width or "line CD" measured in a horizontal direction substantially parallel to the bottom surface 412 of the wafer 101. The spacing between the final features 405A depends on a plurality of factors. For example, the variation in the spacing between different final features 405A can depend on the formation of the core 1 feature 401A, the core 2 feature 402A, the side spacer 415A, and the side spacer 425A. The spacing between the final features 405A may desirably be uniform. Also, it may be desirable for the line width or line CD of the final feature 405A to be uniform across the wafer 101. The variation between the line CDs of the final features 405A across the wafer is referred to as critical dimension non-uniformity (CDNU). It is desirable to minimize CDNU across the wafer 101. CDNU can lead to device failures for some dies formed on the wafer 101 and / or variations in device performance for different dies formed on the same wafer or different wafers. Embodiments of the present disclosure provide the implementation of automated feedforward and / or feedback control for a double patterning process to manage the introduced variability (e.g., minimize CDNU).

[0066] FIG. 5 is a flow diagram showing a method for generating a mathematical model including one or more sensitivity coefficients for implementing automated feedforward and / or feedback control for a multi-patterning process implemented on a substrate and for managing variability introduced during each step of the multi-patterning process. For example, the mathematical model can be used for feedback control by determining variations in the output of the multi-patterning process (e.g., the dimensions of the final features on the wafer) that may be caused by process variability. In another example, the mathematical model can be used for feedforward control by adjusting variations in the input variables for the process steps (e.g., variations in the dimensions of the incoming PR mandrel from the desired dimensions) while implementing the multi-patterning process such that the output (e.g., the dimensions of the final features on the wafer) meets the target.

[0067] The mathematical model includes one or more sensitivity coefficients that provide sensitivity of feature dimensions (e.g., dimensions of final features, trims, depositions) to temperature and time. These sensitivity coefficients can be determined through empirical tests such as measurements of process variations or disturbances.

[0068] At 510, the method includes performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features. The test wafers may be blanket wafers and / or topography wafers (e.g., having features). For example, the series of process steps may be included in a multi-patterning process (e.g., SADP process) performed on the wafers and includes at least one process step (e.g., the first patterning of the SADP process). The first process step in the series of process steps is performed under a first process condition. At 520, the method includes performing a series of process steps on a second plurality of test wafers, each of the second plurality of test wafers forming a plurality of features. More specifically, the first process step is performed under a second process condition.

[0069] In that way, one or more sensitivity coefficients can be generated using the variation between the first and second pluralities of test wafers determined (e.g., measured) at an intermediate position within the series of process steps or at the end of the performance of the series of process steps, and for example, a mathematical model can be constructed. In particular, at 530, the method includes measuring a first dimension of a plurality of features located on the first plurality of test wafers. Also, at 540, the method includes measuring a second dimension of a plurality of features located on the second plurality of test wafers. The measurement of the first or second dimension can be achieved by measuring each of the plurality of features on the respective plurality of test wafers and determining a plurality of dimensions. The average of the plurality of dimensions becomes the first or second dimension. The plurality of features can be measured at an intermediate point or at the end of the series of process steps.

[0070] At 550, the method includes determining sensitivity coefficients for a plurality of features related to the change in dimension and the change in process condition. In one embodiment, the sensitivity coefficient is based on the difference between the first process condition and the second process condition and the difference between the first dimension and the second dimension.

[0071] In one embodiment, the first process condition is the first temperature of the pedestal and / or the ESC of the pedestal, and the pedestal is configured for wafer support. The first process step can be an etching process step, and the etching process can include a trim process. In this case, the second process condition is the second temperature of the pedestal and / or the ESC. Considering the above, the sensitivity coefficient can be a trim sensitivity coefficient related to the change in the dimensions of a plurality of features and the change in the temperature of the ESC and / or the pedestal. In one embodiment, the sensitivity coefficient can indicate the sensitivity of the etching and / or trim process (as the first process step) to temperature, which is converted to the dimensions determined from the final features formed at the end of the multi-patterning process. In another embodiment, the dimensions are determined from the intermediate features formed during the multi-patterning process.

[0072] In another embodiment, the first process condition is the first period for performing an etching process step as the first process step, and the etching process can include a trim process. The second process condition is the second period for performing the etching and / or trim process step. Considering the above, the sensitivity coefficient can be a trim sensitivity coefficient related to the change in the dimensions of a plurality of features when performing the etching and / or trim process step and the change in time. In one embodiment, the sensitivity coefficient can indicate the sensitivity of the etching and / or trim process (as the first process step) to time, which is converted to the dimensions determined from the final features formed at the end of the multi-patterning process. In another embodiment, the dimensions are determined from the intermediate features formed during the multi-patterning process.

[0073] In another embodiment, the first process condition is the first temperature of the ESC and / or pedestal configured for wafer support. The first process step can be a deposition step. The second process condition is the second temperature of the ESC and / or pedestal. Considering the above, the sensitivity coefficient can be a deposition sensitivity coefficient related to the change in the dimensions of a plurality of features and the change in the temperature of the ESC and / or pedestal. In one embodiment, the sensitivity coefficient can indicate the sensitivity of the deposition process (as the first process step) to temperature, which is converted to dimensions determined from the final features formed at the end of the multi-patterning process. In another embodiment, the dimensions are determined from intermediate features formed during the multi-patterning process.

[0074] In yet another embodiment, the first process condition is the first number of cycles of a deposition step (e.g., ALD) that is the first process step. The second process condition is the second number of cycles of the deposition step. Considering the above, the sensitivity coefficient is a deposition sensitivity coefficient related to the change in the dimensions of a plurality of features when performing the deposition process step as the first process step and the change in the number of atomic layer deposition cycles. In one embodiment, the sensitivity coefficient can indicate the sensitivity of the deposition process (as the first process step) to temperature, which is converted to dimensions determined from the final features formed at the end of the multi-patterning process. In another embodiment, the dimensions are determined from intermediate features formed during the multi-patterning process.

[0075] FIG. 6A is a flowchart 600A showing a method of automated feedback control for a multi-patterning process implemented on a substrate to manage variability introduced during one or more steps of the multi-patterning process, according to one embodiment of the present disclosure. For example, the multi-patterning process may be a self-aligned double patterning process. The feedback control involves observing the dimensions of the final features formed on the wafer after the multi-patterning process is performed, adjusting one or more processes, and correcting the variation of those dimensions from a target or desired dimension on subsequent wafers.

[0076] In one embodiment, the multi-patterning process is a SADP process. The feedback control is applied during the first patterning of the SADP process and may include a wet etching process and a deposition process that may include a trim process. The first patterning in the SADP process is performed in a first chamber, and the second patterning in the SADP process is performed in a second chamber. The feedback control can be implemented to adjust the process in the first patterning performed in the first chamber.

[0077] At 610, the method includes performing a series of process steps on a wafer to obtain a plurality of features, where the process steps are performed under process conditions. For example, the series of process steps may be a multi-patterning process such as a SADP process. The process steps can be included within the first patterning of the SADP process. Also, the features may be final features formed at the end of a series of process steps, such as the final feature 405A in FIG. 4H.

[0078] At 620, the method includes measuring the dimensions of a plurality of features after performing a series of process steps. In particular, each of the dimensions of the plurality of features is measured to obtain a plurality of dimensions. The dimensions can be measured from the final features formed after completing a series of process steps such as an SADP process. For example, the dimension can be line CD of the final feature 405A in FIG. 4H. The average of the plurality of dimensions becomes the dimensions of the plurality of features.

[0079] At 630, the method includes determining the difference between the measured dimensions and the target dimensions for the plurality of features. For example, the target dimension can be the customer-specified line CD of the final feature 405A formed by the SADP process.

[0080] Using feedback control, at least one process step in the first patterning of a multi-patterning (e.g., SADP) process is adjusted to enable subsequent wafers to achieve the dimensions of the final features that match the target dimensions. In particular, at 640, the method includes modifying the process conditions for the process steps based on the differences and sensitivity coefficients for the plurality of features related to the change in dimensions and the change in process conditions. As described above, the sensitivity coefficient can be a mathematical model used to associate the variation in output (e.g., the dimensions of the final features on the wafer) with the variability of the process. In that way, considering the variation in output, the change in process conditions can be determined from the sensitivity coefficient to achieve an output having the target dimensions. Accordingly, a series of process steps including the modified process steps is performed on at least one other subsequent wafer, thereby enabling the subsequent wafer to achieve the dimensions of the final features that are the target dimensions.

[0081] In one embodiment, the process conditions are the temperature of the ESC and / or pedestal configured to support the wafer. For example, the process conditions can be one or more temperatures applied to one or more heater zones of the ESC and / or pedestal. The process step can be an etching process step that can include a trim process. In that case, the sensitivity coefficient can be a trim sensitivity coefficient related to the change in the dimensions of a plurality of features, as well as the temperature change of the ESC and / or pedestal, or the temperature change of the heater zones within the ESC and / or pedestal. That is, the sensitivity coefficient indicates the sensitivity of the etching and / or trim process to temperature, which is converted to the dimensions determined from the final features formed at the end of the multi-patterning process. Thus, the temperature can be corrected when performing subsequent etching process steps on the wafer.

[0082] In another embodiment, the process conditions are the temperature of the ESC and / or pedestal configured for wafer support. For example, the process conditions can be one or more temperatures applied to one or more heater zones of the ESC and / or pedestal. The process step can be a deposition step. In that case, the sensitivity coefficient can be a deposition sensitivity coefficient related to the change in the dimensions of a plurality of features, as well as the change in the temperature of the ESC and / or pedestal, or the change in the temperature of one or more heater zones of the ESC and / or pedestal. That is, the sensitivity coefficient can indicate the sensitivity of the deposition process to temperature, which is converted to dimensions determined from the final features formed at the end of the multi-patterning process. Thus, the temperature can be adjusted (e.g., for one or more heater zones) when performing subsequent wafer deposition process steps. In yet another embodiment, the process step can be a combination of an etching process step that can include a trim process and a deposition step. In that case, the sensitivity coefficient indicates the sensitivity of both the etching process and the deposition process, which is converted to dimensions determined from the final features, and the sensitivity coefficient is related to the change in the dimensions of a plurality of features and the change in the temperature of the ESC and / or pedestal. Thus, the steady-state temperature can be adjusted when performing subsequent wafer etching and deposition process steps.

[0083] In one embodiment, the process conditions are the time for performing the process step, and the process step is an etching process that can include a trim process. In that case, the sensitivity coefficient can be a trim sensitivity coefficient related to the change in the dimensions of a plurality of features and the change in time when performing the etching process. That is, the sensitivity coefficient indicates the sensitivity of the etching and / or trim process to time, which is converted to dimensions determined from the final features formed at the end of the multi-patterning process. Thus, the period for performing the etching and / or trim process can be adjusted for subsequent wafers.

[0084] In another embodiment, the process condition is the number of cycles of the deposition step which is a process step. In that case, the sensitivity coefficient can be a deposition sensitivity coefficient related to the change in the dimensions of a plurality of features when performing the deposition step and the change in the number of atomic layer deposition cycles. Thus, the number of ALD cycles can be corrected on subsequent wafers. In another case, the deposition sensitivity coefficient is related to the change in the dimensions of a plurality of features when performing the deposition step and the change in the overall period. Thus, the overall period for performing the deposition can be corrected on subsequent wafers.

[0085] FIG. 6B shows the non-uniformity of the dimensional distribution (e.g., line CD) of a plurality of final features after performing the SADP process on a wafer, such as those shown in FIGS. 4A-4H. For example, the SADP process is performed on a wafer placed on a pedestal having a temperature of 50 degrees Celsius across each of its heater zones. As shown, the dimension of line CD of the final feature in the outer radial zone 660 is about 192 angstroms. Also, the dimension of line CD of the final feature in the inner radial zone 650 is about 194 angstroms. That is, the final features on the wafer have a dome-shaped distribution of dimensions with respect to line CD, and the final features in the inner radial zone 650 are wider than the final features in the outer radial zone 660. A difference of about 2 angstroms exists between the dimensions of line CD of the final features located in the inner and outer radial zones. For example, if it is desired to select a trim sensitivity coefficient to provide feedback control and thereby achieve a flat profile across the wafer having dimensions similar to those seen in the outer radial zone 660, a temperature change is applied to one or more heater zones corresponding to the inner radial zone 650. Thus, a modified temperature is applied to one or more heater zones to reduce the dimension of the inner radial zone 650 (e.g., by only 2 angstroms), whereby the dimension of line CD with respect to the final features across the wafer is flat (e.g., the dimension is about 192 angstroms across the wafer). As described above, the sensitivity coefficient indicates the sensitivity of the etching and / or trim process to temperature, which is converted to the dimension of line CD determined from the final features formed at the end of the multipatterning process. The trim sensitivity coefficient is defined by Equation 1.

Number

[0086] FIG. 7 is a flow diagram showing a method of automated feedforward control for a multi-patterning process implemented on a substrate to manage variability introduced during one or more steps of the multi-patterning process according to an embodiment of the present disclosure. Feedforward control enables local fine-tuning to minimize wafer-wide variations by correcting variability in control parameters and / or process conditions using advanced software algorithms in combination with unique hardware technologies. For example, feedforward control involves measuring and / or determining one control parameter of the process of the multi-patterning process implemented on the wafer, and reducing the impact of that variability on the output of the multi-patterning process for that wafer (e.g., the final line CD dimension of the wafer) in response to the variability of that control parameter from a desired value. Feedforward control requires a mathematical model that accurately predicts the impact of variability in control parameters on the output of the multi-patterning process for a particular wafer. In particular, in the case of feedforward control, the corrections made to the process conditions of the process steps in the SADP process are based on process knowledge.

[0087] In a feedforward system, accounting for variability in control parameters is based on knowledge about the process in the multi-patterning process in the form of a mathematical model that includes sensitivity coefficients, and knowledge or measurements about process variations. In one embodiment, the critical dimension of the final feature formed at the end of the multi-patterning process is the desired dimension. In another embodiment, the critical dimension of the final feature may be different from the desired one.

[0088] In one embodiment, the multi-patterning process is a SADP process. Feed-forward control is applied in the first patterning of the SADP process and may include a wet etching process that may include a trim process and a deposition process. The first patterning in the SADP process is performed in a first chamber, and the second patterning in the SADP process is performed in a second chamber. Feed-forward control can be implemented to adjust the process in the first patterning performed in the first chamber.

[0089] At 710, the method includes measuring the incoming ADI dimension of the mandrel on the wafer. In particular, the ADI dimensions of a plurality of PR mandrels on the incoming wafer can be measured, and the wafer is introduced into a chamber configured to perform the first patterning of the SADP process. The average of the ADI dimensions can be taken to determine the incoming ADI dimension of a representative mandrel, and the incoming ADI dimension is used for feed-forward control. For example, FIG. 4A shows the ADI dimension of the PR mandrel 403.

[0090] In the case of the SADP process, there is a desired incoming ADI dimension of the PR mandrel that minimizes the variability introduced when performing the steps of the SADP process. At 720, the method includes determining the difference between the incoming ADI dimension of the mandrel and the desired ADI dimension, where the difference is the variability. Any difference or variability in the incoming ADI dimension of the PR mandrel from the desired ADI dimension affects subsequent steps of the SADP process that are based on the process conditions where the incoming ADI dimension is the desired ADI dimension. Embodiments of the present disclosure can account for the variability of the incoming ADI dimension and reduce the impact of that variability on the SADP process (e.g., such that the line CD dimension of the features formed during the performance of the SADP process is similar to the desired dimension). For example, the variability can include an increase in the incoming ADI dimension from the desired ADI dimension, or the variability can include a decrease in the incoming ADI limit dimension from the desired ADI limit dimension. Accordingly, the change in the process conditions in the first patterning of the SADP process can be implemented by feedforward control to account for the variability of the incoming ADI dimension of the PR mandrel.

[0091] At 730, the method includes modifying the time for performing the etching process step based on the difference or variability in the incoming ADI dimension of the PR mandrel from the desired ADI dimension and the etching rate of the etching process step, where the etching process step can include a trim process step. For example, the etching rate can be based on a sensitivity coefficient related to the change in the ADI limit dimension and the change in time (e.g., per unit time and a given temperature). The modification of the time is performed to achieve the desired ADT dimension of the core feature based on the incoming ADI dimension. The core feature is formed when performing the first patterning process of the self-aligned double patterning (SADP) process.

[0092] For example, an incoming ADI dimension of 320 angstroms may be larger than a desired ADI limit dimension of 300 angstroms. FIG. 4B shows the implementation of a wet etching and trim process to form a core 1 feature 401A having an ADT limit dimension. Due to the variability of the incoming ADI limit dimension, subsequent process steps assuming no variability in the incoming ADI limit dimension (i.e., the desired ADI dimension) will generate an ADT limit dimension of the core feature that is larger than desired. For illustrative purposes, the ADT limit dimension of the core feature may be 20 angstroms larger than the desired ADT limit dimension. Considering the variability of the incoming ADI limit dimension (e.g., an increase of 20 angstroms), the time to perform the etching and / or trim process step can be increased from the normal time to achieve the desired ADT limit dimension for each of the core features (assuming the incoming PR mandrel is the desired ADI limit dimension). That is, extending the time to perform the etching and / or trim process step takes into account the variability of the incoming ADI limit dimension of the PR mandrel and allows for more lateral etching to be performed on the core feature to achieve the desired ADT limit dimension. In particular, the increased time for etching can etch 10 angstroms laterally from each side of a representative core feature. In that way, the ADT limit dimension of the core feature formed during the SADP process becomes the same as the desired ADT dimension of the core feature. Thus, the impact of process condition variability (i.e., an increase in the incoming ADI limit dimension from the desired ADI limit dimension) is minimized by feed-forward control by adjusting the process conditions of subsequent process steps (i.e., adjusting the time of the etching and / or trim process step).

[0093] Feedforward control can be implemented to account for changes in process conditions from specified process conditions for one or more subsequent process steps. In particular, at 740, the method includes receiving a change in a process step of a second patterning process of the SADP process, according to one embodiment of the present disclosure. For example, the second patterning process can include a dry etching process, and thus the corresponding process conditions for the dry etching process can be changed.

[0094] At 750, the method includes determining a modified ASD dimension for an oxide layer over a core feature, based on the change in the second patterning process. That is, the ASD dimension can have a desired dimension based on the original process conditions expected when performing the dry etching process during the second patterning process. FIG. 4C shows the implementation of a conformal deposition and selective etching process for forming a spacer 1 DEP 415 over a core 1 feature 401A, where the spacer 1 DEP 415 has an ASD limit dimension measured in a horizontal direction substantially parallel to the bottom surface 412 of the wafer 101. However, a change in the second patterning process may require a change in the ASD dimension for the oxide layer by feedforward control, and this change is associated with the modified ASD dimension.

[0095] As described above, the oxide layer as the spacer 1 DEP 415 conforming to the core 1 feature 401A can be formed by atomic layer deposition. Since the modified ASD dimension is known, at 760, the method includes determining the deposition rate of the ALD process and the number of deposition cycles to achieve the modified ASD dimension for the core feature (e.g., in the lateral direction) on which the oxide layer is to be deposited when performing the atomic layer deposition (ALD) process. For example, the deposition rate can be based on a sensitivity coefficient related to the change in the ASD dimension per deposition cycle (e.g., for a given temperature). Thus, changes to the process conditions in subsequent process steps (e.g., dry etching in the second patterning of the SADP process) are accounted for by feed-forward control by adjusting the process conditions of the previous process step (i.e., adjusting the number of deposition cycles to achieve the modified ASD dimension for the oxide layer on the corresponding core feature when performing atomic layer deposition in the first patterning of the SADP process).

[0096] FIG. 8A shows a workflow 800A for determining a sensitivity coefficient and performing feedback and / or feed-forward control when implementing a multi-patterning process, according to an embodiment of the present disclosure. The workflow 800A can be implemented in any of the multi-patterning processes introduced previously in FIGS. 4-7, using the sensitivity coefficient described above and also explained in FIGS. 8B-8D. is.

[0097] For illustrative purposes, the multi-patterning process shown in workflow 800A includes a first patterning process 804 and a second patterning process 806 such as the SADP process described above with reference to FIGS. 4A-4H. However, it is understood that any number of process steps of any multi-patterning process can be implemented for the purpose of implementing feedback and / or feedforward control. For example, as described above with reference to FIGS. 4A-4H, the first patterning process 804 includes etching and trimming (e.g., wet etching and / or trimming) and a deposition process, and the second patterning process 806 includes etching and / or trimming (e.g., dry etching and / or trimming) and a deposition process.

[0098] As described above, empirical tests are performed for the purpose of constructing a mathematical model that can be used for feedback and / or feedforward control. For example, feedback control can adjust the variability of the control parameters or process conditions of the multi-patterning process. In another example, the mathematical model can be used for feedforward control by adjusting the variation of the input variables for the process steps (e.g., the variation of the size of the incoming PR mandrel from the desired size, or the change to the subsequent process steps in the second patterning) while performing the multi-patterning process such that the output (e.g., the size of the final feature on the wafer) achieves the target. The mathematical model includes one or more sensitivity coefficients that provide the sensitivity of the feature size (e.g., the size of the final feature, trim, deposition) to temperature and time. These sensitivity coefficients can be determined through empirical tests such as the measurement of process variations or disturbances.

[0099] As previously described in connection with FIG. 5, for the purpose of determining the sensitivity coefficient, tests can be performed on a plurality of test wafers 802 (e.g., blanket wafers or feature / topography wafers) under two process conditions. For purposes of illustration, in the first patterning of process 804, the first process condition includes a first steady state (SS) temperature and the second process condition includes a second steady state temperature. Other process conditions have been previously described and are further explained with respect to FIGS. 8B-8D.

[0100] Accordingly, etching and trimming and deposition processes using the process conditions are performed on a plurality of test wafers 802 for the first patterning process 804 and / or the second patterning process 806. In particular, the etching and trimming and deposition processes in the first patterning of process 804 can be performed on a wafer (e.g., a feature / topography wafer) so as to include the first patterning 804 of the SADP process, and features having ADI critical dimensions and features having ASD critical dimensions, as well as other features having other critical dimensions, can be determined (e.g., measured by a metrology tool). Additionally, the difference or delta data of the ADI and ASD critical dimensions can be collected between the two process conditions. Other measurements of the features can be made at any point during the first patterning process 804 and / or the second patterning process 806, and the dimensions of the final features formed at the end of the second patterning process 806 can also be measured. Also, the temperature readings can include a set of temperature versus x-y coordinate data on the wafer corresponding to locations on the wafer.

[0101] In one embodiment, transient temperature conditions are considered when determining the sensitivity coefficient 810 in one embodiment. In particular, typically, deposition is performed after reaching a steady-state temperature, such as when the wafer reaches a temperature corresponding to the heater zone of the ESC, while etching and trim processes are performed under transient temperature conditions, such as while the wafer has reached the steady-state temperature. The transient temperature conditions define the actual change in temperature during etching and / or trim processes before reaching the steady-state temperature. Thus, when determining the difference in measured values of features within the wafer while performing process steps under two process conditions, the transient temperature conditions can be considered.

[0102] Based on the collected data, as described above, the trim and deposition sensitivity coefficients 810 can be determined. For example, the difference between the critical dimension of the feature and the measured temperature conditions for two process conditions can be used to generate the etching and / or trim as well as the deposition sensitivity coefficient 810. Also, blanket deposition profile data and / or measurements may be used to determine the deposition sensitivity coefficient 810. For example, a blanket deposition process can be performed on the wafer, and the blanket deposition profile data and / or measurements are determined (e.g., from a metrology tool) to determine the sensitivity coefficient (e.g., deposition rate, etc.). In addition, difference data of deposition thickness between two process conditions can be collected during the first patterning of process 804 to determine the deposition sensitivity coefficient. The sensitivity coefficient 810 is further described in relation to FIGS. 8B-8D.

[0103] The sensitivity coefficient 810 can be used for feedback and / or feedforward control based on one or more measured values of the control parameters obtained during and / or at the end of the multipatterning process. That is, feedback control 812 can be used to adjust the process conditions for processing subsequent wafers based on the measurements made on the current wafer, as described above with respect to FIG. 6A. Also, feedforward control 814 can be performed on the current wafer to adjust the variability of the critical dimensions of the features measured during the implementation of the first patterning process so that the variability does not affect the subsequent process, as described above with respect to FIG. 7. Further, feedforward control 816 can be performed on the current wafer and can adjust the changes in the process parameters and / or process conditions for the subsequent process (e.g., the changes to the process in the second patterning process 806), as described above with respect to FIG. 7.

[0104] For example, in the case of feedback control 812, after performing a multi-patterning process (e.g., SADP process), it may be desirable to have a flat profile across the entire wafer. The critical dimension of the final feature on the process wafer 808 can be determined (e.g., from a metrology tool), and the measurement can include x-y coordinate data on the wafer. If the measurement indicates that the critical dimension is different from the desired setting, the adjustment to the process conditions can be determined based on the corresponding sensitivity coefficient and the difference between the measured dimension and the desired dimension. For example, the measurement can indicate a dome-shaped profile for the process wafer 808, and the dimension of the final feature (e.g., line CD) is larger in the inner radial zone than in the outer radial zone of the final feature. The feedback control can be implemented by providing an adjustment to the heater zone (e.g., a new temperature for the heater zone) to account for the average difference between the measured dimension and the desired dimension (e.g., the dimension of the final feature after performing multi-patterning) using the corresponding sensitivity coefficient. In that way, after adjusting the process conditions for subsequent process wafers 808, there is a flat profile of the dimensions of the final feature across both the inner and outer radial zones.

[0105] Implement feed - forward control 814 to adjust the variability of the critical dimension (e.g., ADI) of a feature (e.g., incoming PR mandrel) measured during the implementation of a first patterning process so that the variability does not affect a subsequent process (e.g., a second patterning process) and the features formed thereafter match their desired dimensions. As described above, when the measured incoming ADI critical dimension deviates from the desired critical dimension, an adjustment can be made to the process of the first patterning process so that the output from the first patterning process matches the expected dimension. For example, if the incoming ADI critical dimension is too large, an increase in the etching and / or trim process can be implemented to neutralize the impact of the variability on subsequent processes. In that way, the dimensions of the intermediate and / or final features (e.g., line CD) of the current wafer formed when implementing a multi - patterning process using feed - forward control can match the desired dimensions.

[0106] In addition, feed - forward control 816 can be implemented to adjust changes in process parameters and / or process conditions (e.g., changes to the process in the second patterning process 806) made to a subsequent process when processing the current wafer. That is, feed - forward control can be implemented to adjust changes made to a subsequent process step (e.g., a second patterning process 806 such as dry etching) that requires a change to a previous process step (e.g., the first patterning process 804). For example, an adjustment to a process step in one or more steps in the first patterning process 804 can include changes to the etching and / or trim process to achieve a newly determined target ASD dimension (e.g., temperature, time, etc.) and / or changes to a deposition process (e.g., blanket thickness) to achieve a newly determined target ASD dimension, etc.

[0107] FIG. 8B is a diagram 800B showing the temperature profile evolution of an etching and / or trimming process for two different steady-state temperature conditions to determine the trim sensitivity to temperature when implementing feedback and / or feedforward control for a multipatterning process according to an embodiment of the present disclosure. The y-axis represents temperature and the x-axis represents the elapsed time for implementing the etching and / or trimming process. Two different process conditions are presented in FIG. 800B, including a first temperature (temperature 1) and a second temperature (temperature 2). Temperature profile 830 shows the evolution of the temperature on the wafer when implementing the first patterning (etching and / or trimming process) of a multipatterning process (e.g., SADP process) using the first process condition (temperature 1). Temperature profile 835 shows the evolution of the temperature on the wafer when implementing the first patterning (etching and / or trimming process) of a multipatterning process (e.g., SADP process) using the second process condition (temperature 2). The area under each temperature profile up to time t1 corresponds to the total heat input applied to the corresponding wafer, and the total heat applied also corresponds to the amount of trimming performed on the wafer. As shown, time t1 occurs during the etching and / or trimming process, which typically occurs within the first 30 to 60 seconds after placing the wafer on the ESC. Thus, up to time t1, the difference or delta heat input between the two process conditions is indicated by area 837. Additionally, as shown for each of temperature profiles 830 and 835, the amount of trimming corresponding to the wafers undergoing the etching and / or trimming process using two different process conditions can be measured. In another embodiment, as described above, a measured value of line CD determined from the final feature formed at the end of the multipatterning process is obtained. A trim sensitivity coefficient can be determined that relates the sensitivity of the etching and / or trimming process to temperature and is defined by Equation 2 below. In some cases, Equation 2 is closely related to Equation 1 presented previously.

Equation

[0108] FIG. 8C is FIG. 800C showing the temperature profile evolution of an etching and / or trim process for steady-state temperature conditions operating under two different time constraints (e.g., process conditions) for determining the trim sensitivity to time when implementing feedback and / or feedforward control for a multipatterning process according to an embodiment of the present disclosure. The y-axis represents temperature and the x-axis represents the elapsed time for implementing the etching and / or trim process. Two different process conditions including a first time (t1) and a second time (t2) are presented in FIG. 800B. Temperature profile 830 shows the evolution of the temperature on the wafer when implementing a first patterning (e.g., etching and / or trim process) of a multipatterning process (e.g., SADP process) using two different process conditions (e.g., t1 and t2). The area under the temperature profile 830 up to a specific time (e.g., time t1 or time t2) corresponds to the total heat input applied to the corresponding wafer, and the total heat applied also corresponds to the amount of trimming performed on the wafer. Thus, the difference or delta heat input between the two process conditions is indicated by area 839 between the two times t1 and t2. Additionally, the amount of trimming corresponding to the wafers undergoing the etching and / or trim process up to time t1 and up to time t2 (two different process conditions) can be measured. In another embodiment, as described above, a measured value of line CD determined from the final feature formed at the end of the multipatterning process is obtained. A trim sensitivity coefficient can be determined that relates the sensitivity of the etching and / or trim process to time and is defined by Equation 3 below.

Equation

[0109] FIG. 8D is a diagram 800D showing the determination of deposition rates of a deposition process implemented for two different steady-state temperature conditions according to an embodiment of the present disclosure, where the deposition rate is based on deposition sensitivity to temperature and can be used when implementing feedback and / or feedforward control for a multipatterning process. The y-axis represents temperature and the x-axis represents the elapsed time for performing an etching and / or trim process. Two different process conditions are presented in FIG. 800D, including a first temperature (temperature 1) and a second temperature (temperature 2). Temperature profile 840 shows the development of temperature on the wafer when performing a first patterning (etching and / or trim process) of a multipatterning process (e.g., SADP process) using the first process condition (temperature 1). Temperature profile 845 shows the development of temperature on the wafer when performing a first patterning (etching and / or trim process) of a multipatterning process (e.g., SADP process) using the second process condition (temperature 2). The deposition process typically occurs after the wafer reaches a steady-state temperature, as indicated by boundary line 847. The etching and trim processes take up to 30 seconds, but the deposition process can be carried out over a longer period (e.g., 200 seconds) and mostly occurs when the wafer is in a steady state with respect to temperature. The area under each temperature profile up to time t1 corresponds to the total heat input applied to the corresponding wafer, and the total heat applied also roughly corresponds to the amount of deposition formed on the wafer. As shown, the deposition process is carried out until time t1, which occurs after boundary line 847. The difference or delta heat input between the two process conditions is indicated by area 849. Additionally, as shown for each of temperature profiles 840 and 845, the thickness of the deposition layer corresponding to the wafer undergoing an etching and / or trim process using two different process conditions can be measured. In another embodiment, as described above, a measurement of line CD determined from the final feature formed at the end of the multipatterning process is obtained.The deposition sensitivity coefficient (or deposition rate) that correlates the sensitivity of the deposition process to temperature can be determined and is defined by Equation 4 below.

Equation

[0110] In addition, the deposition thickness can be determined by a deposition sensitivity coefficient (or deposition rate) that correlates the sensitivity of the deposition process to the number of atomic layer deposition (ALD) cycles being performed. That is, the deposition thickness is closely related to the number of ALD cycles performed (e.g., at a given temperature). In particular, a deposition sensitivity coefficient (e.g., deposition rate) that correlates the sensitivity of the deposition process to the number of ALD cycles performed can be determined and is defined by Equation 5 below.

Equation

[0111] FIG. 9 shows a control module 900 for controlling the system described above. In one embodiment, the control module 110 of FIG. 1A may include some of the exemplary components of the control module 900. For example, the control module 900 can include a processor, a memory, and one or more interfaces. The control module 900 can be used to control devices within the system based at least in part on sensed values. By way of example only, the control module 900 can control one or more of valve 902, filter heater 904, pump 906, Heater zone 930 , and other devices 908 based on sensed values and other control parameters. The control module 900 receives sensed values from, by way of example only, pressure gauge 910, flow meter 912, and / or other sensors 916. The control module 900 can also be used to control the delivery of precursors and the process conditions during film deposition. The control module 900 typically includes one or more memory devices and one or more processors.

[0112] The control module 900 can control the operation of the precursor delivery system and the deposition apparatus. The control module 900 executes a computer program including a series of instructions for controlling process timing, feed system temperature, pressure difference across the filter, valve position, gas mixing, chamber pressure, chamber temperature, substrate temperature, RF power level, substrate chuck or pedestal position, and other parameters of a particular process. The control module 900 can also monitor the pressure difference and automatically switch the delivery of the vapor precursor from one or more paths to one or more other paths. In some embodiments, other computer programs stored in a memory device associated with the control module 900 can be used.

[0113] Typically, there is a user interface associated with the control module 900. The user interface can include a display 918 (e.g., a display screen and / or a graphical software display of the apparatus and / or process conditions), and a user input device 920 such as a pointing device, keyboard, touch screen, microphone, etc.

[0114] The computer program for controlling the delivery, deposition, and other processes of the precursor in the process sequence can be written in any conventional computer-readable programming language (e.g., assembly language, C, C++, Pascal, Fortran, etc.). The compiled object code or script is executed by the processor to perform the tasks identified by the program.

[0115] The control module parameters are related to process conditions such as, for example, filter pressure difference, process gas composition and flow rate, temperature, pressure, plasma conditions such as RF power level and low frequency RF frequency, cooling gas pressure, and chamber wall temperature.

[0116] System software can be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control the operation of the chamber components necessary to perform the deposition process of the present invention. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.

[0117] The substrate positioning program can include program code for loading a substrate onto a pedestal or chuck and controlling chamber components used to control the spacing between the substrate and other parts of the chamber such as gas inlets and / or targets. The process gas control program can include code for controlling gas composition and flow rate to stabilize the pressure within the chamber, and optionally code for flowing gas into the chamber prior to deposition. The filter monitoring program includes code for comparing the measured difference to a predetermined value and / or code for switching paths. The pressure control program can include code for controlling the pressure of the chamber, for example, by adjusting a throttle valve in the chamber's exhaust system. The heater control program can include code for controlling the current to a heating unit for heating components of the precursor delivery system, the substrate, and / or other parts of the system. Alternatively, the heater control program can control the delivery of a heat transfer gas (such as helium) to the substrate chuck.

[0118] Examples of sensors that can be monitored during deposition include, but are not limited to, a mass flow control module, pressure sensors such as pressure manometer 910, and thermocouples located in the delivery system, pedestal, or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain desired process conditions. The foregoing has described the implementation of embodiments of the present disclosure in single or multi-chamber semiconductor processing tools.

[0119] In some embodiments, the controller is part of a system, and such a system may be part of the examples described above. Such a system can comprise semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or particular processing components (such as substrate pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after processing of a semiconductor wafer or substrate. Such electronics may be referred to as a “controller” and may control various components or subcomponents of one or more systems. The controller may be programmed to control any of the processes disclosed herein, depending on the processing requirements and / or the type of system. Such processes include delivery of processing gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, position and motion setting, loading and unloading of substrates to and from tools, and loading and unloading of substrates to and from other transfer tools and / or load locks connected or interfaced with a particular system.

[0120] In a broad sense, a controller may be defined as an electronic device having various integrated circuits, logics, memories, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., a microcontroller that executes program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), and may define operation parameters for executing a specific process on, or for, a semiconductor substrate or for a system. The operation parameters may, in some embodiments, be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0121] In some embodiments, the controller may be part of a computer that is integrated or coupled with the system or otherwise network-connected to the system, or may be coupled to such a computer, or a combination thereof. For example, the controller may be within the "cloud" or may be all or part of a fab host computer system. This enables remote access to wafer processing. The computer may enable remote access to the system, monitor the current progress of fabrication operations, consider the history of past fabrication operations, consider trends or performance criteria from multiple fabrication operations, change the parameters of the current process, set the processing steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may be able to provide a process recipe to the system through a network. Such a network may include a local network or the Internet.

[0122] The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data identifies parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the controller is configured to interact with or control. Thus, as described above, the controller may be distributed, for example, by comprising one or more individual controllers that are networked together and cooperate towards a common purpose (such as the processes and controls described herein). Examples of distributed controllers for such purposes include one or more integrated circuits on a chamber, which are remotely located (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits combined to control processes in the chamber.

[0123] Exemplary systems can include, but are not limited to, a plasma etching chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0124] As described above, depending on one or more process steps performed by a tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, a main computer, another controller, or a tool used for material transport to load and unload a wafer container to and from tool locations and / or load ports within a semiconductor manufacturing factory.

[0125] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. The individual elements or features of a particular embodiment are generally not limited to that particular embodiment and, where applicable, are interchangeable and can be used in the selected embodiment, even if not specifically illustrated or described. Also, it can be modified in many ways. Such modifications should not be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

[0126] The foregoing embodiments have been described in some detail for purposes of clarity of understanding, but it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the embodiments are to be regarded as illustrative rather than restrictive, and the embodiments should not be limited to the details described herein, but may be modified within the scope and equivalents of the claims. The present invention can also be realized, for example, in the following aspects. Application Example 1: A method comprising: performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features, the first process step in the series of process steps being performed under a first process condition, the series of process steps including at least one process step; performing the series of process steps on a second plurality of test wafers, each of the second plurality of test wafers forming the plurality of features, the first process step being performed under a second process condition; measuring a first dimension of the plurality of features located on the first plurality of test wafers; measuring a second dimension of the plurality of features located on the second plurality of test wafers; and determining a sensitivity coefficient for the plurality of features related to a change in dimension and a change in process condition. A method comprising the above. Application Example 2: The method according to claim 1, wherein said determining determines the sensitivity coefficient based on a difference between the first process condition and the second process condition and a difference between the first dimension and the second dimension. A method comprising the above. Application Example 3: The method according to claim 1, wherein the first process condition is a first temperature of a pedestal configured to support the test wafer, and the first process step is an etching process step, the second process condition is a second temperature of the pedestal. A method. Application Example 4: The method according to claim 3, wherein the sensitivity coefficient is a trim sensitivity coefficient related to a change in dimension of the plurality of features and a change in temperature of a pedestal configured to support the test wafer when performing an etching process step as the first process step. Application Example 5: The method according to claim 1, wherein The first process condition is a first period for performing an etching process step as the first process step, The second process condition is a second period for performing a trimming process step, Method. Application Example 6: The method according to claim 5, wherein the sensitivity coefficient is a trimming sensitivity coefficient related to a change in dimensions of the plurality of features and a change in time when performing an etching process step as the first process step. Application Example 7: The method according to claim 1, wherein the first process condition is a first temperature of a pedestal configured for wafer support, and the first process step is a deposition step, and the second process condition is a second temperature of the pedestal. Method. Application Example 8: The method according to claim 7, wherein the sensitivity coefficient is a deposition sensitivity coefficient related to a change in dimensions of the plurality of features and a change in temperature of a pedestal configured to support a test wafer when performing a deposition process step as the first process step. Application Example 9: The method according to claim 1, wherein the first process condition is a first number of cycles of a deposition step that is the first process step, and the second process condition is a second number of cycles of the deposition step. Method. Application Example 10: The method according to claim 9, wherein the sensitivity coefficient is a deposition sensitivity coefficient related to a change in dimensions of the plurality of features and a change in the number of atomic layer deposition cycles when performing a deposition process step as the first process step. Application Example 11: The method according to claim 1, wherein measuring the first dimension includes measuring each of the plurality of features on the first plurality of test wafers and determining a plurality of dimensions, and determining an average of the plurality of dimensions that is the first dimension. Method. Application Example 12: The method according to claim 11, wherein each of the plurality of features is measured at the end of the series of process steps, the series of process steps is a self-aligned double patterning (SADP) process, and the first process step is included in the first patterning of the SADP process. Method. Application Example 13: The method according to claim 11, Each of the plurality of features is measured at the end of the first process step, method. Application Example 14: The method according to claim 1, wherein measuring the second dimension comprises measuring each of the plurality of features on the plurality of second test wafers to determine a plurality of dimensions, and determining an average of the plurality of dimensions that is the second dimension Method. Application Example 15: The method according to claim 14, wherein each of the plurality of features is measured at the end of the series of process steps, the series of process steps is a self-aligned double patterning (SADP) process, the first process step is included in the first patterning of the SADP process, Method. Application Example 16: The method according to claim 14, wherein each of the plurality of features is measured at the end of the first process step, method. Application Example 17: The method according to claim 1, wherein each of the plurality of first test wafers and each of the plurality of second test wafers is a blanket wafer, method. Application Example 18: The method according to claim 1, wherein each of the plurality of first test wafers and each of the plurality of second test wafers is a topography wafer, method. Application Example 19: A method, comprising performing a series of process steps on a wafer to obtain a plurality of features, the process steps being performed under process conditions, measuring the dimensions of the plurality of features after performing the series of process steps, determining the difference between the measured dimensions and the target dimensions for the plurality of features, and modifying the process conditions for the process steps based on the difference and the sensitivity coefficient for the plurality of features related to changes in dimensions and changes in process conditions Method. Application Example 20: The method according to claim 19, further comprising performing the series of process steps using the modified process conditions for the process steps on another wafer Method. Application Example 21: The method according to claim 19, wherein modifying the process conditions comprises modifying the temperature of a pedestal configured for wafer support, the temperature being used when performing the process step that is an etching process step including, The sensitivity coefficient is a trimming sensitivity coefficient related to a change in dimensions of the plurality of features and a change in temperature of the pedestal when the etching process step is performed. Method. Application Example 22: The method according to claim 19, wherein modifying the process conditions includes modifying the time for performing the process step which is an etching process step, and the sensitivity coefficient is a trimming sensitivity coefficient related to a change in dimensions of the plurality of features and a change in time when the etching process step is performed. Method. Application Example 23: The method according to claim 19, wherein modifying the process conditions includes modifying the temperature of a pedestal configured for wafer support, the temperature being used when performing the process step which is a deposition step, and the sensitivity coefficient is a deposition sensitivity coefficient related to a change in dimensions of the plurality of features and a change in temperature of the pedestal when the deposition process step is performed. Method. Application Example 24: The method according to claim 19, wherein modifying the process conditions includes modifying the number of cycles of a deposition step which is the process step, and the sensitivity coefficient is a deposition sensitivity coefficient related to a change in dimensions of the plurality of features and a change in the number of atomic layer deposition cycles when the deposition step is performed. Method. Application Example 25: The method according to claim 19, wherein measuring the dimensions includes measuring each of the plurality of features to determine a plurality of dimensions, and determining an average of the plurality of dimensions, the average being the dimension. Method. Application Example 26: The method according to claim 25, wherein each of the plurality of features is measured at the end of the series of process steps, the series of process steps is a self-aligned double patterning (SADP) process, and the process step is included in a first patterning of the SADP process. Method. Application Example 27: A method comprising measuring an incoming ADI dimension of a mandrel on a wafer, and determining a difference between the incoming ADI dimension of the mandrel and a desired ADI dimension. Performing the etching process step based on the difference in the etching process steps and the etching rate, and modifying the time to achieve the desired ADT dimension of the core feature based on the incoming ADI dimension, wherein the core feature is formed when performing the first patterning process of a self-aligned double patterning (SADP) process, and Receiving a change in the second patterning process of the SADP process, and Determining a modified ASD dimension for the oxide layer on the core feature based on the change in the second patterning process, and When performing an atomic layer deposition (ALD) process, determining the number of deposition cycles to achieve the modified ASD dimension based on the deposition rate of the ALD process and the desired ADT dimension of the core feature A method comprising. Application Example 28: The method according to claim 27, wherein Performing the number of deposition cycles in the ALD process performed within the first patterning process A method further comprising. Application Example 29: The method according to claim 27, wherein The change in the second patterning process is a change in a dry etching process. Application Example 30: The method according to claim 27, wherein Said determining the difference Comprises determining that the incoming ADI dimension is greater than the desired ADI dimension A method comprising. Application Example 31: The method according to claim 27, wherein Said determining the difference Comprises determining that the incoming ADI dimension is smaller than the desired ADI dimension A method comprising. Application Example 32: The method according to claim 27, wherein Determining the etching rate based on a sensitivity coefficient related to a change in the ADI dimension and a change in time, and determining the etching rate A method further comprising. Application Example 33: The method according to claim 27, wherein Determining the deposition rate of the ALD process based on a sensitivity coefficient related to a change in the ASD dimension per deposition cycle A method further comprising.

Claims

1. A method comprising: Performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features, wherein a first process step in the series of process steps is performed under a first process condition, and the series of process steps includes at least one process step; Performing the series of process steps on a second plurality of test wafers, each of the second plurality of test wafers forming the plurality of features, wherein the first process step is performed under a second process condition; Measuring a first dimension of the plurality of features located on the first plurality of test wafers; Measuring a second dimension of the plurality of features located on the second plurality of test wafers; Determining a sensitivity coefficient for the plurality of features related to a change in dimension and a change in process condition; and comprising: The first process condition is a first temperature of a pedestal configured to support a wafer, and the first process step is a deposition step; The second process condition is a second temperature of the pedestal. A method.

2. The method according to claim 1, wherein said determining determines the sensitivity coefficient based on a difference between the first process condition and the second process condition and a difference between the first dimension and the second dimension. A method comprising:

3. The method according to claim 1, wherein the first process condition is a first temperature of a pedestal configured to support the test wafer, and the first process step is an etching process step; The second process condition is the second temperature of the pedestal. Method.

4. The method according to claim 3, wherein the sensitivity coefficient is a trim sensitivity coefficient related to a change in dimensions of the plurality of features and a change in temperature of a pedestal configured to support a test wafer when performing an etching process step as the first process step.

5. The method according to claim 1, wherein the first process condition is a first period for performing an etching process step as the first process step, and the second process condition is a second period for performing a trim process step. Method.

6. The method according to claim 5, wherein the sensitivity coefficient is a trim sensitivity coefficient related to a change in dimensions of the plurality of features and a change in time when performing an etching process step as the first process step.

7. The method according to claim 1, wherein the sensitivity coefficient is a deposition sensitivity coefficient related to a change in dimensions of the plurality of features and a change in temperature of a pedestal configured to support a test wafer when performing a deposition process step as the first process step.

8. A method comprising: performing a series of process steps on a first plurality of test wafers, each of the first plurality of test wafers forming a plurality of features, the first process step in the series of process steps being performed under a first process condition, the series of process steps including at least one process step. Performing the series of process steps on the second plurality of test wafers, each of the second plurality of test wafers forming the plurality of features, and the first process step being performed under a second process condition; Measuring a first dimension of the plurality of features located on the first plurality of test wafers; Measuring a second dimension of the plurality of features located on the second plurality of test wafers; Determining a sensitivity coefficient for the plurality of features related to a change in dimension and a change in process condition; comprising; The first process condition is a first number of cycles of a deposition step that is the first process step; The second process condition is a second number of cycles of the deposition step; A method.

9. The method according to claim 8, wherein The sensitivity coefficient is a deposition sensitivity coefficient related to a change in the dimension of the plurality of features and a change in the number of atomic layer deposition cycles when performing a deposition process step as the first process step. A method.

10. The method according to claim 1, wherein Said measuring the first dimension comprises Measuring each of the plurality of features on the first plurality of test wafers to determine a plurality of dimensions; Determining an average of the plurality of dimensions that is the first dimension; comprising. A method.

11. The method according to claim 10, wherein Each of the plurality of features is measured at the end of the series of process steps; The series of process steps is a self-aligned double patterning (SADP) process; The first process step is included in the first patterning of the SADP process, method. **Claim 12** The method according to claim 10, wherein each of the plurality of features is measured at the end of the first process step. **Claim 13** The method according to claim 1, wherein measuring the second dimension comprises: measuring each of the plurality of features on the second plurality of test wafers to determine a plurality of dimensions; and determining an average of the plurality of dimensions that is the second dimension. **Claim 14** The method according to claim 13, wherein each of the plurality of features is measured at the end of the series of process steps, the series of process steps is a self-aligned double patterning (SADP) process, and the first process step is included in the first patterning of the SADP process. **Claim 15** The method according to claim 13, wherein each of the plurality of features is measured at the end of the first process step. **Claim 16** The method according to claim 1, wherein each of the first plurality of test wafers and each of the second plurality of test wafers is a blanket wafer. **Claim 17** The method according to claim 1, wherein each of the first plurality of test wafers and each of the second plurality of test wafers is a topography wafer. **Claim 18** A method, Performing a series of process steps on a wafer to obtain a plurality of features, wherein the process steps are to be performed under process conditions, and measuring the dimensions of the plurality of features after performing the series of process steps, determining the difference between the measured dimensions and the target dimensions for the plurality of features, modifying the process conditions for the process steps based on the difference and the sensitivity coefficient for the plurality of features related to the change in dimensions and the change in process conditions, including, wherein modifying the process conditions is modifying the temperature of a pedestal configured for wafer support, the temperature being used when performing the process step that is a deposition step, including, wherein the sensitivity coefficient is a deposition sensitivity coefficient related to the change in the dimensions of the plurality of features and the change in the temperature of the pedestal when performing the process step, Method.

19. The method according to claim 18, wherein performing the series of process steps using the modified process conditions for the process steps for another wafer. The method further including.

20. The method according to claim 18, wherein modifying the process conditions is modifying the temperature of a pedestal configured for wafer support, the temperature being used when performing the process step that is an etching process step, including, wherein the sensitivity coefficient is a trim sensitivity coefficient related to the change in the dimensions of the plurality of features and the change in the temperature of the pedestal when performing the etching process step, Method.

21. The method according to claim 18, wherein modifying the process conditions comprises modifying the time for performing the process step which is an etching process step and the sensitivity coefficient is a trimming sensitivity coefficient related to the change in the dimensions of the plurality of features and the change in time when performing the etching process step. Method.

22. A method comprising: performing a series of process steps on a wafer to obtain a plurality of features, the process steps being performed under process conditions; measuring the dimensions of the plurality of features after performing the series of process steps; determining the difference between the measured dimensions and the target dimensions for the plurality of features; modifying the process conditions for the process steps based on the difference and the sensitivity coefficient for the plurality of features related to the change in dimensions and the change in process conditions; and modifying the process conditions comprises modifying the number of cycles of a deposition step which is the process step; and the sensitivity coefficient is a deposition sensitivity coefficient related to the change in the dimensions of the plurality of features and the change in the number of atomic layer deposition cycles when performing the deposition step. Method.

23. The method according to claim 18, wherein measuring the dimensions comprises measuring each of the plurality of features to determine a plurality of dimensions; determining the average of the plurality of dimensions, the average being the dimension. A method comprising

24. The method according to claim 23, each of the plurality of features is measured at the end of the series of process steps, the series of process steps is a self-aligned double patterning (SADP) process, the process step is included in the first patterning of the SADP process, A method.

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