Memory device

Abstract

To provide a semiconductor device including a transistor using a highly reliable oxide semiconductor by solving the problem in which transistors using oxide semiconductors are sometimes less reliable than transistors using amorphous silicon.SOLUTION: Impurities such as hydrogen, nitrogen, and carbon contained in an oxide semiconductor film become a factor that deteriorates the semiconductor characteristics of the oxide semiconductor film. For example, hydrogen and nitrogen contained in the oxide semiconductor film cause a negative shift in a threshold voltage of a transistor using the oxide semiconductor film. Furthermore, nitrogen, carbon, and rare gas contained in the oxide semiconductor film inhibit the formation of a crystalline region in the oxide semiconductor film. Therefore, by reducing the impurity concentration of the oxide semiconductor film, a highly reliable transistor is manufactured.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing an oxide semiconductor film and a method for manufacturing a semiconductor device.

[0002] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor thin film materials that can be used in transistors are Silicon-based semiconductor materials are widely known as semiconductor materials, but oxide semiconductors are also attracting attention as other materials. It has been done.

[0004] For example, a semiconductor with an electron carrier concentration of 10 18 / cm 3 is less than A transistor using an oxide semiconductor containing In, Ga, and Zn is disclosed. The sputtering method is considered to be the most suitable method for forming a compound semiconductor film (see Patent Document 1). .). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] Transistors using oxide semiconductors have the following characteristics compared to transistors using amorphous silicon: Therefore, a transistor using an oxide semiconductor with high reliability was developed. The present invention provides a semiconductor device having a

[0007] A method for forming an oxide semiconductor film for this purpose will also be described. [Means for solving the problem]

[0008] Impurities such as hydrogen, nitrogen, and carbon contained in the oxide semiconductor film are This can cause the characteristics to deteriorate.

[0009] For example, hydrogen and nitrogen contained in the oxide semiconductor film generate carriers in the oxide semiconductor film. Therefore, the presence of hydrogen and nitrogen makes it possible to form a transistor using an oxide semiconductor film. This causes a negative shift in the threshold voltage of the transistor. This will lead to a decline in.

[0010] In addition, nitrogen, carbon, and a rare gas contained in the oxide semiconductor film form a crystalline region in the oxide semiconductor film. For example, nitrogen and carbon dioxide molecules can inhibit the formation of chlorophyll. Since the molecular diameter is large, the formation of a crystalline region is particularly inhibited in an oxide semiconductor film. In addition, when a carbon atom is substituted for a metal atom in the oxide semiconductor film, a crystal is formed at the substituted site. It cuts the structure.

[0011] Therefore, obtaining an oxide semiconductor film with few impurities is important for achieving a highly reliable transistor. It is important to obtain

[0012] Specifically, the hydrogen concentration in the oxide semiconductor film was measured by secondary ion mass spectrometry (SIMS). Measurement by secondary ion mass spectrometry shows that it is less than 5×10 1 9 atoms / cm 3 and preferably less than 5×10 18 atoms / cm 3 and more preferably less than 1×10 and even more preferably less than 5×10 18 atoms / cm 3 and even more preferably less than 5×10 17 atoms / cm 3 shall be as follows.

[0013] Also, the nitrogen concentration in the oxide semiconductor film is less than 5×10 19 atoms / c m 3 and preferably less than 5×10 18 atoms / cm 3 and more preferably less than 1×10 1 8 atoms / cm 3 and even more preferably less than 5×10 17 atoms / cm 3 shall be as follows.

[0014] Also, the carbon concentration in the oxide semiconductor film is less than 5×10 19 atoms / c m 3 and preferably less than 5×10 18 atoms / cm 3 and more preferably less than 1×10 1 8 atoms / cm 3 and even more preferably less than 5×10 17 atoms / cm 3 shall be as follows.

[0015] A transistor using the oxide semiconductor film contains hydrogen (including water, etc.) in the oxide semiconductor film. ​​When electrons are generated due to the hydrogen (including rare hydrogen) and nitrogen, the gate voltage does not need to be applied and the drain current still flows (also called normally-on). Note that the drain current refers to the current between the source and drain of the transistor. Also, the gate voltage refers to the potential difference between the gate potential and the source potential when the source potential is used as a reference. Therefore, the threshold voltage shifts in the negative direction. Transistors using an oxide semiconductor film often show an n-type, and the threshold voltage shifts in the negative direction to become a normally-on characteristic.

[0016] In addition, after manufacturing a transistor using an oxide semiconductor film, the threshold voltage of the transistor may vary due to the incorporation of hydrogen or nitrogen into the oxide semiconductor film. The variation in the threshold voltage significantly impairs the reliability of the transistor. Therefore, in order to obtain a highly reliable transistor, it is necessary to reduce the hydrogen and nitrogen contained in the oxide semiconductor film and the film in contact with the oxide semiconductor film.

[0017] Similarly, it is known that electrons are generated due to oxygen vacancies in the oxide semiconductor film. In order to prevent oxygen vacancies from occurring in the oxide semiconductor film, the oxide semiconductor film preferably has interstitial oxygen.

[0018] The interstitial oxygen can compensate for the oxygen vacancies generated in the oxide semiconductor film.

[0019] In a transistor using an oxide semiconductor film, when the oxide semiconductor film is single crystal, there is no interstitial oxygen for compensating oxygen vacancies, so oxygen vacancies are caused in the oxide semiconductor film due to this, and can compensate for it.

[0020] In a transistor using an oxide semiconductor film, when the oxide semiconductor film is single crystal, there is no interstitial oxygen for compensating oxygen vacancies, so oxygen vacancies are caused in the oxide semiconductor film due to the oxygen vacancies and there is no interstitial oxygen for compensating the oxygen vacancies, so the oxygen vacancies are caused in the oxide semiconductor film due to the oxygen vacancies A carrier is generated. Therefore, the threshold voltage of the transistor may shift in the negative direction. For this reason, the oxide semiconductor film is preferably non-single crystal. Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

[0021] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

[0022] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure having a crystal region and an amorphous region in an amorphous phase. The crystal region is often sized to fit within a cube with a side length of less than 100 nm. Also, in an observation image by a transmission electron microscope (TEM: Transmission Electron Microscope), the boundary between the amorphous region and the crystal region contained in the CAAC-OS film is not clear. Also, grain boundaries (also called grain boundaries) cannot be confirmed in the CAAC-OS film by TEM. Therefore, the decrease in electron mobility due to grain boundaries is suppressed in the CAAC-OS film. The crystal regions contained in the CAAC-OS film are aligned such that the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal regions. In this specification, when simply described as perpendicular Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film. The crystal regions contained in the CAAC-OS film are aligned such that the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal regions. In this specification, when simply described as perpendicular The crystal regions contained in the CAAC-OS film are aligned such that the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal regions. In this specification, when simply described as perpendicular

[0023] The crystal regions contained in the CAAC-OS film are aligned such that the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal regions. In this specification, when simply described as perpendicular The crystal regions contained in the CAAC-OS film are aligned such that the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal regions. In this specification, when simply described as perpendicular The crystal regions contained in the CAAC-OS film are aligned such that the c-axis is parallel to the normal vector of the surface to be formed of the CAAC-OS film or the normal vector of the surface, and when viewed from a direction perpendicular to the ab-plane, they have a trigonal or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal regions. In this specification, when simply described as perpendicular , the range of 85° or more and 95° or less shall also be included. In addition, when simply described as parallel, , the range of -5° or more and 5° or less shall also be included.

[0024] Note that in the CAAC-OS film, the distribution of the crystal regions does not have to be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystal regions may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS film, the crystal regions in the impurity-added region may be amorphized.

[0025] The c-axis of the crystal regions included in the CAAC-OS film aligns in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface. Therefore, depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may point in different directions from each other. Note that the direction of the c-axis of the crystal regions is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS film is formed. The crystal regions are formed

[0026] by film formation or by performing a crystallization treatment such as heat treatment after film formation. A transistor using the CAAC-OS film can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0027] In order to enhance the crystallinity of the oxide semiconductor film, the flatness of the film formation surface and the

[0028] film formation method of the oxide semiconductor film are important. Specifically, the film formation surface of the oxide semiconductor film has an average surface roughness (Ra) of 1 nm or less, preferably It is 0.3 nm or less, more preferably 0.1 nm or less.

[0029] Also, the oxide semiconductor film is preferably formed using a sputtering method in an oxygen gas atmosphere while heating the substrate. At this time, the film is formed so as to contain as few impurities as possible that inhibit the formation of crystal regions in the oxide semiconductor film.

[0030] A specific example of an impurity that inhibits the formation of crystal regions in the oxide semiconductor film is carbon dioxide. In addition, some rare gases (helium, neon, argon, krypton, and xenon), nitrogen, carbon monoxide, and atoms or molecules with a large atomic or molecular diameter such as hydrocarbons can also be impurities that inhibit the formation of crystal regions in the oxide semiconductor film.

[0031] In order to prevent the above-mentioned impurities from being incorporated into the oxide semiconductor film, it is necessary to reduce the impurities in the target, the film-forming gas, and the film-forming chamber.

[0032] Specifically, a film-forming gas with a purity of 8N or higher, preferably 9N or higher, may be used.

[0033] Also, the impurities present in the film-forming chamber may be reduced as follows.

[0034] The impurities present in the film-forming chamber are determined by the balance between the exhaust volume and the leak volume. Therefore, it is preferable to increase the exhaust volume of the film-forming chamber and decrease the leak volume.

[0035] The exhaust volume of the film-forming chamber depends on the type and capacity of the vacuum pump, as well as the length and thickness of the connected piping. For example, the piping connecting the vacuum pump can have a larger exhaust volume if it is short and thick.

[0036] ​​​​​In addition, by connecting different types of vacuum pumps in parallel, various types of gases can be exhausted. For example, it is preferable to use a turbo molecular pump and a cryopump connected in parallel.

[0037] Also, the same type of vacuum pumps can be connected in parallel. For example, when two cryopumps are connected in parallel, it is possible to use one for evacuation while the other is being regenerated. By doing so, the downtime of the apparatus due to regenerating the cryopump can be shortened, and productivity can be increased. Also, by using a plurality of vacuum pumps to evacuate simultaneously, a higher evacuation capacity can be obtained.

[0038] On the other hand, it is necessary to reduce the leakage amount of the film formation chamber.

[0039] Examples of the leakage of the film formation chamber include internal leakage due to impurities adsorbed on the inner wall of the film formation chamber and external leakage from the seal part.

[0040] For example, in order to remove impurities adsorbed on the inner wall of the film formation chamber, the film formation chamber may be evacuated while being heated. By heating the film formation chamber, the impurities adsorbed on the inner wall of the film formation chamber desorb from the inner wall of the film formation chamber, so that the impurities can be efficiently evacuated.

[0041] Also, it is preferable to perform dummy film formation. Dummy film formation means depositing a film on a dummy substrate to deposit a film on the dummy substrate and the inner wall of the film formation chamber, and confining the impurities in the film formation chamber and the adsorbed substances on the inner wall of the film formation chamber in the film. Dummy film formation may be performed while heating the film formation chamber.

[0042] ​​​​​​​​​​In addition, in order to remove impurities present in the film formation chamber, an inert gas such as heated rare gas or oxygen gas is supplied to increase the pressure in the film formation chamber, and after a certain period of time, the film formation chamber is exhausted again. By supplying the heated gas, the impurities adsorbed in the film formation chamber can be desorbed, and the impurities present in the film formation chamber can be reduced. Note that this treatment is effective when repeated. In order to supply an inert gas such as heated rare gas or oxygen gas, a gas heating mechanism may be provided in the film formation apparatus itself. By providing a gas heating mechanism in the film formation apparatus itself, the piping distance from the gas heating mechanism to the film formation chamber etc. can be shortened, so that the gas can be supplied to the film formation chamber etc. while maintaining a high temperature.

[0043] Using such a method, the leak rate is 3×10 -5 Pa·m 3 / s or less, preferably 1×10 -5 Pa·m 3 / s or less, more preferably 3×10 -6 Pa·m 3 / s or less, more preferably 1×10 -6 Pa·m 3 / s or less, even more preferably 3×10 -7 Pa ·m 3 / s or less.

[0044] Note that the leak rate of a gas with a mass-to-charge ratio (m / z) = 28 (such as nitrogen molecules) is 1×1 0 -5 Pa·m 3 / s or less, preferably 3×10 -6 Pa·m 3 / s or less.

[0045] Note that the leak rate of a gas with m / z = 44 (such as carbon dioxide molecules) is 3×10 -6 P a·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0046] In addition, the leak rate of the gas with m / z = 18 (such as water molecules) is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less.

[0047] Using such a method, specifically, the pressure in the film formation chamber is 1×10 -4 Pa or less, preferably is 3×10 -5 Pa or less, more preferably 1×10 -5 Pa or less.

[0048] In the film formation chamber as described above, an oxide semiconductor film is formed.

[0049] In addition, when forming the oxide semiconductor film, it is preferable to remove impurities adsorbed on the film formation surface of the oxide semiconductor film in advance. It is preferable to remove impurities adsorbed on the film formation surface of the oxide semiconductor film in advance.

[0050] Specifically, plasma treatment and / or heat treatment may be performed to remove impurities adsorbed on the film formation surface of the oxide semiconductor film. In addition, the aforementioned plasma treatment and heat treatment are preferably performed in a reduced pressure atmosphere. In this specification, the reduced pressure atmosphere means an atmosphere with a pressure of 10 Pa or less, 1 Pa or less, 1×10 -2 Pa or less, or 1×10 -4 Pa or less.

[0051] In addition, after performing the treatment to remove impurities adsorbed on the film formation surface of the oxide semiconductor film, it is preferable to move it to the film formation chamber of the oxide semiconductor film without exposing it to the atmosphere so that impurities are not adsorbed again. It is preferable to move it to the film formation chamber of the oxide semiconductor film without exposing it to the atmosphere so that impurities are not adsorbed again.

[0052] Here, the oxide semiconductor film is formed with the substrate heating temperature being 100°C or higher and 650°C or lower, preferably 15 0°C or higher and 600°C or lower, more preferably 200°C or higher and 500°C or lower. By setting the substrate heating temperature within the above range, the impurity concentration contained in the oxide semiconductor film can be reduced and an oxide semiconductor film with high crystallinity can be easily obtained.

[0053] Also, it is preferable to perform a heat treatment after forming the oxide semiconductor film. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 30 0°C or higher and 600°C or lower in an inert atmosphere , a reduced-pressure atmosphere or an oxidizing atmosphere. By the heat treatment, the impurity concentration contained in the oxide semiconductor film can be reduced and an oxide semiconductor film with high crystallinity can be easily obtained.

[0054] A transistor using the oxide semiconductor film formed as described above has high reliability and the variation in the threshold voltage is also small.

Advantages of the Invention

[0055] It is possible to provide an oxide semiconductor film with reduced impurities such as hydrogen, nitrogen, and carbon, low carrier density, and high crystallinity.

[0056] It is possible to provide a highly reliable transistor with a small variation in the threshold voltage using the aforementioned oxide semiconductor film.

[0057] It is possible to provide a highly reliable semiconductor device having excellent characteristics and including the aforementioned transistor.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0059] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below. In describing the configuration of the invention with reference to the drawings, the same reference numerals are commonly used between different drawings. When referring to similar ones, the hatch pattern is also the same, and there may be cases where no particular reference numerals are attached.

[0060] Note that the ordinal numbers attached as first, second, etc. are used for convenience and do not indicate the process order or the stacking order Also, the specific names shown in this specification are not for identifying the invention.

[0061] (Embodiment 1) In this embodiment, a method for forming an oxide semiconductor film with few impurities and a transistor using the oxide semiconductor film will be described.

[0062] First, the configuration of a film forming apparatus with less impurity mixing during film formation will be described with reference to FIG. 1.

[0063] FIG. 1(A) shows a multi-chamber film forming apparatus. The film forming apparatus includes a substrate supply chamber 11 having three cassette ports 14 for accommodating substrates, a load lock chamber 12a and a load lock chamber 12b, a transfer chamber 13, a substrate heating chamber 15, a film forming chamber 10a, a film forming chamber 10b, and a film forming chamber 10c. The substrate supply chamber 11 is connected to the load lock chamber 12a and the load lock chamber 12b, the transfer chamber 13, the substrate heating chamber 15, the film forming chamber 10a, the film forming chamber 10b, and the film forming ​​It is connected to chamber 12b. The load lock chambers 12a and 12b are connected to the transfer chamber 13 It is connected to the transfer chamber 13. The substrate heating chamber 15, the film forming chambers 10a, 10b, and 10c are only connected to the transfer chamber 13 Gate valves are provided at the connection parts between the chambers, and each chamber can be independently maintained in a vacuum state. Although not shown, the transfer chamber 13 has one or more substrate transfer robots Here, it is preferable that the substrate heating chamber 15 also serves as a plasma processing chamber. The single wafer type multi-chamber film forming apparatus does not require exposing the substrate to the atmosphere between processes, and can suppress the adsorption of impurities on the substrate In addition, the order of film formation, heat treatment, etc. can be freely constructed Note that the number of film forming chambers, load lock chambers, and substrate heating chambers is not limited to the above numbers, and may be appropriately determined according to the installation space and process

[0064] An example of the film forming chamber (sputtering chamber) shown in Fig. 1(A) will be described with reference to Fig. 2(A). The film forming chamber 10 includes a target 32, a target holder 34 that supports the target, a substrate holder 42 that supports a substrate with a substrate heater 44 embedded therein, and a shutter plate 48 that is rotatable about a shutter shaft 46 Here, the target holder 34 is connected to an RF power source 50 that supplies power via a matcher 52. The film forming chamber 10 is also connected to a gas supply source 56 via a precision machine 54, as well as a vacuum pump 58 and a vacuum pump 59 Here, the film forming chamber 10, the RF power source 50, the shutter shaft 46, the shutter plate 48, and the substrate holder 42 are grounded. However, depending on the purpose, one or more of the film forming chamber 10, the shutter shaft 46, the shutter plate 48, and the substrate holder 42 may be electrically floated

[0065] ​​​​​​​​​Also, the vacuum pump is not limited to only two vacuum pumps, namely vacuum pump 58 and vacuum pump 59, and three or more vacuum pumps may be provided, or only one of them may be provided. For example, another vacuum pump may be provided in series with vacuum pump 58.

[0066] As the vacuum pump used for vacuum pump 58, vacuum pump 59, etc., a roughing pump such as a dry pump and a high-vacuum pump such as a sputter ion pump, a turbo molecular pump, and a cryopump may be appropriately combined. Since the turbo molecular pump stably exhausts gases with a large atomic diameter or molecular diameter and has a low maintenance frequency, it is excellent in productivity. On the other hand, it is known that it has a low exhaust capacity for hydrogen and water. Therefore, it is effective to further combine a cryopump with a high exhaust capacity for atoms and molecules with a relatively high melting point such as water, or a sputter ion pump with a high exhaust capacity for highly reactive atoms and molecules. Also, a vacuum pump in which a cryotrap is connected to a turbo molecular pump may be used. The temperature of the refrigerator of the cryotrap is set to 100 K or lower, preferably 80 K or lower. Also, when the cryotrap has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because it enables efficient exhaust. For example, the temperature of the first-stage refrigerator may be set to 100 K or lower, and the temperature of the second-stage refrigerator may be set to 20 K or lower.

[0067] Note that since the cryopump is a trapping type, it is necessary to perform regeneration regularly. Since the cryopump cannot exhaust while it is being regenerated, it is considered to have low productivity and is rarely used in mass production equipment. To solve this problem, the cryopump ​​​​​​It is okay to connect two or more units in parallel. By connecting two or more cryopumps in parallel, Even if one cryopump is regenerating, the remaining cryopump can be used to pump the gas. Alternatively, the cryopump and the turbomolecular pump may be connected in parallel. In this case, for example, For example, a turbo molecular pump is used to evacuate the gas during film formation, and a cryopump is used at other times. By pumping, the frequency of cryopump regeneration can be reduced.

[0068] In addition, a plurality of gas supply sources 56 and refiners 54 may be provided. Depending on the number of deposition chambers, deposition gas supply sources and purification machines can be increased. In that case, the flow rate of the deposition gas between each refiner and the deposition chamber 10 is controlled by a A mass flow controller may be provided to control the flow rate of the film forming chamber 10 and the refiner 5. It may be connected to the piping between 4.

[0069] In addition, an example of providing a gas heating mechanism between the refiner 54 and the film forming chamber 10 will be described with reference to FIG. 38(A) to 38(C) show details from the gas supply source 56 to the film forming chamber 10. Shows.

[0070] FIG. 38(A) shows a gas heating mechanism 57 connected to the film forming chamber 10 through piping. The structure 57 and the mass flow controller 55 are connected through piping. The gas purifier 54 is connected to the gas supply source 56 through a pipe. The structure is connected through

[0071] FIG. 38(B) shows a case in which the film forming chamber 10 and the mass flow controller 55 are directly connected through piping. The mass flow controller 55 and the gas heating mechanism 57 are connected through a pipe, and the gas heating mechanism 57 and the purifier 54 are connected through a pipe, and the purifier 54 and the gas supply source 56 are connected through a pipe.

[0072] In addition, in order to use the heated gas, it is preferable to use a mass flow controller that can accurately control the gas flow rate of the heated gas.

[0073] Figure 38(C) shows a structure in which the film formation chamber 10 and the gas heating mechanism 57 are connected through a pipe, the gas heating mechanism 57 and the purifier 54 are connected through a pipe, and the purifier 54 and the gas supply source 56 are connected through a pipe.

[0074] Figure 38(C) does not have a mass flow controller, but a gas flow rate control mechanism different from the mass flow controller may be provided. Or, a mechanism may be provided to supply a constant gas flow rate.

[0075] The configuration of Figure 38(C) may be used when it is not necessary to control the gas flow rate with high precision. The mass flow controller is relatively expensive and requires regular maintenance and part replacement. As shown in Figure 38(C), the cost of the device can be reduced by not providing a mass flow controller.

[0076] For example, for reducing impurities in the film formation chamber 10 using the heated gas described later, the configuration of Figure 38(C) may be used.

[0077] The gas heating mechanism 57 heats the gas supplied to the film formation chamber 10 to 40°C or higher and 400°C Alternatively, it can be heated to 50°C or higher and 200°C or lower.

[0078] Next, the film formation chamber shown in Fig. 2(A) will be described. Although not shown, if a magnet is provided inside or below the target holder 34, it is preferable because a high-density plasma can be confined near the target. This method is called the magnetron sputtering method, and it has a high deposition rate, low plasma damage to the substrate, and good film quality. In the magnetron sputtering method, if the magnet is rotatable, the deviation of the magnetic field can be reduced so that the utilization efficiency of the target is increased and the variation in film quality within the plane of the substrate can be reduced. In the magnetron sputtering method, making the magnet rotatable can reduce the deviation of the magnetic field so that the utilization efficiency of the target is increased and the variation in film quality within the plane of the substrate can be reduced.

[0079] Also, here an RF power supply was used as the sputtering power supply, but it is not necessarily limited to an RF power supply. Depending on the application, a DC power supply or an AC power supply can be used, or two or more types of power supplies can be provided so that they can be switched. When using a DC power supply or an AC power supply, the matching device between the power supply and the target holder becomes unnecessary.

[0080] Also, the substrate holder 42 needs to be provided with a chuck mechanism for supporting the substrate. Examples of the chuck mechanism include the electrostatic chuck method and the clamp method. To improve the uniformity of the film quality and film thickness within the plane of the substrate, a rotation mechanism may be provided on the substrate holder 42. Also, multiple substrate holders can be provided to form a film formation chamber capable of forming films on multiple substrates at once. Also, a configuration without providing the shutter shaft 46, the shutter plate 48, and the substrate heater 44 is also acceptable. In Fig. 2(A), the target is upward and the substrate is downward, but the target In Fig. 2(A), the target is upward and the substrate is downward, but the target ​​​​A configuration where the target is downward and the substrate is upward, or a configuration where the target and the substrate face each other horizontally is also acceptable. It may also be configured as such.

[0081] The substrate heating chamber 15 may be heated using, for example, a resistance heating element or the like. Alternatively, it may be heated by heat conduction or heat radiation from a medium such as a heated gas. For example, RTA (Rapid Thermal Anneal) such as GRT A (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTA heats the object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. GRT A performs a heat treatment using a high-temperature gas. An inert gas is used as the gas. A(Gas Rapid Thermal Anneal), LRTA(Lamp Ra pid Thermal Anneal), etc. of RTA(Rapid Thermal Anneal) can be used. LRTA heats the object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. GRT A performs a heat treatment using a high-temperature gas. An inert gas is used as the gas. A is used to heat the object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. GRT A performs a heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0082] For example, the substrate heating chamber 15 may be configured as shown in Fig. 2(B). The substrate heating chamber 15 has a substrate holder 42 with a substrate heater 44 embedded therein. The substrate heating chamber 15 is connected to a gas supply source 56 via a purifier 54, and a vacuum pump 58 and a vacuum pump 59. Instead of the heating mechanism by the substrate heater, an LRTA may be provided at a position facing the substrate holder. In that case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. The substrate heating chamber 15 has a substrate holder 42 with a substrate heater 44 embedded therein. The substrate heating chamber 15 is connected to a gas supply source 56 via a purifier 54, and a vacuum pump 58 and a vacuum pump 59. Instead of the heating mechanism by the substrate heater, an LRTA may be provided at a position facing the substrate holder. In that case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. The substrate heating chamber 15 has a substrate holder 42 with a substrate heater 44 embedded therein. The substrate heating chamber 15 is connected to a gas supply source 56 via a purifier 54, and a vacuum pump 58 and a vacuum pump 59. Instead of the heating mechanism by the substrate heater, an LRTA may be provided at a position facing the substrate holder. In that case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. Instead of the heating mechanism by the substrate heater, an LRTA may be provided at a position facing the substrate holder. In that case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. In that case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. In that case, a reflector may be provided on the substrate holder 42 to efficiently transfer heat to the substrate. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42. Here, when the substrate heating chamber 15 also serves as a plasma processing chamber, the substrate holder 42 is connected to an RF power source 50 via a matcher 52, and a counter electrode 68 is provided facing the substrate holder 42.

[0083] Note that the back pressure of the film formation chamber 10 and the substrate heating chamber 15 is 1×10-4 Pa or less, preferably 3 ×10 -5 Pa or less, more preferably 1×10 -5 Pa or less.

[0084] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a partial pressure of a gas with m / z = 18 of 3×10 - 5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less is.

[0085] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a partial pressure of a gas with m / z = 28 of 3×10 - 5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less is.

[0086] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a partial pressure of a gas with m / z = 44 of 3×10 - 5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less is.

[0087] Note that the film formation chamber 10 and the substrate heating chamber 15 have a leak rate of 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0088] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a leak rate of a gas with m / z = 18 of 1 ×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m3 / s or less.

[0089] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a leak rate of 1 ×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0090] In addition, the film formation chamber 10 and the substrate heating chamber 15 have a leak rate of 3.0% for the gas with m / z=44. ×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0091] The leak rate depends on external and internal leaks. External leaks occur due to tiny holes or seals. An internal leak is when gas flows into the vacuum system from outside due to a valve failure or other reasons. This is caused by leakage from partitions such as valves and gas released from internal components. In order to keep the above values ​​or less, measures must be taken to prevent both external and internal leaks. There is.

[0092] For example, it is advisable to seal the opening and closing parts of the deposition chamber with a metal gasket. , using a metal material coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have a higher adhesion than O-rings and can reduce external leakage. In addition, the impurities of metal materials coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using the dynamics function, the release of gas containing impurities from the metal gasket is suppressed, and the internal This can reduce internal leakage.

[0093] As members constituting the film forming apparatus, use aluminum, chromium, titanium, zirconium, nickel or vanadium that contain little impurity-emitting gas. Further, the above materials may be used after being coated with an alloy material containing iron, chromium and nickel. Alloy materials containing iron, chromium and nickel are rigid, heat-resistant and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like to reduce the surface area, the emitted gas can be reduced.

[0094] Alternatively, the members of the film forming apparatus may be coated with iron fluoride, aluminum oxide, chromium oxide or the like.

[0095] The members of the film forming apparatus are preferably composed of only metal materials as much as possible. For example, even when installing a viewing window composed of quartz or the like, the surface should be thinly coated with iron fluoride, aluminum oxide, chromium oxide or the like to suppress the emitted gas.

[0096] In addition, when providing a purification device for the film forming gas, the length of the pipe from the purification device to the film forming chamber is 5 m or less, preferably 1 m or less. By setting the length of the pipe to 5 m or less or 1 m or less, the influence of the emitted gas from the pipe can be reduced according to the length.

[0097] Furthermore, for the pipe of the film forming gas, it is preferable to use a metal pipe whose inside is coated with iron fluoride, aluminum oxide, chromium oxide or the like. The above-mentioned pipe, for example, compared with SUS316L-EP pipe has less emission amount containing impurities and can reduce the mixing of impurities into the film forming gas. Also, for the joints of the pipes, it is preferable to use high-performance ultra-small metal gasket joints (UPG joints). Also, by configuring all the materials of the pipes with metal materials, compared with the case of using resin or the like, the generated emitted gas can be reduced.​​​​​ It is preferable that the influence of sputtering and external leakage can be reduced.

[0098] The adsorbates present in the film-forming chamber do not affect the pressure in the film-forming chamber while they are adsorbed, but when the film-forming chamber is exhausted, they release gas. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with a high exhaust capacity to desorb as much as possible the adsorbates present in the film-forming chamber and exhaust it in advance. In addition, in order to promote the desorption of the adsorbates, the film-forming chamber may be heated. By heating, the desorption rate of the adsorbates can be increased by about 10 times. The heating may be performed at 100 °C or higher and 450 °C or lower. At this time, when removing the adsorbates while supplying an inert gas, the desorption rate of substances such as water that are difficult to desorb by simple exhaust can be further increased. In addition, by heating the supplied inert gas to about the same temperature as the heating temperature of the film-forming chamber, the desorption rate of the adsorbates can be further increased. Here, it is preferable to use a noble gas as the inert gas. Also, depending on the type of film to be formed, oxygen or the like may be used instead of the inert gas. For example, when forming an oxide film, it may be preferable to use oxygen, which is the main component of the oxide.

[0099] Alternatively, it is preferable to increase the pressure inside the film-forming chamber by supplying an inert gas such as heated noble gas or an oxygen gas, and then perform a process of exhausting the film-forming chamber again after a certain period of time. By supplying the heated gas, the desorption of the adsorbates inside the film-forming chamber becomes easier. In addition, this process is effectively repeated in the range of 2 to 30 times, preferably 5 to 15 times. Specifically, the temperature is 40 °C or higher and 400 °C or lower, preferably 50 °C or higher and 200 °C or higher. By supplying an inert gas or oxygen, etc., the pressure in the film deposition chamber is set to 0.1 Pa or more and 1 kPa or less, 1 Pa or more and 1 kPa or less, or 5 Pa or more and 100 Pa or less, and the period for maintaining the pressure is set to 1 minute or more and 300 minutes or less, or 5 minutes or more and 120 minutes or less. Then,

[0100] The desorption rate of the adsorbed substances can be further increased by performing dummy film deposition. The dummy substrate preferably uses a material that emits little gas, for example, the same material as the substrate 100 described later.

[0101] Figure 1(B) shows a film deposition apparatus with a different configuration from that of Figure 1(A). The film deposition apparatus has a load lock chamber 22a, a substrate heating chamber 25, a film deposition chamber 20a, a film deposition chamber 20b, and a load lock chamber 22 b. The load lock chamber 22a is connected to the substrate heating chamber 25, the substrate heating chamber 25 is connected to the film deposition chamber 20a, the film deposition chamber 20a is connected to the film deposition chamber 20b, and the film deposition chamber 20b is connected to the load lock chamber 22b. Gate valves are provided at the connection parts between the chambers, and each chamber can be maintained in a vacuum state independently. The film deposition chambers 20a and 20b have the same configuration as the film deposition chambers 10a, 10b, and 10c in Figure 1 (A). Also, the substrate heating chamber 25 has the same configuration as the substrate heating chamber 15 in Figure 1(A). The substrate is transported only in one direction of the arrow shown in Figure 1(B), and the substrate inlet and outlet are different. Different from the single-wafer type multi-chamber film deposition apparatus in Figure 1(A), since it does not have a transfer chamber, the installation area can be reduced. Note that the number of film deposition chambers, load lock chambers, and substrate heating chambers is not limited to the numbers described above. It is not necessary, and it may be appropriately selected according to the installation space and process. For example, the film formation chamber 20b may be omitted, or a second substrate heating chamber or a third film formation chamber connected to the film formation chamber 20b may be provided .

[0102] By forming an oxide semiconductor film using the above film forming apparatus, the incorporation of impurities into the oxide semiconductor film can be suppressed. Furthermore, by forming a film in contact with the oxide semiconductor film using the above film forming apparatus, the incorporation of impurities from the film in contact with the oxide semiconductor film into the oxide semiconductor film can be suppressed. .

[0103] Next, a method for forming an oxide semiconductor film with low concentrations of hydrogen, nitrogen, and carbon, which are impurities, will be described.

[0104] The oxide semiconductor film is formed in an oxygen gas atmosphere with the substrate heating temperature being 100°C or higher and 600°C or lower, preferably 150°C or higher and 550°C or lower, more preferably 200°C or higher and 500°C or lower. The thickness of the oxide semiconductor film is 1 nm or more and 40 nm or less, preferably 3 nm or more and 20 n m or less. The higher the substrate heating temperature during film formation, the lower the impurity concentration of the obtained oxide semiconductor film. Also, the atomic arrangement in the oxide semiconductor film is ordered and densified, and a polycrystalline film or a CAAC-OS film is more likely to be formed. Furthermore, by forming the film in an oxygen gas atmosphere, since no extra atoms such as noble gases are contained, a polycrystalline film or a CAAC-OS film is more likely to be formed. However, a mixed atmosphere of oxygen gas and noble gas may also be used. In that case, the ratio of oxygen gas is 30% by volume or more, preferably 50% by volume or more, more preferably 80% by volume or more. However, if it is made too thin, the influence of interface scattering becomes strong, resulting in a decrease in the field-effect mobility. There are cases.

[0105] The oxide semiconductor film is formed with a film formation pressure of 0.8 Pa or less, preferably 0.4 Pa or less, and the distance between the target and the substrate is 40 mm or less, preferably 25 mm or less. By forming the oxide semiconductor film under such conditions, the frequency of collision between sputtered particles and other sputtered particles, gas, or ions can be reduced. That is, according to the film formation pressure, the distance between the target and the substrate is made smaller than the mean free path of sputtered particles, gas, or ions, so that impurities incorporated into the film can be reduced.

[0106] For example, the mean free path at a pressure of 0.4 Pa and a temperature of 25 °C (absolute temperature of 298 K) is 48.7 mm for hydrogen molecules (H2), 57.9 mm for helium atoms (He), water molecules ( H2O) is 31.3 mm, ethane molecules (CH4) is 13.2 mm, neon atoms (Ne) is 42.3 mm, nitrogen molecules (N2) is 23.2 mm, carbon monoxide molecules (CO) is 16.0 m m, oxygen molecules (O2) is 26.4 mm, argon atoms (Ar) is 28.3 mm, carbon dioxide molecules (CO2) is 10.9 mm, krypton atoms (Kr) is 13.4 mm, xenon atoms (Xe) is 9.6 mm. Note that if the pressure is doubled, the mean free path becomes half, and if the absolute temperature is doubled, the mean free path becomes twice as long.

[0107] The mean free path is determined by pressure, temperature, and the diameter of atoms or molecules. When pressure and temperature are constant, the larger the diameter of atoms or molecules, the shorter the mean free path. Note , the diameter of each atom or each molecule is 0.218 nm for H2, 0.200 nm for He, 0.272 nm for H2O is 0.272 nm, 0.419 nm for CH4, 0.234 nm for Ne, 0.316 nm for N2, 0.380 nm for CO, 0.296 nm for O2, 0.286 nm for Ar, 0.460 nm for CO2 is 0.460 nm, 0.415 nm for Kr, 0.491 nm for Xe.

[0108] Therefore, the larger the diameter of the atom or molecule, the shorter the mean free path, and when incorporated into the film, the growth of the crystal region is inhibited due to the large diameter of the atom or molecule. Therefore, for example, it can be said that atoms and molecules having a diameter of Ar or more tend to become impurities.

[0109] Here, classical molecular dynamics calculations were performed to evaluate whether the crystal structure can be maintained when CO2 is added between the layers of the In-Ga-Zn-O crystal.

[0110] Figure 30 is a schematic diagram of the In-Ga-Zn-O crystal, and CO2 was added to the layer indicated by the arrow in Figure 30. The addition amount of CO2 was 0.07% (5 .19×10 19 .19×10 19 per cm 3 ), 0.15% (1.04×10 20 per cm 3 ), 0.2 2% (1.65×10 20 per cm 3 ), 0.30% (2.08×10 20 per cm 3 ), 0.37% (2.60×10 20 per cm 3 ), 0.44% (3.11×10 20 per / cm 3 ), 0.52% (3.63×10 20 per cm 3 ​)、0.59% (4.15×10 20 pieces / cm 3 ) or 0.67% (4.67×10 20 pieces / cm 3 ) was used as the ratio.

[0111] In the calculation, Materials Explorer 5.0 manufactured by Fujitsu Limited was used , with the temperature at 298 K, the pressure at 1 atm, the time step width at 0.2 fs, and the number of steps at 5 million times .

[0112] As a result, when the ratio of adding CO2 is 0.07% - 0.52%, the In - Ga - Zn - O crystal is retained. When the ratio of adding CO2 is 0.59% - 0.67%, the In - Ga -Zn - O crystal could not be retained.

[0113] That is, it can be seen that in order to obtain an In - Ga - Zn - O crystal, the ratio of CO2 to all atoms of the In - Ga - Zn - O crystal needs to be 0.52% or less or less than 0.59%.

[0114] Next, heat treatment is performed. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 600°C or lower, in a reduced - pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. By the heat treatment, the impurity concentration in the oxide semiconductor film can be reduced. Also, an oxide semiconductor film with high crystallinity is likely to be obtained. The oxidizing atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases such as oxygen, ozone, and nitrous oxide.

[0115] As the above - mentioned heat treatment, it is preferable to perform the heat treatment in a reduced - pressure atmosphere or an inert atmosphere and then switch to an oxidizing atmosphere while maintaining the temperature and perform further heat treatment. This is because in a reduced - pressure atmosphere When heat treatment is performed in an air or inert atmosphere, the impurity concentration in the oxide semiconductor film can be reduced This is because oxygen vacancies are simultaneously generated. The oxygen vacancies generated at this time can be reduced by heat treatment in an oxidizing atmosphere.

[0116] By performing heat treatment on the oxide semiconductor film after film formation in addition to substrate heating during film formation, the impurity concentration in the film can be reduced.

[0117] By using the film forming apparatus as described above, an oxide semiconductor film with few impurities can be obtained . The oxide semiconductor film with few impurities has a small carrier density and high crystallinity, resulting in excellent semiconductor characteristics. Therefore, high reliability can be obtained when used in a transistor .

[0118] Specifically, the hydrogen concentration in the oxide semiconductor film is less than 5×10 19 atom s / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably 1× 10 18 atoms / cm 3 , even more preferably 5×10 17 atoms / cm 3 or less .

[0119] Also, the nitrogen concentration in the oxide semiconductor film is less than 5×10 19 atoms / c m 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably 1×10 1 8 atoms / cm 3 or less, even more preferably 5×1017 atoms / cm 3 shall be as follows as follows

[0120] Also, the carbon concentration in the oxide semiconductor film is 5 × 10 19 atoms / c m 3 less than, preferably 5 × 10 18 atoms / cm 3 or less, more preferably 1 × 10 1 8 atoms / cm 3 or less, even more preferably 5 × 10 17 atoms / cm 3 shall be as follows as follows

[0121] Also, the oxide semiconductor film has the amount of gas released at m / z = 2 (such as hydrogen molecules), m / z = 18, m / z = 28, and m / z = 44 by temperature-programmed desorption gas spectroscopy (TDS: Thermal Desorp tion Spectroscopy) analysis being 1 × 10 or less, preferably 1 × 10 19 atoms / cm 3 or less, respectively. 18 atoms / cm 3 or less shall be as follows

[0122] Note that for the method of measuring the amount of gas released by TDS analysis, refer to the method of measuring the amount of oxygen atoms released described later. Take it into consideration.

[0123] Next, the transistor using the oxide semiconductor film formed using the above-described film forming apparatus will be described with reference to FIGS. 3 to 8.

[0124] The transistors shown in FIGS. 3 to 6 are excellent in productivity because the number of photolithography process steps is small. The transistors shown in FIGS. 3 to 6 are display devices with a relatively large transistor size and are excellent in productivity. It is often used in settings such as...

[0125] First, the structure of the transistor shown in FIG. 3 will be described. FIG. 3(A) is a top view of the transistor. The cross-sectional view corresponding to the dashed line A-B shown in FIG. 3(A) is FIG. 3(B).

[0126] The transistor shown in FIG. 3(B) includes a base insulating film 102 provided on a substrate 100, a oxide semiconductor film 106 provided on the base insulating film 102, a pair of electrodes 116 provided on the oxide semiconductor film 106 and in contact with at least a part of the oxide semiconductor film 106, a gate insulating film 112 provided to cover the oxide semiconductor film 106 and the pair of electrodes 116, and a gate electrode 104 provided to overlap the oxide semiconductor film 106 with the gate insulating film 112 therebetween.

[0127] Here, for the oxide semiconductor film 106, an oxide semiconductor film with a low impurity concentration described in this embodiment may be applied.

[0128] The thickness of the oxide semiconductor film 106 is set to be 1 nm or more and 50 nm or less. Preferably, the thickness is 3 nm or more and 20 nm or less. In particular, for a transistor with a channel length of 30 nm or less, by setting the thickness of the oxide semiconductor film 106 to about 5 nm, the short-channel effect can be suppressed and stable electrical characteristics can be obtained.

[0129] The oxide semiconductor film 106 preferably contains at least In and Zn. Further, in addition to In and Zn, the oxide semiconductor film 106 preferably contains Ga, Sn, Hf, or Al in order to reduce the variation in the electrical characteristics of the transistor.

[0130] Alternatively, in addition to In and Zn, the oxide semiconductor film 106 may contain one or more selected from lanthanoids La, Ce, Pr, Nd, Sm, Eu, G d, Tb, Dy, Ho, Er, Tm, Yb, and Lu to reduce the variation in the electrical characteristics of the transistor.

[0131] As the oxide semiconductor film 106, for example, an In-Zn-O-based material which is a binary metal oxide , Sn-Zn-O-based material, Al-Zn-O-based material, Zn-Mg-O-based material, Sn-Mg- O-based material, In-Mg-O-based material, In-Ga-O-based material, a ternary metal oxide such as an I n-Ga-Zn-O-based material, In-Al-Zn-O-based material, In-Sn-Zn-O-based material , Sn-Ga-Zn-O-based material, Al-Ga-Zn-O-based material, Sn-Al-Zn-O-based material, In-Hf-Zn-O-based material, In-La-Zn-O-based material, In-Ce-Zn- O-based material, In-Pr-Zn-O-based material, In-Nd-Zn-O-based material, In-Sm-Z n-O-based material, In-Eu-Zn-O-based material, In-Gd-Zn-O-based material, In-Tb -Zn-O-based material, In-Dy-Zn-O-based material, In-Ho-Zn-O-based material, In- Er-Zn-O-based material, In-Tm-Zn-O-based material, In-Yb-Zn-O-based material, I n-Lu-Zn-O-based material, a quaternary metal oxide such as an In-Sn-Ga-Zn-O-based material , In-Hf-Ga-Zn-O-based material, In-Al-Ga-Zn-O-based material, In-S n-Al-Zn-O-based material, In-Sn-Hf-Zn-O-based material, In-Hf-Al-Z n-O-based material can be used.

[0132] For example, the In-Ga-Zn-O-based material contains In, Ga, and Zn as main components. ​It means oxide, and the ratio of In, Ga, and Zn is not limited.

[0133] For example, in a transistor using an In-Sn-Zn-O-based material, a relatively high field-effect mobility can be obtained relatively easily. Specifically, the field-effect mobility of the transistor is 31 cm 2 / Vs or more, 40 cm 2 / Vs or more, 60 cm 2 / Vs or more, 80 cm 2 / Vs or more, or 100 cm 2 / Vs or more. In addition, even with materials other than the In-Sn-Zn-O-based material (for example, an In-Ga-Zn-O-based material), the field-effect mobility can be increased by reducing the defect density.

[0134] When an In-Zn-O-based material is used as the oxide semiconductor film 106, in terms of atomic ratio, In / Zn = 0.5 or more and 50 or less, preferably In / Zn = 1 or more and 20 or less, more preferably In / Zn = 1.5 or more and 15 or less. By setting the atomic ratio of Zn within the above range, the field-effect mobility of the transistor can be improved. Here, when the atomic ratio of the compound is In :Zn:O = X:Y:Z, it is preferable that Z > 1.5X + Y.

[0135] As the oxide semiconductor film 106, a material represented by the chemical formula InMO3(ZnO) m (m > 0) may be used. Here, M represents one or more metal elements selected from Zn, Ga, Al, Mn, Sn, Hf, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co may be used.

[0136] The oxide semiconductor film 106 is selected from materials with a bandgap of 2 .5 eV or more, preferably 2.8 eV or more, and more preferably 3.0 eV or more in order to reduce the off-current of the transistor. Select.

[0137] In addition, it is preferable that the oxide semiconductor film 106 has reduced alkali metals and alkaline earth metals, etc., and is an oxide semiconductor film 106 with an extremely low impurity concentration. If the oxide semiconductor film 106 has the aforementioned impurities, recombination within the bandgap occurs due to the levels formed by the impurities, and the off-current of the transistor increases.

[0138] Also, the alkali metal concentration in the oxide semiconductor film 106 is such that in SIMS, the sodium concentration is 5×10 16 atoms / cm 3 or less, preferably 1×10 16 atoms / cm 3 or less, and more preferably 1×10 15 atoms / cm 3 or less. Similarly, the lithium concentration is 5×10 15 atoms / cm 3 or less, preferably 1×10 15 atoms / c m 3 or less. Similarly, the potassium concentration is 5×10 15 atoms / cm 3 or less, preferably 1×10 15 atoms / cm 3 or less.

[0139] By using the oxide semiconductor film 106 shown above, the off-current of the transistor can be reduced. Specifically, for example, when the channel length is 3 μm and the channel width is 1 μm, the off-current of the transistor is 1×10 -18 A or less, 1×10-21 A or less, or 1×10 -24 A can be made as follows.

[0140] The oxide semiconductor film 106 is non-single crystal. In particular, it preferably has crystallinity. For example, a polycrystalline film or a CAAC-OS film is used.

[0141] An example of the crystal structure included in the CAAC-OS film will be described in detail with reference to FIGS. 14 to 17. Unless otherwise specified, in FIGS. 14 to 17, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is the ab-plane. When simply referring to the upper half or the lower half, it means the upper half or the lower half when divided by the ab-plane. In FIG. 14, O surrounded by a circle indicates O with a coordination number of 4, and O surrounded by a double circle indicates O with a coordination number of 3.

[0142] FIG. 14(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter referred to as 4 coordinate O) adjacent to In. Here, the structure in which only the adjacent oxygen atoms are shown for one metal atom is called a small group. The structure of FIG. 14(A) has an octahedral structure, but is shown in a planar structure for simplicity. In the upper half and the lower half of FIG. 14(A), there are three 4-coordinate O atoms each. The small group shown in FIG. 14(A) has a charge of 0.

[0143] FIG. 14(B) shows a structure having one 5-coordinate Ga, three 3-coordinate oxygen atoms (hereinafter referred to as 3 coordinate O) adjacent to Ga, and two 4-coordinate O adjacent to Ga. All the 3-coordinate O atoms are present on the ab-plane. In the upper half and the lower half of FIG. 14(B), there is one 4-coordinate O atom each. Also, since In can also have a coordination number of 5, the structure shown in FIG. 14(B) can be taken. The small group shown in Fig. 14(B) has a charge of 0.

[0144] Fig. 14(C) shows a structure having one 4 - coordinated Zn and four 4 - coordinated O's adjacent to the Zn. There is one 4 - coordinated O in the upper half of Fig. 14(C) and three 4 - coordinated O's in the lower half. Or, there may be three 4 - coordinated O's in the upper half of Fig. 14(C) and one 4 - coordinated O in the lower half. The small group shown in Fig. 14(C) has a charge of 0. Or, there may be three 4 - coordinated O's in the upper half of Fig. 14(C) and one 4 - coordinated O in the lower half. The small group shown in Fig. 14(C) has a charge of 0. The small group shown in Fig. 14(C) has a charge of 0.

[0145] Fig. 14(D) shows a structure having one 6 - coordinated Sn and six 4 - coordinated O's adjacent to the Sn. There are three 4 - coordinated O's in the upper half of Fig. 14(D) and three 4 - coordinated O's in the lower half. The small group shown in Fig. 14(D) has a charge of + 1. The small group shown in Fig. 14(D) has a charge of + 1.

[0146] Fig. 14(E) shows a small group containing two Zn's. There is one 4 - coordinated O in the upper half of Fig. 14(E) and one 4 - coordinated O in the lower half. The small group shown in Fig. 14(E) has a charge of - 1. There is one 4 - coordinated O in the upper half of Fig. 14(E) and one 4 - coordinated O in the lower half. The small group shown in Fig. 14(E) has a charge of - 1. The small group shown in Fig. 14(E) has a charge of - 1.

[0147] Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell). Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell).

[0148] Here, the rules for the combination of these small groups will be described. The three O's in the upper half of the 6 - coordinated In shown in Fig. 14(A) each have three adjacent In's downward, and the three O's in the lower half each have three adjacent In's upward. The one O in the upper half of the 5 - coordinated Ga shown in Fig. 14(B) has one adjacent Ga downward, and the one O in the lower half has one adjacent Ga upward. The one O in the upper half of the 4 - coordinated Zn shown in Fig. 14(C) has one The three O's in the upper half of the 6 - coordinated In shown in Fig. 14(A) each have three adjacent In's downward, and the three O's in the lower half each have three adjacent In's upward. The one O in the upper half of the 5 - coordinated Ga shown in Fig. 14(B) has one adjacent Ga downward, and the one O in the lower half has one adjacent Ga upward. The one O in the upper half of the 5 - coordinated Ga shown in Fig. 14(B) has one adjacent Ga downward, and the one O in the lower half has one adjacent Ga upward. adjacent Zn downward. has adjacent Zn, and the three O atoms in the lower half each have three adjacent Zn atoms in the upward direction. This way, the number of O atoms with four - coordination in the upward direction of the metal atom and the number of adjacent metal atoms in the downward direction of that O are equal. Similarly, the number of O atoms with four - coordination in the downward direction of the metal atom and the number of adjacent metal atoms in the upward direction of that O are equal. Since O has four - coordination, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, when the sum of the number of O atoms with four - coordination in the upward direction of the metal atom and the number of O atoms with four - coordination in the downward direction of another metal atom is 4, two types of small groups having metal atoms can bond to each other. For example, when a six - coordination metal atom (In or Sn) bonds through the four - coordination O atoms in the lower half, since there are three four - coordination O atoms, it will bond with either a five - coordination metal atom (Ga or In), or a four - coordination metal atom (Zn).

[0149] Metal atoms having these coordination numbers bond through four - coordination O atoms in the c - axis direction. In addition, multiple small groups bond to form a medium group so that the total charge of the layer structure becomes 0.

[0150] Fig. 15(A) shows a model diagram of the medium group constituting the layer structure of the In - Sn - Zn - O - based material. Fig. 15(B) shows a large group composed of three medium groups. Note that Fig. 1 5(C) shows the atomic arrangement when observing the layer structure of Fig. 15(B) from the c - axis direction.

[0151] In Fig. 15(A), for simplicity, the three - coordination O atoms are omitted, and only the number of four - coordination O atoms is shown. For example, there are three four - coordination O atoms each in the upper half and the lower half of Sn, which is indicated by a round frame. is shown as 3. Similarly, in Fig. 15(A), there is one 4-coordinate O each in the upper and lower halves of In, which is shown as 1 in the round frame. Also, similarly, in Fig. 15 (A), there is one 4-coordinate O in the lower half and three 4-coordinate O in the upper half of Zn, and there is one 4-coordinate O in the upper half and three 4-coordinate O in the lower half of Zn are shown.

[0152] In the middle group that constitutes the layer structure of the In-Sn-Zn-O system material in Fig. 15(A), in order from the top, Sn with three 4-coordinate O each in the upper and lower halves is combined with In with one 4-coordinate O each in the upper and lower halves, and the In is combined with Zn with three 4-coordinate O in the upper half. Through one 4-coordinate O in the lower half of the Zn, it is combined with In with three 4-coordinate O each in the upper and lower halves. The In is combined with a small group consisting of two Zn with one 4-coordinate O in the upper half. Through one 4-coordinate O in the lower half of this small group, it is combined with Sn with three 4-coordinate O each in the upper and lower halves. This is the structure. A plurality of these middle groups are combined to form a large group.

[0153] Here, in the case of 3-coordinate O and 4-coordinate O, the charge per bond can be considered to be -0.6 67 and -0.5 respectively. For example, the charges of In (6-coordinate or 5-coordinate), Zn (4 -coordinate), and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4 respectively. Therefore, the small group containing Sn has a charge of +1. Thus, in order to form a layer structure containing Sn, a charge of -1 to cancel out the charge of +1 is required. As a structure with a charge of -1, as shown in Fig. 14(E), a small group containing two Zn can be mentioned. For example, Sn ​​​​​​​​​ If there is one small group containing one Zn and one small group containing two Zn, the charges will cancel each other out, so that the total charge of the layer structure can be set to 0. As a result, the total charge of the layer structure can be made zero.

[0154] Specifically, by repeating the large group shown in Fig. 15(B), a crystal (In2SnZn3O8) of an In-Sn-Zn-O-based material can be obtained. Note that the layer structure of the obtained In-Sn-Zn-O-based material is In2SnZnO6(ZnO) -O system material can be represented by the composition formula (m is a natural number). Sn-Zn-O-based material can be represented by the composition formula (m is a natural number). m (m is a natural number.) and can be represented by the following composition formula.

[0155] In addition, there are also In-Sn-Ga-Zn-O-based materials which are oxides of quaternary metals, and In-Ga-Zn-O-based materials, In-Al-Zn-O-based materials which are oxides of ternary metals, Sn-Ga-Zn-O-based materials, Al-Ga-Zn-O-based materials, Sn-Al-Zn-O-based materials materials, In-Hf-Zn-O-based materials, In-La-Zn-O-based materials, In-Ce-Zn- O-based materials, In-Pr-Zn-O-based materials, In-Nd-Zn-O-based materials, In-Sm-Z n-O-based materials, In-Eu-Zn-O-based materials, In-Gd-Zn-O-based materials, In-Tb -Zn-O-based materials, In-Dy-Zn-O-based materials, In-Ho-Zn-O-based materials, In- Er-Zn-O-based materials, In-Tm-Zn-O-based materials, In-Yb-Zn-O-based materials, I n-Lu-Zn-O-based materials, and In-Zn-O-based materials, Sn- Zn-O-based materials, Al-Zn-O-based materials, Zn-Mg-O-based materials, Sn-Mg-O-based materials In-Mg-O-based materials, In-Ga-O-based materials, etc. are used, the situation is the same.

[0156] For example, FIG. 16(A) shows a model diagram of the middle group that constitutes the layer structure of the In-Ga-Zn-O-based material.

[0157] In FIG. 16(A), the middle group that constitutes the layer structure of the In-Ga-Zn-O-based material is such that, in order from the top, In with three 4-coordinate O atoms each in the upper and lower halves, Zn with one 4-coordinate O atom in the upper half, binds to In, and through the three 4-coordinate O atoms of the lower half of the Zn, Ga with one 4-coordinate O atom each in the upper and lower halves binds to the Zn, and through the one 4-coordinate O atom of the lower half of the Ga, In with three 4-coordinate O atoms each in the upper and lower halves binds. This middle group combines in multiple numbers to form a large group.

[0158] FIG. 16(B) shows a large group composed of three middle groups. Note that FIG. 16(C) shows the atomic arrangement when observing the layer structure of FIG. 16(B) from the c-axis direction.

[0159] Here, since the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3 respectively, a small group containing any of In, Zn, and Ga has a charge of 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0.

[0160] Also, the middle group that constitutes the layer structure of the In-Ga-Zn-O-based material is not limited to the middle group shown in FIG. 16(A), and large groups can also be formed by combining middle groups with different arrangements of In, Ga, and Zn.

[0161] Specifically, by repeating the large group shown in FIG. 16(B), In-Ga-Zn ​​​​​​​​​​​​Crystals of the -O-based material can be obtained. Note that the layer of the obtained In-Ga-Zn-O-based material structure can be represented by a composition formula of InGaO3(ZnO) n (n is a natural number).

[0162] In the case of n = 1 (InGaZnO4), for example, it can have the crystal structure shown in Fig. 17(A) . Note that in the crystal structure shown in Fig. 17(A), as explained in Fig. 14(B), Ga and In take a 5-fold coordination, so a structure in which Ga is replaced by In is also possible.

[0163] Also, in the case of n = 2 (InGaZn2O5), for example, it can have the crystal structure shown in Fig. 17(B) . Note that in the crystal structure shown in Fig. 17(B), as explained in Fig. 14(B) , Ga and In take a 5-fold coordination, so a structure in which Ga is replaced by In is also possible.

[0164] Here, in the large group of InGaZnO4 shown in Fig. 16(B), the change in the crystal state when one carbon atom (C) is introduced was evaluated using first-principles calculations.

[0165] Note that for the calculation, the first-principles calculation software CASTEP manufactured by Accelrys was used. Also , the pseudopotential was of the ultrasoft type and the cutoff energy was 300 eV. .

[0166] Fig. 31(A) shows the positions where C is introduced in the large group of InGaZnO4. Fig. 31(B) shows the crystal state after introducing C and optimizing the structure in the large group of InGaZnO4.

[0167] According to Fig. 31(B), when C is introduced, C binds to O, and the interatomic distance between the original Ga and O has widened.

[0168] That is, it can be seen that when C is present in the In-Ga-Zn-O-based material, it becomes difficult to maintain the crystal structure. It can be seen.

[0169] Next, in the large group of InGaZnO4, the change in the crystal state when one carbon dioxide molecule (CO2) is introduced was evaluated using first-principles calculations. It was evaluated using first-principles calculations.

[0170] Note that for the calculations, the first-principles calculation software CASTEP manufactured by Accelrys was used. Also, the pseudopotential was of the ultrasoft type, and the cutoff energy was set to 300 eV. Also, the pseudopotential was of the ultrasoft type, and the cutoff energy was set to 300 eV. .

[0171] Figure 39(A) shows the position where CO2 is introduced in the large group of InGaZnO4. The crystal states in Figures 39(B), 39(C), and 39(D) respectively show the intermediate process of structure optimization when CO2 is introduced at the position shown in Figure 39(A) in the large group of InGaZnO4. Here, Figure 39(D) is closest to the most optimal structure, followed by Figure 39(C) and then Figure 39(B) in order of approaching the most optimal structure. . Figures 39(B), 39(C), and 39(D) show the crystal states, respectively, of the intermediate process of structure optimization when CO2 is introduced at the position shown in Figure 39(A) in the large group of InGaZnO4. O4. The crystal states in Figures 39(B), 39(C), and 39(D) respectively show the intermediate process of structure optimization when CO2 is introduced at the position shown in Figure 39(A) in the large group of InGaZnO4. Here, Figure 39(D) is closest to the most optimal structure, followed by Figure 39(C) and then Figure 39(B) in order of approaching the most optimal structure. Here, Figure 39(D) is closest to the most optimal structure, followed by Figure 39(C) and then Figure 39(B) in order of approaching the most optimal structure. (C), and Figure 39(B) in order of approaching the most optimal structure.

[0172] In Figure 39(B), CO2 is substituted for a part of the large group of InGaZnO4. After that, as shown in Figure 39(C), the interlayer of InGaZnO4 expands near CO2, and then, as shown in Figure 39(D), CO2 separates and the interlayer of InGaZnO4 further expands. After that, as shown in Figure 39(C), the interlayer of InGaZnO4 expands near CO2, and then, as shown in Figure 39(D), CO2 separates and the interlayer of InGaZnO4 further expands. , and then, as shown in Figure 39(D), CO2 separates and the interlayer of InGaZnO4 further expands. It has expanded.

[0173] That is, it can be seen that when CO2 is present in the In-Ga-Zn-O-based material, it becomes difficult to maintain the crystal structure. It can be seen.

[0174] The crystalline state of an oxide semiconductor film used for a transistor applicable to a semiconductor device according to an aspect of the present invention will be described below.

[0175] In evaluating the crystalline state, X-ray diffraction (XRD) analysis of the oxide semiconductor film was performed. For the XRD analysis, an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used and measured by the Out-of-Plane method.

[0176] Samples A and B were prepared as samples for which XRD analysis was performed. The manufacturing methods of Samples A and B will be described below.

[0177] First, a dehydrogenated quartz substrate was prepared.

[0178] Next, an In-Sn-Zn-O film was formed on the quartz substrate to a thickness of 100 nm.

[0179] The In-Sn-Zn-O film was formed using a sputtering apparatus with a power of 100 W (DC) in an oxygen gas atmosphere. The target used was an In-Sn-Zn-O target with In:Sn:Zn = 1:1:1 [atomic ratio]. Note that the substrate heating temperature during film formation was room temperature (without heating) or 200 °C. The sample thus manufactured was designated as Sample A.

[0180] Next, heat treatment was performed on the sample manufactured in the same manner as Sample A at a temperature of 650 °C. The heat treatment was first performed for 1 hour in a nitrogen gas atmosphere, and then further heat treatment was performed for 1 hour in an oxygen gas atmosphere without lowering the temperature. The sample thus manufactured was designated as Sample B.

[0181] ​​​​​​​Figure 28 shows the XRD results of Sample A and Sample B. In Sample A, no peak derived from crystals was observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg - 38 deg.

[0182] That is, it can be seen that an oxide semiconductor film having crystallinity can be obtained by performing heat treatment on the sample at a temperature of 650°C.

[0183] There is no major limitation on the substrate 100, but it should at least have heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 100. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, etc. can also be applied, and it is preferable to use those with semiconductor elements provided thereon as the substrate 100.

[0184] In addition, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, there is also a method in which a transistor is fabricated on a non-flexible substrate and then the transistor is peeled off and transferred to the flexible substrate 100 which is the substrate. In that case, it is advisable to provide a release layer between the non-flexible substrate and the transistor.

[0185] The underlying insulating film 102 is made of one of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium oxide. ​​​​​Select the above and it may be used in a single layer or a laminate.

[0186] The base insulating film 102 preferably has sufficient flatness. Specifically, the average surface roughness (R a) is 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less, and a film serving as a base is provided. By setting Ra to be equal to or less than the above numerical values, crystal regions are more likely to be formed in the oxide semiconductor film 10 6. Note that Ra is the center line average roughness defined in JIS B0601 extended three-dimensionally so that it can be applied to a surface, and can be expressed as "the value obtained by averaging the absolute values of the deviations from the reference surface to the specified surface", and is defined by Equation 1. 6. Note that Ra is the center line average roughness defined in JIS B0601 extended three-dimensionally so that it can be applied to a surface, and can be expressed as "the value obtained by averaging the absolute values of the deviations from the reference surface to the specified surface", and is defined by Equation 1. from the reference surface to the specified surface", and is defined by Equation 1. from the reference surface to the specified surface", and is defined by Equation 1.

[0187]

Equation

[0188] In Equation 1, S0 refers to the area of the measurement surface (the rectangular area represented by the four points of the coordinates (x1, y1) (x1, y2) (x2, y 1) (x2, y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Micros cope). cope).

[0189] Oxynitride silicon indicates a substance having a higher oxygen content than nitrogen in its composition. For example, oxygen is 50 atomic % or more and 70 atomic % or less, nitrogen is 0.5 atomic % or more and 15 atomic % or less , silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0 atomic % or more and 10 atomic % or less. Nitrided oxide silicon indicates a substance having a higher nitrogen content than oxygen in its composition. For example, oxygen is 5 atomic % or more and 30 atomic % or less, nitrogen is 20 atomic % or more and 45 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0 atomic % or more and 10 atomic % or less. , silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0 atomic % or more and 10 atomic % or less. Nitrided oxide silicon indicates a substance having a higher nitrogen content than oxygen in its composition. For example, oxygen is 5 atomic % or more and 30 atomic % or less, nitrogen is 20 atomic % or more and 45 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0 atomic % or more and 10 atomic % or less. It refers to those containing from more than atomic % to 55 atomic %, silicon from 25 atomic % to 35 atomic %, and hydrogen from 10 atomic % to 25 atomic % inclusive. However, the above ranges are those when measured using the Rutherford Backscattering Spectroscopy (RBS) and the Hydrogen Forward Scattering Spectroscopy (HFS). rometry). Also, the composition of the constituent elements takes a value such that the total does not exceed 100 atomic %. Moreover, it is preferable to use an insulating film that releases oxygen by heat treatment for the underlying insulating film 102.

[0190] "Releasing oxygen by heat treatment" means that in TDS analysis, the amount of oxygen released, converted to oxygen atoms, is 1.0×10

[0191] atoms / cm or more, or 3.0×10 18 atoms / cm 3 or more. 20 atoms / cm 3 Here, the method for measuring the amount of oxygen released used in TDS analysis will be described below.

[0192] The total amount of gas released during TDS analysis is proportional to the integral value of the ionic strength of the released gas.

[0193] Thus, the total amount of gas released can be calculated by comparing this integral value with a standard sample. For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the insulating film, the amount of oxygen molecules released from the insulating film (N

[0194] ) can be obtained by Equation 2. Here, all of the gas detected with a mass number of 32 obtained from the TDS analysis is oxygen. and the TDS analysis results of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) can be obtained by Equation 2. Here, all of the gas detected with a mass number of 32 obtained from the TDS analysis is oxygen. Moreover, all of the gas detected with a mass number of 32 obtained from the TDS analysis is oxygen. It is assumed to be derived from elemental molecules. Although there is also CH3OH with a mass number of 32, it is considered unlikely to exist here and is not considered here. Also, regarding oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely small. Moreover, for oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18, which are isotopes of oxygen atoms, they are not considered because their abundance ratios in nature are extremely small.

[0195]

Number

[0196] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S H2 is the integrated value of the ionic strength when the standard sample is analyzed by TDS. Here, the reference value of the standard sample is set as N H2 / S H2 . S O2 is the integrated value of the ionic strength when the insulating film is analyzed by TDS . α is a coefficient that affects the ionic strength in TDS analysis. Regarding the details of Equation 2 , refer to Japanese Patent Application Laid-Open No. 6-275697. The oxygen release amount of the above insulating film was measured using a temperature programmed desorption analyzer EMD-WA1000S / W manufactured by Electron Science Co., Ltd., with a silicon wafer containing 1×10 1×10 16 atoms / cm 3 of hydrogen atoms as the standard sample.

[0197] Also, in TDS analysis, a part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above α includes the ionization rate of oxygen molecules, by evaluating the release amount of oxygen molecules, the release amount of oxygen atoms can also be estimated. Moreover, since the above α includes the ionization rate of oxygen molecules, by evaluating the release amount of oxygen molecules, the release amount of oxygen atoms can also be estimated.

[0198] Note that N​​​​O2 is the amount of oxygen molecules released. When converted to oxygen atoms, the amount released is twice the amount of oxygen molecules released.

[0199] In the above configuration, the film that releases oxygen by heat treatment may be silicon oxide (S iO X (X>2)). Silicon oxide with excess oxygen (SiO X (X>2)) means that it contains more oxygen atoms per unit volume than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

[0200] By supplying oxygen from the underlying insulating film 102 to the oxide semiconductor film 106, the interface state density between the oxide semiconductor film 106 and the underlying insulating film 102 can be reduced. As a result, carriers are captured at the interface between the oxide semiconductor film 106 and the underlying insulating film 102 due to operations such as the operation of the transistor, etc., can be suppressed, and a highly reliable transistor can be obtained.

[0201] Furthermore, charges may be generated due to oxygen deficiency in the oxide semiconductor film 106. Generally, part of the oxygen deficiency in the oxide semiconductor film 106 becomes a donor and releases electrons that are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, oxygen is sufficiently supplied from the underlying insulating film 102 to the oxide semiconductor film 106, and preferably, the oxide semiconductor film 106 contains an excessive amount of oxygen, so that the oxygen deficiency in the oxide semiconductor film 106, which is a factor causing the threshold voltage to shift in the negative direction, can be reduced.

[0202] The excess oxygen is mainly the oxygen present in the interstices of the oxide semiconductor film 106, and the oxygen concentration is 1 ×10 16 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less. By setting the oxygen concentration present in the interstices of the oxide semiconductor film 106 within the aforementioned range, no strain or the like occurs, and the crystal region does not collapse, which is preferable.

[0203] The pair of electrodes 116 is selected from one or more of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T a and W, their nitrides, oxides, and alloys, and may be used either as a single layer or as a stacked layer. Alternatively, an oxide or oxynitride containing at least In and Zn may be used instead. For example, an In-Ga-Zn-O-N-based material or the like may be used.

[0204] The gate insulating film 112 may be formed by the same method and the same materials as the underlying insulating film 102 should be.

[0205] The gate electrode 104 may be formed by the same method and the same materials as the pair of electrodes 116 should be.

[0206] Next, the structure of the transistor shown in FIG. 4 will be described. FIG. 4(A) is a top view of the transistor. The cross-sectional view corresponding to the dashed-dotted line A-B shown in FIG. 4(A) is FIG. 4(B).

[0207] The transistor shown in FIG. 4(B) includes an underlying insulating film 102 provided on a substrate 100, a pair of electrodes 216 provided on the underlying insulating film 102, and an oxide semiconductor film 2 provided on the pair of electrodes 216 and in contact with at least a part of the pair of electrodes 216 and the underlying insulating film 102 and the underlying insulating film 102. 06 and a gate insulating film provided to cover a pair of electrodes 216 and an oxide semiconductor film 206 212, and a gate electrode 204 provided to overlap the oxide semiconductor film 206 with the gate insulating film 212 therebetween. It has.

[0208] Note that the pair of electrodes 216, the oxide semiconductor film 206, the gate insulating film 212, and the gate electrode 204 may be provided using the same method and the same materials as the pair of electrodes 116, the oxide semiconductor film 106, the gate insulating film 112, and the gate electrode 104, respectively.

[0209] Next, the structure of the transistor shown in FIG. 5 will be described. FIG. 5(A) is a top view of the transistor. FIG. 5(B) is a cross-sectional view corresponding to the dashed line A-B shown in FIG. 5(A). The transistor shown in FIG. 5(B) has a gate electrode 304 provided on a substrate 100, a gate insulating film 312 provided to cover the gate electrode 304, an oxide semiconductor film 306 provided to overlap the gate electrode 304 with the gate insulating film 312 therebetween, and a pair of electrodes 316 provided on the oxide semiconductor film 306 and in contact with at least a part of the oxide semiconductor film 306. Note that it is preferable to provide a protective insulating film 318 to cover the oxide semiconductor film 306 and the pair of electrodes 316.

[0210] The transistor shown in FIG. 5(B) has a gate electrode 304 provided on a substrate 100, a gate insulating film 312 provided to cover the gate electrode 304, an oxide semiconductor film 306 provided to overlap the gate electrode 304 with the gate insulating film 312 therebetween, and a pair of electrodes 316 provided on the oxide semiconductor film 306 and in contact with at least a part of the oxide semiconductor film 306. The transistor shown in FIG. 5(B) has a gate electrode 304 provided on a substrate 100, a gate insulating film 312 provided to cover the gate electrode 304, an oxide semiconductor film 306 provided to overlap the gate electrode 304 with the gate insulating film 312 therebetween, and a pair of electrodes 316 provided on the oxide semiconductor film 306 and in contact with at least a part of the oxide semiconductor film 306. The transistor shown in FIG. 5(B) has a gate electrode 304 provided on a substrate 100, a gate insulating film 312 provided to cover the gate electrode 304, an oxide semiconductor film 306 provided to overlap the gate electrode 304 with the gate insulating film 312 therebetween, and a pair of electrodes 316 provided on the oxide semiconductor film 306 and in contact with at least a part of the oxide semiconductor film 306. The transistor shown in FIG. 5(B) has a gate electrode 304 provided on a substrate 100, a gate insulating film 312 provided to cover the gate electrode 304, an oxide semiconductor film 306 provided to overlap the gate electrode 304 with the gate insulating film 312 therebetween, and a pair of electrodes 316 provided on the oxide semiconductor film 306 and in contact with at least a part of the oxide semiconductor film 306. Note that it is preferable to provide a protective insulating film 318 to cover the oxide semiconductor film 306 and the pair of electrodes 316. Note that the pair of electrodes 316, the oxide semiconductor film 306, the gate insulating film 312, and the gate electrode

[0211] Note that the pair of electrodes 316, the oxide semiconductor film 306, the gate insulating film 312, and the gate electrode 304 may be provided using the same method and the same materials as the pair of electrodes 116, the oxide semiconductor film 106, the gate insulating film 112, and the gate electrode 104, respectively.

[0212] Also, the protective insulating film 318 may be provided using the same method and the same materials as the base insulating film 102. That's all.

[0213] Next, the structure of the transistor shown in FIG. 6 will be described. FIG. 6(A) is a top view of the transistor. The cross-sectional view corresponding to the dashed line A-B shown in FIG. 6(A) is FIG. 6(B).

[0214] The transistor shown in FIG. 6(B) has a gate electrode 304 provided on a substrate 100, a gate insulating film 312 provided to cover the gate electrode 304, a pair of electrodes 416 provided on the gate insulating film 312, and an oxide semiconductor film 406 that is on the pair of electrodes 416 and is provided in contact with at least a part of the pair of electrodes 416 and the gate insulating film 312. In addition, it is preferable to provide a protective insulating film 418 to cover the pair of electrodes 416 and the oxide semiconductor film 406. Note that the pair of electrodes 416, the oxide semiconductor film 406, and the protective insulating film 418 may be provided using the same method and the same materials as the pair of electrodes 116, the oxide semiconductor film 106, and the protective insulating film 318, respectively. That's all.

[0215]

[0216] Compared with the transistors shown in FIGS. 3 to 6, the transistors shown in FIGS. 7 and 8 have a slightly more complicated process, but have a small parasitic capacitance and are less likely to cause a short-channel effect. Therefore, it is a structure suitable for a fine transistor that requires excellent electrical characteristics.

[0217] Next, the structure of the transistor shown in FIG. 7 will be described. FIG. 7(A) is a top view of the transistor. The cross-sectional view corresponding to the dashed line A-B shown in FIG. 7(A) is FIG. 7(B).

[0218] The transistor shown in Fig. 7(B) includes a base insulating film 502 provided on a substrate 100, and a protective film 520 provided around the base insulating film 502, and an oxide semiconductor film 506 including a high-resistance region 506a and a low-resistance region 506b provided on the base insulating film 502 and the protective film 520, a gate insulating film 512 provided on the oxide semiconductor film 506, a gate electrode 504 provided so as to overlap the oxide semiconductor film 506 with the gate insulating film 512 interposed therebetween, a sidewall insulating film 524 provided in contact with a side surface of the gate electrode 504, and a pair of electrodes 516 provided on the oxide semiconductor film 506 and in contact with at least a part of the oxide semiconductor film 506. It is preferable to provide a protective insulating film 518 so as to cover the gate electrode 504, the sidewall insulating film 524, and the pair

[0219] of electrodes 516. Further, it is preferable to provide a wiring 522 in contact with the pair of electrodes 516 through an opening provided in the protective insulating film 518. Note that the pair of electrodes 516, the gate insulating film 512, the protective insulating

[0220] film 518, and the gate electrode 504 may be provided using the same method and the same materials as those of the pair of electrodes 116, the gate insulating film 112, the protective insulating film 318, and the gate electrode 104, respectively. Further, the oxide semiconductor film 506 may be provided by using the gate electrode 504 as a mask, adding an impurity having a function of reducing the resistance value of the oxide When compared with the case of addition using the ion doping method, the incorporation of hydrogen into the oxide semiconductor film is less, which is preferable. However, the ion doping method is not excluded. That is, it is not something that excludes the ion doping method.

[0221] Note that the oxide semiconductor film 506 may be provided by using the gate electrode 504 and the sidewall insulating film 524 as masks, adding an impurity having a function of reducing the resistance value of the oxide semiconductor film through the gate insulating film 512, and forming a high-resistance region 506a and a low-resistance region 506b. In that case, the region overlapping with the sidewall insulating film 524 becomes the high-resistance region 506a instead of the low-resistance region 506b (see Fig. 7(C)).

[0222] Note that by adding an impurity through the gate insulating film 512, damage caused during the addition of the impurity to the oxide semiconductor film 506 can be reduced. However, the impurity may be implanted without using the gate insulating film 512.

[0223] Also, the underlying insulating film 502 may be formed by processing an insulating film provided in the same manner and using the same materials as the underlying insulating film 102 to provide a groove portion.

[0224] Also, the protective film 520 may be formed by depositing an insulating film so as to fill the groove portion provided in the underlying insulating film 502, and then performing a chemical mechanical polishing (CMP) treatment.

[0225] The protective film 520 selects one or more of silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium oxide, and uses them in a single layer or a laminate. That's all that is required.

[0226] The protective film 520 preferably has the property of not permeating oxygen even when heat-treated for, for example, one hour in the temperature range of 250°C or higher and 450°C or lower, more preferably 150°C or higher and 800°C or lower. Preferably, it has the property of not permeating oxygen even when heat-treated for, for example, one hour in the temperature range. That's preferable.

[0227] Due to the above properties, when the protective film 520 is provided around the underlying insulating film 502, it is possible to reliably suppress the oxygen released from the underlying insulating film 502 by heat treatment from diffusing outward from the transistor. In this way, since oxygen is retained in the underlying insulating film 502, it is possible to prevent a decrease in the field-effect mobility of the transistor, reduce variations in the threshold voltage, and improve the reliability. and improve the reliability. and improve the reliability. and improve the reliability.

[0228] However, a structure without the protective film 520 can also be adopted.

[0229] The sidewall insulating film 524 is formed by providing an insulating film covering the gate electrode 504 and then etching the insulating film. Anisotropic etching is used for the etching. The sidewall insulating film 524 can be formed self-alignedly by performing an anisotropic etching process on the insulating film. For example, it is preferable to use the dry etching method. Examples of the etching gas used in the dry etching method include gases containing fluorine such as trifluoromethane, octafluorocyclobutane, and tetrafluoromethane. A rare gas or hydrogen may be added to the etching gas. It is preferable to use the reactive ion etching method (RIE method) in which a high-frequency voltage is applied to the substrate. Anisotropic etching is used for the etching. The sidewall insulating film 524 can be formed self-alignedly by performing an anisotropic etching process on the insulating film. Anisotropic etching is used for the etching. The sidewall insulating film 524 can be formed self-alignedly by performing an anisotropic etching process on the insulating film. This can be achieved. For example, it is preferable to use the dry etching method. Examples of the etching gas used in the dry etching method include gases containing fluorine such as trifluoromethane, octafluorocyclobutane, and tetrafluoromethane. Examples of the etching gas used in the dry etching method include gases containing fluorine such as trifluoromethane, octafluorocyclobutane, and tetrafluoromethane. A rare gas or hydrogen may be added to the etching gas. The dry etching method preferably uses the reactive ion etching method (RIE method) in which a high-frequency voltage is applied to the substrate. This can be achieved. For example, it is preferable to use the dry etching method.

[0230] Also, the wiring 522 may be provided using the same method and the same material as the gate electrode 104. Good.

[0231] Next, the structure of the transistor shown in FIG. 8 will be described. FIG. 8(A) is a top view of the transistor. FIG. 8(B) is a cross-sectional view corresponding to the dashed line A - B shown in FIG. 8(A). The cross-sectional view corresponding to the dashed line A - B shown in FIG. 8(A) is FIG. 8(B).

[0232] The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. The transistor shown in FIG. 8(B) includes a base insulating film 602 provided on a substrate 100, a pair of electrodes 616 provided in the groove portion of the base insulating film 602, an oxide semiconductor film 606 having a high-resistance region 606a and a low-resistance region 606b provided on the base insulating film 602 and the pair of electrodes 616, a gate insulating film 612 provided on the oxide semiconductor film 606, and a gate electrode 604 provided so as to overlap the oxide semiconductor film 606 with the gate insulating film 612 interposed therebetween. Note that it is preferable to provide a protective insulating film 618 so as to cover the gate insulating film 612 and the gate electrode 604. Also, it is preferable to provide a wiring 622 in contact with the pair of electrodes 616 through openings provided in the protective insulating film 618, the gate insulating film 612, and the oxide semiconductor film 606. Good.

[0233] Note that the gate insulating film 612, the protective insulating film 618, the oxide semiconductor film 606, the wiring 622, and the gate electrode 604 may be provided using the same method and the same material as the gate insulating film 112, the protective insulating film 318, the oxide semiconductor film 506, the wiring 522, and the gate electrode 104, respectively. Note that the gate insulating film 612, the protective insulating film 618, the oxide semiconductor film 606, the wiring 622, and the gate electrode 604 may be provided using the same method and the same material as the gate insulating film 112, the protective insulating film 318, the oxide semiconductor film 506, the wiring 522, and the gate electrode 104, respectively. Note that the gate insulating film 612, the protective insulating film 618, the oxide semiconductor film 606, the wiring 622, and the gate electrode 604 may be provided using the same method and the same material as the gate insulating film 112, the protective insulating film 318, the oxide semiconductor film 506, the wiring 522, and the gate electrode 104, respectively. Good.

[0234] Also, the base insulating film 602 may be formed by processing an insulating film provided using the same method and the same material as the base insulating film 102 to provide a groove portion. Also, the base insulating film 602 may be formed by processing an insulating film provided using the same method and the same material as the base insulating film 102 to provide a groove portion.

[0235] Also, a pair of electrodes 616 may be formed by forming a conductive film so as to fill a groove provided in the base insulating film 602, and then performing a CMP process.

[0236] The field-effect mobility of the transistor will be described below with reference to FIGS. 18 to 21.

[0237] Not limited to oxide semiconductors, the field-effect mobility of a transistor is measured lower than the field-effect mobility that should be originally obtained for various reasons. Factors that reduce the field-effect mobility include defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Here, the field-effect mobility when it is assumed that there are no defects inside the semiconductor is theoretically derived using the Levinson model. Using the Levinson model, the field-effect mobility is theoretically derived assuming that there are no defects inside the semiconductor.

[0238] Let the original field-effect mobility of the transistor be μ0, and the field-effect mobility μ measured when it is assumed that there is some potential barrier (such as a grain boundary) in the semiconductor is expressed by Equation 3.

[0239]

Equation

[0240] Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In the Levinson model, it is assumed that the height E of the potential barrier is derived from defects and is expressed by Equation 4.

[0241]

Equation

[0242] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the semiconductor's​​​​​​​​ The permittivity, n is the carrier density per unit area of the channel, C ox is the gate insulation film capacitance per unit area, V gs is the gate voltage, and t is the thickness of the channel. Note that if the thickness is 30 nm or less of the semiconductor layer, the thickness of the channel may be the same as the thickness of the semiconductor layer.

[0243] The drain current I in the linear region ds is expressed by Equation 5.

[0244]

Equation

[0245] Here, L is the channel length and W is the channel width. Here, L and W are assumed to be 10 μm . Also, V ds is the drain voltage.

[0246] Taking the logarithm of both sides of Equation 5 gives Equation 6.

[0247]

Equation

[0248] Since the right side of Equation 6 is a function of V gs , the defect density N is obtained from the slope of the straight line of the graph obtained by plotting the measured values with the vertical axis being ln(I ds / V gs ) and the horizontal axis being 1 / V gs . That is, the defect density N in the semiconductor is obtained from the V -I gs characteristics of the transistor. ds The defect density N in the semiconductor depends on the substrate temperature during the film formation of the semiconductor. As the semiconductor, In, S

[0249] ​The ratio of In and Zn is In:Sn:Zn = 1:1:1 [atomic ratio] for In-Sn-Zn - When an oxide semiconductor formed using an -O target is used, the defect density N is 1×10 12 / cm 2 or so.

[0250] Based on the defect density N in the above-described oxide semiconductor, when calculated using Equation 3 and Equation 4 , the intrinsic field-effect mobility μ0 of the transistor is 120 cm 2 / Vs. Therefore, For an ideal transistor without defects in the oxide semiconductor and at the interface between the oxide semiconductor and the gate insulating film in contact therewith, the field-effect mobility μ0 is 120 cm 2 / Vs. However, in an oxide semiconductor with many defects, the field-effect mobility μ of the transistor is about 30 cm / Vs 2 . .

[0251] Also, even if there are no defects inside the semiconductor, the transport characteristics of the transistor are affected by interface scattering between the channel and the gate insulating film. The field-effect mobility μ1 at a location x away from the gate insulating film interface is represented by Equation 7. The electric field at a location x away from the gate insulating film interface The field-effect mobility μ1 is represented by Equation 7.

[0252]

Equation

[0253] Here, D is the electric field strength by the gate electrode, B is a constant, and l is the depth at which the influence of interface scattering occurs . B and l can be obtained from the actual measurement of the electrical characteristics of the transistor. From the actual measurement of the electrical characteristics of the transistor using the above oxide semiconductor, B = 4.75×10 7 cm / s, l = 10 nm can be obtained. When D increases, that is, when V gsWhen it increases, since the second term of Equation 7 increases, it can be seen that the field-effect mobility μ1 decreases. The result of calculating the field-effect mobility μ2 of an ideal transistor without defects in the oxide semiconductor and at the interface between the oxide semiconductor and the gate insulating film in contact therewith is shown in FIG. 18. For the calculation, Sentaurus Device manufactured by Synopsys was used, and the bandgap of the oxide semiconductor was set to 2.8 eV, the electron affinity was set to 4.7 eV, the relative permittivity was set to 15, and the thickness was set to 15 nm.

[0254] Furthermore, the work function of the gate was set to 5.5 eV, and the work functions of the source and drain were set to 4.6 eV. Also, the thickness of the gate insulating film was 100 nm, and the relative permittivity was 4.1. Also, both the channel length and the channel width were 10 μm, and V was 0.1 V. Using Sentaurus Device manufactured by Synopsys, the bandgap of the oxide semiconductor was 2.8 eV, the electron affinity was 4.7 eV, the relative permittivity was 15, and the thickness was 15 nm. Furthermore, the work function of the gate was 5.5 eV, and the work functions of the source and drain were 4.6 eV. Also, the thickness of the gate insulating film was 100 nm, and the relative permittivity was 4.1. Also, both the channel length and the channel width were 10 μm, and V was 0.1 V. As shown in FIG. 18, when V is near 1 V, the field-effect mobility μ2 has a peak of 100 cm ds / Vs or more, but when V

[0255] becomes even higher, the influence of interface scattering increases, and it can be seen that the field-effect mobility μ2 decreases. gs is near 1 V, the field-effect mobility μ2 has a peak of 100 cm 2 / Vs or more, but when V becomes even higher, the influence of interface scattering increases, and it can be seen that the field-effect mobility μ2 decreases. gs becomes even higher, the influence of interface scattering increases, and it can be seen that the field-effect mobility μ2 decreases. The result of the calculation for the case where such an ideal transistor is miniaturized is shown in FIGS. 19 to

[0256] FIG. 21. Note that for the calculation, a transistor having the structure shown in FIG. 7 is assumed. The result of the calculation for the case where such an ideal transistor is miniaturized is shown in FIGS. 19 to

[0257] Here, the resistivity of the low-resistance region 506b is 2×10 -3 Ωcm, the width of the gate electrode 504 is 3 3 nm, the width of the sidewall insulating film 524 is 5 nm, and the channel width is 40 nm. Note that the channel region is described by the name of the high-resistance region 506a for convenience, but here the channel region is It is assumed to be a genuine semiconductor.

[0258] Sentaurus Device manufactured by Synopsys was used for the calculation. Figure 19 shows the I (solid line) and the field-effect mobility μ (dotted line) ds of the transistor with the structure shown in Figure 7 (B) with respect to V gs . Note that I ds is calculated with V ds set to 1V, and the field-effect mobility μ is calculated with V ds set to 0.1V. Here, when the thickness of the gate insulating film is 15nm, it is shown in Figure 1 9(A), when it is 10nm, it is shown in Figure 19(B), and when it is 5nm, it is shown in Figure 19(C) respectively.

[0259] From Figure 19, the thinner the gate insulating film, the lower the drain current I gs in the off state (here, the range from V of -3V to 0V is meant).). On the other hand, there is no significant change in the peak ds value of the field-effect mobility μ or the drain current I in the on state (here, the range from V gs of 0V to 3V is meant). From Figure 19, it can be seen that when V ds is near 1V, I gs exceeds 10 μA, which is required for memories and other semiconductor devices. ds It can be seen that it exceeds 10 μA, which is required for memories and other semiconductor devices.

[0260] Similarly, calculations are being performed for the transistor shown in Figure 7(C). The transistor shown in Figure 7(C) differs from the transistor shown in Figure 7(B) in that it has an oxide semiconductor film 507 having a high-resistance region 507a and a low-resistance region 507b. Specifically, , the transistor shown in Figure 7(C) has an oxide semiconductor film 5 superimposed on the sidewall insulating film 524 ​The region of 07 is included in the high-resistance region 507a. That is, the transistor has an offset region with a width of the sidewall insulating film 524 and is a transistor having an offset region with a width of the sidewall insulating film 524. Note that the width of the offset region is also referred to as the offset length (Loff) (see Fig. 7(A)). For convenience, Loff is assumed to have the same width on the left and right. (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience. (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience.

[0261] In the transistor shown in Fig. 7(C), when Loff is 5 nm, the V-dependencies of the drain current I d s (solid line) and the field-effect mobility μ (dotted line) are shown in Fig. 20. Note that I gs is calculated with V d s set to 1 V, and the field-effect mobility μ is calculated with V ds set to 0.1 V. Here, the case where the thickness of the gate insulating film is 15 nm is shown in Fig. 20(A), the case where it is 10 nm is shown in Fig. 20(B), and the case where it is 5 nm is shown in Fig. 20(C), respectively. ds (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience. Here, the case where the thickness of the gate insulating film is 15 nm is shown in Fig. 20(A), the case where it is 10 nm is shown in Fig. 20(B), and the case where it is 5 nm is shown in Fig. 20(C), respectively. (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience.

[0262] Also, Fig. 21 shows the V-dependencies of the drain current I (solid line) and the field-effect mobility μ (dotted line) of the transistor shown in Fig. 7(C) with Loff set to 15 nm ds (solid line) and the field-effect mobility μ (dotted line) of the transistor shown in Fig. 7(C) with Loff set to 15 nm gs (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience. . Note that I ds is calculated with V ds set to 1 V, and the field-effect mobility μ is calculated with V ds set to 0.1 V (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience. (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience. (Refer to Fig. 7(A).). Note that Loff is assumed to have the same width on the left and right for convenience.

[0263] From the calculation results shown in Figs. 20 and 21, similar to Fig. 19, in both cases, the thinner the gate insulating film , the more off-state (here, Vgs refers to the range from -3V to 0V.) The drain current I decreases. On the other hand, the peak value of the field-effect mobility μ and the drain current I in the on state (here, V ds refers to the range from 0V to 3V.) show no significant change. gs is It can be seen that there is no significant change in the drain current I ds in the range from 0V to 3V. .

[0264] Note that the peak of the field-effect mobility μ is about 80 cm 2 / Vs in Fig. 19, but about 60 cm / Vs in Fig. 20 2 and about 40 cm 2 / Vs in Fig. 21. It can be seen that Loff decreases as it increases. Also, I in the off state shows a similar trend. ds It can also be seen that I in the on state decreases as the offset length Loff increases, but it is much gentler compared to the decrease in I in the off state. Also, from any of the calculation results, it can be seen that when V ds is near 1V, I exceeds 10 μA required for memory and the like. ds in the off state. gs is near 1V, I ds exceeds 10 μA required for memory and the like.

[0265] Next, the electrical characteristics of the transistor using the oxide semiconductor will be described.

[0266] Fig. 22 is a top view and a cross-sectional view showing the structure of the fabricated transistors (Sample 1 and Sample 2). Fig. 22(A) is a top view of the transistor. Also, Fig. 22(B) is a cross-sectional view corresponding to the dashed line A - B in Fig. 22( A). The transistor shown in Fig. 22(B) includes a base insulating film 702 provided on a substrate 700, an oxide semiconductor film 706 provided on the base insulating film 702, and an oxide semiconductor film 706 in contact with

[0267] the base insulating film 702, and an oxide semiconductor film 706 in contact with the base insulating film 702, and an oxide semiconductor film 706 in contact with A pair of electrodes 716, an oxide semiconductor film 706, and a gate insulating film 712 provided on the pair of electrodes 716, and a gate electrode 704 provided to overlap the oxide semiconductor film 706 with the gate insulating film 712 interposed therebetween. A layer insulating film 718 covering the gate insulating film 712 and the gate electrode 704, a wiring 722 connected to the pair of electrodes 716

[0268] through an opening provided in the layer insulating film 718, and a protection insulating film 728 covering the layer insulating film 718 and the wiring 722 are provided. As the substrate 700, a glass substrate is used. As the base insulating film 702, a silicon oxide film is used. As the oxide semiconductor film 706, an In-Sn-Zn-O film is used. As the pair of electrodes 716, a tungsten film is used. As the gate insulating

[0269] film 712, a silicon oxide film is used. As the gate electrode 704, a laminated structure of a tantalum nitride film and a tungsten film is used. As the layer insulating film 718, a laminated structure of

[0270] a silicon oxynitride film and a polyimide film is used. As the wiring 722, a laminated structure in which a titanium film, an aluminum

[0271] film, and a titanium film are formed in this order is used. As the The treatment was carried out using a sputtering device, with a bias power of 200 W (RF) applied to the substrate 700 side. The mixture was added and left for 3 minutes.

[0272] Next, while maintaining the vacuum state, a silicon oxide film, which is the base insulating film 702, is formed to a thickness of 300 nm. The film was deposited to a thickness of 100 nm.

[0273] The silicon oxide film was formed by sputtering in an oxygen gas atmosphere at a power of 1500 W (R The film was formed as follows: F) The target was a quartz target. The temperature was set to 100°C.

[0274] Next, the surface of the base insulating film 702 was subjected to CMP processing and flattened to approximately Ra=0.2 nm.

[0275] Next, an In-Sn-Zn-O film, which is an oxide semiconductor film, was formed to a thickness of 15 nm.

[0276] The In-Sn-Zn-O film was formed using a sputtering device with a volume ratio of argon:oxygen=2:3. The film was deposited in a mixed atmosphere of In:Sn The In-Sn-Zn-O target with an atomic ratio of 1:1:1 was used. The substrate heating temperature during deposition was set to 200°C.

[0277] Next, only sample 2 was subjected to a heat treatment at a temperature of 650°C. The heat treatment was first performed in a nitrogen gas atmosphere. The sample was then heated for 1 hour in an oxygen gas atmosphere while maintaining the temperature. Heat treatment was carried out.

[0278] Next, the oxide semiconductor film is processed by a photolithography process to form an oxide semiconductor film 70. 6 was formed.

[0279] Next, a tungsten film was formed to a thickness of 50 nm.

[0280] The tungsten film was formed using a sputtering apparatus with a power of 1000 W (DC) in an argon gas atmosphere. The substrate heating temperature during film formation was 200°C.

[0281] Next, the tungsten film was processed by a photolithography process to form a pair of electrodes 716. formed.

[0282] Next, a silicon oxide film serving as the gate insulating film 712 was formed to a thickness of 100 nm. Note that the relative permittivity of the silicon oxide film was 3.8.

[0283] The silicon oxide film serving as the gate insulating film 712 was formed in the same manner as the underlying insulating film 702.

[0284] Next, a tantalum nitride film and a tungsten film were formed in this order to thicknesses of 15 nm and 13 5 nm, respectively.

[0285] The tantalum nitride film was formed using a sputtering apparatus with a power of 1000 W (DC) in a mixed atmosphere of argon:nitrogen = 5:1. Note that substrate heating was not performed during film formation.

[0286] The tungsten film was formed using a sputtering apparatus with a power of 4000 W (DC) in an argon gas atmosphere. The substrate heating temperature during film formation was 200°C.

[0287] Next, the tantalum nitride film and the tungsten film were processed by a photolithography process to form the gate electrode 704.

[0288] Next, a silicon oxynitride film serving as the interlayer insulating film 718 was formed to a thickness of 300 nm.​​

[0289] The silicon oxynitride film that becomes the interlayer insulating film 718 was formed using a PCVD apparatus with a mixed atmosphere of monosilane: nitrogen nitrite = 1:200 and a power of 35 W (RF). During film formation, the substrate heating temperature was 325°C.

[0290] Next, the silicon oxynitride film that becomes the interlayer insulating film 718 was processed by a photolithography process.

[0291] Next, a photosensitive polyimide that becomes the interlayer insulating film 718 was formed to a thickness of 1500 nm.

[0292] Next, the photosensitive polyimide that becomes the interlayer insulating film 718 was exposed using the photomask used in the photolithography process of the silicon oxynitride film that becomes the interlayer insulating film 718, and then developed. Next, heat treatment was performed to cure the photosensitive polyimide film, and together with the silicon oxynitride film, the interlayer insulating film 718 was formed. The heat treatment was performed at a temperature of 300°C in a nitrogen gas atmosphere.

[0293] Next, a titanium film, an aluminum film, and a titanium film were formed in this order to thicknesses of 50 nm, 10 0 nm, and 5 nm, respectively.

[0294] Both layers of the titanium film were formed using a sputtering apparatus with a power of 100 0 W (DC) in an argon gas atmosphere. Substrate heating was not performed during film formation.

[0295] The aluminum film was formed using a sputtering apparatus with a power of 1000 W (DC) in an argon gas atmosphere. Substrate heating was not performed during film formation.

[0296] Next, the titanium film, aluminum film, and titanium film were processed by a photolithography process to form wiring 722.

[0297] Next, a photosensitive polyimide film, which is the protective insulating film 728, was formed to a thickness of 1500 nm.

[0298] Next, the photosensitive polyimide was exposed using the photomask used in the photolithography process of the wiring 722, and then developed to form an opening in the protective insulating film 728 that exposes the wiring 722. formed.

[0299] Next, heat treatment was performed to cure the photosensitive polyimide film. The heat treatment was performed in the same manner as the heat treatment for the photosensitive polyimide film used in the interlayer insulating film 718.

[0300] Through the above steps, a transistor having the structure shown in FIG. 22(B) was fabricated.

[0301] Next, the electrical characteristics of the transistor having the structure shown in FIG. 22(B) were evaluated.

[0302] In the transistor having the structure shown in FIG. 22(B), the V gs -I ds characteristics were measured, and the results of Sample 1 are shown in FIG. 23(A), and the results of Sample 2 are shown in FIG. 23(B). The transistors used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, Lov of 3 μm on one side (total 6 μm), and dW of 3 μm on one side (total 6 μm). Also, V was set to 10 V. ds and used.

[0303] Also, when comparing Sample 1 and Sample 2, it can be seen that the field-effect mobility of the transistor increases by performing heat treatment after forming the oxide semiconductor film. The inventors believe that this is due to the heat treatment and It was considered that this was because the impurity concentration in the oxide semiconductor film was reduced. Therefore, by performing a heat treatment after forming the oxide semiconductor film, the impurity concentration in the oxide semiconductor film was reduced, and as a result, it was found that the field-effect mobility of the transistor could be brought closer to the ideal field-effect mobility. Thus, it can be seen that by performing a heat treatment after forming the oxide semiconductor film, the impurity concentration in the oxide semiconductor film is reduced, and as a result, the field-effect mobility of the transistor is increased.

[0304] Next, a BT test was performed on Sample 1 and Sample 2. The BT test will be described below.

[0305]

[0306] First, the substrate temperature was set to 25°C, V ds was set to 10V, and the V gs -I ds characteristics of the transistor were measured. Note that V ds represents the drain voltage (the potential difference between the drain and the source). Next, the substrate temperature was set to 150°C, and V ds was set to 0.1V. Next, 20V was applied to V so that the electric field strength applied to the gate insulating film became 2 MV / cm, and it was held for 1 hour as it was. gs Next, V gs was set to 0V. Next, the substrate temperature was set to 25°C, and V ds was set to 10V, and the V -I gs ds characteristics of the transistor were measured. This is called the positive BT test.

[0307] Similarly, first, the substrate temperature was set to 25°C, and V ds was set to 10V, and the V gs -I d s characteristics of the transistor were measured. Next, the substrate temperature was set to 150°C, and V dswas set to 0.1V. Next, , V was adjusted so that the electric field strength applied to the gate insulating film became -2MV / cm gs and -20V was applied and held for 1 hour. Next, V gs was set to 0V. Next, with the substrate temperature at 25°C and, V ds was set to 10V, and the V gs -I ds measurement of the transistor was performed. This is called the minus BT test.

[0308] The results of the plus BT test of Sample 1 are shown in Fig. 24(A), and the results of the minus BT test are shown in Fig. 24(B ). Also, the results of the plus BT test of Sample 2 are shown in Fig. 25(A), and the results of the minus BT test are shown in Fig. 25(B). In the figures, arrows are attached to clearly show the variation of the V gs -I ds characteristics before and after the BT test. For clarity.

[0309] The variations in the threshold voltage due to the plus BT test and the minus BT test of Sample 1 were 1.80V and -0.42V, respectively. Also, the variations in the threshold voltage due to the plus BT test and the minus BT test of Sample 2 were 0.79V and 0.76V, respectively. It can be seen that Samples 1 and 2 have small variations in the threshold voltage before and after the BT test and are highly reliable

[0310] transistors. Next, in the transistor of Sample 2, the relationship between the substrate temperature and the electrical characteristics was evaluated.

[0311] The transistors used for the measurement had a channel length L of 3μm, a channel width W of 10μm, Lov

[0312] of 3μm on one side (total 6μm), and dW of 0μm. Note that V ds ​was set to 10V. Incidentally, , the substrate temperature was set at -40°C, -25°C, 25°C, 75°C, 125°C, and 150°C.

[0313] Fig. 26(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 26(B) shows the relationship between the substrate temperature and the field-effect mobility. is shown.

[0314] From Fig. 26(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. Incidentally, the range was -40°C (0.38V) to 150°C (-1.08V).

[0315] Also, from Fig. 26(B), it can be seen that the higher the substrate temperature, the lower the field-effect mobility. Incidentally, the range was -40°C (37.4 cm 2 / Vs) to 150°C (33.4 cm 2 / Vs ).

[0316] Thus, it can be seen that Sample 2 has little variation in electrical characteristics within the above temperature range. .

[0317] It can be seen that the transistor shown above has a high field-effect mobility and high reliability.

[0318] Similarly, the off-current per 1 μm of channel width of a transistor applicable to a semiconductor device according to an aspect of the present invention was evaluated.

[0319] Samples were fabricated in the same manner as Sample 2. Incidentally, the transistors used for measurement had L = 3 μm , W = 10 cm, Lov = 2 μm, and dW = 0 μm.

[0320] Fig. 27 shows the relationship between the off-current of the transistor and the reciprocal of the substrate temperature (absolute temperature) during measurement. Here, for simplicity, the value obtained by multiplying the reciprocal of the substrate temperature by 1000 during measurement (1000 / The horizontal axis is (T).

[0321] The method for measuring the off-current of a transistor will be briefly described below. For convenience, the transistor to be measured is called the first transistor.

[0322] The drain of the first transistor is connected to the floating gate FG, and the floating gate FG is connected to the gate of the second transistor.

[0323] First, the first transistor is turned off, and then a charge is applied to the floating gate FG Note that a constant drain voltage is applied to the second transistor.

[0324] At this time, the charge on the floating gate FG gradually leaks through the first transistor When the charge on the floating gate FG leaks out, the source potential of the second transistor changes Based on the change amount of this source potential with respect to time, the amount of charge leaking from the first transistor can be estimated, and the off-current can be measured

[0325] From FIG. 27, for the fabricated transistor, when the substrate temperature during measurement is 85°C, the off-current per channel width of 1 μm was 2×10 -21 A / μm (2 zA / μm).

[0326] Thus, it can be seen that the off-current of the fabricated transistor is extremely small.

[0327] As described above, by using an oxide semiconductor film with few impurities, a transistor with high reliability can be obtained

[0328] Also, a transistor with excellent electrical characteristics can be obtained. ​​

[0329] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is.

[0330] (Embodiment 2) In this embodiment, a liquid crystal display device manufactured using the transistor shown in Embodiment 1 will be described. Note that, in this embodiment, an example in which a transistor according to one aspect of the present invention is applied to a liquid crystal display device will be described, but the present invention is not limited thereto. For example, it is easily conceivable by those skilled in the art that a transistor according to one aspect of the present invention can be applied to an EL (Electroluminescence) display device. FIG. 9 shows a circuit diagram of a liquid crystal display device of an active matrix driving method. The liquid crystal display device includes source lines SL_1 to SL_a, gate lines GL_1 to GL_b, and a plurality of pixels 2200. The pixel 2200 includes a transistor 2230, a capacitor

[0331] 2220, and a liquid crystal element 2210. By arranging such pixels 2200 in a matrix, the pixel portion of the liquid crystal display device is configured. Note that, when simply referring to a source line or a gate line, it is described as a source line SL or a gate line GL. As the transistor 2230, the transistor shown in Embodiment 1 can be used. By using the transistor according to one aspect of the present invention, a display device with high display quality and high reliability can be obtained.

[0332]

[0333] The gate line GL is connected to the gate of the transistor 2230, and the source line SL is connected to the source of the transistor 2 Connect to the source of 230, and the drain of the transistor 2230 connects to one capacitive electrode of the capacitor 2220 and one pixel electrode of the liquid crystal element 2210. The other capacitive electrode of the capacitor 2220 and the other pixel electrode of the liquid crystal element 2210 are connected to the common electrode. Also, the common electrode may be provided in the same layer and made of the same material as the gate line GL. Also, the gate line GL is connected to the gate driving circuit. The gate driving circuit may include the transistors shown in Embodiment 1. The other capacitive electrode of the capacitor 2220 and the other pixel electrode of the liquid crystal element 2210 are connected to the common electrode. Also, the common electrode may be provided in the same layer and made of the same material as the gate line GL. Also, the gate line GL is connected to the gate driving circuit. The gate driving circuit may include the transistors shown in Embodiment 1.

[0334] Also, the source line SL is connected to the source driving circuit. The source driving circuit may include the transistors shown in Embodiment 1. Also, the source line SL is connected to the source driving circuit. The source driving circuit may include the transistors shown in Embodiment 1.

[0335] In addition, either or both of the gate driving circuit and the source driving circuit may be formed on a separately prepared substrate and connected using methods such as COG (Chip On Glass), wire bonding, or TAB (Tape Automated Bonding). In addition, either or both of the gate driving circuit and the source driving circuit may be formed on a separately prepared substrate and connected using methods such as COG (Chip On Glass), wire bonding, or TAB (Tape Automated Bonding).

[0336] Also, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element. Also, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element. When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, the charge supplied from the source line SL becomes the drain current of the transistor 2230 and the charge is accumulated in the capacitor 2220. After charging for one row, the transistors 2230 in that row become off and the voltage is no longer applied from the source line SL, but the capacitor 2220 Also, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element.

[0337] Also, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element. When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, the charge supplied from the source line SL becomes the drain current of the transistor 2230 and the charge is accumulated in the capacitor 2220. After charging for one row, the transistors 2230 in that row become off and the voltage is no longer applied from the source line SL, but the capacitor 2220

[0338] When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, the charge supplied from the source line SL becomes the drain current of the transistor 2230 and the charge is accumulated in the capacitor 2220. After charging for one row, the transistors 2230 in that row become off and the voltage is no longer applied from the source line SL, but the capacitor 2220 When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, the charge supplied from the source line SL becomes the drain current of the transistor 2230 and the charge is accumulated in the capacitor 2220. After charging for one row, the transistors 2230 in that row become off and the voltage is no longer applied from the source line SL, but the capacitor 2220 When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, the charge supplied from the source line SL becomes the drain current of the transistor 2230 and the charge is accumulated in the capacitor 2220. After charging for one row, the transistors 2230 in that row become off and the voltage is no longer applied from the source line SL, but the capacitor 2220 When a potential is applied to the gate line GL so that it is equal to or higher than the threshold voltage of the transistor 2230, the charge supplied from the source line SL becomes the drain current of the transistor 2230 and the charge is accumulated in the capacitor 2220. After charging for one row, the transistors 2230 in that row become off and the voltage is no longer applied from the source line SL, but the capacitor 2220 The required voltage can be maintained by the stored charge. Then, it proceeds to charge the capacitor 2220 in the next line. In this way, the capacitors in lines 1 to b are charged. Since the transistor 2230 has a low off - current, the charge held in the capacitor 2220 is difficult to leak, and it is possible to reduce the capacitance of the capacitor 2220.

[0339] As a result, the power consumption required for charging can be reduced.

[0340] As described above, by using the transistor according to one aspect of the present invention, a liquid crystal display device with low power consumption, high display quality, and high reliability can be obtained.

[0341] This embodiment can be used in appropriate combination with other embodiments.

[0342] (Embodiment 3) In this embodiment, an example of manufacturing a memory, which is a semiconductor device, using the transistor shown in Embodiment 1 will be described.

[0343] Typical examples of volatile memories include DRAM (Dynamic Random Access Memory) that stores information by selecting transistors constituting memory elements and accumulating charges in capacitors, and SRAM (Static Random Access Memory) that holds stored contents using circuits such as flip - flops.

[0344] The transistor shown in Embodiment 1 can be applied to some of the transistors included in the memory.

[0345] ​​​​​​​​For example, a memory cell constituting a semiconductor device to which the transistor shown in Embodiment 1 is applied will be described with reference to FIG. 10 by taking an example thereof.

[0346] FIG. 10(A) shows a cross-sectional view of the memory cell. The transistor 3340 includes a base insulating film 3102 provided on a substrate 3100, a protective film 312 0 provided around the base insulating film 3102, an oxide semiconductor film 3106 having a high-resistance region 3106a and a low-resistance region 3106b provided on the base insulating film 3102 and the protective film 3120, a gate insulating film 3112 provided on the oxide semiconductor film 3106, a gate electrode 3104 provided so as to overlap with the oxide semiconductor film 3106 with the gate insulating film 3112 interposed therebetween, a sidewall insulating film 3124 in contact with a side surface of the gate electrode 3104, and a pair of electrodes 311 6 that are in contact with at least the oxide semiconductor film 3106. Here, the substrate 3100, the base insulating film 3102, the protective film 3120, the oxide semiconductor film 3106 the gate insulating film 3112, the gate electrode 3104, the sidewall insulating film 3124, and the pair of electrodes 3 116 may be provided using the same method and the same materials as the substrate 100, the base insulating film 502, the protective film 520, the oxide semiconductor film 50

[0347] 6, the gate insulating film 512, the gate electrode 504, the sidewall insulating film 524, and the pair of electrodes 516 respectively.

[0348] Further, the transistor 3340 includes an interlayer insulating film 3 328 provided to cover the transistor 3340, and an electrode 3326 provided on the interlayer insulating film 3328. One of the pair of electrodes 3116, the interlayer insulating film 3328, and the electrode 3326 form a capacitor It constitutes 3330. Although a parallel-plate capacitor is shown in the figure, a stacked or trench capacitor may be used to increase the capacitance. The interlayer insulating film 3328 may be provided using the same method and the same materials as the protective insulating film 518. Also, the electrode 3326 may be provided using the same method and the same materials as the pair of electrodes 516.

[0349] Furthermore, the transistor 3340 is provided covering the interlayer insulating film 3328 and the electrode 3326 with the interlayer insulating film 3118, and the wiring 3122 that connects to the other of the pair of electrodes 3116 through the openings provided in the interlayer insulating film 3118 and the interlayer insulating film 3328. Note that, although not shown, a protective film covering the interlayer insulating film 3118 and the wiring 3122 may be provided. By providing the protective film, the minute leakage current caused by surface conduction of the interlayer insulating film 3118 can be reduced, and the off-current of the transistor can be reduced. The wiring 3122 may be provided using the same method and the same materials as the wiring 522.

[0350] Figure 10(B) is a circuit diagram of the memory cell shown in Figure 10(A). The memory cell has a transistor Tr and a capacitor C connected to one of the source and drain of the transistor Tr. Note that the side of the capacitor C not connected to one of the source and drain of the transistor Tr is grounded. Also, the gate of the transistor Tr is connected to the word line WL, and one of the source or drain of the transistor Tr is connected to the bit line BL. Also, the bit line BL is connected to the sense amplifier SAmp. Note that the transistor Tr corresponds to the transistor 3340, and the capacitor C corresponds to the capacitor 3330. ​

[0351] The time change of the potential held in the capacitor C gradually decreases due to the off-current of the transistor Tr as shown in Fig. 1 0(C). It is known that it gradually decreases. The potential initially charged from V0 to V1 decreases to VA, which is the limit point for reading data1, as time passes . This period is defined as the holding period T_1. That is, in the case of a binary DRAM, it is necessary to perform a refresh operation during the holding period T_1 .

[0352] Here, by applying the transistor 3340 to the transistor Tr, the off-current of the transistor Tr can be made extremely small, so the holding period T_1 can be lengthened . That is, since it becomes possible to increase the interval between refresh operations, the power consumption of the memory cell can be reduced. Also, since the reliability of the transistor Tr is high, a memory cell with high reliability can be obtained .

[0353] For example, when a memory cell is configured with a transistor having an off-current of 1×10 -18 A or less, 1×10 -21 A or less, preferably 1×10 -24 A or less, the interval between refresh operations can be set to several tens of seconds to several decades .

[0354] As described above, by applying the transistor according to one aspect of the present invention, a semiconductor device with high reliability and low power consumption can be obtained .

[0355] Next, an example different from Fig. 10 of the memory cell constituting the semiconductor device to which the transistor shown in Embodiment 1 is applied will be described with reference to Fig. 11 .

[0356] ​​​FIG. 11(A) shows a cross-sectional view of a memory cell. Transistor 3350 is on a substrate 3100 and has a base insulating film 3382 provided thereon, and a semiconductor film 3384 having a first resistance region 3384a, a second resistance region 3384b, and a third resistance region 3384c provided on the base insulating film 3382 , a gate insulating film 3386 provided on the semiconductor film 3384, and a gate electrode 3392 provided so as to overlap with the first resistance region 3384a via the gate insulating film 3386 , and a sidewall insulating film 3394 in contact with a side surface of the gate electrode 3392. In the semiconductor film 3384 , the resistance decreases in the order of the first resistance region 3384a, the second resistance region 3384b, and the third resistance region 3384c. Note that the first resistance region 3384a forms a channel when a voltage equal to or higher than the threshold voltage of the transistor 3350 is applied to the gate electrode 3392 . Although not shown, a pair of electrodes in contact with the third resistance region 3384c may be provided . As the transistor 3350, a transistor using a semiconductor film other than an oxide semiconductor film, for example, a semiconductor film containing a Group 14 element such as a polycrystalline silicon film, a single crystal silicon film, a polycrystalline germanium film, or a single crystal germanium film may be used, or a transistor using the oxide semiconductor film shown in Embodiment 1 may be used .

[0357]

[0358] Also, an interlayer insulating film 3396 is provided in contact with the transistor 3350. Note that since the interlayer insulating film 3396 is also the formation surface of the transistor 3340, the surface of the interlayer insulating film 3396 is made as flat as possible . Specifically, it is preferable that the surface of the interlayer insulating film 3396 has an Ra of 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less .

[0359] ​​​​​​​ The interlayer insulating film 3396 may be provided in a single-layer or laminated structure, and it is preferable that the film in contact with the oxide semiconductor film 3106 is an insulating film that releases oxygen by heat treatment.

[0360] A transistor 3340 is provided on the interlayer insulating film 3396. One of the pair of electrodes 3116 of the transistor 3340 is connected to the gate electrode 3392 of the transistor 3350. Also, a capacitor 3330 is formed by one of the pair of electrodes 3116 of the transistor 3340, the interlayer insulating film 3328, and the electrode 3326. Although a parallel-plate capacitor is shown in the figure, a stacked or trench capacitor may be used to increase the capacitance.

[0361] Figure 11(B) is a circuit diagram of the memory cell shown in Figure 11(A). The memory cell includes a transistor Tr_1, a transistor Tr_2, a capacitor C, and a floating gate FG connected to the drain of the transistor Tr_1 and the gate of the transistor Tr_2. The gate of the transistor Tr_1 is connected to the gate line GL_1, the source of the transistor Tr_1 is connected to the source line SL_1, the source of the transistor Tr_2 is connected to the source line SL_2, and the drain of the transistor Tr_2 is connected to the drain line DL_2. Also, the side of the capacitor C that is not connected to the floating gate FG is connected to the capacitance line CL. Note that the transistor Tr_1 corresponds to the transistor 3340, the transistor Tr_2 corresponds to the transistor 3350, and the capacitor C corresponds to the capacitor 3330.

[0362] Note that the memory cell shown in this embodiment utilizes the fact that the threshold value of transistor Tr_2 varies according to the potential of the floating gate FG. For example, FIG. 11( C) is a diagram for explaining the relationship between the potential V of the capacitance wiring CL and the drain current I CL flowing through transistor Tr_2 ds _2.

[0363] Here, the floating gate FG can adjust its potential via transistor Tr_1. For example, assume the potential of the source line SL_1 is VDD. At this time, by setting the potential of the gate line GL_1 to be equal to or higher than the potential obtained by adding VDD to the threshold voltage Vth of transistor Tr_1, the potential of the floating gate FG can be set to HIGH. Also, by setting the potential of the gate line GL_1 to be equal to or lower than the threshold voltage Vth of transistor Tr_1, the potential of the floating gate FG can be set to LOW. Therefore, either the V -I _2 curve shown with FG = LOW or the

[0364] V CL -I ds _2 curve shown with FG = HIGH can be obtained. That is, when FG = LOW, since I V CL -I ds _2 is small at V CL = 0V, it represents data 0. Also, when FG = HIGH, ds since I V CL -I ds _2 is large at V = 0V, it represents data 1. In this way, data can be stored.

[0365] Here, by applying transistor 3340 to transistor Tr_1, the transistor Since the off-current of transistor Tr_1 can be made extremely small, the charge accumulated in the floating gate FG shown in Fig. 11(B) can be prevented from leaking unintentionally through transistor Tr_1. Therefore, data can be retained over a long period. Also, since the field-effect mobility of transistor Tr_1 is high, the memory cell can be operated at high speed. The charge accumulated in the floating gate FG is prevented from leaking unintentionally through transistor Tr_1. Therefore, data can be retained over a long period. Also, since the field-effect mobility of transistor Tr_1 is high, the memory cell can be operated at high speed. The charge accumulated in the floating gate FG is prevented from leaking unintentionally through transistor Tr_1. Therefore, data can be retained over a long period. Also, since the field-effect mobility of transistor Tr_1 is high, the memory cell can be operated at high speed.

[0366] As described above, by applying the transistor according to one aspect of the present invention, a semiconductor device with high reliability, low power consumption, and capable of high-speed operation can be obtained. As described above, by applying the transistor according to one aspect of the present invention, a semiconductor device with high reliability, low power consumption, and capable of high-speed operation can be obtained.

[0367] This embodiment may be used in combination with other embodiments.

[0368] (Embodiment 4) The transistor shown in Embodiment 1 and the semiconductor device shown in Embodiment 3 can be used at least in part to form a CPU (Central Processing Unit). The transistor shown in Embodiment 1 and the semiconductor device shown in Embodiment 3 can be used at least in part to form a CPU (Central Processing Unit). The transistor shown in Embodiment 1 and the semiconductor device shown in Embodiment 3 can be used at least in part to form a CPU (Central Processing Unit).

[0369] Fig. 12(A) is a block diagram showing a specific configuration of the CPU. The CPU shown in Fig. 12(A) includes an arithmetic circuit (ALU: Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189 on a substrate 1190. The substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. The CPU shown in Fig. 12(A) includes an arithmetic circuit (ALU: Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189 on a substrate 1190. The CPU shown in Fig. 12(A) includes an arithmetic circuit (ALU: Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189 on a substrate 1190. The CPU shown in Fig. 12(A) includes an arithmetic circuit (ALU: Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189 on a substrate 1190. The CPU shown in Fig. 12(A) includes an arithmetic circuit (ALU: Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189 on a substrate 1190. The CPU shown in Fig. 12(A) includes an arithmetic circuit (ALU: Arithmetic Logic Unit) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, a bus interface (Bus I / F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I / F) 1189 on a substrate 1190. The substrate 1190 can be a semiconductor substrate, an SOI substrate, a glass substrate, etc. They exist. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in Fig. 12(A) is only an example with its configuration simplified. An actual CPU has various configurations depending on its application.

[0370] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, and after being decoded, are input to the ALU controller 1192, the inter rupt controller 1194, the register controller 1197, and the timing controller 1195.

[0371] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU program according to their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU. During the execution of the CPU program, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits according to their priorities and mask states. The register controller 1197 generates addresses for the register 1196 and reads from and writes to the register 1196 according to the state of the CPU. The register controller 1197 generates addresses for the register 1196 and performs read and write operations on the register 1196 according to the state of the CPU.

[0372] Also, the timing controller 1195 generates signals for controlling the operation timing of the ALU 1191, the ALU controller 119 2, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 generates internal clock signals based on the reference clock signal CLK1. It includes an internal clock generation unit that generates CLK2, and supplies the clock signal CLK2 to each of the above various circuits.

[0373] In the CPU shown in FIG. 12(A), the semiconductor device of Embodiment 3 is provided in the register 1196 is provided.

[0374] In the CPU shown in FIG. 12(A), the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the semiconductor device included in the register 1 196, it is selected whether to hold data by a phase inversion element or to hold data by a capacitor is selected. When holding data by a phase inversion element is performed, the power supply voltage is supplied to the semiconductor device in the register 1196. When holding data by a capacitor is performed, the data is rewritten to the capacitor, and the supply of the power supply voltage to the semiconductor device in the register 119 6 can be stopped.

[0375] Regarding power supply stop, as shown in FIG. 12(B) or FIG. 12(C), between the semiconductor device group and the nodes to which the power supply potential VDD or the power supply potential VSS is applied, a switching element is provided to perform it. The circuits of FIGS. 12(B) and 12(C) will be described below. is performed.

[0376] In FIGS. 12(B) and 12(C), an example of the configuration of a storage circuit including a transistor with an extremely small off-current shown in Embodiment 1 is shown in the switching element for controlling the supply of the power supply potential to the semiconductor device. is shown.

[0377] The storage device shown in FIG. 12(B) includes a switching element 1141 and a semiconductor device 1142 in multiple It has a semiconductor device group 1143. Specifically, each semiconductor device 114 In 2, the semiconductor device shown in Embodiment 3 can be used. Each semiconductor device 1142 included in the semiconductor device group 1143 is supplied with the high-level power supply potential VDD via the switching element 1141. Further, each semiconductor device 1142 included in the semiconductor device group 1143 is supplied with the potential of the signal IN and the potential of the low-level power supply potential VSS.

[0378] In FIG. 12(B), as the switching element 1141, the transistor shown in Embodiment 1 can be used. The switching of the transistor is controlled by the signal SigA applied to its gate.

[0379] Note that in FIG. 12(B), the switching element 1141 is shown having only one transistor, but it is not limited to this, and it may have a plurality of transistors. When the switching element 1141 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, in series, or in a combination of series and parallel.

[0380] Also, FIG. 12(C) shows an example of a storage device in which the low-level power supply potential VSS is supplied to each semiconductor device 1142 included in the semiconductor device group 1143 via the switching element 1141. The switching element 1141 can control the supply of the low-level power supply potential VSS to each semiconductor device 1142 included in the semiconductor device group 1143.

[0381] ​​​​​​​​​​​​ Between a group of semiconductor devices and nodes supplied with a power supply potential VDD or a power supply potential VSS, a switching element is provided, and it is possible to temporarily stop the operation of the CPU and stop the supply of the power supply voltage, and it is also possible to hold data even in such a case, and power consumption can be reduced. For example, even while a user of a personal computer has stopped inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing the power consumption.

[0382] Also, by using the transistor shown in Embodiment 1 and the semiconductor device shown in Embodiment 3, a CPU capable of high-speed operation with low power consumption can be obtained.

[0383] Here, the CPU has been described as an example, but it can also be applied to LSIs such as DSP (Digital Signal P rocessor), custom LSI, and FPGA (Field Programmabl e Gate Array).

[0384] This embodiment may be used in combination with other embodiments.

[0385] (Embodiment 5) In this embodiment, examples of electronic devices to which Embodiments 1 to 4 can be applied will be described.

[0386] FIG. 13(A) shows a portable information terminal. The portable information terminal includes a housing 4300, buttons 4301, a microphone 4302, a display unit 4303, a speaker 4304, and a camera 430 5, and has functions as a mobile phone.

[0387] ​​Figure 13(B) is a display. The display includes a housing 4310 and a display unit 431 1.

[0388] Figure 13(C) is a digital still camera. The digital still camera includes a housing 4320 a button 4321, a microphone 4322, and a display unit 4323.

[0389] By using the transistor according to one aspect of the present invention, an electronic device with low power consumption and good quality can be obtained.

[0390] This embodiment can be used in appropriate combination with other embodiments.

Example

[0391] In this example, the pressure and leak rate in the film deposition chamber of a sputtering apparatus to which one aspect of the present invention is applied are shown.

[0392] The film deposition chamber has a volume of 1.40 m 3 and a turbo molecular pump and a cryotrap are provided in parallel. A roughing vacuum pump is also provided as an auxiliary pump.

[0393] After the film deposition chamber was opened to the atmosphere, it was evacuated for 6 hours using a turbo molecular pump.

[0394] Next, when the total pressure in the film deposition chamber reached 5×10 -4 Pa, the cryotrap was started. Thereafter, chamber baking was performed at 400°C for 12 hours.

[0395] Next, in the film deposition chamber, dummy film deposition was performed until the film thickness reached 10 μm (until the integrated power reached 50 kWh). Note that the dummy film deposition was performed with a substrate temperature of 250°C and a film deposition pressure of 0.3 Pa. The deposition power was 9kW (AC), and the deposition gas was argon at 50sccm and oxygen at 50 The test was performed for 920 seconds per substrate at a target-substrate distance of 150 mm. - For film formation, In-Ga-Zn-O ternary layer with In:Ga:Zn=1:1:1 [atomic ratio] was used. Get was used.

[0396] In this way, the total pressure in the deposition chamber was 2.16×10 -5 P The partial pressure of the gas with m / z = 2 is 8.63 x 10 -6 Pa, m / z=18 The partial pressure is 8.43 x 10 -6 Pa, the partial pressure of the gas with m / z = 28 is 1.66 × 10 -5 P The partial pressure of a gas with m / z = 40 (such as argon atoms) is 3.87 × 10 -7 Pa and The partial pressure of the gas with m / z=44 is 5.33×10 -6 It was Pa.

[0397] Figure 29 shows the total pressure in the deposition chamber and the partial pressure of each gas. The white circle indicates the total pressure, and the black circle indicates the m / z= The open triangles indicate the partial pressure of the gas at m / z=18, and the black triangles indicate the partial pressure of the gas at m / z=2 The partial pressure of the gas at m / z=8, the white squares are the partial pressure of the gas at m / z=40, and the black squares are the partial pressure of the gas at m / z=4 The partial pressure of the gas is 4. Note that Fig. 29 shows the pressures in the deposition chamber and the vacuum pump exhaust. The relationship between the pressure and the time from when the pressure was stopped is shown. The measurement was performed using a mass meter (also called Q-mass) Qulee CGM-051.

[0398] The leak rate of the entire deposition chamber was estimated to be 9.84×10 - 6 Pa·m 3 / s, m / z = 2 gas is 3.24 × 10 -6 Pa·m 3 / s, m / z = 18, the gas is 4.46 × 10 -9 Pa·m 3 / s, m / z=28 is 7. 74×10 -6 Pa·m 3 / s, m / z = 40 gas is 8.72 × 10 -8 Pa·m 3 / s, m / z = 44 gas is 7.89 × 10 -7 Pa·m 3 / s.

[0399] The leak rate is the ratio of the pressure in the deposition chamber to the time after the vacuum pump has stopped. Specifically, the pressures were calculated from the relationship between the pressure at 1 minute after the vacuum pump was stopped and the pressure at 15 The difference between each pressure at 1000 rpm was divided by the time and multiplied by the volume of the deposition chamber to obtain the leak rate. EXAMPLES

[0400] In this embodiment, the deposition chamber of the sputtering apparatus shown in the first embodiment is further provided with a This is achieved by supplying heated inert gases such as rare gases to remove any impurities present. An example will be shown in which the pressure in the deposition chamber is increased and then the deposition chamber is evacuated again after a certain period of time has elapsed.

[0401] Specifically, argon gas at a temperature of 70° C. was introduced into the deposition chamber so that the pressure was 20 Pa. After supplying for 1 hour, the vacuum pump was evacuated for 10 minutes. Repeated 0 times.

[0402] In this way, the total pressure in the deposition chamber after further removing impurities was 1.34×10 -5 P a, the partial pressure of the gas with m / z = 2 is 7.58 × 10 -6The partial pressure of the gas with Pa and m / z = 18 is 5.79×10 -6 Pa, and the partial pressure of the gas with m / z = 28 is 8.40×10 -6 P a, and the partial pressure of the gas with m / z = 40 is 1×10 -7 Pa or less (below the measurement lower limit) and the partial pressure of the gas with m / z = 44 is 1×10 -7 Pa or less (below the measurement lower limit).

[0403] Figure 37 shows the relationship between the total pressure in the film formation chamber and the time after stopping the vacuum pump exhaust. Note that each pressure was measured using a quadrupole mass spectrometer Qulee CGM-051 manufactured by ULVAC, Inc. Note that a detector M-11 manufactured by ULVAC, Inc. was used as the detector.

[0404] Estimating the leak rate from the total pressure thus obtained, the entire film formation chamber is 6.94×10 -6 Pa·m 3 / s, the gas with m / z = 2 is 3.13×10 -6 Pa·m 3 / s, m / z = 18 is 3.20×10 -9 Pa·m 3 / s, the gas with m / z = 28 is 3.1 2×10 -6 Pa·m 3 / s, the gas with m / z = 40 is 7.27×10 -8 Pa·m 3 / s, the gas with m / z = 44 is 3.20×10 -7 Pa·m 3 / s.

[0405] Note that the leak rate was calculated from the relationship between each pressure in the film formation chamber and the time after stopping the vacuum pump exhaust. Specifically, the total pressure at 1 minute and 15 minutes after stopping the vacuum pump exhaust The value obtained by dividing the difference from the total pressure of the previous day by the time and multiplying by the volume of the film deposition chamber was defined as the leak rate.

[0406] Table 1 shows a comparison of the pressures and leak rates of Example 1 and Example 2.

[0407]

Table 1

[0408] As shown above, by supplying heated argon gas, the pressure in the film deposition chamber was increased, and after a certain period of time, the film deposition chamber was evacuated again. As a result, the impurities present in the film deposition chamber could be further reduced compared to Example 1. As a result, it was found that the release of impurities was reduced and the pressures and leak rates in the film deposition chamber were reduced.

Example

Example

[0409] In this example, TDS analysis, SIMS, and XRD analysis were performed on a sample formed using the film deposition chamber of the sputtering apparatus shown in Example 1.

Example

[0410] The sample was fabricated by forming an In-Ga-Zn-O film with a thickness of 100 nm on a glass substrate.

Example

[0411] The film formation conditions of the In-Ga-Zn-O film are shown below.

[0412] The substrate temperature was 250 °C, the film formation pressure was 0.3 Pa, the film formation power was 9 kW (AC), the film formation gas was 50 sccm of argon and 50 sccm of oxygen, and the target-substrate distance was 150 mm. Also, an In-Ga-Zn -O target with an In:Ga:Zn = 1:1:1 [atomic ratio] was used.

Example

[0413] First, TDS analysis was performed.

[0414] For the TDS analysis, an EMD-WA1000S temperature-programmed desorption analyzer manufactured by Denshi Kagaku Corporation was used. / W.

[0415] The TDS analysis results of the sample are shown in Fig. 32. Here, Fig. 32(A) shows the ion intensity of the gas with m / z = 18, Fig. 32(B) shows the ion intensity of the gas with m / z = 28, and Fig. 32(C) shows the ion intensity of the gas with m / z = 44. In Fig. 32, the solid line represents the ion intensity without heat treatment, and the dotted line represents the ion intensity when heat treatment is performed at 350 °C for 1 hour in a nitrogen gas atmosphere after film formation, followed by heat treatment for 1 hour in an oxidizing atmosphere (80 vol% nitrogen gas and 20 vol% oxygen gas).

[0416] From the obtained ion intensities, it can be seen that for the In-Ga-Zn-O film, the emission amounts of the gas with m / z = 18, the gas with m / z = 28, and the gas with m / z = 44 are reduced by performing heat treatment after film formation.

[0417] Next, SIMS of the sample was performed.

[0418] For the SIMS, an IMS 7fR manufactured by CAMECA was used.

[0419] Fig. 33 shows the depth profile of hydrogen by SIMS.

[0420] Fig. 34 shows the depth profile of carbon by SIMS.

[0421] Fig. 35 shows the depth profile of nitrogen by SIMS.

[0422] In Figs. 33 to 35, the solid line represents the depth profile without heat treatment, and the dotted ​​​​​The wire was heat-treated at a temperature of 450 °C for 1 hour in a nitrogen gas atmosphere after film formation, and then in an oxidative atmosphere (80 vol% nitrogen, 20 vol% oxygen) for 1 hour. The depth profile is shown.

[0423] From the obtained depth profile, it can be seen that the In-Ga-Zn-O film reduces the concentrations of hydrogen, carbon, and nitrogen by performing heat treatment after film formation.

[0424] Next, XRD analysis of the sample was performed.

[0425] For the XRD analysis, an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used and measured by the Out-of-Plane method.

[0426] Fig. 36 shows the XRD results of the In-Ga-Zn-O film.

[0427] In Fig. 36, the solid line shows the XRD results without heat treatment, and the dotted line shows the XRD results when heat treatment was performed at a temperature of 450 °C for 1 hour in a nitrogen gas atmosphere after film formation, and then in an oxidative atmosphere (80 vol% nitrogen, 20 vol% oxygen) for 1 hour.

[0428] In Fig. 36, it can be seen that all samples have a plurality of crystalline peaks. Also, it can be seen that the intensity of the crystalline peaks increases by performing heat treatment after film formation.

[0429] The In-Ga-Zn-O film formed using the film formation chamber of the sputtering apparatus shown in Example 1 is found to have a low impurity concentration and a crystalline region.

Explanation of symbols

[0430] 10 Film formation chamber 10a Film formation chamber 10b Film formation chamber 10c Film formation chamber 11 Substrate supply chamber 12a Load lock chamber 12b Load lock chamber 13 Transfer chamber 14 Cassette port 15 Substrate heating chamber 20a Film formation chamber 20b Film formation chamber 22a Load lock chamber 22b Load lock chamber 25 Substrate heating chamber 32 Target 34 Target holder 42 Substrate holder 44 Substrate heater 46 Shutter shaft 48 Shutter plate 50 RF power supply 52 Matching unit 54 Purifier 55 Mass flow controller 56 Gas supply source 57 Gas heating mechanism 58 Vacuum pump 59 Vacuum pump 68 Counter electrode 100 Substrate 102 Underlying insulating film 104 Gate electrode 106 Oxide semiconductor film 112 Gate insulating film 116 Pair of electrodes 204 Gate electrode 206 Oxide semiconductor film 212 Gate insulating film 216 Pair of electrodes 304 Gate electrode 306 Oxide semiconductor film 312 Gate insulating film 316 Pair of electrodes 318 Protective insulating film 406 Oxide semiconductor film 416 Pair of electrodes 418 Protective insulating film 502 Underlying insulating film 504 Gate electrode 506 Oxide semiconductor film 506a High-resistance region 506b Low-resistance region 507 Oxide semiconductor film 507a High-resistance region 507b Low-resistance region 512 Gate insulating film 516 Pair of electrodes 518 Protective insulating film 520 Protective film 522 Wiring 524 Sidewall insulating film 602 Underlying insulating film 604 Gate electrode 606 Oxide semiconductor film 606a High-resistance region 606b Low-resistance region 612 Gate insulating film 616 Pair of electrodes 618 Protective insulating film 622 Wiring 700 Substrate 702 Underlying insulating film 704 Gate electrode 706 Oxide semiconductor film 712 Gate insulating film 716 Pair of electrodes 718 Interlayer insulating film 722 Wiring 728 Protective insulating film 1141 Switching element 1142 Semiconductor device 1143 Group of semiconductor devices 1189 ROM interface 1190 Substrate 1191 ALU 1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 Pixel 2210 Liquid Crystal Element 2220 Capacitor 2230 Transistor 3100 Substrate 3102 Underlying Insulating Film 3104 Gate Electrode 3106 Oxide Semiconductor Film 3106a High-Resistance Region 3106b Low-Resistance Region 3112 Gate Insulating Film 3116 Pair of Electrodes 3118 Interlayer Insulating Film 3120 Protective Film 3122 Wiring 3124 Sidewall Insulating Film 3326 Electrode 3328 Interlayer Insulating Film 3330 Capacitor 3340 Transistor 3350 Transistor 3382 Underlying Insulating Film 3384 Semiconductor Film 3384a Resistance Region 3384b Resistance Region 3384c Resistance Region 3386 Gate Insulating Film 3392 Gate Electrode 3394 Sidewall Insulating Film 3396 Interlayer Insulating Film 4300 Housing 4301 Button 4302 Microphone 4303 Display Unit 4304 Speaker 4305 Camera 4310 Housing 4311 Display Unit 4320 Housing 4321 Button 4322 Microphone 4323 display unit

Claims

1. having a memory cell, said memory cell having a transistor and a capacitor, one of the source or drain of said transistor being electrically connected to a bit line, the other of the source or drain of said transistor being electrically connected to one electrode of said capacitor, the gate electrode of said transistor being electrically connected to a word line, said transistor having an oxide semiconductor layer having a channel formation region, a first insulating layer on said oxide semiconductor layer, and said gate electrode on said first insulating layer, said oxide semiconductor layer having a crystal oriented such that the c-axis takes a direction perpendicular to the surface of said oxide semiconductor layer, in a cross-sectional view in the channel length direction of said transistor, an end portion of said first insulating layer has a region protruding from said gate electrode and is located on the upper surface of said oxide semiconductor layer, said capacitor having a pair of electrodes and a second insulating layer between said pair of electrodes, one of said pair of electrodes having a region in contact with the upper surface of said oxide semiconductor layer, said second insulating layer having a region in contact with the upper surface of said gate electrode, the other of said pair of electrodes having a region in contact with the upper surface of said second insulating layer, A memory device in which, after a potential is applied to one electrode of said capacitor when said transistor is turned on, the charge applied to said capacitor is retained when said transistor is turned off.

2. having a memory cell, said memory cell having a transistor and a capacitor, one of the source or drain of said transistor being electrically connected to a bit line, The other of the source or drain of the transistor is electrically connected to one electrode of the capacitor. The gate electrode of the transistor is electrically connected to a word line. The transistor has an oxide semiconductor layer having a channel formation region, a first insulating layer on the oxide semiconductor layer, and the gate electrode on the first insulating layer. The oxide semiconductor layer has a crystal oriented such that the c-axis takes a direction perpendicular to the surface of the oxide semiconductor layer. In a cross-sectional view in the channel length direction of the transistor, an end portion of the first insulating layer has a region protruding from the gate electrode and is located on the upper surface of the oxide semiconductor layer. The oxide semiconductor layer has a hydrogen concentration measured by secondary ion mass spectrometry of 5×10 １９ atoms / cm ３ less than The capacitor has a pair of electrodes and a second insulating layer between the pair of electrodes. One of the pair of electrodes has a region in contact with the upper surface of the oxide semiconductor layer. The second insulating layer has a region in contact with the upper surface of the gate electrode. The other of the pair of electrodes has a region in contact with the upper surface of the second insulating layer. A memory device in which, after a potential is applied to one electrode of the capacitor when the transistor is turned on, the charge applied to the capacitor is retained when the transistor is turned off.

3. In claim 1 or claim 2, The oxide semiconductor layer is a memory device that is an oxide semiconductor layer of In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-Ga-O system, In-Ga-Zn-O system, In-Al-Zn-O system, In-Sn-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Hf-Zn-O system, In-La-Zn-O system, In-Ce-Zn-O system, In-Pr-Zn-O system, In-Nd-Zn-O system, In-Sm-Zn-O system, In-Eu-Zn-O system, In-Gd-Zn-O system, In-Tb-Zn-O system, In-Dy-Zn-O system, In-Ho-Zn-O system, In-Er-Zn-O system, In-Tm-Zn-O system, In-Yb-Zn-O system, In-Lu-Zn-O system, In-Sn-Ga-Zn-O system, In-Hf-Ga-Zn-O system, In-Al-Ga-Zn-O system, In-Sn-Al-Zn-O system, In-Sn-Hf-Zn-O system, In-Hf-Al-Zn-O system.

4. In any one of Claims 1 to 3, the oxide semiconductor layer has a carbon concentration measured by secondary ion mass spectrometry of less than 5×10 １９ atoms / cm ３ is a memory device.

5. In any one of Claims 1 to 4, the oxide semiconductor layer has a nitrogen concentration measured by secondary ion mass spectrometry of less than 5×10 １９ atoms / cm ３ is a memory device.

6. In any one of Claims 1 to 5, the off-current of the transistor is 1×10 －１８ A or less, and is a memory device.

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