Circuit module and electronic device

Abstract

To reduce signal transmission loss.SOLUTION: A circuit module 100 includes a slave substrate 101 having a signal line 11 and a master substrate 102 fixed to the slave substrate 101. The signal line 11 has a signal pattern 111, which is a conductor pattern, the signal pattern 111 facing a main surface 1191 of the master substrate 102 and arranged on a main surface 1171 of the slave substrate 101. The master substrate 102 has a conductor plane 15 arranged on the main surface 1191 so as to face the signal pattern 111 with spacing.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to signal transmission technology.

Background Art

[0002] Generally, when performing digital signal communication between two semiconductor elements, a signal line is used as a signal transmission line. The signal line is formed on a substrate such as a printed wiring board, and the two semiconductor elements are mounted on the substrate. In order to suppress signal crosstalk between signal lines, on the substrate, the signal lines are generally adjacent to the ground layer or the power supply layer via an insulating layer. Patent Document 1 discloses a printed wiring board in which a conductor layer on which signal lines are arranged is arranged adjacent to the ground layer or the power supply layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] With the increasing functionality of electronic devices, the signal transmission speed tends to increase. Along with the high speed of signals, the problem of an increasing signal attenuation amount has become prominent. When the signal attenuation amount increases in a signal line, the signal waveform is distorted in the process of the signal wave propagating through the signal line, and there is a risk of malfunction in the semiconductor element on the receiving side of the signal.

[0005] An object of the present invention is to reduce signal transmission loss.

Means for Solving the Problems

[0006] One aspect of the present invention includes a first substrate including a first base material having a first surface, a second substrate including a second base material having a second surface facing the first surface, the second substrate being electrically connected and mechanically fixed to the first substrate, a first semiconductor element and a second semiconductor element mounted on the first substrate on a side of a third surface opposite to the first surface of the first base material, the first substrate having a signal line connecting the first semiconductor element and the second semiconductor element, the signal line including a first conductor pattern disposed in a first conductor layer closer to the first surface than the third surface, and the second substrate having a second conductor pattern disposed in a second conductor layer closer to the second surface than a fourth surface opposite to the second surface of the second base material and facing the first conductor pattern with a gap therebetween. 2 A circuit module characterized by the above.

Advantages of the Invention

[0007] According to the present invention, transmission loss of signals is reduced.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Best Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a digital camera 600 according to an embodiment. The digital camera 600 is an interchangeable-lens digital camera and includes a camera body 601. The camera body 601 is an example of an electronic device. A lens unit (lens barrel) 602 including a lens is detachable from the camera body 601. Note that the lens unit and the camera body may be integrated to form an electronic device.

[0010] The camera body 601 includes a housing 611, a circuit module 100, and a circuit module 200. The circuit module 100 and the circuit module 200 are housed inside the housing 611. Also, a battery (not shown) is housed inside the housing 611. The circuit module 100 and the circuit module 200 are connected by a flexible printed wiring board 300.

[0011] The circuit module 200 is an imaging module in the present embodiment. The circuit module 200 includes a printed wiring board 201 and an image sensor 202 mounted on the printed wiring board 201. The image sensor 202 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 202 has a function of converting light incident through the lens unit 602 into an electrical signal.

[0012] In this embodiment, the circuit module 100 is an image processing module. The circuit module 100 includes a parent substrate 102, a circuit unit 110 mounted on the parent substrate 102, and a power supply unit 130 mounted on the parent substrate 102. The power supply unit 130 is a power supply circuit that supplies the power required for the operation of each part of the circuit unit 110 to the circuit unit 110 by converting the voltage supplied from a battery (not shown) into a predetermined power supply voltage V0 and applying it to the circuit unit 110. The power supply voltage V0 is a DC voltage.

[0013] FIG. 2(a) is a plan view of the circuit module 100 according to the embodiment. FIG. 2(b) is a cross-sectional view of the circuit module 100 according to the embodiment. FIG. 3 is a cross-sectional view of the circuit module 100 taken along line III-III of FIG. 2(b).

[0014] The circuit unit 110 includes a daughter substrate 101, a logic LSI (Large Scale Integration) 103 mounted on the daughter substrate 101, and two memory ICs (Integrated Circuit) 104 mounted on the daughter substrate 101. The logic LSI 103 is an example of a first semiconductor element. The memory IC 104 is an example of a second semiconductor element. Also, the daughter substrate 101 is an example of a first substrate, and the parent substrate 102 is an example of a second substrate. Note that the number of memory ICs 104, that is, the number of second semiconductor elements, is two in this embodiment, but it may be one or three or more.

[0015] The logic LSI 103 is an element that performs image processing. Specifically, the logic LSI 103 has a function of acquiring an electrical signal indicating image data from the image sensor 202, performing a process of correcting the acquired electrical signal, and generating corrected image data. Also, the logic LSI 103 functions as a memory controller that controls the memory IC 104. The memory IC 104 is a memory element capable of storing data such as image data, and can store the data transmitted from the logic LSI 103 under the control of the logic LSI 103.

[0016] The signals that can be communicated between the logic LSI 103 and each memory IC 104 are digital signals such as data signals, address signals, command signals, and clock signals. In this embodiment, the digital signals are single-ended signals. The transmission speed of the digital signals is 200 Mbps or more, preferably 2 Gbps or more, and more preferably 5 Gbps or more. When the transmission speed of the digital signal is 2 Gbps, the fundamental wave frequency of the digital signal is 1 GHz, the third harmonic is 3 GHz, and the fifth harmonic is 5 GHz. Thus, the higher the transmission speed of the digital signal, the higher the frequency of the signal wave components included in the digital signal.

[0017] The logic LSI 103 and each memory IC 104 operate by applying a power supply voltage V0, for example, a DC voltage of 1.1 V, by the power supply unit 130. Note that the power supply unit 130 may be mounted on the daughter board 101 instead of the mother board 102, or may be mounted on a board other than the mother board 102 and the daughter board 101. That is, the power supply unit 130 only needs to be able to supply power to the logic LSI 103 and each memory IC 104, and may be arranged inside the housing 611.

[0018] In this embodiment, by unitizing the logic LSI 103 and the memory IC 104, the development efficiency is improved. Also, the logic LSI 103 and the memory IC 104 are arranged close to each other so as to reduce the transmission loss of the digital signal. Thereby, miniaturization of the circuit unit 110 is also achieved.

[0019] In this embodiment, the daughter board 101 is a rigid board. The base material of the daughter board 101 may be any board such as a semiconductor board such as silicon, a ceramic board, or a glass epoxy board, but from the viewpoints of cost and procurement ease, a glass epoxy board is preferable. The glass epoxy board is a board in which a glass cloth is impregnated with an epoxy resin. In this embodiment, the daughter board 101 is a rigid printed wiring board using an insulating base material as the base material.

[0020] In this embodiment, the parent substrate 102 is a rigid substrate. The base material of the parent substrate 102 may be any substrate such as a semiconductor substrate like silicon, a ceramic substrate, or a glass epoxy substrate, but from the viewpoints of cost and procurement ease, a glass epoxy substrate is preferable. In this embodiment, the parent substrate 102 is a rigid printed wiring board using an insulating base material as the base material.

[0021] The daughter substrate 101 has an insulating base material 117 which is an example of a first insulator portion, and a conductor portion disposed inside or outside the insulating base material 117. The insulating base material 117 has a main surface 1171 which is an example of a first surface, and a main surface 1172 which is an example of a third surface and is opposite to the main surface 1171. The main surface 1171 is the surface facing the parent substrate 102. The logic LSI 103 and each memory IC 104 are mounted on the main surface 1172.

[0022] The parent substrate 102 has an insulating base material 119 which is an example of a second insulator portion, and a conductor portion disposed inside or outside the insulating base material 119. The insulating base material 119 has a main surface 1191 which is an example of a second surface, and a main surface 1192 which is an example of a fourth surface and is opposite to the main surface 1191. The main surface 1191 is the surface facing the circuit unit 110, that is, the daughter substrate 101. The circuit unit 110 is mounted on the main surface 1191. In a plan view, that is, when viewed in the Z direction perpendicular to the main surface 1191, the daughter substrate 101 is smaller in size than the parent substrate 102.

[0023] In this embodiment, the circuit unit 110 is mounted on the parent substrate 102 such that the main surface 1171 and the main surface 1191 face each other. There are no logic LSI 103 and each memory IC 104 between the main surface 1171 and the main surface 1191, and the distance between the main surface 1171 and the main surface 1191 can be narrowed.

[0024] The logic LSI 103 is electrically and mechanically connected to the daughter board 101 by a plurality of connection terminals 106. Specifically, the logic LSI 103 is connected to a plurality of pads arranged on the main surface 1172 of the daughter board 101 by the plurality of connection terminals 106. In this way, the plurality of connection terminals 106 are arranged between the logic LSI 103 and the main surface 1172 and are used to fix the logic LSI 103 to the daughter board 101.

[0025] Also, each memory IC 104 is electrically and mechanically connected to the daughter board 101 by a plurality of connection terminals 107. Specifically, each memory IC 104 is connected to a plurality of pads arranged on the main surface 1172 of the daughter board 101 by the plurality of connection terminals 107. In this way, the plurality of connection terminals 107 are arranged between the corresponding memory IC 104 and the main surface 1172 and are used to fix the corresponding memory IC 104 to the daughter board 101.

[0026] The daughter board 101 is electrically and mechanically connected to the mother board 102 by a plurality of connection terminals 108. Specifically, a plurality of pads arranged on the main surface 1171 of the daughter board 101 and a plurality of pads arranged on the main surface 1191 of the mother board 102 are connected by the plurality of connection terminals 108. In this way, the plurality of connection terminals 108 are arranged between the main surface 1171 and the main surface 1191 and are used to fix the daughter board 101 to the mother board 102. Each of the connection terminals 106, 107, 108 includes a bonding material such as solder.

[0027] The sub-substrate 101 has at least two conductor layers, in this embodiment, two conductor layers 1011 and 1012. The conductor layer 1011 is an example of the first conductor layer. The conductor layer 1012 is an example of the second conductor layer. The conductor layers 1011 and 1012 are layers in which conductive conductor patterns, that is, metal foils are disposed. Each of the conductor layers 1011 and 1012 is a surface layer. That is, the conductor layer 1011 is defined on the main surface 1171, and the conductor layer 1012 is defined on the main surface 1172. That is, the sub-substrate 101 preferably has at least two surface layers, and may have inner layers (conductor layers) in addition to the two surface layers. In this embodiment, the conductor layer 1012 is a conductor layer adjacent to the conductor layer 1011 via an insulating material (dielectric material) of the insulating substrate 117. The conductor layer 1011 is covered with a solder resist film 118 which is a first solder resist film disposed on the main surface 1171 except for the portions connected to the respective connection terminals 108. In the conductor layer 1011, the solder resist film 118 may be disposed on the portion without the conductor pattern.

[0028] The parent substrate 102 may have at least one conductor layer. The parent substrate 102 preferably has two or less conductor layers. In this embodiment, it has two conductor layers 1021 and 1022. The conductor layers 1021 and 1022 are layers in which conductive conductor patterns, that is, metal foils are disposed. Each of the conductor layers 1021 and 1022 is a surface layer. That is, the conductor layer 1021 is defined on the main surface 1191, and the conductor layer 1022 is defined on the main surface 1192. That is, the parent substrate 102 preferably has at least the surface layer on the main surface 1191 side, and may have the surface layer on the main surface 1192 side and / or inner layers (conductor layers) in addition to the surface layer on the main surface 1191 side. The conductor layer 1021 is covered with a solder resist film 120 which is a second solder resist film disposed on the main surface 1191 except for the portions connected to the respective connection terminals 108. In the conductor layer 1021, the solder resist film 120 may be disposed on the portion without the conductor pattern.

[0029] The conductor layer 1022 may be omitted. In this case, the parent substrate 102 is a substrate having only one conductor layer 1021 as at least one conductor layer.

[0030] The sub-substrate 101 has a plurality of signal lines 11 corresponding to each of the two memory ICs 104. For example, the logic LSI 103 and each memory IC 104 are electrically connected by 40 to 50 signal lines 11. Each signal line 11 is formed of a metal such as copper, that is, a conductor.

[0031] The plurality of connection terminals 106 include a power supply terminal 1061, a ground terminal 1062, and a plurality of transmission terminals 1063. In FIG. 2(b), only one power supply terminal 1061 and one ground terminal 1062 are shown, but there may be a plurality of each.

[0032] The plurality of connection terminals 107 include a power supply terminal 1071, a ground terminal 1072, and a plurality of reception terminals 1073. In FIG. 2(b), only one power supply terminal 1071 and one ground terminal 1072 are shown, but there may be a plurality of each.

[0033] A power supply voltage V0 is applied between the power supply terminal 1061 and the ground terminal 1062 via the line L0 of the circuit module 100, that is, the power supply line L1 and the ground line L2, whereby the logic LSI 103 operates. Also, a power supply voltage V0 is applied between the power supply terminal 1071 and the ground terminal 1072 via the line L0, that is, the power supply line L1 and the ground line L2, whereby the memory IC 104 operates. The line L0 is formed of a metal such as copper, that is, a conductor. The line L0 includes a power supply line L1 having a power supply potential V1 and a ground line L2 having a ground potential V2. Here, the potential difference (V1 - V2) between the power supply potential V1 and the ground potential V2 is the power supply voltage V0, which is the operating voltage of the logic LSI 103 and the memory IC 104.

[0034] Each transmission terminal 1063 is a terminal for transmitting a digital signal. Each reception terminal 1073 is a terminal for receiving a digital signal. Each signal line 11 is electrically connected to the corresponding transmission terminal 1063 of the logic LSI 103 and the corresponding reception terminal 1073 of the memory IC 104. Thereby, digital signals can be transmitted between the logic LSI 103 and each memory IC 104 via each signal line 11.

[0035] As shown in Fig. 2(a), a plurality of signal lines 11 corresponding to each memory IC 104 are arranged in parallel with spaces therebetween. From the viewpoint of miniaturization of the circuit unit 110, that is, miniaturization of the circuit module 100, it is preferable that the spaces between the plurality of signal lines 11 are as narrow as possible. At that time, in order to reduce crosstalk between the plurality of signal lines 11, it is preferable that they are close to a reference line with a stable potential and little potential fluctuation, such as the ground line L2 or the power line L1.

[0036] Here, the circuit module of the comparative example will be described. Fig. 8(a) is a cross-sectional view of a circuit module 100X of the comparative example. Fig. 8(b) is a cross-sectional view of the circuit module 100X along line VIIIB-VIIIB shown in Fig. 8(a). The circuit module 100X includes a logic LSI 103X, a memory IC 104X, and a substrate 102X on which the logic LSI 103X and the memory IC 104X are mounted. The substrate 102X is a rigid printed wiring board having three or more conductor layers, for example, a substrate having six conductor layers.

[0037] The logic LSI 103X is connected to the substrate 102X by a plurality of connection terminals 106X, and the memory IC 104X is connected to the substrate 102X by a plurality of connection terminals 107X. The plurality of connection terminals 106X include a transmission terminal 1063X for transmitting a signal, a power supply terminal 1061X, and a ground terminal 1062X. The plurality of connection terminals 107X include a reception terminal 1073X for receiving a signal, a power supply terminal 1071X, and a ground terminal 1072X.

[0038] In the six conductor layers of the substrate 102X, the conductor layers numbered 1 to 6 are defined in order from the surface layer on which the logic LSI 103X and the memory IC 104X are mounted toward the opposite surface layer. The six conductor layers are arranged at intervals in the Z direction through the insulator of the insulating base material 119X. The power supply terminal 1061X of the logic LSI 103X and the power supply terminal 1071X of the memory IC 104X are connected by a conductor pattern L1X arranged in the first conductor layer. The ground terminal 1062X of the logic LSI 103X and the ground terminal 1072X of the memory IC 104X are connected by a wiring including a conductor pattern L2X arranged in the third conductor layer of the substrate 102X. The transmission terminal 1063X of the logic LSI 103X and the reception terminal 1073X of the memory IC 104X are connected by a signal line including a signal pattern 111X arranged in the second conductor layer. Therefore, the signal pattern 111X is arranged sandwiched between the conductor patterns L1X and L2X through the insulator. In addition, various conductor patterns 116X are also arranged in the fourth to sixth conductor layers. A solder resist film 120X is formed on the conductor pattern L1X.

[0039] The insulating base material 119X is made of an insulator (dielectric) having a higher relative permittivity than the relative permittivity of the solder resist film 120X, for example, glass epoxy. The signal pattern 111X is disposed adjacent to the conductor patterns L1X and L2X through the insulating material (dielectric material) of the insulating base material 119X. Thereby, crosstalk of digital signals propagating through the signal pattern 111X is suppressed. Since the signal pattern 111X is disposed to face the conductor patterns L1X and L2X through a dielectric material having a high relative permittivity, as the digital signal speeds up, the dielectric loss due to the dielectric material of the insulating base material 119X increases, and the digital signal is distorted. In particular, the attenuation amounts of harmonic components in the digital signal, for example, the third harmonic component and the fifth harmonic component, increase. And among the third harmonic component and the fifth harmonic component, in particular, the attenuation amount of the fifth harmonic component increases. When the transmission speed of the digital signal becomes 200 Mbps or more, the distortion of the digital signal becomes large, and when the transmission speed of the digital signal becomes 2 Gbps or more, the distortion of the digital signal becomes remarkable. In particular, when the transmission speed of the digital signal becomes 5 Gbps or more, the distortion of the digital signal becomes even more remarkable. Here, for example, when the transmission speed of the digital signal is 2 Gbps, the frequency of the third harmonic is 3 GHz and the frequency of the fifth harmonic is 5 GHz with respect to the fundamental wave frequency 1 GHz of the digital signal. Therefore, the attenuation amount is large in the high frequency band of 3 GHz or more, and particularly large in the high frequency band of 5 GHz or more.

[0040] In the present embodiment, the signal line 11 includes the signal pattern 111 disposed on the main surface 1171, that is, on the conductor layer 1011. The signal pattern 111 is a strip-shaped conductor pattern. The signal line 11 also includes a signal via 112 extending in the Z direction that connects the transmission terminal 1063 and the signal pattern 111, and a signal via 113 extending in the Z direction that connects the reception terminal 1073 and the signal pattern 111. The signal pattern 111 is composed of a conductor pattern, that is, a metal foil such as copper foil. Each of the signal vias 112 and 113 is a via conductor. Note that a conductor pattern 121 is disposed on the conductor layer 1012.

[0041] In addition, the parent substrate 102 has a conductor plane 15 disposed on the main surface 1191, that is, on the conductor layer 1021. The conductor plane 15 is also composed of a metal foil such as a copper foil. The conductor plane 15 is a solid conductor pattern. Note that a conductor pattern 122 is disposed on the conductor layer 1022. The signal pattern 111 and the conductor plane 15 face each other with a space D1 in the Z direction so as not to be short-circuited. The conductor plane 15 is a part of a line L0 used to apply a power supply voltage V0 to the logic LSI 103 and the memory IC 104.

[0042] In this embodiment, the conductor plane 15 is a part of a ground line L2 having a ground potential V2 among the lines L0. Since the signal pattern 111 and the conductor plane 15 are disposed on the main surfaces 1171 and 1191 facing each other, respectively, the signal pattern 111 and the conductor plane 15 are close to each other. That is, the signal pattern 111 and the conductor plane 15 face each other. Therefore, a return current with respect to the signal current flowing through the signal pattern 111 easily flows through the conductor plane 15, and crosstalk between the signal lines 11 is suppressed. Also, even in the signal lines 11 through which high-speed digital signals propagate, stable characteristic impedance can be realized.

[0043] In addition, the dielectric loss is proportional to the relative dielectric constant of the dielectric between the signal line and the ground line (or power supply line). In this embodiment, there is no insulating material (dielectric material) of the insulating substrates 117 and 119 between the signal pattern 111 and the conductor plane 15. Therefore, the dielectric loss due to the insulating substrates 117 and 119 is reduced, and the distortion of the digital signal propagating through the signal line 11, that is, the transmission loss of the digital signal is reduced. In particular, since the attenuation amount of the harmonic component of the digital signal in the high-frequency band is reduced, the transmission loss of the digital signal is reduced.

[0044] The Z-direction interval D1 between the signal pattern 111 and the conductor plane 15 is preferably narrower than the Z-direction interval D2 between the conductor layer 1011 and the conductor layer 1012 adjacent to each other in the daughter substrate 101. Thereby, the electric field coupling between the signal pattern 111 and the conductor plane 15 is strengthened, the dielectric loss is more effectively reduced, the distortion of the digital signal propagating through the signal line 11, that is, the transmission loss of the digital signal is effectively reduced. In addition, the local variation in the characteristic impedance of the signal pattern 111 is reduced, and the characteristic impedance can be stabilized at a desired value, for example, 60 Ω. Also, the mechanical strength of the daughter substrate 101 is increased. Thus, in this embodiment, a characteristic impedance of a desired value can be realized with a two-layer daughter substrate 101, which is effective for cost reduction. Also, for the mother substrate 102, it is possible to realize a characteristic impedance of a desired value with a two-layer substrate or a single-sided substrate.

[0045] Here, between the signal pattern 111 and the conductor plane 15, there are solder resist films 118 and 120 having a relative permittivity lower than that of the insulating base materials 117 and 119. For example, the relative permittivity of the insulating base materials 117 and 119 is 4.3, and the relative permittivity of the solder resist films 118 and 120 is 3.0. Since the relative permittivity of the solder resist films 118 and 120 protecting the signal pattern 111 and the conductor plane 15 respectively is lower than the relative permittivity of the insulating base materials 117 and 119, the dielectric loss is reduced and the transmission loss of the digital signal is reduced.

[0046] Also, it is preferable that there is an air gap D3 between the signal pattern 111 and the conductor plane 15. This is because the relative permittivity of air is lower than the relative permittivity of the insulating base materials 117 and 119 and the relative permittivity of the solder resist films 118 and 120. The relative permittivity of air is 1.0. In this embodiment, the air gap D3 is the Z-direction interval between the solder resist film 118 and the solder resist film 120. The presence of the air gap D3 effectively reduces the dielectric loss and effectively reduces the transmission loss of the digital signal.

[0047] As shown in Fig. 2(a), when viewed in the Z direction, all of the signal patterns 111 of each signal line 11 are located within the region surrounded by the outer shape of the conductor plane 15. Thereby, crosstalk of signals can be effectively suppressed. Also, as shown in Fig. 2(a), when viewed in the Z direction, all of the signal lines 11 are located within the region surrounded by the outer shape of the conductor plane 15. Thereby, crosstalk of signals can be more effectively suppressed.

[0048] Note that although it is preferable that the conductor plane 15 be at the ground potential V2, it is not limited thereto. The potential of the conductor plane 15 may be a potential with little fluctuation as long as it is a potential for determining the amplitude of the digital signal (electrical signal) transmitted by the logic LSI 103, and may be, for example, the power supply potential V1.

[0049] Here, the signal pattern 111 has a conductor surface 1111 facing the conductor plane 15 and a conductor surface 1112 that is on the surface opposite to the conductor surface 1111 and contacts the main surface 1171 of the insulating base material 117. Also, the conductor plane 15 has a conductor surface 151 facing the signal pattern 111 and a conductor surface 152 that is on the surface opposite to the conductor surface 151 and contacts the main surface 1191 of the insulating base material 119. The conductor surface 1111 is an example of a first conductor surface, and the conductor surface 1112 is an example of a second conductor surface. The conductor surface 151 is an example of a third conductor surface, and the conductor surface 152 is an example of a fourth conductor surface.

[0050] In this embodiment, in order to prevent peeling between the insulating base material 117 and the signal pattern 111, that is, to bring the insulating base material 117 and the signal pattern 111 into close contact, the main surface 1171 of the insulating base material 117 and the conductor surface 1112 of the signal pattern 111 are rough surfaces. By making each of the surfaces 1171 and 1112 a rough surface, the insulating base material 117 and the signal pattern 111 are fixed by an anchor effect.

[0051] Similarly, to prevent the peeling between the insulating substrate 119 and the conductor plane 15, that is, to bring the insulating substrate 119 and the conductor plane 15 into close contact, the main surface 1191 of the insulating substrate 119 and the conductor surface 152 of the conductor plane 15 are rough surfaces. By making each of the surfaces 1191 and 152 a rough surface, the insulating substrate 119 and the conductor plane 15 are fixed by the anchor effect.

[0052] With the increase in the speed of digital signals, the signal current tends to concentrate on the surface of the signal pattern 111 due to the skin effect. In particular, among the signal currents, the higher the frequency component, the easier it is to concentrate on the thin portion near the surface of the signal pattern 111. For example, the third harmonic component and the fifth harmonic component flow through a portion closer to the surface than the fundamental wave component, and the fifth harmonic component flows through a portion closer to the surface than the third harmonic component. The higher the transmission speed of the digital signal, that is, the higher the frequency of the fundamental wave of the digital signal, the more prominent the skin effect becomes.

[0053] In this embodiment, since the signal pattern 111 faces the conductor plane 15, the signal current tends to concentrate on the conductor surface 1111 of the signal pattern 111 that faces the conductor plane 15 among the conductor surfaces 1111 and 1112. In this embodiment, the surface roughness of the conductor surface 1111 is smaller than the surface roughness of the conductor surface 1112. Here, since the conductor surface 1112 is in contact with the main surface 1171, the surface roughness of the conductor surface 1112 is the same as the surface roughness of the main surface 1171. That is, the surface roughness of the conductor surface 1111 is smaller than the surface roughness of the main surface 1171. The surface roughness of the conductor surface 1111 is preferably 0.005 μm or more and 0.05 μm or less in terms of the arithmetic mean roughness Ra, and the surface roughness of the conductor surface 1112, that is, the surface roughness of the main surface 1171, is preferably 0.5 μm or more and 5 μm or less. In this way, the signal current tends to concentrate on the smooth conductor surface 1111 rather than the rough conductor surface 1112, so the resistance loss of the signal current becomes smaller and the attenuation amount of the signal current becomes smaller. As a result, the signal current can easily flow through the signal pattern 111, and the transmission loss of the signal is reduced.

[0054] Also, in the conductor plane 15, a return current flows in a direction opposite to the direction in which the signal current flows. In the present embodiment, since the conductor plane 15 faces the signal pattern 111, the return current tends to concentrate on the conductor surface 151 of the conductor plane 15 that faces the signal pattern 111 among the conductor surfaces 151 and 152 of the conductor plane 15. In the present embodiment, the surface roughness of the conductor surface 151 is smaller than the surface roughness of the conductor surface 152. Here, since the conductor surface 152 is in contact with the main surface 1191, the surface roughness of the conductor surface 152 is the same as the surface roughness of the main surface 1191. That is, the surface roughness of the conductor surface 151 is smaller than the surface roughness of the main surface 1191. The surface roughness of the conductor surface 151 is preferably 0.005 μm or more and 0.05 μm or less in terms of the arithmetic mean roughness Ra, and the surface roughness of the conductor surface 152, that is, the surface roughness of the main surface 1191, is preferably 0.5 μm or more and 5 μm or less. In this way, the return current tends to concentrate on the conductor surface 151 having a smooth surface rather than the conductor surface 152 having a rough surface, so that the resistance loss of the return current is reduced and the attenuation amount of the return current is reduced. As a result, the return current easily flows through the conductor plane 15, and as a result, the signal current also flows smoothly, and the signal transmission loss is reduced. Note that the conductor surface 1111 and the conductor surface 151 can be made into smooth surfaces by plating a metal on the surface of the metal foil.

[0055] [Modification Example] In the above embodiment, the case where the air gap D3 exists, that is, D3 > 0, has been described, but the present invention is not limited thereto. For example, as shown in FIG. 4(a), the air gap D3 may be extremely small or the air gap D3 may not exist. In these cases, it is possible to omit only one of the solder resist films 118 and 120.

[0056] Also, if the air gap D3 exists, the solder resist film 120 may be omitted as shown in FIG. 4(b), and the conductor plane 15 may be exposed to air. Also, if the air gap D3 exists, the solder resist film 118 may be omitted as shown in FIG. 5(a), and the signal pattern 111 may be exposed to air. Also, if the air gap D3 exists, both the solder resist films 118 and 120 may be omitted as shown in FIG. 5(b), and the signal pattern 111 and the conductor plane 15 may be exposed to air.

[0057] (Example) Regarding the circuit module 100 of the above embodiment and the circuit module 100X of the above comparative example, the signal transmission characteristics were obtained by computer simulation.

[0058] (Example 1) The circuit module 100 used in Example 1 corresponds to the circuit module 100 of the above embodiment. The material of the conductor was mainly copper. Each of the signal pattern 111 and the conductor plane 15 was a copper foil with a plated surface. The wiring width of the signal pattern 111 was 125 μm. The thickness of each solder resist film 118, 120 was 20 μm. The interval D1 was 20 μm.

[0059] As a suitable method for realizing the interval D1 = 20 μm, after applying paste-like cream solder to either the daughter substrate 101 or the mother substrate 102 by screen printing or the like, the daughter substrate 101 is placed on the mother substrate 102. Then, it can be realized by heating in a reflow furnace to melt the cream solder and then cooling to solidify the molten solder. However, the connection method is not limited to solder bonding. In the case of solder bonding, it is desirable from the viewpoint of mounting reliability that the pitch of the connection terminals 108 is wider than the pitch of the terminals of the logic LSI 103 and the pitch of the terminals of the memory IC 104 on the daughter substrate 101.

[0060] The insulating materials of the insulating substrates 117 and 119 were made into composite materials in which glass fibers were impregnated with an epoxy resin. The relative permittivity of the insulating substrates 117 and 119 was set to 4.3, and the relative permittivity of the solder resist films 118 and 120 was set to 3.0. In the above form, the characteristic impedance of the signal pattern 111 was 60 Ω.

[0061] (Comparative Example 1) The circuit module 100X used in Comparative Example 1 corresponds to the circuit module 100X of the above Comparative Example. The material of the conductor was mainly copper. The insulating substrate 119X was made into a composite material in which glass fibers were impregnated with an epoxy resin. The relative permittivity of the insulating substrate 119X was set to 4.3.

[0062] The thickness of the copper foil such as the signal pattern 111X and the conductor pattern L2X was set to 18 μm. Since the conductor pattern L1X is a layer that touches air, plating is applied to the surface. Therefore, the thickness of the conductor pattern L1X was set to 43 μm, which is thicker than the signal pattern 111X and the conductor pattern L2X. The distance between the signal pattern 111X and the conductor pattern L1X was 200 μm, and the distance between the signal pattern 111X and the conductor pattern L2X was 400 μm. The wiring width of the signal pattern 111X was set to 125 μm. In the above form, the characteristic impedance of the signal pattern 111X was 60 Ω.

[0063] (Simulation Results of Example 1 and Comparative Example 1) FIG. 6 is a graph showing the transmission characteristics of Example 1 and Comparative Example 1. In FIG. 6, the vertical axis represents the transmission characteristics, and the horizontal axis represents the frequency. The wiring length of each of the signal patterns 111 and 111X was set to 100 mm. The graph shown in FIG. 6 is a graph showing the simulation results of the transmission characteristics of each of the signal patterns 111 and 111X at frequencies from 1 MHz to 20 GHz. In FIG. 6, reference numeral 301 represents the transmission characteristics of Example 1, and reference numeral 302 represents the transmission characteristics of Comparative Example 1. As the simulator, HyperLynx of Siemens EDA Japan Co., Ltd. was used.

[0064] The transmission characteristic indicates, by voltage ratio, how much of the sine-wave electrical signal applied to the input terminal of signal pattern 111,111X is transmitted (propagated) to the output terminal. The denominator of the voltage ratio is the voltage at the input terminal, and the numerator of the voltage ratio is the voltage at the output terminal.

[0065] At 5 GHz, the transmission characteristic 302 of Comparative Example 1 was -2.87 dB, and the amplitude of the sine wave was attenuated by about 30%. In contrast, the transmission characteristic 301 of Example 1 was -0.36 dB, and the amplitude of the sine wave was attenuated by about 4%. From the above results, according to the signal pattern 111 of Example 1, the transmission characteristic of the signal wave is greatly improved compared to the signal pattern 111X of Comparative Example 1. That is, in the 2 Gbps signal transmission, in the signal pattern 111X of Comparative Example 1, the signal component of 5 GHz, which is the harmonic five times that of the fundamental wave, is attenuated by about 30%, so there is a risk of transmission failure due to waveform deterioration. In contrast, in the signal pattern 111 of Example 1, since the attenuation of the signal component of 5 GHz, which is the harmonic five times that of the fundamental wave, is about 4%, waveform deterioration is suppressed more than in Comparative Example 1. Therefore, in Example 1, high-speed transmission of digital signals can be realized.

[0066] It is considered that the transmission characteristic 301 as shown in FIG. 6 is due to the small dielectric tangent, that is, the dielectric loss, between the signal pattern 111 and the conductor plane 15 in the structure of the circuit module 100 of Example 1.

[0067] Also, although the signal pattern 111X of Comparative Example 1 is arranged sandwiched between the conductor patterns L1X and L2X, the surface of the copper foil such as the signal pattern 111X included in the substrate 102X is roughened in order to increase the strength of the substrate 102X having three or more layers by the anchor effect. Since the surface of the copper foil is roughened, the resistance loss due to the skin effect increases, and it is considered that the attenuation of the sine wave is large. On the other hand, in the signal pattern 111 of Example 1, the conductor surface 1111 of the signal pattern 111 and the conductor surface 151 of the conductor plane 15 facing the conductor surface 1111 are each copper-plated and have a smooth surface. The flatness of each of the conductor surfaces 1111 and 151 is good, so the resistance loss due to the skin effect is small, and the attenuation of the signal wave can be suppressed.

[0068] In FIG. 6, the difference between the transmission characteristics 301 and 302 at 20 GHz is larger than the difference between the transmission characteristics 301 and 302 at 5 GHz. Thus, as the transmission speed of the digital signal increases, the difference between the transmission characteristic 301 and the transmission characteristic 302 becomes larger. That is, in Example 1, as the transmission speed of the digital signal increases, the effect of reducing the attenuation amount of the digital signal becomes higher.

[0069] (Example 2) FIG. 7 is a graph showing the simulation results of Example 2. In Example 2, the characteristic impedance of the signal pattern 111 was simulated when the interval D1, the width w of the signal pattern 111, and the thickness hr of each solder resist film 118 and 120 were changed with the configuration of Example 1.

[0070] In order to ensure the quality of the digital signal in high-speed transmission, impedance matching is also important. Considering reducing the reflection of the signal wave in the memory IC 104 and the signal via 113, the characteristic impedance in the signal pattern 111 is preferably 40 Ω or more and 80 Ω or less, and more preferably 60 Ω.

[0071] From the graph shown in FIG. 7, in order to keep the characteristic impedance in the signal pattern 111 in the range of 40 Ω or more and 80 Ω or less, the interval D1 is preferably 8 μm or more and 130 μm or less. Also, in order to make the characteristic impedance in the signal pattern 111 60 Ω, the interval D1 is preferably 12 μm or more and 70 μm or less. At that time, the width w of the signal pattern 111 is preferably 25 μm or more and 150 μm or less.

[0072] In this way, by bringing the signal pattern 111 closer to the conductor plane 15, even if the width w of the signal pattern 111 is narrow, the impedance of the signal line 11 can be matched to the impedance of the input terminals of the logic LSI 1103 and the memory IC 104. Therefore, while wiring the signal patterns 111 at high density, crosstalk between the signal lines 11 can be suppressed, and transmission loss in the high-frequency band can be reduced.

[0073] The present invention is not limited to the embodiments described above, and many modifications are possible within the technical idea of the present invention. Also, the effects described in the embodiments are merely an enumeration of the most preferable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

[0074] Also, in the above-described embodiment, the case where the circuit unit of the present invention is applied to an imaging device such as a digital camera as an electronic device has been described, but the present invention is not limited to this. The electronic unit of the present invention can also be applied to an image forming device such as a printer, a copier, a facsimile, and a multifunction device having these functions as an electronic device.

[0075] Also, in the above-described embodiment, the case where the daughter board 101 and the mother board 102 are fixed by solder bonding has been described, but the present invention is not limited to this. For example, it may be a case where they are fixed by a fixing jig (not shown).

[0076] Also, in the above-described embodiment, the case where the logic LSI 103 and the memory IC 014 are mounted on the daughter board 101 has been described, but the present invention is not limited to this. For example, another board may be mounted on the daughter board 101, and the logic LSI 103 and the memory IC 014 may be mounted on that another board.

Explanation of Reference Numerals

[0077] 11... signal line, 15... conductor plane, 100... circuit module, 101... daughter board (first board), 102... mother board (second board), 111... signal pattern

Claims

1. A first substrate including a first base material having a first surface, a second substrate including a second base material having a second surface facing the first surface, the second substrate being electrically connected and mechanically fixed to the first substrate, and a first semiconductor element and a second semiconductor element mounted on the first substrate on a side of a third surface opposite to the first surface of the first base material, wherein the first substrate has a signal line connecting the first semiconductor element and the second semiconductor element, the signal line including a first conductor pattern disposed in a first conductor layer closer to the first surface than the third surface, and the second substrate has a second conductor pattern disposed in a second conductor layer closer to the second surface than a fourth surface opposite to the second surface of the second base material so as to face the first conductor pattern with a gap therebetween. A circuit module, characterized in that.

2. The circuit module according to claim 1, characterized in that the first substrate and the second substrate are soldered together.

3. The circuit module according to claim 1 or 2, characterized in that the first conductor pattern is disposed between the first surface and the second surface.

4. The circuit module according to any one of claims 1 to 3, characterized in that the second conductor pattern is disposed between the first surface and the second surface.

5. The circuit module according to any one of claims 1 to 4, characterized in that no conductor exists between the first conductor pattern and the second conductor pattern between a region between the first semiconductor element and the second semiconductor element and the second substrate.

6. The first semiconductor element performs image processing and / or controls the second semiconductor element. The circuit module according to any one of claims 1 to 5, characterized in that...

7. The second semiconductor element is a memory element. The circuit module according to any one of claims 1 to 6, characterized in that...

8. The second conductor pattern is a part of a line used to apply a power supply voltage to the first semiconductor element and the second semiconductor element. The circuit module according to any one of claims 1 to 7, characterized in that...

9. The second conductor pattern is set to a ground potential. The circuit module according to any one of claims 1 to 8, characterized in that...

10. The second substrate has a power supply line used to apply a power supply voltage to the first semiconductor element and the second semiconductor element. The power supply line includes a third conductor pattern disposed in a third conductor layer closer to the fourth surface than the second surface. The circuit module according to any one of claims 1 to 9, characterized in that...

11. The distance between the first conductor pattern and the second conductor pattern is narrower than the distance between the first conductor layer in which the first conductor pattern is disposed and a conductor layer adjacent to the first conductor layer via an insulator in the first substrate. The circuit module according to any one of claims 1 to 10, characterized in that...

12. The distance between the first conductor pattern and the second conductor pattern is 8 μm or more and 130 μm or less. The circuit module according to any one of claims 1 to 11, characterized in that...

13. The width of the first conductor pattern is 150 μm or less. The second conductor pattern faces both ends in the width direction of the first conductor pattern. The circuit module according to any one of claims 1 to 12, characterized in that...

14. At least one of the first substrate and the second substrate is glass epoxy. The circuit module according to any one of claims 1 to 13, characterized in that...

15. The first substrate is silicon. The circuit module according to any one of claims 1 to 13, characterized in that...

16. The first substrate has a first film with a relative permittivity lower than that of the first substrate, which is arranged to cover the first conductor pattern, and / or The second substrate has a second film with a relative permittivity lower than that of the second substrate, which is arranged to cover the second conductor pattern. The circuit module according to any one of claims 1 to 15, characterized in that...

17. The signal line transmits a digital signal. The circuit module according to any one of claims 1 to 16, characterized in that...

18. The first substrate is provided with a third semiconductor element mounted on the side of the third surface, Taking the signal line connecting the first semiconductor element and the second semiconductor element as a first signal line, the first substrate has a second signal line connecting the first semiconductor element and the third semiconductor element, The second signal line includes a fourth conductor pattern arranged in the first conductor layer, The second conductor pattern faces the fourth conductor pattern with a gap therebetween. The circuit module according to any one of claims 1 to 17, characterized in that...

19. There is an air gap between the first conductor pattern and the second conductor pattern. The circuit module according to any one of claims 1 to 18, characterized by the above.

20. A housing, The circuit module according to any one of claims 1 to 19, disposed inside the housing, An electronic device comprising the same.

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