Integrated Circuit Device and Oscillator

Abstract

To provide an integrated circuit device and the like capable of suppressing reduction in heating performance caused by parasitic resistance of a heat generating transistor.SOLUTION: An integrated circuit device 20 includes a heat generating circuit 22 controlled on the basis of a temperature control signal. The heat generating circuit 22 includes a heat generating transistor TR that has a plurality of parallel-connected transistors whose gate voltages are controlled on the basis of the temperature control signal. A resistance value of a source resistor of the heat generating transistor TR is smaller than that of a drain resistor of the heat generating transistor TR.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an integrated circuit device, an oscillator, and the like.

Background Art

[0002] Conventionally, an integrated circuit device having a heat-generating circuit has been known. For example, Patent Document 1 discloses a heating element capable of reducing the possibility of disconnection due to electromigration by adopting a layout arrangement in which current from a pad to a diffusion layer flows through a via along the shortest path. This Patent Document 1 discloses a layout of an integrated circuit device configured such that a plurality of transistors for heat generation control are connected in parallel.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Parasitic resistances exist in the source region and the drain region of the transistors for heat generation control. When attempting to miniaturize an integrated circuit device having a heat-generating circuit, etc., it has been found that the heat generation performance of the heat-generating circuit deteriorates due to the parasitic resistance of the source region.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to an integrated circuit device including a heat-generating circuit controlled based on a temperature control signal, the heat-generating circuit including heat-generating transistors having a gate voltage controlled based on the temperature control signal and connected in parallel, wherein a resistance value of a source resistance of the heat-generating transistors is smaller than a resistance value of a drain resistance of the heat-generating transistors.

[0006] Another aspect of the present disclosure relates to an oscillator including the integrated circuit device described above and a resonator whose temperature is controlled by the integrated circuit device.

Brief Description of the Drawings

[0007]

Figure 1

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Modes for Carrying Out the Invention

[0008] Hereinafter, this embodiment will be described. Note that the embodiment described below does not unduly limit the content described in the claims. Also, not all of the configurations described in this embodiment are essential constituent elements.

[0009] 1. Integrated Circuit Device FIG. 1 shows a configuration example of an integrated circuit device 20 according to this embodiment. The integrated circuit device 20 according to this embodiment includes a heat generating circuit 22 that is controlled based on a temperature control signal GC. The heat generating circuit 22 includes a heat generating transistor TR whose gate voltage is controlled based on the temperature control signal GC. The heat generating transistor TR is, for example, a MOS (Metal Oxide Semiconductor) transistor, and specifically, for example, an n-type MOS transistor. Also, as will be described with reference to FIGS. 3 to 8 below, the heat generating transistor TR has a plurality of transistors. The plurality of transistors are provided in parallel between the drain and the source of the heat generating transistor TR, and the temperature control signal GC is input to the gates of the plurality of transistors. The temperature control signal GC is input from, for example, outside the integrated circuit device 20. Note that the temperature control signal GC may be generated inside the integrated circuit device 20.

[0010] Also, in FIG. 1, the integrated circuit device 20 includes a current limiting resistor RL. The current limiting resistor RL is provided between the node of the high potential side power supply VDD and the drain of the heat generating transistor TR. The source of the heat generating transistor TR is connected to the node of the ground, which is the low potential side power supply. In this embodiment, the ground is appropriately described as GND. GND can also be called VSS. The current limiting resistor RL is constituted by, for example, a diffusion layer. The current limiting resistor RL is constituted by, for example, the same diffusion layer as the diffusion layer constituting the drain of the heat generating transistor TR. It should be noted that a modified embodiment in which the current limiting resistor RL is constituted by a polysilicon layer or the like is also possible. The current limiting resistor RL is used as a resistor that limits the overcurrent flowing from the node of VDD to the heat generating transistor TR at the time of startup due to the power-on of VDD or the like. For example, when the drain voltage of the heat generating transistor TR is VDR and the current limiting resistor RL is R, at startup, the current flowing through the heat generating transistor TR is limited to IL = (VDD - VDR) / R by the current limiting resistor RL. As an example, when VDD is 3.0V, the drain voltage VDR is 0.5V, and the resistance value of the current limiting resistor RL is 2.5Ω, the current flowing through the heat generating transistor TR is limited to about 1A. And after startup due to power-on or the like, until the steady-state heat generation control of the heat generating transistor TR is performed based on the temperature control signal GC, the joule heat generated by the current flowing through the current limiting resistor RL becomes the dominant heat of the integrated circuit device 20, which is the heater IC. On the other hand, when the steady-state heat generation control of the heat generating transistor TR is performed based on the temperature control signal GC, the current flowing from VDD to the ground through the current limiting resistor RL and the heat generating transistor TR is controlled to a current of about 0.1A to 0.3A. As a result, the joule heat generated by the on-current flowing through the heat generating transistor TR becomes the dominant heat of the integrated circuit device 20, which is the heater IC.

[0011] FIG. 2 shows a detailed configuration example of the integrated circuit device 20. In FIG. 2, the integrated circuit device 20 includes a temperature sensor 24 in addition to the heat generating circuit 22. The integrated circuit device 20 can also include diodes DI3, DI4, resistors RE1, RE2, RT, a power supply pad PVDD, a ground pad PGND, pads PGC, PTS. Note that the integrated circuit device 20 of the present embodiment is not limited to the configuration of FIG. 2, and various modifications such as omitting some of its components, adding other components, or changing its components to other types of components are possible.

[0012] Pad PGC is a pad to which the temperature control signal GC is input. Pad PTS is a pad from which the temperature detection signal TS from the temperature sensor 24 is output. The power supply pad PVDD is a pad to which the power supply voltage VDD is supplied, and the ground pad PGND is a pad to which the ground GND is supplied.

[0013] The temperature sensor 24 is a sensor that detects temperature. Specifically, the temperature sensor 24 outputs a temperature-dependent voltage that changes according to the temperature of the environment as the temperature detection signal TS. For example, the temperature sensor 24 generates the temperature detection signal TS, which is a temperature detection voltage, using a circuit element having temperature dependence. Specifically, the temperature sensor 24 outputs the temperature detection signal TS whose voltage changes depending on the temperature by using the temperature dependence of the forward voltage of the PN junction. For example, in FIG. 2, the temperature sensor 24 includes diodes DI1, DI2 provided in series between the node of the pad PTS, which is the output pad of the temperature detection signal TS, and the node of GND, with the direction from the node of the pad PTS to the node of GND being the forward direction. Then, the temperature sensor 24 outputs the temperature detection signal TS, which is a temperature detection voltage based on the forward voltage of the PN junctions of these diodes DI1, DI2. Note that a resistor RT is provided between the node of the pad PTS and the diode DI1 of the temperature sensor 24.

[0014] Diodes DI3, DI4, and resistor RE1 are circuits for electrostatic protection. Diode DI3 is provided between the input node N1 of the temperature control signal GC input from pad PGC and the node of VDD, and is a diode with the forward direction from the input node N1 to the node of VDD. Diode DI4 is provided between the input node N1 of the temperature control signal GC and the node of GND, and is a diode with the forward direction from the node of GND to the input node N1. Resistor RE1 is provided between the input node N1 of the temperature control signal GC and the gate node N2 of the heat-generating transistor TR, and protects the gate of the heat-generating transistor TR.

[0015] Resistor RE2 is a pull-down resistor that sets the gate of the heat-generating transistor TR to GND when the heat generation control of the heat-generating transistor TR is not being performed. Resistor RE2 is provided between the gate node N2 of the heat-generating transistor TR and the node of GND.

[0016] There is a requirement for miniaturization of the integrated circuit device 20. For example, when the integrated circuit device 20, which is a heater IC, is built into the oscillator 4 as shown in FIG. 15 described later, if the oscillator 4 is miniaturized, it is necessary to reduce the layout area of the integrated circuit device 20 as well to achieve miniaturization. On the other hand, since the heat generation ability of the heater IC is determined by the size of the heat-generating transistor TR, in order to realize a heater IC with the same heat generation ability, it is necessary to maintain the size of the heat-generating transistor TR. Therefore, it is necessary to reduce the layout area of the integrated circuit device 20 while maintaining the W / L, which is the size of the heat-generating transistor TR, to achieve miniaturization.

[0017] On the one hand, as shown in FIGS. 1 and 2, source resistance RS and drain resistance RD, which are parasitic resistances, exist in the source region and drain region of the heating transistor TR. When the integrated circuit device 20 is miniaturized, it has been found that the heat generation performance of the heating transistor TR deteriorates due to this parasitic resistance. For example, in the aforementioned Patent Document 1, as the layout arrangement of the heating transistor TR, a stepped arrangement and a linear arrangement are shown. However, in any of these arrangements, the width of the source region, which is a diffusion region, is equal to the width of the drain region, and the source resistance RS and the drain resistance RD are equal. With the conventional IC size, these source resistance RS and drain resistance RD did not cause much problem. However, with the miniaturization of the heater IC, the source resistance RS and the drain resistance RD increase. In particular, due to the increase in the source resistance RS, the gate-source voltage VGS of the heating transistor TR decreases, and it has been found that the current flowing through the heating transistor TR is restricted. When the current is restricted, the heat generation amount of the heating transistor TR becomes small, and the heat generation performance deteriorates.

[0018] In this regard, as shown in FIGS. 1 and 2, the integrated circuit device 20 of the present embodiment includes a heat generating circuit 22 that is controlled based on a temperature control signal GC. The heat generating circuit 22 includes a heat generating transistor TR having a plurality of transistors whose gate voltages are controlled based on the temperature control signal GC and are connected in parallel. In the present embodiment, the resistance value R1 of the source resistance RS of the heat generating transistor TR is smaller than the resistance value R2 of the drain resistance RD of the heat generating transistor TR. The source resistance RS is, for example, a resistance due to the parasitic resistance of the source region of the heat generating transistor TR. The source resistance RS is, for example, the resistance of the source region of the heat generating transistor TR, and is, for example, the resistance in the current path from the channel end of the source region of the heat generating transistor TR to the GND node. The drain resistance RD is, for example, a resistance due to the parasitic resistance of the drain region of the heat generating transistor TR. The drain resistance RD is, for example, the resistance of the drain region of the heat generating transistor TR, and is, for example, the resistance in the current path from the channel end of the drain region of the heat generating transistor TR to one end of the current limiting resistor RL. When there is no current limiting resistor RL, the drain resistance RD is the resistance in the current path from the channel end of the drain region of the heat generating transistor TR to the VDD node.

[0019] For example, in the prior art of Patent Document 1, the widths of the source regions and the drain regions of the plurality of transistors constituting the heat generating transistor TR are equal, and the relationship R1 = R2 holds for the resistance value R1 of the source resistance RS and the resistance value R2 of the drain resistance RD. On the other hand, in the integrated circuit device 20 of the present embodiment, the relationship R1 < R2 holds for the resistance value R1 of the source resistance RS and the resistance value R2 of the drain resistance RD of the heat generating transistor TR. For example, a plurality of transistors and the like constituting the heat generating transistor TR are arranged in a layout so that the relationship R1 < R2 holds. Specifically, for example, the relationship R1 < 0.8 × R2 holds, and the resistance value R1 of the source resistance RS is less than 80% of the resistance value R2 of the drain resistance RD. More preferably, the relationship R1 < 0.6 × R2 holds, and the resistance value R1 of the source resistance RS is less than 60% of the resistance value R2 of the drain resistance RD.

[0020] For example, in FIGS. 1 and 2, let the gate voltage of the heating transistor TR set by the temperature control signal GC be VG, the voltage between the gate and source of the heating transistor TR be VGS, and the current flowing through the heating transistor TR be Id. At this time, the relationship VGS = VG - R1×Id holds. That is, when the resistance value R1 of the source resistance RS increases, for the same gate voltage VG, the voltage VGS between the gate and source of the heating transistor TR decreases, the heat generation amount of the heating transistor TR becomes smaller, and the heat generation performance deteriorates.

[0021] In this regard, in the present embodiment, the relationship R1 < R2 holds for the resistance values R1 and R2 of the source resistance RS and the drain resistance RD. Therefore, it is possible to suppress the decrease in the voltage VGS = VG - R1×Id between the gate and source of the heating transistor TR, and it is possible to suppress the decrease in the heat generation ability caused by the parasitic resistance of the heating transistor TR. On the other hand, even if the resistance value R2 of the drain resistance RD relatively increases due to the decrease in the resistance value R1 of the source resistance RS, this increase in the resistance value R2 does not adversely affect the voltage VGS = VG - R1×Id between the gate and source of the heating transistor TR. That is, since the drain resistance RD performs the same function as the current limiting resistor RL in FIGS. 1 and 2, by reducing the resistance value R1 of the source resistance RS and arranging the layout such that the resistance value R2 of the drain resistance RD increases, it is possible to effectively suppress the decrease in the heat generation ability of the heating transistor TR due to the parasitic resistance.

[0022] 2. Layout Arrangement of the Heating Transistor Next, the layout arrangement of the heating transistor TR will be described. FIG. 3 is a first arrangement example of the heating transistor TR. Here, the direction orthogonal to the direction DR1 is defined as DR2. Also, the direction opposite to the direction DR1 is defined as DR3, and the direction opposite to the direction DR2 is defined as DR4. The directions DR1, DR2, DR3, and DR4 are the first direction, the second direction, the third direction, and the fourth direction, respectively.

[0023] As shown in FIG. 3, the heating transistor TR includes a plurality of transistors T1, T2, T3, T4, T5, and T6. The transistors T1, T2, T3, T4, T5, and T6 are the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, respectively. A temperature control signal GC is input to the gates of these plurality of transistors T1 to T6, and they are provided in parallel between the drain and the source of the heating transistor TR. Note that FIG. 3 is a schematic diagram of the layout arrangement of the heating transistor TR, and the lengths of the plurality of transistors T1 to T6 in the direction DR1 and the number of columns in the direction DR2 are different from the actual layout arrangements in FIGS. 13 and 14 described later. Similarly, the layout arrangements in FIGS. 5, 6, and 8 described later are also schematic diagrams.

[0024] In FIG. 3, in a plan view, the plurality of transistors T1 to T6 are arranged such that the longitudinal direction of the gates is along the direction DR1. The plan view is, for example, a plan view in a direction orthogonal to the semiconductor substrate of the integrated circuit device 20. And the plurality of transistors T1 to T6 are arranged side by side along the direction DR2 orthogonal to the direction DR1. That is, the gates of the transistors T1 to T6 are along the direction DR1 whose longitudinal direction is the first direction. Also, when the second direction orthogonal to the direction DR1 is defined as the direction DR2, the transistor T2 is arranged on the DR2 side of the transistor T1, the transistor T3 is arranged on the DR2 side of the transistor T2, and the transistor T4 is arranged on the DR2 side of the transistor T3. The same applies to the transistors T5 and T6. Thus, the transistors T1 to T6 are arranged side by side along the direction DR2.

[0025] Also, in FIG. 3, a via VCS that connects a metal wiring ALS and a diffusion region that constitutes the source region of the heating transistor TR to the metal wiring ALS is disposed. This metal wiring ALS corresponds to, for example, the pad wiring of the ground pad PGND in FIGS. 13 and 14 described later, and GND is supplied. Also, in FIG. 3, a via VCD that electrically connects a metal wiring ALD and a diffusion region that constitutes the drain region of the heating transistor TR is disposed. This metal wiring ALD corresponds to, for example, the pad wiring of the power supply pad PVDD in FIGS. 13 and 14 described later, and VDD is supplied. The metal wirings ALS and ALD are realized by, for example, a metal layer of the integrated circuit device 20 such as an aluminum layer.

[0026] FIG. 4 shows a schematic cross-sectional view of the heating transistor TR. As shown in FIG. 4, the metal wiring ALS, which is the metal wiring pattern on the source side, is connected to an n-type diffusion region, which is an n+-diffusion region that constitutes the source region of the heating transistor TR, via a via VCS. Also, the metal wiring ALD, which is the metal wiring pattern on the drain side, is connected to an n-type diffusion region, which is an n+-diffusion region that constitutes the drain region of the heating transistor TR, via a via VCD. Note that in FIG. 4, a current limiting resistor RL, which is not shown in FIG. 3, is shown. The current limiting resistor RL is realized by the diffusion resistance of the diffusion region that constitutes the drain region of the heating transistor TR, and is provided between the heating transistor TR and the power supply pad PVDD as shown in FIGS. 13 and 14 described later.

[0027] As shown in FIG. 3, the width WS of the source region S of the transistor T1 in the direction DR2 in a plan view is larger than the width WD of the drain region D of the transistor T1 in the direction DR2. The source region S of the transistor T1, which is the first transistor, is the first source region, and the drain region D is the first drain region. That is, in FIG. 3, the relationship WS>WD holds for the width WS of the source region S and the width WD of the drain region D of the transistor T1. Specifically, for example, the relationship WS>1.2×WD holds, and the width WS of the source region S is larger than 1.2 times the width WD of the drain region D. More desirably, the relationship WS>1.4×WD holds, and the width WS of the source region S is larger than 1.4 times the width WD of the drain region D.

[0028] Regarding the width WS of the source region S and the width WD of the drain region D of the transistor T1 that constitutes the heat-generating transistor TR in this way, by establishing the relationship WS>WD, it becomes possible to make the resistance value R1 of the source resistance RS smaller than the resistance value R2 of the drain resistance RD. For example, in FIG. 3, the resistance value R1 of the source resistance RS corresponding to the resistance in the current path from the via VCS of the metal wiring ALS to which GND is supplied to the channel end of the source region S of the transistor T1 can be made smaller than the resistance value R2 of the drain resistance RD. Therefore, it becomes possible to effectively suppress the decrease in the gate-source voltage of the heat-generating transistor TR and the decrease in the heat generation performance due to the source resistance RS.

[0029] Moreover, the plurality of transistors of the heating transistor TR includes the transistor T2. As shown in FIG. 3, in a plan view, the width in the direction DR2 of the source region S of the transistor T2 is larger than the width WD in the direction DR2 of the drain region D of the transistor T2. The source region S of the transistor T2, which is the second transistor, is the second source region, and the drain region D of the transistor T2 is the second drain region. That is, in FIG. 3, the relationship WS>WD holds for the width WS of the source region S and the width WD of the drain region D of the transistor T2. Similar to the case of the transistor T1, in the transistor T2 as well, for example, the relationship WS>1.2×WD holds, and more desirably, the relationship WS>1.4×WD holds.

[0030] Thus, with respect to the widths WS of the source regions S and the widths WD of the drain regions D of the transistors T1 and T2 constituting the heating transistor TR, by the relationship WS>WD holding, it becomes possible to make the resistance value R1 of the source resistance RS smaller than the resistance value R2 of the drain resistance RD. As a result, it becomes possible to effectively suppress the reduction in the gate-source voltage of the heating transistor TR and the reduction in the heating performance due to the source resistance RS.

[0031] Also, the source region S of the transistor T1 and the source region S of the transistor T2 form a shared source region of the transistor T1 and the transistor T2. That is, the source region S is shared by the transistors T1 and T2. By sharing the source region S in this way between the transistors T1 and T2, even when the width WS of the source region S of the transistors T1 and T2 is increased such that WS > WD, an increase in the width in the direction DR2 of the heat-generating transistor TR can be suppressed. That is, if the width WS of the source region S is increased and the source regions S of the transistors T1 and T2 are arranged side by side along the direction DR2 without making them a shared source region, a situation will occur where the width in the direction DR2 of the heat-generating transistor TR increases. Sharing the source region S can prevent such a situation from occurring. Therefore, the width WS of the source region S can be increased to reduce the resistance value R1 of the source resistance RS, and an increase in the layout area of the heat-generating transistor TR can also be suppressed.

[0032] Regarding the other transistors T3, T4, T5, and T6 that make up the heat-generating transistor TR, similar to the transistors T1 and T2, the relationship WS > WD holds for the width WS of the source region S and the width WD of the drain region D. As a result, it becomes possible to make the resistance value R1 of the source resistance RS of the heat-generating transistor TR smaller than the resistance value R2 of the drain resistance RD. Also, the source region S is shared between the transistor T3 and the transistor T4, and the source region S is shared between the transistor T5 and the transistor T6. Thereby, the width WS of the source region S can be increased to reduce the resistance value R1 of the source resistance RS, and an increase in the layout area of the heat-generating transistor TR can also be suppressed.

[0033] Also, in FIG. 3, the polysilicon line forming the gate G of transistor T1 is wired along direction DR1, folded back at the end of transistor T1 on the DR1 side, and then wired along direction DR3, thereby forming the gate G of transistor T2. Further, this polysilicon line is folded back at the end of transistor T2 on the DR3 side and wired along direction DR1, thereby forming the gate G of transistor T3. Then, the polysilicon line is folded back at the end of transistor T3 on the DR1 side and wired along direction DR3, thereby forming the gate G of transistor T4. The gates G of transistors T5 and T6 are formed in the same manner. Although not particularly limited, as an example, the width WS of the source region S is about 8 μm, for example, the width WD of the drain region D is about 3 μm, and the channel length L corresponding to the width of the gate G is about 3 μm, for example.

[0034] FIG. 5 shows a second arrangement example of the heating transistor TR. FIG. 5 is a layout arrangement example in which the shapes of the ends of the source regions S and the drain regions D of a plurality of transistors of the heating transistor TR are stepped.

[0035] In FIG. 5, the plurality of transistors of the heating transistor TR include transistors T1 and T2, and the width WS of the source regions S of transistors T1 and T2 in direction DR2 in a plan view is larger than the width WD of the drain regions D of transistors T1 and T2 in direction DR2.

[0036] Also, the plurality of transistors of the heating transistor TR include transistor T3B provided in direction DR1 of transistor T1. Transistor T3B is a third transistor. And in a plan view, the width WS of the source region S of transistor T3B in direction DR2 is larger than the width in direction DR2 of the drain region D of transistor T3B. The source region S of transistor T3B is a third source region, and the drain region D of transistor T3B is a third drain region.

[0037] In FIG. 5, the gate G of transistor T1 and the gate G of transistor T3B are arranged with a displacement in the direction DR2. The gate G of transistor T1 is the first gate, and the gate G of transistor T3B is the third gate. That is, at the end of transistor T1 on the DR1 side, the gate G of transistor T3B is arranged at a position displaced toward the DR2 side from the gate G of transistor T1. For example, the polysilicon line forming the gate G is bent and wired toward the DR2 side at the end of transistor T1 on the DR1 side. At the boundary between transistor T1 and transistor T3B, for example, no channel is formed.

[0038] In this way, it is possible to realize a layout arrangement of transistors T1 and T3B in which the shapes of the channel-side ends of transistors T1 and T3B are not linear along the direction DR1 as shown in FIG. 3, but are stepped in the direction DR1. Also in this case, since the width WS of the source region S of transistors T1 and T3B is larger than the width WD of the drain region D, the resistance value R1 of the source resistance RS of the heat-generating transistor TR can be made smaller than the resistance value R2 of the drain resistance RD. As a result, it is possible to suppress a decrease in the gate-source voltage of the heat-generating transistor TR due to the source resistance RS and a decrease in the heat generation performance.

[0039] Also, in FIG. 5, the plurality of transistors of the heating transistor TR include transistors T3B and T4B in addition to transistors T1 and T2. Transistor T3B is the third transistor, and transistor T4B is the fourth transistor. Transistor T3B is provided in the direction DR1 of transistor T1, and transistor T4B is provided in the direction DR1 of transistor T2. As shown in FIG. 5, the source regions S of transistor T1 and transistor T2 form a shared source region. The source region S of transistor T1 is the first source region, and the source region S of transistor T2 is the second source region. Also, the source regions S of transistor T3B and transistor T4B form a shared source region. The source region S of transistor T3B is the third source region, and the source region S of transistor T4B is the fourth source region.

[0040] And the gate G of transistor T3B is arranged with a displacement in the direction DR2 with respect to the gate G of transistor T1. Also, the gate G of transistor T4B is arranged with a displacement in the direction DR4, which is the opposite direction of direction DR2, with respect to the gate G of transistor T2. The gates of transistors T1, T2, T3B, and T4B are the first gate, the second gate, the third gate, and the fourth gate, respectively.

[0041] In this way, a layout arrangement of transistors T1, T2, T3B, and T4B can be realized such that the shapes of the channel-side ends of transistors T1 and T3B are stepped in the direction DR1, and the shapes of the channel-side ends of transistors T2 and T4B are stepped in the direction DR1. And as shown in FIG. 5, the width WS of the shared source region S of transistors T1 and T2 can be made larger than the width WS of the shared source region S of transistors T3B and T4B. For example, in the shared source region S of transistors T1 and T2, more current flows than in the shared source region S of transistors T3B and T4B. This is because the current flowing from the shared source region S of transistors T3B and T4B to the drain region D also flows to the shared source region S of transistors T1 and T2. Therefore, as shown in FIG. 5, by arranging the layout so that the width WS of the shared source region S through which more current flows becomes larger, it becomes possible to set an appropriate width WS of the source region S according to the amount of current.

[0042] Also in this case, the width of the shared source region S of transistors T1 and T2 is larger than the width of the drain region D of transistors T1 and T2, and the width of the shared source region S of transistors T3B and T4B is larger than the width of the drain region D of transistors T3B and T4B.

[0043] In this way, by making the width of the shared source region S of transistors T1 and T2 larger than the width of its drain region D, and also making the width of the shared source region S of transistors T3 and T4 larger than the width of its drain region D, the resistance value R1 of the source resistance RS of the heat-generating transistor TR can be made smaller than the resistance value R2 of the drain resistance RD. Therefore, it becomes possible to suppress the reduction of the gate-source voltage of the heat-generating transistor TR due to the source resistance RS and the reduction of the heat generation performance.

[0044] Fig. 6 shows a third arrangement example of the heat-generating transistor TR. The integrated circuit device 20 of the present embodiment to which the third arrangement example of Fig. 6 is applied includes a heat-generating circuit 22 controlled based on the temperature control signal GC. The heat-generating circuit 22 includes a heat-generating transistor TR whose gate voltage is controlled based on the temperature control signal GC and which has a plurality of transistors T1 to T6 connected in parallel, a metal wiring ALS overlapping the plurality of transistors T1 to T6 in a plan view, and a plurality of vias VC having one end connected to the metal wiring ALS and the other end connected to a plurality of source regions of the plurality of transistors T1 to T6. The metal wiring ALS is a wiring for supplying ground to the source of the heat-generating transistor TR. In Fig. 6, this metal wiring ALS is arranged so as to overlap the plurality of transistors T1 to T6 constituting the heat-generating transistor TR in a plan view. For example, the metal wiring ALS having a solid pattern is arranged so as to overlap the plurality of transistors T1 to T6 of the heat-generating transistor TR in a plan view. For example, a wide metal wiring ALS corresponding to the width in the direction DR2 of the arrangement region of the plurality of transistors T1 to T6 constituting the heat-generating transistor TR is arranged so as to overlap the plurality of transistors T1 to T6 of the heat-generating transistor TR in a plan view. The width of the metal wiring ALS in the direction DR2 is a width covering the plurality of vias VC connected to the plurality of source regions of the plurality of transistors T1 to T6.

[0045] For example, Fig. 7 shows a schematic cross-sectional view of the heat-generating transistor TR of Fig. 6. As shown in Fig. 7, the metal wiring ALS extends from the position of the via VCS connected to the n-type diffusion region in the direction DR1 and is wired so as to overlap above the plurality of transistors T1 to T6 constituting the heat-generating transistor TR. Note that there may be a portion of the transistors T1 to T6 that does not overlap the metal wiring ALS in a plan view.

[0046] Also, in FIG. 6, a plurality of vias VC are provided, one end of which is connected to the metal wiring ALS and the other end of which is connected to the plurality of source regions of the plurality of transistors T1 to T6. And in FIG. 6, these plurality of vias VC are provided at positions overlapping the plurality of source regions of the plurality of transistors T1 to T6 in a plan view. For example, the via VC that supplies GND to the source region of the transistor T1 is provided at a position overlapping the source region of the transistor T1, and the via VC that supplies GND to the source region of the transistor T2 is provided at a position overlapping the source region of the transistor T2. Similarly, the vias VC that supply GND to the source regions of the transistors T3, T4, T5, and T6 are provided at positions overlapping the source regions of the transistors T3, T4, T5, and T6, respectively.

[0047] In this way, ground can be supplied from the metal wiring ALS that overlaps the plurality of transistors T1 to T6 of the heat-generating transistor TR in a plan view, to the source regions of the plurality of transistors T1 to T6, via the plurality of vias VC that overlap the source regions in a plan view. For this reason, the current from the source regions of the plurality of transistors T1 to T6 flows to the ground via the metal wiring ALS and the plurality of vias VC having a lower resistance value than the diffusion region constituting the source region. Therefore, it becomes possible to substantially reduce the resistance value R1 of the source resistance RS of the heat-generating transistor TR. As a result, it becomes possible to effectively suppress the decrease in the gate-source voltage of the heat-generating transistor TR due to the source resistance RS and the decrease in the heat generation performance.

[0048] In addition, since the wiring pattern of the metal wiring ALS can also be formed into a large wiring pattern with a wide width in the direction DR2, it becomes possible to prevent disconnection or short circuit of the metal wiring ALS or the via VC due to electromigration. That is, since a large current flows through the heat-generating transistor TR, if the metal wiring ALS is thin, there is a risk of disconnection or short circuit due to electromigration. In this regard, in FIG. 8, a wide metal wiring ALS having a width that overlaps the entire surface of the source regions of the plurality of transistors T1 to T6 of the heat-generating transistor TR is arranged. Therefore, even when a large current flows through the heat-generating transistor TR, it is possible to prevent disconnection or short circuit from occurring.

[0049] In addition, the plurality of transistors of the heat-generating transistor TR include a transistor T1 and a transistor T2 whose source region is shared with the transistor T1. The transistors T1 and T2 are the first transistor and the second transistor, respectively. Then, as shown in FIG. 6, the first via group GVC1 of the plurality of vias is arranged so as to overlap the shared source region of the transistor T1 and the transistor T2 in a plan view. For example, the first via group GVC1 is arranged so as to overlap the shared source region between the gate of the transistor T1 and the gate of the transistor T2.

[0050] In this way, ground can be supplied to the common source region of the transistors T1 and T2 from the metal wiring ALS through the first via group GVC1 arranged so as to overlap the common source region of the transistors T1 and T2 in a plan view. Therefore, the parasitic resistance that becomes the source resistance RS is only the parasitic resistance in the current path from one end of the first via group GVC1 to the channel side end of the common source region, so that the resistance value R1 of the source resistance RS can be effectively reduced. As a result, it becomes possible to effectively suppress the decrease in the gate-source voltage of the heat-generating transistor TR due to the source resistance RS and the decrease in the heat generation performance.

[0051] When the longitudinal direction of the gate of the transistor T1 is defined as the direction DR1, the first via group GVC1 is arranged along the direction DR1 in the shared source region of the transistors T1 and T2. For example, in FIG. 6, the first via group GVC1 is arranged along the direction DR1 from the ground-side end to the VDD-side end of the shared source region of the transistors T1 and T2. In this way, the first via group GVC1 arranged along the direction DR1 so as to overlap in the common source region of the transistors T1 and T2 in plan view enables the supply of ground to the common source region. Therefore, the parasitic resistance in the current path from one end of the first via group GVC1 arranged along the direction DR1 to the channel-side end of the common source region can be reduced, and the resistance value R1 of the source resistance RS can be made even smaller more effectively.

[0052] Also in FIG. 6, a plurality of columns of the first via group GVC1 are arranged side by side along the direction DR2 along the direction DR1. For example, the first row of the via groups of the first via group GVC1 is arranged along the direction DR1, and on the DR2 side of this first row of via groups, the second row of the via groups of the first via group GVC1 is arranged along the direction DR1. Although FIG. 6 shows the case where the number of columns of the first via group GVC1 is 2, the number of columns may be 3 or more.

[0053] By arranging a plurality of columns of the first via group GVC1 so as to overlap in the common source region of the transistors T1 and T2 in plan view, one end of the first via group GVC1 can be connected to a position close to the channel of each transistor in the common source region of the transistors T1 and T2. As a result, the resistance value R1 of the source resistance RS can be made even smaller more effectively, and it becomes possible to suppress the reduction in the gate-source voltage of the heat-generating transistor TR due to the source resistance RS and the resulting reduction in heat generation performance.

[0054] Also, in FIG. 6, the plurality of transistors of the heating transistor TR include transistor T3 and transistor T4 whose source region is shared with transistor T3. Transistors T3 and T4 are the third transistor and the fourth transistor, respectively. And as shown in FIG. 6, the second via group GVC2 of the plurality of vias is arranged so as to overlap the shared source region of transistors T3 and T4 in a plan view. For example, the second via group GVC2 is arranged so as to overlap the shared source region between the gate of transistor T3 and the gate of transistor T4.

[0055] In this way, ground can be supplied to the common source region of transistors T3 and T4 from the metal wiring ALS through the second via group GVC2 arranged so as to overlap the common source region of transistors T3 and T4 in a plan view. Therefore, the parasitic resistance that becomes the source resistance RS is only the parasitic resistance in the current path from one end of the second via group GVC2 to the channel side end of the common source region, so that the resistance value R1 of the source resistance RS can be effectively reduced. As a result, it becomes possible to effectively suppress the reduction of the gate-source voltage of the heating transistor TR due to the source resistance RS and the reduction of the heating performance.

[0056] Also, the plurality of transistors of the heating transistor TR include transistor T5 and transistor T6 whose source region is shared with transistor T5, and the third via group GVC3 of the plurality of vias is arranged so as to overlap the shared source region of transistors T5 and T6 in a plan view. For example, the third via group GVC3 is arranged so as to overlap the shared source region between the gate of transistor T5 and the gate of transistor T6.

[0057] In FIG. 7, the width of the source region of each transistor among the plurality of transistors of the heat-generating transistor TR is larger than the width of the drain region. However, if the resistance value R1 of the source resistance RS can be sufficiently reduced by arranging a plurality of vias VC so as to overlap in plan view on the source region of each transistor, the width of the source region does not have to be larger than the width of the drain region. For example, the widths of the source region and the drain region may be made the same, and a plurality of vias VC may be arranged so as to overlap in plan view with respect to the source region.

[0058] FIG. 8 shows a fourth arrangement example of the heat-generating transistor TR. In FIG. 8, the metal wiring ALS has a lattice pattern in which the portion where the via VC is absent becomes a hole portion HL. That is, a metal wiring ALS having a lattice pattern is provided in which wiring exists so as to overlap the via VC in plan view at the portion where the via VC exists, and a hole portion HL is formed at the portion where the via VC does not exist. For example, a mesh-like metal wiring ALS is provided in which the portion where the via VC is absent becomes a hole portion HL.

[0059] In this way, ground can be supplied from the metal wiring ALS having a lattice pattern that overlaps the plurality of transistors T1 to T6 of the heat-generating transistor TR in plan view to the source regions of the plurality of transistors T1 to T6 via a plurality of vias VC that overlap the source regions in plan view. For this reason, the current from the source regions of the plurality of transistors T1 to T6 flows to the ground via the metal wiring ALS having a low resistance value and the plurality of vias VC, so that the resistance value R1 of the source resistance RS of the heat-generating transistor TR can be substantially reduced.

[0060] Also, in the metal wiring ALS having a lattice pattern, for example, by making the width of the wiring between the two hole portions HL thick enough not to be disconnected due to electromigration, it becomes possible to prevent problems such as disconnection and short circuit due to electromigration.

[0061] Also, as shown in FIG. 8, the metal wiring ALS includes a wiring portion LP1 provided along the first via group GVC1, a wiring portion LP2 provided along the second via group GVC2, and wiring portions LP3 and LP4 that intersect the wiring portion LP1 and the wiring portion LP2 and are arranged at a given distance from each other. The wiring portions LP1, LP2, LP3, and LP4 are the first wiring portion, the second wiring portion, the third wiring portion, and the fourth wiring portion, respectively. That is, the wiring portion LP1 is a portion of the metal wiring ALS that is wired along the direction DR1 so as to overlap the first via group GVC1 in plan view. The wiring portion LP2 is a portion of the metal wiring ALS that is wired along the direction DR1 so as to overlap the second via group GVC2 in plan view. The wiring portions LP3 and LP4 are portions of the metal wiring ALS that intersect the wiring portions LP1 and LP2. And by arranging the wiring portions LP3 and LP4 at a given distance from each other, a hole portion HL is formed between the wiring portion LP3 and the wiring portion LP4.

[0062] With the metal wiring ALS having such wiring portions LP1, LP2, LP3, and LP4, for example, a metal wiring ALS having a lattice pattern in which a portion where the via VC does not exist becomes the hole portion HL can be realized. And by supplying ground to the source regions of the plurality of transistors T1 to T6 from such a lattice pattern metal wiring ALS via a plurality of vias VC that overlap the source regions in plan view, it becomes possible to substantially reduce the resistance value R1 of the source resistance RS of the heat-generating transistor TR. Also, by setting the thickness of each of the wiring portions LP1, LP2, LP3, and LP4 to a thickness such that disconnection or the like does not occur due to electromigration, it becomes possible to prevent problems such as disconnection and short circuit due to electromigration.

[0063] In any case of FIGS. 6 and 8, it is desirable to wire the metal wiring ALS with a width such that problems due to electromigration do not occur from the ground pad PGND in FIG. 13 described later to the arrangement region of the heat-generating transistor TR.

[0064] Fig. 9 shows an equivalent circuit of the heating transistor TR and parasitic resistances, and Fig. 10 shows the gate voltage-current characteristics of the heating transistor TR. The equivalent circuit and circuit constants in Fig. 9 are extracted by a circuit simulator, and detailed explanations are omitted here. Fig. 10 shows the gate voltage-current characteristics of the heating transistor TR obtained by circuit simulation using, for example, the equivalent circuit in Fig. 9. In Fig. 10, the horizontal axis is the gate voltage VG of the heating transistor TR, and the vertical axis is the current Id flowing through the heating transistor TR. The gate voltage VG is the voltage of the temperature control signal GC, and the current Id is the current flowing between the drain and source of the heating transistor TR. A1 is the gate voltage-current characteristics of the heating transistor TR when the method of this embodiment is applied, and A2 is the gate voltage-current characteristics when the method of this embodiment is not applied. The gate voltage in the steady state of temperature control is, for example, about VG = 2.4V. By applying the method of this embodiment to reduce the source resistance RS, as shown in A3, it becomes possible to increase the current Id flowing through the heating transistor TR when VG = 2.4V. For example, if the source resistance RS is large without applying the method of this embodiment, the current Id when VG = 2.4V is as shown in A4. Therefore, by applying the method of this embodiment, the current Id flowing through the heating transistor TR can be increased by Idif, and the heat generation performance of the heating transistor TR can be improved.

[0065] FIG. 11 shows an example of the resistance values of the source resistance RS, the on-resistance, and the drain resistance RD when the method of the present embodiment is not applied. Specifically, FIG. 11 shows the circuit simulation results when the widths of the source region and the drain region of the transistor constituting the heating transistor TR are both about 5.5 μm. On the other hand, FIG. 12 shows an example of the resistance values of the source resistance RS, the on-resistance, and the drain resistance RD when the method of the present embodiment is applied. Specifically, FIG. 12 shows the circuit simulation results when the width of the source region is enlarged to about 8 μm and the width of the drain region is correspondingly reduced to about 3 μm. In FIGS. 11 and 12, the respective resistance values when the gate voltage is 2.0V, 2.4V, and 2.8V are shown. Note that the resistance value of the current limiting resistor RL is set to 1 Ω.

[0066] As shown in FIG. 12, by increasing the width of the source region, the resistance value of the source resistance RS can be reduced and the on-resistance value can also be reduced. By reducing the resistance value of the source resistance RS, it is possible to suppress a decrease in the gate-source voltage of the heating transistor TR caused by the source resistance RS, and to improve the heating performance. Also in FIG. 12, although the resistance value of the drain resistance RD increases as the width of the drain region increases, no decrease in the gate-source voltage of the heating transistor TR occurs even if the resistance value of the drain resistance RD increases. And for the amount by which the resistance value of the drain resistance RD increases, for example, an adjustment to reduce the resistance value of the current limiting resistor RL can be made. Note that the improvement in the heating ability shown in A1 and A3 of FIG. 10 and FIG. 12 can also be realized by the method of expanding the width of the source region as shown in FIGS. 3 and 5, or by the method of arranging the metal wiring ALS and the via VC as shown in FIGS. 6 and 8.

[0067] 3. Layout arrangement of the integrated circuit device Fig. 13 shows an example of the layout arrangement of the integrated circuit device 20 of the present embodiment. The outer shape of the integrated circuit device 20 has a side SD1 and a side SD2 which is the opposite side of the side SD1. Also, the outer shape of the integrated circuit device 20 can include a side SD3 that intersects the sides SD1 and SD2, and a side SD4 which is the opposite side of the side SD3. The side SD4 intersects the sides SD1 and SD2. The sides SD1, SD2, SD3, and SD4 are the first side, the second side, the third side, and the fourth side, respectively. The outer shape of the integrated circuit device 20 is, for example, the outer shape of the semiconductor substrate on which the integrated circuit device 20 is realized. In Fig. 13, the direction from the side SD1 to the side SD2 is the direction DR1 which is the first direction. And the sides SD1 and SD2 are the sides along the direction DR2 that is orthogonal to the direction DR1, and the sides SD3 and SD4 are the sides along the direction DR1.

[0068] The integrated circuit device 20 includes a ground pad PGND and a power supply pad PVDD. And in Fig. 13, along the side SD1, a ground pad PGND that is electrically connected to the source of the heat-generating transistor TR is arranged. Here, a plurality of ground pads PGND are arranged along the side SD1, and as an example, 5 ground pads PGND are arranged. Also in Fig. 13, along the side SD2, a power supply pad PVDD that supplies the power supply voltage VDD to the drain of the heat-generating transistor TR is arranged. Here, a plurality of power supply pads PVDD are arranged along the side SD2, and as an example, 3 power supply pads PVDD are arranged. Since a large current flows through the heat-generating transistor TR, it is desirable to arrange such a plurality of ground pads PGND and a plurality of power supply pads PVDD in this way. Note that the number of arrangements of the ground pad PGND and the power supply pad PVDD is not limited to the number of arrangements in Fig. 13 and is arbitrary. Also in Fig. 13, a temperature sensor 24 is arranged on the side of the ground pad PGND in the direction DR4. Also, on the side of the power supply pad PVDD in the direction DR2, a pad PGC which is an input pad of the temperature control signal GC is arranged, and on the side of the power supply pad PVDD in the direction DR4, a pad PTS which is an output pad of the temperature detection signal TS of the temperature sensor 24 is arranged. Note that the arrangement of the temperature sensor 24, the pad PGC, and the pad PTS in Fig. 13 is an example and is not limited to such an arrangement.

[0069] As shown in FIG. 13, the heat-generating transistor TR is disposed between the ground pad PGND and the power supply pad PVDD. For example, the ground pad PGND is disposed on the DR1 side in the direction SD1 of the side of the integrated circuit device 20, the heat-generating transistor TR is disposed on the DR1 side of the ground pad PGND, and the power supply pad PVDD is disposed on the DR1 side of the heat-generating transistor TR. In FIG. 13, the heat-generating transistor TR composed of a plurality of transistors as described in FIGS. 3 to 8 is disposed on the DR1 side of the ground pad PGND such that, for example, the longitudinal direction is along the direction DR2. For example, the ground pad PGND and the heat-generating transistor TR are arranged side by side along the direction DR1.

[0070] In this way, it becomes possible to electrically connect the source of the ground pad PGND and the heat-generating transistor TR by a short-path route, and also to electrically connect the drain of the heat-generating transistor TR and the power supply pad PVDD by a short-path route or the like. Therefore, it is possible to reduce the adverse effect exerted by the parasitic resistance or the like existing in the path on the heat generation performance of the heat-generating transistor TR, and to improve the heat generation performance.

[0071] Also, as described with reference to FIGS. 1 and 2, the integrated circuit device 20 includes a current limiting resistor RL having one end electrically connected to the power supply pad PVDD and the other end electrically connected to the drain of the heat-generating transistor TR. As shown in FIG. 13, the current limiting resistor RL is disposed between the heat-generating transistor TR and the power supply pad PVDD. For example, the current limiting resistor RL is disposed on the DR1 side of the heat-generating transistor TR, and the power supply pad PVDD is disposed on the DR1 side of the current limiting resistor RL. For example, the current limiting resistor RL is disposed on the DR1 side of the heat-generating transistor TR such that, for example, the longitudinal direction is along the direction DR2. For example, the heat-generating transistor TR and the current limiting resistor RL are arranged side by side along the direction DR1. Also, the current limiting resistor RL and the power supply pad PVDD are arranged side by side along the direction DR1.

[0072] By doing so, one end of the current limiting resistor RL and the power supply pad PVDD can be connected by a short path, and the other end of the current limiting resistor RL and the drain of the heat generating transistor TR can be connected by a short path. Therefore, the heat generating transistor TR, the current limiting resistor RL, and the power supply pad PVDD can be compactly arranged, for example, along the direction DR1, and a reduction in the layout area of the integrated circuit device 20 can be realized.

[0073] FIG. 14 shows an example of the layout arrangement of the integrated circuit device 20 of the present embodiment, and examples of the layout arrangements of the diffusion regions DF1 and DF2 and the vias VCS and VCD. The n-type diffusion region DF1 is formed in a path from the region of the ground pad PGND to the source region of the heat generating transistor TR. For example, the diffusion region DF1 is formed in a path from the region of the ground pad PGND to the source region of the heat generating transistor TR with a width wider than the width in the direction DR2 of the plurality of ground pads PGND. In the region of the ground pad PGND, the diffusion region DF1 is formed below the ground pad PGND. The n-type diffusion region DF2 is formed in a path from the drain region of the heat generating transistor TR to the region of the power supply pad PVDD. For example, the diffusion region DF2 is formed in a path from the drain region of the heat generating transistor TR to the region of the power supply pad PVDD with a width wider than the width in the direction DR2 of the plurality of power supply pads PVDD. In the region of the power supply pad PVDD, the diffusion region DF2 is formed below the power supply pad PVDD. In the region of the heat generating transistor TR, as shown in FIGS. 3, 5, 6, and 8, the convex portion of the diffusion region DF1 serving as the source region and the concave portion of the diffusion region DF2 serving as the drain region face each other, and the concave portion of the diffusion region DF1 serving as the source region and the convex portion of the diffusion region DF2 serving as the drain region are arranged to face each other.

[0074] As shown in FIG. 14, the current limiting resistor RL includes a plurality of diffusion resistors RL1 to RLm connected in parallel between the power supply pad PVDD and the drain of the heat generating transistor TR. That is, one end of the plurality of diffusion resistors RL1 to RLm is connected to the power supply pad PVDD and the other end is connected to the drain of the heat generating transistor TR, and they are connected in parallel between the power supply pad PVDD and the drain of the heat generating transistor TR.

[0075] By configuring the current limiting resistor RL with the plurality of diffusion resistors RL1 to RLm connected in parallel between the power supply pad PVDD and the drain of the heat generating transistor TR in this way, it becomes possible to realize a current limiting resistor RL with a desired resistance value with a small layout area.

[0076] Also, when the direction from side SD1 to side SD2 is defined as direction DR1 and the direction orthogonal to direction DR1 is defined as direction DR2, the longitudinal direction of each diffusion resistor is along direction DR1, and they are arranged side by side along direction DR2. For example, a plurality of narrow-width diffusion resistors RL1 to RLm with direction DR1 as the longitudinal direction are arranged side by side along direction DR2. For example, a plurality of hole portions that become slits with respect to the diffusion region DF2 are formed, and the diffusion region between one hole portion and the adjacent hole portion becomes each diffusion resistor of the diffusion resistors RL1 to RLm. The width of each diffusion resistor of the plurality of diffusion resistors RL1 to RLm in direction DR2 is, for example, about 4 to 6 μm, and the length in direction DR1 is, for example, about 40 to 50 μm.

[0077] In this way, by arranging the plurality of diffusion resistors RL1 to RLm with a narrow width in direction DR2 side by side along direction DR2, it becomes possible to realize a current limiting resistor RL with a desired resistance value while reducing the length L3 in direction DR1 of the layout area of the current limiting resistor RL. As a result, it becomes possible to achieve both the compactification of the integrated circuit device 20 and a current limiting resistor RL with a desired resistance value.

[0078] As shown in FIG. 14, the integrated circuit device 20 includes a plurality of vias VCS arranged so as to overlap with the ground pad PGND in a plan view. For example, the plurality of vias VCS are arranged on the entire surface of each pad of the ground pad PGND. One end of the plurality of vias VCS is electrically connected to the ground pad PGND, and the other end is electrically connected to the source of the heat-generating transistor TR. These vias VCS correspond to the vias VCS in FIGS. 4 and 7.

[0079] In this way, the ground pad PGND can be electrically connected to the diffusion region DF1 directly below it through the plurality of vias VCS, so that it can be electrically connected to the source of the heat-generating transistor TR. Therefore, it becomes possible to reduce the parasitic resistance formed on the source side of the heat-generating transistor TR, and it becomes possible to suppress the deterioration of the heat generation performance of the heat-generating transistor TR caused by the parasitic resistance.

[0080] Similarly, the integrated circuit device 20 includes a plurality of vias VCD arranged so as to overlap with the power supply pad PVDD in a plan view. For example, the plurality of vias VCD are arranged on the entire surface of each pad of the power supply pad PVDD. One end of the plurality of vias VCD is electrically connected to the power supply pad PVDD. The other end of the plurality of vias VCD is connected to one end of a current limiting resistor RL whose other end is electrically connected to the drain of the heat-generating transistor TR.

[0081] For example, as a layout arrangement method of the comparative example of the present embodiment, after extending the diffusion region DF2 from the end on the drain region side of the heat-generating transistor TR in the direction DR1, it is bent in the direction DR2 or the direction DR4. For example, a method of extending the diffusion region DF2 to the location of the power supply pad PVDD arranged on the direction DR2 side or the direction DR4 side of the heat-generating transistor TR is conceivable. In the method of this comparative example, the diffusion region DF2 extending over a long distance as described above is used as the current limiting resistor RL. However, in the method of this comparative example, the region for extending and arranging the diffusion region DF2 becomes wasted, and the layout area of the integrated circuit device 20 is increased.

[0082] In this regard, according to the layout arrangement of the present embodiment shown in FIGS. 13 and 14, a plurality of diffusion resistors RL1 to RLm are arranged in a compact layout region with a short length L3 in the direction DR1, thereby realizing the layout of the current limiting resistor RL. Therefore, the heat generating transistor TR and the current limiting resistor RL can be arranged between the ground pad PGND and the power supply pad PVDD with a compact layout area. As a result, compared with the method of the above-described comparative example, the layout area of the integrated circuit device 20 can be significantly reduced, and the miniaturization of the integrated circuit device 20 can be realized.

[0083] In FIGS. 13 and 14, the length L1 in the direction DR1 of the region of the heat generating transistor TR is, for example, about 220 to 260 μm, and the length in the direction DR2 is, for example, about 700 to 900 μm. As an example, a transistor with a channel length L of, for example, 3 μm and a channel width W of, for example, 240 μm is arranged as each column of transistors of the heat generating transistor TR with the direction DR1 as the longitudinal direction. And such transistors in each column are arranged, for example, about 100 columns along the direction DR2. Note that the transistors in each column may be divided into a plurality of parts and arranged, for example, along the direction DR1. For example, by not forming a channel under the gate, the transistors in each column can be divided into, for example, 8 stages and arranged.

[0084] In this embodiment, while aiming for miniaturization of the integrated circuit device 20, the heat generation performance of the heat-generating transistor TR is maintained. As described with reference to FIGS. 13 and 14, in order to reduce the layout area of the integrated circuit device 20, the length L3 in the direction DR1 of the region of the current limiting resistor RL is reduced. For example, by realizing the current limiting resistor RL by connecting in parallel a plurality of narrow diffusion resistors RL1 to RLm, the length L3 in the direction DR1 can be reduced. And, by reducing the length L3 in the direction DR1 of the region of the current limiting resistor RL by this amount, the length L1 in the direction DR1 of the region of the heat-generating transistor TR is increased. While increasing the length L1 in the direction DR1 of the region of the heat-generating transistor TR, the length L2 in the direction DR2 is reduced. Thereby, the transistor size W / L of the heat-generating transistor TR can be maintained, and the heat generation performance can be maintained. And by reducing the length L2 in the direction DR2 of the region of the heat-generating transistor TR, miniaturization of the integrated circuit device 20 can be realized. Therefore, it becomes possible to achieve both miniaturization of the integrated circuit device 20 and maintenance of the heat generation performance of the heat-generating transistor TR.

[0085] 4. Oscillator FIG. 15 shows a structural example of the oscillator 4 of this embodiment. The oscillator 4 includes the integrated circuit device 20 of this embodiment and a vibrator 10 whose temperature is controlled by the integrated circuit device 20. For example, the integrated circuit device 20 which is a heater IC has a heat generation circuit 22, and by the heat generation of this heat generation circuit 22, it becomes possible to control the temperature of the vibrator 10. For example, when the temperature control signal GC in FIGS. 1 and 2 is input to the gate of the heat-generating transistor TR, the heat generation of the heat generation circuit 22 is controlled, and the temperature of the vibrator 10 is controlled by this control of the heat generation.

[0086] More specifically, the oscillator 4 in FIG. 15 includes an integrated circuit device 20, a vibrator 10, an integrated circuit device 30 having an oscillation circuit 32 shown in FIG. 16 for oscillating the vibrator 10 described later, a first package 13 that houses the vibrator 10 and the integrated circuit device 30, and a second package 17 that houses the integrated circuit device 20 and the first package 13. The integrated circuit device 20 is a first integrated circuit device, and the integrated circuit device 30 is a second integrated circuit device.

[0087] In this way, a thermostatic chamber type crystal oscillator (OCXO) can be realized with the first package 13 that houses the vibrator 10 and the integrated circuit device 30 for oscillating the vibrator 10 as a thermostatic chamber. For example, on the upper surface of the first package 13, the integrated circuit device 20 of this embodiment, which is a heater IC, is arranged, and the temperature of the first package 13, which is the thermostatic chamber, is controlled by controlling the heat generation of the heat generation circuit 22 of the integrated circuit device 20 based on the temperature control signal GC. Thereby, for example, even if the ambient temperature changes, temperature control is performed to keep the temperature of the vibrator 10 constant, and a thermostatic chamber type crystal oscillator can be realized.

[0088] Also, according to the structure of the oscillator 4 in FIG. 15, it is also possible to use an oscillator of an existing product including the vibrator 10, the integrated circuit device 30, and the first package 13 that houses the vibrator 10 and the integrated circuit device 30. That is, by housing an oscillator of an existing product including the vibrator 10, the integrated circuit device 30, and the first package 13 together with the integrated circuit device 20, which is a heater IC, in the second package 17, a thermostatic chamber type crystal oscillator can be realized. Therefore, it becomes possible to realize a thermostatic chamber type crystal oscillator that effectively utilizes an oscillator of an existing product, and the product cost, development cost, development period, etc. can be reduced.

[0089] Also, the oscillator 4 in FIG. 15 is provided in the second package 17 and includes an integrated circuit device 40 that outputs a temperature control signal GC to the integrated circuit device 20. The integrated circuit device 40 is a third integrated circuit device. The integrated circuit device 40 has an oven control circuit 46 as shown in FIG. 16 described later, and the temperature control signal GC from this oven control circuit 46 is input to the integrated circuit device 20, and heat generation control of the heat generation circuit 22 is performed. In this way, by the integrated circuit device 40 performing temperature control based on the temperature control signal GC, heat generation control of the heat generation circuit 22 of the integrated circuit device 20 is performed, and thereby temperature control of the first package 13 serving as a thermostat is performed, and a thermostat type crystal oscillator is realized. Note that in this embodiment, a modified embodiment without providing the integrated circuit device 40 is also possible. For example, the oven control circuit 46 may be provided in the integrated circuit device 20 to realize oven control of the thermostat type crystal oscillator.

[0090] Next, the structure of the oscillator 4 in FIG. 15 will be specifically described. In FIG. 15, the first package 13 is formed of, for example, ceramic or the like, has an accommodation space SP1 inside thereof, and the oscillator 10 and the integrated circuit device 30 are accommodated in this accommodation space SP1. The accommodation space SP1 is hermetically sealed and is desirably in a depressurized state close to a vacuum state. The first package 13 can preferably protect the oscillator 10 and the integrated circuit device 30 from impacts, dust, heat, moisture, etc. Also, the first package 13 is also used as a thermostat of the thermostat type crystal oscillator.

[0091] The first package 13 has a base 11 and a lid 12. Specifically, the first package 13 is composed of a base 11 that supports the vibrator 10 and the integrated circuit device 30, and a lid 12 joined to the base 11 so as to form an accommodation space SP1 therebetween. The vibrator 10 is supported via terminal electrodes on a stepped portion provided inside the base 11. The integrated circuit device 30 is disposed on the inner bottom surface of the base 11. Electrical connections between the integrated circuit device 30 and the vibrator 10, and between the integrated circuit device 30 and other integrated circuit devices 20, 40 are made using bonding wires BW and internal wirings of the first package 13 and the second package 17.

[0092] The second package 17 is formed of, for example, ceramic or the like, has an accommodation space SP2 inside thereof, and the first package 13 and the integrated circuit device 20 are accommodated in this accommodation space SP2. The accommodation space SP2 is hermetically sealed and desirably in a depressurized state close to a vacuum state. The second package 17 can preferably protect the integrated circuit device 20 and the first package 13 from impacts, dust, heat, moisture, etc.

[0093] The second package 17 has a base 15 and a lid 16. Specifically, the second package 17 is composed of a base 15 that supports the first package 13 and the like, and a lid 16 joined to the base 15 so as to form an accommodation space SP2 therebetween. The first package 13 is disposed on the inner bottom surface of the base 15.

[0094] Further, a recess is formed on the bottom surface of the second package 17. An integrated circuit device 40 is mounted on the bottom surface of the recess. Various modifications such as disposing the integrated circuit device 40 in the accommodation space SP2 of the second package 17 are possible. Further, external terminals 18 and 19 are formed on the outer bottom surface of the second package 17. The external terminals 18 and 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. Thereby, it becomes possible to output a clock signal or the like generated by the oscillator 4 to the external device. The electrical connection between the external terminals 18 and 19 and the integrated circuit device 40 or the like is performed using bonding wires BW or internal wiring such as the second package 17.

[0095] Note that the structure of the oscillator 4 is not limited to that shown in FIG. 15, and various modifications are possible. For example, an integrated circuit device 20 may be provided in the space in which the vibrator 10 is accommodated to perform oven control. For example, the integrated circuit device 20 may be provided between the stepped portion of the base 11 and the vibrator 10 so that the heat generated by the integrated circuit device 20 is directly transmitted to the vibrator 10. Alternatively, an oscillation circuit may be provided in the integrated circuit device 20 of the present embodiment, and the integrated circuit device 20 may be disposed in the space in which the vibrator 10 is accommodated.

[0096] FIG. 16 shows a configuration example of the oscillator 4. As shown in FIG. 16, the oscillator 4 of the present embodiment includes a vibrator 10 and integrated circuit devices 20, 30, and 40, and outputs a clock signal CK2.

[0097] The vibrator 10 is an element that generates mechanical vibration by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a crystal vibrating piece. For example, the vibrator 10 can be realized by a crystal vibrating piece that undergoes thickness-shear vibration with a cut angle such as AT cut or SC cut, a tuning fork type crystal vibrating piece, or a double tuning fork type crystal vibrating piece. Note that the vibrator 10 of the present embodiment can also be realized by various vibrating pieces such as vibrating pieces other than the thickness-shear vibration type, tuning fork type, or double tuning fork type, or piezoelectric vibrating pieces formed of materials other than crystal. For example, as the vibrator 10, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator as a silicon vibrator formed using a silicon substrate, or the like may be employed.

[0098] The integrated circuit device 30 includes an oscillation circuit 32, an output circuit 34, and a temperature sensor 36. The oscillation circuit 32 is a circuit that oscillates the vibrator 10. For example, the oscillation circuit 32 generates an oscillation signal by oscillating the vibrator 10. For example, the oscillation circuit 32 can be realized by a driving circuit for oscillation and active elements such as capacitors and resistors. The driving circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The driving circuit is the core circuit of the oscillation circuit 32, and the driving circuit oscillates the vibrator 10 by voltage-driving or current-driving the vibrator 10. As the oscillation circuit 32, various types of oscillation circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used. Also, a variable capacitance circuit may be provided in the oscillation circuit 32. And by adjusting the capacitance of this variable capacitance circuit, the oscillation frequency can be adjusted. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor. Note that the connection in the present embodiment is an electrical connection. An electrical connection means that electrical signals are communicably connected, and it is a connection that enables the transmission of information by electrical signals. The electrical connection may be a connection via passive elements or the like.

[0099] The output circuit 34 outputs a clock signal CK1 based on the oscillation signal from the oscillation circuit 32. For example, the output circuit 34 buffers the oscillation signal and outputs it as the clock signal CK1. Then, this clock signal CK1 is input to the integrated circuit device 40.

[0100] The temperature sensor 36 is a sensor that detects temperature. Specifically, the temperature sensor 36 detects the ambient temperature and outputs a temperature detection signal TS2 that changes according to the ambient temperature to the integrated circuit device 40. For example, the temperature sensor 36 uses a circuit element with temperature dependence to generate the temperature detection signal TS2. For example, the temperature sensor 36 outputs a temperature detection signal TS2 whose voltage changes depending on temperature by using the temperature dependence of the forward voltage of the PN junction. Alternatively, the temperature sensor 36 may output digital temperature detection data as the temperature detection signal TS2.

[0101] The integrated circuit device 20 includes a heating circuit 22 and a temperature sensor 24 as described in FIGS. 1 and 2. The heating of the heating circuit 22 is controlled based on the temperature control signal GC from the integrated circuit device 40. Also, the temperature sensor 24 generates a temperature detection signal TS and outputs it to the integrated circuit device 40. Note that the temperature sensor 24 may output digital temperature detection data as the temperature detection signal TS.

[0102] The integrated circuit device 40 includes a clock signal generation circuit 42, an output circuit 43, a processing circuit 44, an oven control circuit 46, and a temperature sensor 48. The clock signal generation circuit 42 receives the clock signal CK1 generated based on the oscillation signal of the vibrator 10 from the integrated circuit device 30. The clock signal generation circuit 42 is, for example, a PLL circuit, generates a clock signal CK2 with a frequency multiplied by the clock signal CK1, and this clock signal CK2 is buffered by the output circuit 43 and output to the outside. As the clock signal generation circuit 42, for example, a fractional-N type PLL circuit capable of fractional frequency multiplication can be used.

[0103] The processing circuit 44 performs temperature compensation processing, various correction processes, and control processing for each circuit block of the integrated circuit device 40. The processing circuit 44 performs temperature compensation processing to keep the frequency of the clock signal CK2 constant even when the temperature fluctuates. For example, in the integrated circuit device 40, a temperature detection signal TS from the temperature sensor 24 of the integrated circuit device 20 and a temperature detection signal TS2 from the temperature sensor 36 of the integrated circuit device 30 are input. Also, a temperature sensor 48 is provided inside the integrated circuit device 40. The processing circuit 44 performs temperature compensation processing based on the temperature detection results of these temperature sensors 24, 36, and 48. Specifically, the processing circuit 44 includes a digital signal processing circuit 45 that performs digital signal processing. The digital signal processing circuit 45 operates as a DSP (Digital Signal Processor) and performs digital signal processing including, for example, temperature compensation processing. The digital signal processing circuit 45 also performs digital filter processing as digital signal processing. For example, it performs digital filter processing such as FIR (Finite Impulse Response) and IIR (Infinite Impulse Response). The digital signal processing circuit 45 also performs digital signal processing for aging correction. For example, it performs Kalman filter processing as digital signal processing for aging correction. The digital signal processing circuit 45 also performs neural network processing as digital signal processing. For example, based on the temperature detection results of the external temperature sensors 24, 36 and the internal temperature sensor 48 of the integrated circuit device 40, it performs neural network processing of AI (Artificial Intelligence) to estimate the temperature of the vibrator 10.

[0104] The oven control circuit 46 controls the heat generation of the heat generation circuit 22 by outputting a temperature control signal GC to the heat generation circuit 22 of the integrated circuit device 20, thereby performing oven control on the vibrator 10 provided in the constant temperature bath. That is, the oven control circuit 46 controls the heat generation of the heat generation circuit 22 to perform temperature control on the constant temperature bath, which is the oven where the vibrator 10 is provided. For example, the oven control circuit 46 performs temperature control so that the oven temperature, which is the temperature of the constant temperature bath, reaches the set temperature. In FIG. 15, the first package 13 functions as a constant temperature bath. The oven control circuit 46 can be realized by, for example, a PI control circuit (Proportional-Integral Controller) realized by an integration circuit composed of an operational amplifier, resistors, capacitors, etc.

[0105] As described above, the integrated circuit device of the present embodiment includes a heat generation circuit controlled based on a temperature control signal. The heat generation circuit includes a heat generation transistor having a plurality of transistors connected in parallel and whose gate voltage is controlled based on the temperature control signal, and the resistance value of the source resistance of the heat generation transistor is smaller than the resistance value of the drain resistance of the heat generation transistor.

[0106] In the present embodiment, the heat generation transistor having a plurality of transistors whose gate voltage is controlled based on the temperature control signal has a source resistance value smaller than the drain resistance value. By making the source resistance value smaller than the drain resistance value in this way, when the temperature control signal is input to the gate, it becomes possible to suppress a decrease in the gate-source voltage of the heat generation transistor, and it becomes possible to suppress a decrease in the heat generation ability caused by the parasitic resistance of the heat generation transistor.

[0107] Also, in the present embodiment, in a plan view, a plurality of transistors may be arranged side by side such that the longitudinal direction of the gates is along a first direction and along a second direction orthogonal to the first direction. And the plurality of transistors includes a first transistor, and in a plan view, the width of the first source region of the first transistor in the second direction may be larger than the width of the first drain region of the first transistor in the second direction.

[0108] By making the width of the first source region of the first transistor larger than the width of the first drain region in this way, it becomes possible to make the resistance value of the source resistance smaller than the resistance value of the drain resistance, and it becomes possible to suppress the gate-source voltage of the heat-generating transistor from decreasing due to the source resistance and the heat generation performance from decreasing.

[0109] Also, in the present embodiment, the plurality of transistors includes a second transistor, and in a plan view, the width of the second source region of the second transistor in the second direction may be larger than the width of the second drain region of the second transistor in the second direction.

[0110] By making the width of the second source region of the second transistor larger than the width of the second drain region in this way, it becomes possible to make the resistance value of the source resistance smaller than the resistance value of the drain resistance, and it becomes possible to suppress the gate-source voltage of the heat-generating transistor from decreasing due to the source resistance and the heat generation performance from decreasing.

[0111] Also, in the present embodiment, the first source region and the second source region may be a shared source region of the first transistor and the second transistor.

[0112] By sharing the source region between the first transistor and the second transistor in this way, even when the widths of the source regions of the first transistor and the second transistor are increased, an increase in the width of the heat-generating transistor in the second direction can be suppressed. Therefore, by increasing the widths of the source regions of the first transistor and the second transistor, the resistance value of the source resistance can be decreased, and an increase in the layout area of the heat-generating transistor can also be suppressed.

[0113] Also, in this embodiment, the plurality of transistors may include a third transistor provided in the first direction of the first transistor. And in a plan view, the width of the third source region of the third transistor in the second direction may be larger than the width of the third drain region of the third transistor in the second direction. And the first gate of the first transistor and the third gate of the third transistor may be arranged with a shift in position in the second direction.

[0114] In this way, a layout arrangement can be realized in which the shapes of the channel-side ends of the first transistor and the third transistor are stepped in the first direction. And also in this case, since the widths of the source regions of the first transistor and the third transistor are larger than the widths of the drain regions, it becomes possible to make the resistance value of the source resistance of the heat-generating transistor smaller than the resistance value of the drain resistance.

[0115] Also, in this embodiment, the plurality of transistors include a third transistor provided in the first direction of the first transistor and a fourth transistor provided in the first direction of the second transistor, the first source region of the first transistor and the second source region of the second transistor are shared source regions, and the third source region of the third transistor and the fourth source region of the fourth transistor may be shared source regions. And the third gate of the third transistor may be arranged with a shift in position in the second direction with respect to the first gate of the first transistor, and the fourth gate of the fourth transistor may be arranged with a shift in position in the direction opposite to the second direction with respect to the second gate of the second transistor.

[0116] In this way, it is possible to realize a layout arrangement in which the shapes of the channel-side ends of the first transistor and the third transistor are stepped in the first direction, and the shapes of the channel-side ends of the second transistor and the fourth transistor are stepped in the first direction. And since the width of the shared source region of the first transistor and the second transistor is larger than the width of the shared source region of the third transistor and the fourth transistor, it becomes possible to have a layout arrangement in which the width of the shared source region through which more current flows is increased.

[0117] Also, in this embodiment, the width of the shared source region of the first transistor and the second transistor may be larger than the widths of the first drain region of the first transistor and the second drain region of the second transistor, and the width of the shared source region of the third transistor and the fourth transistor may be larger than the widths of the third drain region of the third transistor and the fourth drain region of the fourth transistor.

[0118] In this way, by making the width of the shared source region of the first transistor and the second transistor larger than the width of its drain region, and also making the width of the shared source region of the third transistor and the fourth transistor larger than the width of its drain region, it is possible to make the resistance value of the source resistance of the heat-generating transistor smaller than the resistance value of the drain resistance. Therefore, it becomes possible to suppress the reduction in the gate-source voltage of the heat-generating transistor due to the source resistance and the consequent reduction in the heat generation performance.

[0119] Also, in this embodiment, the outer shape of the integrated circuit device has a first side and a second side that is the opposite side of the first side, and along the first side, a ground pad electrically connected to the source of the heat-generating transistor is arranged, and along the second side, a power supply pad for supplying a power supply voltage to the drain of the heat-generating transistor may be arranged. And the heat-generating transistor may be arranged between the ground pad and the power supply pad.

[0120] By doing so, it becomes possible to electrically connect the ground pad and the source of the heat-generating transistor through a short-circuit path, and also to electrically connect the drain of the heat-generating transistor and the power supply pad through a short-circuit path or the like. Therefore, it is possible to reduce the adverse effects exerted by the parasitic resistance and the like existing in the path on the heat generation performance of the heat-generating transistor, and improve the heat generation performance.

[0121] In addition, in the present embodiment, a current limiting resistor is included, one end of which is electrically connected to the power supply pad and the other end of which is electrically connected to the drain of the heat-generating transistor, and the current limiting resistor may be arranged between the heat-generating transistor and the power supply pad.

[0122] By doing so, one end of the current limiting resistor and the power supply pad can be connected by a short-circuit path, and the other end of the current limiting resistor and the drain of the heat-generating transistor can be connected by a short-circuit path. Therefore, the heat-generating transistor, the current limiting resistor, and the power supply pad can be arranged in a compact layout, and a reduction in the area of the integrated circuit device can be realized.

[0123] In addition, in the present embodiment, the current limiting resistor may include a plurality of diffusion resistors connected in parallel between the power supply pad and the drain of the heat-generating transistor.

[0124] By configuring the current limiting resistor with a plurality of diffusion resistors connected in parallel between the power supply pad and the drain of the heat-generating transistor in this way, it becomes possible to realize a current limiting resistor with a desired resistance value with a small layout area.

[0125] In addition, in the present embodiment, when the direction from the first side to the second side is defined as the first direction and the direction orthogonal to the first direction is defined as the second direction, the longitudinal direction of each diffusion resistor may be along the first direction and they may be arranged side by side along the second direction.

[0126] By arranging a plurality of diffusion resistors having a narrow width in the second direction along the second direction in this way, it becomes possible to realize a current limiting resistor having a desired resistance value while reducing the length in the first direction of the layout region of the current limiting resistor, and it becomes possible to achieve both the compactness of the integrated circuit device and the current limiting resistor having the desired resistance value.

[0127] Further, in the present embodiment, it may include a plurality of vias arranged so as to overlap with the ground pad in a plan view, and one end of the plurality of vias is electrically connected to the ground pad and the other end is electrically connected to the source of the heat generating transistor.

[0128] In this way, the ground pad can be electrically connected to the diffusion region directly below through a plurality of vias and can be electrically connected to the source of the heat generating transistor. Therefore, it becomes possible to reduce the parasitic resistance formed on the source side of the heat generating transistor, and it becomes possible to suppress the deterioration of the heat generation performance of the heat generating transistor caused by the parasitic resistance.

[0129] Further, the present embodiment relates to an oscillator including the integrated circuit device described above and a vibrator whose temperature is controlled by the integrated circuit device.

[0130] In this way, it becomes possible to control the temperature of the vibrator by the heat generation of the heat generating circuit of the integrated circuit device.

[0131] Further, the present embodiment may include a first integrated circuit device which is an integrated circuit device, a vibrator, a second integrated circuit device having an oscillation circuit for oscillating the vibrator, a first package for housing the vibrator and the second integrated circuit device, and a second package for housing the first integrated circuit device and the first package.

[0132] In this way, by controlling the heat generation of the heat generating circuit of the first integrated circuit device based on the temperature control signal, the temperature of the first package which is a thermostatic chamber is controlled, and it becomes possible to realize a thermostatic chamber type crystal oscillator.

[0133] Also, in this embodiment, it may include a third integrated circuit device provided in the second package and outputting a temperature control signal to the first integrated circuit device.

[0134] In this way, by the third integrated circuit device performing temperature control based on the temperature control signal, heat generation control of the heat generating circuit of the first integrated circuit device is performed, and thereby temperature control of the first package serving as a thermostat is performed, so that a thermostat type crystal oscillator is realized.

[0135] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modified examples are intended to be included in the scope of the present disclosure. For example, in the specification or drawings, a term described at least once together with a broader or synonymous different term can be replaced with that different term anywhere in the specification or drawings. Also, all combinations of this embodiment and modified examples are included in the scope of the present disclosure. Further, the configuration, operation, etc. of the integrated circuit device and oscillator are not limited to those described in this embodiment, and various modified implementations are possible.

Explanation of Reference Numerals

[0136] 4…Oscillator, 10…Vibrator, 11…Base, 12…Lid, 13…First Package, 15…Base, 16…Lid, 17…Second Package, 18…External Terminal, 19…External Terminal, 20…Integrated Circuit Device, 22…Heat - generating Circuit, 24…Temperature Sensor, 30…Integrated Circuit Device, 32…Oscillation Circuit, 34…Output Circuit, 36…Temperature Sensor, 40…Integrated Circuit Device, 42…Clock Signal Generation Circuit, 43…Output Circuit, 44…Processing Circuit, 45…Digital Signal Processing Circuit, 46…Oven Control Circuit, 48…Temperature Sensor, ALD, ALS…Metal Wiring, BW…Bonding Wire, CK1, CK2…Clock Signal, D…Drain Region, DF1, DF2…Diffusion Region, DI1, DI2, DI3, DI4…Diode, DR1, DR2, DR3, DR4…Direction, G…Gate, GC…Temperature Control Signal, GVC1…First Via Group, GVC2…Second Via Group, GVC3…Third Via Group, HL…Hole, Id…Current, LP1, LP2, LP3, LP4…Wiring Portion, PGC…Pad, PGND…Ground Pad, PTS…Pad, PVDD…Power Supply Pad, R1, R2…Resistance Value, RD…Drain Resistance, RE1…Resistance, RE2…Resistance, RL…Current - limiting Resistance, RL1~RLm…Diffusion Resistance, RS…Source Resistance, RT…Resistance, S…Source Region, SD1, SD2, SD3, SD4…Side, SP1, SP2…Accommodation Space, T1, T2, T3, T3B, T4, T4B, T5, T6…Transistor, TR…Heat - generating Transistor, TS, TS2…Temperature Detection Signal, VC, VCD, VCS…Via

Claims

1. including a heating circuit controlled based on a temperature control signal, the heating circuit includes a heating transistor having a plurality of transistors connected in parallel and having a gate voltage controlled based on the temperature control signal, the resistance value of the source resistance of the heating transistor is smaller than the resistance value of the drain resistance of the heating transistor, the outer shape of the integrated circuit device has a first side and a second side that is the opposite side of the first side, along the first side, a ground pad electrically connected to the source of the heating transistor is arranged, along the second side, a power supply pad for supplying a power supply voltage to the drain of the heating transistor is arranged, the heating transistor is arranged between the ground pad and the power supply pad, and the integrated circuit device is characterized by this.

2. In the integrated circuit device according to Claim 1, in a plan view, the plurality of transistors are arranged side by side along a second direction orthogonal to a first direction along which the longitudinal direction of the gate extends, the plurality of transistors include a first transistor, in the plan view, the width of the first source region of the first transistor in the second direction is larger than the width of the first drain region of the first transistor in the second direction, and the integrated circuit device is characterized by this.

3. In the integrated circuit device according to Claim 2, the plurality of transistors include a second transistor, in the plan view, the width of the second source region of the second transistor in the second direction is larger than the width of the second drain region of the second transistor in the second direction, and the integrated circuit device is characterized by this.

4. In the integrated circuit device according to Claim 3, The integrated circuit device is characterized in that the first source region and the second source region are shared source regions of the first transistor and the second transistor.

5. In the integrated circuit device according to claim 3 or 4, the plurality of transistors includes a third transistor provided in the first direction of the first transistor, in the plan view, the width of the third source region of the third transistor in the second direction is larger than the width of the third drain region of the third transistor in the second direction, the first gate of the first transistor and the third gate of the third transistor are arranged with a displacement in the second direction, and the integrated circuit device is characterized in that.

6. In the integrated circuit device according to claim 3, the plurality of transistors includes a third transistor provided in the first direction of the first transistor and a fourth transistor provided in the first direction of the second transistor, the first source region of the first transistor and the second source region of the second transistor are shared source regions, the third source region of the third transistor and the fourth source region of the fourth transistor are shared source regions, the third gate of the third transistor is arranged with a displacement in the second direction with respect to the first gate of the first transistor, the fourth gate of the fourth transistor is arranged with a displacement in the direction opposite to the second direction with respect to the second gate of the second transistor, and the integrated circuit device is characterized in that.

7. In the integrated circuit device according to claim 6, the width of the shared source region of the first transistor and the second transistor is larger than the widths of the first drain region of the first transistor and the second drain region of the second transistor, An integrated circuit device, characterized in that the width of the shared source region of the third transistor and the fourth transistor is larger than the widths of the third drain region of the third transistor and the fourth drain region of the fourth transistor. Claim 8 In the integrated circuit device according to any one of claims 1 to 7, including a current limiting resistor having one end electrically connected to the power supply pad and the other end electrically connected to the drain of the heat generating transistor, An integrated circuit device, characterized in that the current limiting resistor is disposed between the heat generating transistor and the power supply pad. Claim 9 In the integrated circuit device according to claim 8, An integrated circuit device, characterized in that the current limiting resistor includes a plurality of diffusion resistors connected in parallel between the power supply pad and the drain of the heat generating transistor. Claim 10 In the integrated circuit device according to claim 9, when the direction from the first side to the second side is defined as the first direction and the direction orthogonal to the first direction is defined as the second direction, the longitudinal direction of each diffusion resistor is along the first direction and the plurality of diffusion resistors are arranged side by side along the second direction. An integrated circuit device characterized by this. Claim 11 In the integrated circuit device according to any one of claims 1 to 10, including a plurality of vias arranged so as to overlap the ground pad in a plan view, An integrated circuit device, characterized in that one end of each of the plurality of vias is electrically connected to the ground pad and the other end is electrically connected to the source of the heat generating transistor. Claim 12 An integrated circuit device according to any one of claims 1 to 11, a vibrator temperature-controlled by the integrated circuit device, An oscillator, characterized by including this. Claim 13 A first integrated circuit device, a vibrator temperature-controlled by the first integrated circuit device, a second integrated circuit device having an oscillation circuit for oscillating the vibrator, a first package housing the vibrator and the second integrated circuit device, a second package housing the first integrated circuit device and the first package, and comprising: The first integrated circuit device includes a heating circuit controlled based on a temperature control signal, the heating circuit includes a heating transistor having a gate voltage controlled based on the temperature control signal and a plurality of transistors connected in parallel, an oscillator, wherein a resistance value of a source resistance of the heating transistor is smaller than a resistance value of a drain resistance of the heating transistor.

14. The oscillator according to claim 13, characterized by comprising a third integrated circuit device provided in the second package and outputting the temperature control signal to the first integrated circuit device.

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