Semiconductor device

Abstract

Provided is a novel semiconductor device. This semiconductor device is provided with: an oxide semiconductor which is a first semiconductor; silicon which is a second semiconductor; and a plurality of memory cells aligned contiguously in a first direction. One of the memory cells is provided with a writing transistor and a reading transistor. The first and second semiconductors extend in the first direction. A part of the first semiconductor functions as a channel forming region for the writing transistor. A part of the second semiconductor functions as a channel forming region for the reading transistor. The second semiconductor is provided with a region which comes into contact with a first layer containing a first metal element.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Note that in this specification and the like, the semiconductor device refers to all things that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, and electronic devices may include semiconductor elements or semiconductor circuits. Also, display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices.

Background Art

[0004] In recent years, with the increase in the amount of data to be handled, semiconductor devices having a larger storage capacity have been demanded. In order to increase the storage capacity per unit area, a three-dimensional structure storage device in which memory cells are stacked is known (Patent Document 1). In a three-dimensional structure storage device, the semiconductor layer is often provided so as to extend in the stacking direction of the memory cells. Also, in a three-dimensional structure storage device, a semiconductor containing many grain boundaries such as polycrystalline silicon is often used for the semiconductor layer.

[0005] Since polycrystalline silicon has many grain boundaries, it is difficult to improve the operating speed and reduce the variation in characteristics between memory cells. For the purpose of reducing grain boundaries and increasing the grain size, a crystallization technique for producing crystalline silicon using a catalyst element such as nickel (Ni) is known (Patent Document 2). Patent Document 2 also discloses the growth mechanism of crystals using a catalyst element and the technical idea of fixing the catalyst element used for crystallization in a gettering region.

[0006] Patent Document 3 discloses the technical idea of applying the crystallization technique using a catalyst element to a memory device having a three-dimensional structure. In recent years, an oxide semiconductor, which is a kind of metal oxide, has attracted attention. Non-Patent Document 1 discloses CAAC-IGZO as an oxide semiconductor. Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO and the like.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] One aspect of the present invention has an object of providing a highly reliable memory device. Or, one object is to provide a memory device with a large storage capacity. Or, one object is to provide a memory device with a small occupied area. Or, one object is to provide a memory device with a high operating speed. Or, one object is to provide a memory device with a low manufacturing cost. Or, one object is to provide a novel memory device. Or, one object is to provide a highly reliable semiconductor device. Or, one object is to provide a semiconductor device with a small occupied area. Or, one object is to provide a semiconductor device with a high operating speed. Or, one object is to provide a semiconductor device with a low manufacturing cost. Or, one object is to provide a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be naturally clarified from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a semiconductor device including a first semiconductor extending in a first direction, a second semiconductor extending in the first direction, and a plurality of memory cells connected in the first direction, wherein each memory cell includes a first transistor and a second transistor, a part of the first semiconductor functions as a channel formation region of the first transistor, a part of the second semiconductor functions as a channel formation region of the second transistor, the first semiconductor includes an oxide semiconductor, the second semiconductor includes silicon, the second semiconductor has a region in contact with a first layer, and the first layer includes a first metal element.

[0012] Another aspect of the present invention includes a structure extending in a first direction, a plurality of first conductors extending in a second direction intersecting the first direction, and a plurality of second conductors extending in the second direction. The structure includes a third conductor, a first insulator, a plurality of fourth conductors, a first semiconductor, a second insulator, a second semiconductor, and a third insulator. At each intersection of the plurality of first conductors and the structure, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged outside the third conductor. At each intersection of the plurality of second conductors and the structure, the first insulator, the fourth conductor, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged outside the third conductor. The first semiconductor includes an oxide semiconductor, the second semiconductor includes silicon, the second semiconductor has a region in contact with a first layer, and the first layer includes a first metal element. This is a semiconductor device.

[0013] The first metal element is an element that functions as a catalyst element. For example, nickel can be used as the first metal element. The first layer may contain impurity elements such as phosphorus.

[0014] The oxide semiconductor preferably contains at least one of indium or zinc. In particular, it preferably contains indium and zinc. Also, various crystalline oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used as the oxide semiconductor.

Advantages of the Invention

[0015] According to one aspect of the present invention, a highly reliable memory device can be provided. Or, a memory device with a large storage capacity can be provided. Or, a memory device with a small occupied area can be provided. Or, a memory device with a high operating speed can be provided. Or, a memory device with a low manufacturing cost can be provided. Or, a novel memory device can be provided. Or, a highly reliable semiconductor device can be provided. Or, a semiconductor device with a small occupied area can be provided. Or, a semiconductor device with a high operating speed can be provided. Or, a semiconductor device with a low manufacturing cost can be provided. Or, a novel semiconductor device can be provided.

[0016] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0017] FIG. 1 is a perspective view of the memory device. FIG. 2 is a cross-sectional view of the memory device. FIG. 3 is a cross-sectional view of the memory string. FIG. 4 is a cross-sectional view of the memory string. FIGS. 5A and 5B are cross-sectional views of the memory string. FIGS. 6A and 6B are cross-sectional views of the memory string. FIG. 7A is a cross-sectional view of the memory element. FIG. 7B is a perspective cross-sectional view of the memory element. FIGS. 8A and 8B are cross-sectional views of the memory string. FIGS. 9A to 9F are cross-sectional views of the memory string. FIGS. 10A and 10B are cross-sectional views of the memory string. FIG. 11A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor. FIG. 11B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film. FIG. 11C is a diagram for explaining the selected area electron diffraction pattern of a CAAC-IGZO film. FIGS. 12A to 12C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 13A to 13C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 14A to 14C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 15A to 15C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 16A to 16C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 17A to 17C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 18A to 18C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 19A to 19C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 20A to 20C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 21A to 21C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 22A to 22C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 23A to 23C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 24A to 24C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 25A to 25D are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. FIGS. 26A to 26C are cross-sectional views for explaining the manufacturing process of a semiconductor device according to one embodiment of the present invention. Figs. 27A to 27C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 28A to 28C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 29A to 29C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 30A to 30C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 31A to 31C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 32A to 32C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 33A to 33C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Figs. 34A to 34C are cross-sectional views for explaining a manufacturing process of a semiconductor device according to an aspect of the present invention. Fig. 35 is a diagram for explaining a circuit configuration example of a memory string. Fig. 36 is an equivalent circuit diagram of a memory element MC. Fig. 37 is a diagram for explaining a circuit configuration example of a memory string. Fig. 38 is a diagram for explaining a circuit configuration example of a memory string. Fig. 39 is a timing chart for explaining a write operation example of a memory string. Figs. 40A and 40B are circuit diagrams for explaining a write operation example of a memory string. Figs. 41A and 41B are circuit diagrams for explaining a write operation example of a memory string. Figs. 42A and 42B are circuit diagrams for explaining a write operation example of a memory string. Figs. 43A and 43B are circuit diagrams for explaining a write operation example of a memory string. Figs. 44A and 44B are timing charts for explaining a read operation example of a memory string. Figs. 45A and 45B are circuit diagrams for explaining a read operation example of a memory string. Figures 46A and 46B are circuit diagrams for explaining an example of a read operation of a memory string. Figures 47A and 47B are diagrams for explaining the Id-Vg characteristics of a transistor. Figure 48 is a block diagram for explaining an example of the configuration of a semiconductor device. Figures 49A to 49C are perspective views for explaining an example of the configuration of a semiconductor device. Figure 50 is a cross-sectional view for explaining a semiconductor device according to one aspect of the present invention. Figures 51A to 51E are diagrams for explaining an example of a storage device. Figures 52A to 52G are diagrams for explaining an example of an electronic device.

Mode for Carrying Out the Invention

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof will be omitted.

[0019] In addition, in the drawings and the like, the positions, sizes, ranges, etc. of the respective configurations shown may not represent the actual positions, sizes, ranges, etc. in order to facilitate the understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but it may not be reflected in the drawing for the sake of easy understanding.

[0020] In addition, in the drawings and the like, for the sake of easy understanding of the description, the description of some components may be omitted.

[0021] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0022] Also, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of the wiring or electrode may function as a terminal.

[0023] Note that in this specification and the like, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0024] Also, since the functions of the source and drain are interchanged depending on operating conditions such as when different polarities of transistors are adopted or when the direction of current changes in circuit operation, it is difficult to limit which is the source or drain. Therefore, in this specification, the terms source and drain can be used interchangeably.

[0025] Also, in this specification and the like, "electrically connected" includes cases where they are directly connected and cases where they are connected via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only the wiring extends.

[0026] In addition, in this specification and the like, "parallel" means, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" mean, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0027] In addition, in this specification and the like, regarding numerical values and measured values, or regarding things, methods, and events that can be converted into numerical values or measured values, when using terms such as "identical", "the same", "equal", or "uniform", unless otherwise specified, they shall include an error of plus or minus 20%.

[0028] Also, in this specification and the like, the terms "adjacent" and "proximate" do not limit that the components are in direct contact. For example, in the expression "electrode B adjacent to insulating layer A", it is not necessary that insulating layer A and electrode B are formed in direct contact, and those including other components between insulating layer A and electrode B are not excluded.

[0029] Also, voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged with each other. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0030] Note that even when denoted as "semiconductor", for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "semiconductor" replaced by "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be interchangeable with each other.

[0031] Also, even when denoted as "semiconductor", for example, when the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use it by replacing "semiconductor" with "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be interchangeable with each other.

[0032] Note that ordinal numbers such as "first" and "second" in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as process order or stacking order. Also, even for terms that do not have ordinal numbers in this specification and the like, ordinal numbers may be attached in the claims to avoid confusion of components. Also, even for terms that have ordinal numbers in this specification and the like, different ordinal numbers may be attached in the claims. Also, even for terms that have ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0033] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conducting state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conducting state").

[0034] Also, in this specification and the like, "on-current" may refer to the current flowing between the source and drain when the transistor is in the on state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the off state.

[0035] In this specification and the like, the high power supply potential VDD (hereinafter also simply referred to as "VDD", "H potential", or "H") refers to a power supply potential having a potential higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS", "L potential", or "L"). Also, VSS refers to a power supply potential having a potential lower than VDD. Further, the ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0036] Also, unless otherwise specified, the transistors shown in this specification and the like are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, its threshold voltage (also referred to as "Vth") is greater than 0V. Also, unless otherwise specified, "supplying an H potential to the gate of the transistor" may be synonymous with "turning on the transistor". Also, unless otherwise specified, "supplying an L potential to the gate of the transistor" may be synonymous with "turning off the transistor".

[0037] In this specification and the like, the gate refers to a gate electrode and part or all of a gate wiring. The gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0038] In this specification and the like, the source refers to a source region, a source electrode, and part or all of a source wiring. The source region refers to a region in a semiconductor layer having a resistivity equal to or less than a certain value. The source electrode refers to a conductive layer connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0039] In addition, in this specification and the like, "drain" refers to a part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to a region in the semiconductor layer where the resistivity is equal to or less than a certain value. The drain electrode refers to a conductive layer of a portion connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0040] In addition, in drawings and the like, in order to make the potential of a wiring, an electrode, or a conductor, etc. easy to understand, "H" indicating the H potential or "L" indicating the L potential may be added adjacent to the wiring, the electrode, or the conductor, etc. Further, for a wiring, an electrode, or a conductor, etc. where a potential change has occurred, "H" or "L" may be added in a surrounded character. Further, when a transistor is in an off state, an "×" symbol may be added superimposed on the transistor.

[0041] In general, a "capacitor" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification and the like, the "capacitor element" includes the case where it is the aforementioned "capacitor". That is, in this specification and the like, the "capacitor element" includes those having a configuration in which two electrodes face each other with an insulator in between, those having a configuration in which two wirings face each other with an insulator in between, or those in which two wirings are arranged with an insulator in between.

[0042] In addition, in this specification and the like, when the same reference numerals are used for a plurality of elements, when it is particularly necessary to distinguish them, identification symbols such as "a", "A", "_1", "_2", "[m,n]", etc. may be added to the reference numerals for description. For example, one of two wirings GL may be described as wiring GLa and the other as wiring GLb.

[0043] (Embodiment 1) FIG. 1 shows a perspective view of a memory device 100 according to one aspect of the present invention. The memory device 100 is a memory device having a three-dimensional stacked structure. FIG. 2 is a cross-sectional view of the portion A1 - A2 shown by the dashed-dotted line in FIG. 1. In FIG. 1 and the like, arrows indicating the X direction, Y direction, and Z direction may be attached. The X direction, Y direction, and Z direction are directions that are orthogonal to each other. In this specification and the like, the direction perpendicular to the upper surface of the substrate 121 described later is defined as the Z direction.

[0044] Also, in this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction". Another one may be referred to as the "second direction" or "second direction". And the remaining one may be referred to as the "third direction" or "third direction".

[0045] FIG. 2 shows a cross-section of the X-Z plane. As described above, for the sake of clarity of explanation, in FIGS. 1 and 2 and the like, some of the components may be omitted.

[0046] <Configuration Example of Memory Device> The memory device 100 according to one aspect of the present invention has a memory cell array 110 (see FIG. 1). The memory cell array 110 has a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane. FIG. 3 shows a cross-sectional configuration example of the memory string 120.

[0047] The memory string 120 includes a plurality of memory elements MC (also referred to as "memory cells") connected in series in the Z direction. In other words, the memory string 120 includes a plurality of memory elements MC connected in series. FIG. 3 shows a case where 5 memory elements MC are connected in series, but the number of memory elements MC included in the memory string 120 is not limited to 5. If the number of memory elements MC included in the memory string 120 is n, n may be an integer of 2 or more.

[0048] In FIG. 3, five memory elements MC are shown as memory element MC_1 to memory element MC_5. When explaining matters common to memory elements MC_1 to MC_5, they are simply shown as "memory element MC". The same applies to other components such as conductor WWL, conductor RWL, and insulator 123.

[0049] Memory string 120 has a transistor STr1 electrically connected to memory element MC_1 and a transistor STr2 electrically connected to memory element MC_5.

[0050] Further, memory device 100 has a plurality of conductors WWL, a plurality of conductors RWL, and conductor SG above substrate 121. The plurality of conductors WWL, the plurality of conductors RWL, and conductor SG extend in the X direction (see FIGS. 1 and 2). Also, conductors WWL, conductor RWL, and conductor SG have a region overlapping memory cell array 110. Conductors WWL, conductor RWL, and conductor SG are stacked in a stepped manner outside memory cell array 110.

[0051] Conductor SG is provided in a layer lower than the plurality of conductors WWL and the plurality of conductors RWL. In FIG. 3, layer 122 is provided on substrate 121, insulator 123_1 is provided on layer 122, and conductor SG is provided on insulator 123_1. Also, conductors WWL and conductor RWL are alternately stacked via insulator 123. For example, in FIG. 3, insulator 123_2 is provided on conductor SG, conductor RWL_1 is provided on insulator 123_2, insulator 123_3 is provided on conductor RWL_1, conductor WWL_1 is provided on insulator 123_3, and insulator 123_4 is provided on conductor WWL_1. Although details will be described later, layer 122 functions as a gettering layer.

[0052] The memory string 120 has a structure 160. The structure 160 is provided so as to penetrate a conductor WWL, a conductor RWL, a conductor SG, and an insulator 123. Further, the structure 160 has a region in contact with the layer 122. A cross-sectional configuration example of the structure 160 is shown in FIG. 4. Note that FIGS. 4 and 3 are cross-sectional views of the same part. In FIG. 4, the conductor WWL, the conductor RWL, the conductor SG, the insulator 123, the layer 122, and the substrate 121 are shown by broken lines.

[0053] The structure 160 has a columnar structure including a conductor 130, an insulator 129, a semiconductor 127, an insulator 126, a semiconductor 125, an insulator 124, and a plurality of conductors 128. In FIG. 4, a center axis 169 of the memory string 120 extending in the Z direction is shown by a two-dot chain line. More specifically, the conductor 130 extends along the center axis 169, and the insulator 129 is provided adjacent to the side surface of the conductor 130. Further, the semiconductor 127 is provided adjacent to the insulator 129, and the insulator 126 is provided adjacent to the semiconductor 127. Further, the semiconductor 125 is provided adjacent to the insulator 126, and the insulator 124 is provided adjacent to the semiconductor 125. The semiconductor 125 has a region in contact with the layer 122. Further, at the intersection of the conductor RWL and the structure 160, a conductor 128 is provided between the insulator 129 and the semiconductor 127.

[0054] FIG. 5A shows a cross-sectional view of the portion B1 - B2 shown by a one-dot chain line in FIG. 3 as viewed from the Z direction. FIG. 5A is a cross-sectional view of the intersection of the conductor WWL and the structure 160. At the intersection, each of the insulator 129, the semiconductor 127, the insulator 126, the semiconductor 125, and the insulator 124 is provided concentrically outside the conductor 130.

[0055] FIG. 5B shows a cross-sectional view of the portion C1 - C2 shown by a one-dot chain line in FIG. 3 as viewed from the Z direction. FIG. 5B is a cross-sectional view of the intersection of the conductor RWL and the structure 160. At the intersection, each of the insulator 129, the conductor 128, the semiconductor 127, the insulator 126, the semiconductor 125, and the insulator 124 is provided concentrically outside the conductor 130.

[0056] In FIGS. 5A and 5B, a cross-section (X-Y cross-section) of one memory string 120 is illustrated, while FIGS. 6A and 6B show an example in which a plurality of memory strings 120 are provided. The plurality of memory strings 120 may be arranged side by side in the X direction, may be arranged side by side in the Y direction, or may be arranged in a matrix.

[0057] An enlarged view of the region 105 shown by the dashed two-dot line in FIG. 3 is shown in FIG. 7A. FIG. 7A corresponds to a cross-sectional view of the memory element MC. A perspective cross-sectional view of the memory element MC is shown in FIG. 7B. Note that, in order to make the structure of the memory element MC easier to understand, the description of the insulator 123 is omitted in FIG. 7B.

[0058] The intersection of the conductor WWL and the structure 160 functions as the transistor WTr. Also, the intersection of the conductor RWL and the structure 160 functions as the transistor RTr. Specifically, the conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the back gate electrode of the transistor WTr. Also, a part of the semiconductor 127 functions as the semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via a part of each of the insulator 126, the semiconductor 125, and the insulator 124. Note that, in this embodiment and the like, an example in which a part of the conductor WWL functions as the gate electrode is shown, but the gate electrode and the conductor WWL may be provided independently of each other and electrically connected to each other.

[0059] The conductor 128 functions as the gate electrode of the transistor RTr. Also, the conductor RWL functions as the back gate electrode of the transistor RTr. A part of the semiconductor 125 functions as the semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor 128) via a part of the insulator 126. Also, the semiconductor layer in which the channel of the transistor RTr is formed overlaps with the back gate electrode (conductor RWL) via a part of the insulator 124. In the present embodiment and the like, an example in which a part of the conductor RWL functions as the back gate electrode is shown, but the back gate electrode and the conductor RWL may be provided independently and electrically connected to each other.

[0060] Also, it is preferable to divide the memory string 120 along the Z direction because the storage capacity per unit area can be increased. When dividing the memory string 120 along the Z direction, the conductor WWL and the conductor RWL may also be divided.

[0061] FIG. 8A shows a state in which the conductor WWL and the memory string 120 are divided by the insulator 153 provided along the X-Z plane, and FIG. 8B shows a state in which the conductor RWL and the memory string 120 are divided by the insulator 153 provided along the X-Z plane. Note that FIG. 8A corresponds to a modified example of the cross section shown in FIG. 5A. FIG. 8B corresponds to a modified example of the cross section shown in FIG. 5B. In FIG. 8 and the like, an a or b is attached to the end of the reference numeral of the divided component.

[0062] As shown in FIG. 8A, the region where the conductor WWL_a and the conductor 130_a overlap functions as the transistor WTr_a. Specifically, the region where the conductor WWL_a, the insulator 124_a, the semiconductor 125_a, the insulator 126_a, the semiconductor 127_a, the insulator 129_a, and the conductor 130_a overlap functions as the transistor WTr_a. The conductor WWL_a functions as the gate electrode of the transistor WTr_a, and the conductor 130_a functions as the back gate electrode of the transistor WTr_a. Also, a part of the semiconductor 127_a functions as the semiconductor layer in which the channel of the transistor WTr_a is formed. The semiconductor layer in which the channel of the transistor WTr_a is formed overlaps with the gate electrode (conductor WWL_a) through a part of the insulator 124_a, a part of the semiconductor 125_a, and a part of the insulator 126_a.

[0063] Also, the region where the conductor WWL_b and the conductor 130_b overlap functions as the transistor WTr_b. Specifically, the region where the conductor WWL_b, the insulator 124_b, the semiconductor 125_b, the insulator 126_b, the semiconductor 127_b, the insulator 129_b, and the conductor 130_b overlap functions as the transistor WTr_b. The conductor WWL_b functions as the gate electrode of the transistor WTr_b, and the conductor 130_b functions as the back gate electrode of the transistor WTr_b. Also, a part of the semiconductor 127_b functions as the semiconductor layer in which the channel of the transistor WTr_b is formed. The semiconductor layer in which the channel of the transistor WTr_b is formed overlaps with the gate electrode (conductor WWL_a) through a part of the insulator 124_b, a part of the semiconductor 125_b, and a part of the insulator 126_b.

[0064] As shown in FIG. 8B, the region where the conductor RWL_a and the conductor 130_a overlap functions as the transistor RTr_a. Specifically, RWL_a, insulator 124_a, semiconductor 125_a, insulator 126_a, semiconductor 127_a, conductor 128_a, insulator 129_a, and conductor 130_a function as the transistor RTr_a. The conductor RWL_a functions as the gate electrode of the transistor RTr_a. Also, the conductor 130_a functions as the back gate electrode of the transistor RTr_a. A part of the semiconductor 125_a functions as the semiconductor layer in which the channel of the transistor RTr_a is formed. The semiconductor layer in which the channel of the transistor RTr_a is formed overlaps the gate electrode (conductor RWL_a) via the insulator 124_a. The semiconductor layer in which the channel of the transistor RTr_a is formed overlaps the back gate electrode (conductor 130_a) via a part of the insulator 126_a, a part of the semiconductor 127_a, a part of the conductor 128_a, and a part of the insulator 129_a.

[0065] Also, the region where the conductor RWL_b and the conductor 130_b overlap functions as the transistor RTr_b. Specifically, RWL_b, insulator 124_b, semiconductor 125_b, insulator 126_b, semiconductor 127_b, conductor 128_b, insulator 129_b, and conductor 130_b function as the transistor RTr_b. The conductor RWL_b functions as the gate electrode of the transistor RTr_b. Also, the conductor 130_b functions as the back gate electrode of the transistor RTr_b. A part of the semiconductor 125_b functions as the semiconductor layer in which the channel of the transistor RTr_b is formed. The semiconductor layer in which the channel of the transistor RTr_b is formed overlaps the gate electrode (conductor RWL_b) via the insulator 124_b. The semiconductor layer in which the channel of the transistor RTr_b is formed overlaps the back gate electrode (conductor 130_b) via a part of the insulator 126_b, a part of the semiconductor 127_b, a part of the conductor 128_b, and a part of the insulator 129_b.

[0066] As described above, by dividing the conductor WWL, the conductor RWL, and the memory string 120, the storage capacity per unit area can be doubled. Note that the method of dividing the memory string 120 is not limited to the above. In FIGS. 8A and 8B, the memory string 120 is divided by the insulator 153 extending in the X direction, but as shown in FIGS. 9A and 9B, the insulator 153 may extend in a direction different from the X direction. Further, as shown in FIGS. 9C to 9F, the memory string 120 may be divided into three or more. FIGS. 9C and 9D show an example of the case where the memory string 120 is divided into three, and FIGS. 9E and 9F show an example of the case where the memory string 120 is divided into four. In this way, the storage capacity per unit area can be increased.

[0067] In FIGS. 9A to 9F, the insulator 153 is preferably arranged so as not to prevent the electrical connection in the X direction of the conductor WWL and the conductor RWL.

[0068] Here, the back gate will be described. The gate and the back gate are arranged so as to overlap via the channel formation region of the semiconductor layer. The back gate can function in the same manner as the gate. Further, by changing the potential of the back gate, the threshold voltage of the transistor can be changed. One of the gate or the back gate may be referred to as the "first gate" or "the first gate", and the other may be referred to as the "second gate" or "the second gate".

[0069] Since the gate and the back gate are formed of a conductive layer or a semiconductor layer having a low resistivity, etc., they have a function (particularly an electrostatic shielding function against static electricity) of preventing the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed. That is, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.

[0070] Also, by controlling the potential of the back gate, the threshold voltage of the transistor can be controlled. The potential of the back gate may be the same as the potential of the gate, or may be the ground potential (GND potential) or an arbitrary potential.

[0071] The semiconductor layer in which the channels of the transistor WTr and the transistor RTr are formed can be used singly or in combination, such as a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor. As the semiconductor material, for example, silicon or germanium can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used. The same applies to the transistors STr1 and STr2.

[0072] Note that the semiconductor layers used for the transistors may be laminated. When laminating the semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

[0073] The transistor RTr is turned on when the memory device 100 reads the data it holds. Therefore, it is preferable to use a semiconductor material with high mobility as the semiconductor layer of the transistor RTr. As such a semiconductor, for example, it is preferable to use a semiconductor whose crystallinity is improved by using a catalyst element disclosed in Patent Document 2. A semiconductor whose crystallinity is improved by using a catalyst element has reduced grain boundaries, and can increase the operating speed of the transistor. Also, since the variation in transistor characteristics is reduced, the operation of the semiconductor device is stabilized and the reliability can be improved. Also, since the variation in transistor characteristics is reduced, the number of memory elements MC provided in one memory string can be increased. Therefore, the memory capacity per unit area can be increased. Therefore, the occupied area of the semiconductor device can be reduced.

[0074] In the present embodiment and the like, silicon with enhanced crystallinity (reduced crystal grain boundaries) using nickel (Ni) as a catalyst element is used for the semiconductor layer of the transistor RTr. The manufacturing method will be described later.

[0075] The transistor WTr is a transistor for writing data into the memory device 100 and holding the written data. The transistor WTr is in an on state during the data writing operation, but is mainly used in an off state. Therefore, it is preferable that the transistor RTr is a transistor with a small off-current. As a semiconductor material used for a transistor with a small off-current, it is preferable to use an oxide semiconductor which is a kind of metal oxide.

[0076] Since the oxide semiconductor has a band gap of 2 eV or more, a transistor (also referred to as an "OS transistor") using an oxide semiconductor for the semiconductor layer in which a channel is formed has an extremely small off-current. When an OS transistor is used for the transistor WTr, the data written in the memory element MC can be held for a long period of time. When an OS transistor is used for the transistor constituting the memory element MC, the memory element MC can be called an "OS memory". Also, the memory string 120 including the memory element MC can be called an "OS memory". Also, the memory device 100 can be called an "OS memory". Also, the OS memory is a kind of memory device. Therefore, the memory element MC and the memory string 120 are also a kind of memory device.

[0077] The OS memory can hold the written data for a period of one year or more, and even ten years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0078] Also, since the written data (charge amount) in the OS memory hardly changes over a long period of time, the OS memory can hold not only binary (1 bit) but also multi-valued (multi-bit) or analog value information.

[0079] In addition, since the OS memory writes charges to the node via a transistor, it does not require the high voltage that was necessary for conventional flash memories, and a high-speed write operation can also be realized. Further, the erase operation before data rewriting performed in flash memories is not necessary for OS memory. Also, since charge injection and extraction into / from the floating gate or charge trapping layer are not performed, the OS memory can perform data writing and reading an almost unlimited number of times. The OS memory has less degradation and higher reliability compared to conventional flash memories.

[0080] In addition, the OS memory does not involve structural changes at the atomic level like magnetic random access memory (MRAM) or resistive random access memory (ReRAM). Therefore, the OS memory has better rewrite resistance than magnetic random access memory and resistive random access memory.

[0081] Also, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is less likely to decrease even in a high-temperature environment. A storage device including the OS memory operates stably even in a high-temperature environment and has high reliability. Also, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor for the transistors constituting the semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment.

[0082] In the present embodiment and the like, IGZO (a metal oxide containing In, Ga, and Zn) is used as the oxide semiconductor used for the semiconductor layer of the transistor WTr. As the oxide semiconductor used for the transistor WTr, various crystalline oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used. The oxide semiconductor will be described in detail later.

[0083] The transistor WTr for writing and holding data is preferably an enhancement-type (normally-off type) transistor to more reliably realize the off state. The transistor RTr for reading data is preferably a depletion-type (normally-on type) transistor with a small threshold voltage to realize a faster operation. Therefore, the threshold voltage of the transistor RTr is preferably smaller than the threshold voltage of the transistor WTr.

[0084] Note that depending on the purpose, application, etc., the semiconductor 125 and the semiconductor 127 may have the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. Also, the semiconductor 125 and the semiconductor 127 may each be a semiconductor in which grain boundaries are reduced using a catalyst element. Further, the semiconductor 125 may be an oxide semiconductor and the semiconductor 127 may be a semiconductor in which grain boundaries are reduced using a catalyst element.

[0085] For the transistor STr1 and the transistor STr2, an OS transistor may be used, or a Si transistor (a transistor using silicon for the semiconductor layer in which a channel is formed) capable of operating faster than the OS transistor may be used.

[0086] Note that Fig. 5A corresponds to the X-Y plane at or near the center of the transistor WTr, and Fig. 5B corresponds to the X-Y plane at or near the center of the transistor RTr. In Fig. 5A and Fig. 5B, when the cross-sectional shape of the conductor 130 viewed from the Z direction is circular, the insulator 129 is provided concentrically outside the conductor 130, the semiconductor 127 is provided concentrically outside the insulator 129, the insulator 126 is provided concentrically outside the semiconductor 127, the semiconductor 125 is provided concentrically outside the insulator 126, and the insulator 124 is provided concentrically outside the semiconductor 125. Also, the conductor 128 is provided concentrically between the insulator 129 and the semiconductor 127.

[0087] Further, the cross-sectional shape of the conductor 130 is not limited to circular. As shown in FIG. 10A, the cross-sectional shape of the conductor 130 may be rectangular. Also, as shown in FIG. 10B, the cross-sectional shape of the conductor 130 may be triangular. Therefore, the cross-sectional shape of the structure 160 viewed from the Z direction is not limited to circular either.

[0088] [Constituent Materials of Semiconductor Device] Subsequently, the constituent materials that can be used in the memory device 100 will be described.

[0089] [Substrate] The memory device 100 can be provided on a substrate. As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, etc. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. Furthermore, there is a substrate provided with a conductor or a semiconductor on an insulator substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on a conductor substrate, etc. Or, those with elements provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, etc.

[0090] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties.

[0091] In the present specification and the like, "oxynitride" refers to a material having a higher oxygen content than nitrogen. For example, "silicon oxynitride" refers to a silicon material having a higher oxygen content than nitrogen. Further, in the present specification and the like, "nitroxide" refers to a material having a higher nitrogen content than oxygen, and "aluminum nitroxide" refers to an aluminum material having a higher nitrogen content than oxygen.

[0092] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low relative permittivity for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0093] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0094] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitroxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0095] Also, the OS transistor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, silicon nitride can be used.

[0096] Also, when an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator functioning as the gate insulator preferably has a region containing oxygen that desorbs by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs by heating is in contact with the semiconductor 125 and / or the semiconductor 127, the oxygen deficiency of the semiconductor 125 and / or the semiconductor 127 can be compensated.

[0097] [Conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0098] Further, as the conductor, a semiconductor doped with a p-type impurity or an n-type impurity to increase the electrical conductivity can be used. Also, for example, when silicon is used as the conductor, a silicide containing titanium, cobalt, or nickel may be used.

[0099] Also, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-described metal element and a conductive material containing nitrogen may be used. Also, a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0100] In the case of using an oxide semiconductor, which is a kind of metal oxide, for the channel formation region of a transistor, it is preferable to use a stacked structure in which a conductor functioning as a gate electrode combines a material containing the above-described metal element and a conductive material containing oxygen. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

[0101] In particular, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the oxide semiconductor in which the channel is formed. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen included in the oxide semiconductor in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0102] [Oxide semiconductor] The oxide semiconductor preferably contains at least one of indium and zinc. In particular, it preferably contains indium and zinc. Further, in addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is included. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, or the like may be included.

[0103] Here, consider the case where the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0104] Note that in this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0105] 〔Classification of crystal structure〕 First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 11A. FIG. 11A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO.

[0106] As shown in FIG. 11A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, "CAAC (c-axis-aligned crystalline)", "nc (nanocrystalline)", and "CAC (cloud-aligned composite)" are included in "Crystalline". Note that "single crystal", "poly crystal", and "completely amorphous" are excluded from the classification of "Crystalline". Further, "single crystal" and "poly crystal" are included in "Crystal".

[0107] Note that the structure within the thick frame shown in Fig. 11A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure completely different from "Crystal" or energetically unstable "Amorphous".

[0108] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained from the grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in Fig. 11B. Note that the GIXD method is also called the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained from the GIXD measurement shown in Fig. 11B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 11B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 11B is 500 nm.

[0109] As shown in Fig. 11B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected at around 2θ = 31°. Note that, as shown in Fig. 11B, the peak at around 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0110] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 11C. FIG. 11C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 11C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0111] As shown in FIG. 11C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0112] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 11A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0113] Subsequently, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0114] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axis of the plurality of crystal regions is oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. The strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0115] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. When a crystal region is composed of a number of minute crystals, the size of the crystal region may be about several tens of nm.

[0116] In the In-M-Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. The In layer may contain element M. The In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0117] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0118] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0119] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0120] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carriers being trapped. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0121] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Thus, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation or defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of an oxide semiconductor having CAAC-OS are stable. For this reason, an oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0122] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nano crystals. Also, nc-OS has no regularity in crystal orientation among different nano crystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as restricted view electron beam diffraction) using an electron beam with a probe diameter larger than the nano crystal (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nano crystal (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0123] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared with the nc-OS and the CAAC-OS. Further, the a-like OS has a higher hydrogen concentration in the film compared with the nc-OS and the CAAC-OS.

[0124] [Constitution of Oxide Semiconductor] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0125] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in a metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0126] Furthermore, the CAC-OS is a configuration in which materials are separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0127] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0128] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0129] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0130] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0131] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, thereby enabling the function of switching (on / off function) to be imparted to CAC-OS. That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on )), high field-effect mobility (μ), and good switching operation can be realized.

[0132] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0133] [Transistor having an oxide semiconductor] Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0134] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 , still more preferably less than 1×10 16 cm -3 , still more preferably less than 1×10 13 cm -3 , still more preferably less than 1×10 12 cm -3It is more preferably less than that. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased and the density of defect levels may be decreased. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect levels is referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor having a low carrier concentration is referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. In some cases, being highly pure intrinsic or substantially highly pure intrinsic is referred to as type i or substantially type i.

[0135] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0136] In addition, the time required for the charge trapped in the trap levels of the oxide semiconductor to disappear is long, and it may behave as if it were a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor having a high density of trap levels may become unstable.

[0137] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

[0138] 〔Impurity〕 Here, the influence of each impurity in the oxide semiconductor will be described.

[0139] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is included, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the concentrations of silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0140] In addition, when an alkali metal or an alkaline earth metal is included in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0141] In addition, when nitrogen is included in the oxide semiconductor, carriers, i.e., electrons, are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is included in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 5×10 19 atoms / cm 3 , preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17atoms / cm 3 Make it as follows.

[0142] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen that binds to metal atoms to form water, oxygen deficiency may be formed. When hydrogen enters this oxygen deficiency, electrons that are carriers may be generated. Also, a part of hydrogen may bind to oxygen that binds to metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 5×10 19 atoms / cm 3 less than, more preferably 1×10 19 atoms / cm 3 less than, even more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 Make it less than.

[0143] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0144] 〔Other semiconductor materials〕 The semiconductor materials that can be used for semiconductor 125 and semiconductor 127 are not limited to the above-described oxide semiconductors. As semiconductor 125 and semiconductor 127, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) may be used as the semiconductor material. In particular, it is preferable to use a layer material that functions as a semiconductor as the semiconductor material.

[0145] In this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0146] Examples of the layered material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogen is a general term for elements belonging to Group 16 and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0147] As the semiconductors 125 and 127, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenides applicable as the semiconductors 125 and 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0148] <Example of manufacturing method of memory device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to FIGS. 12 to 34. In each of FIGS. 12 to 34, A in the figure is a top view seen from the Z direction, and B in the figure is a cross-sectional view of the part indicated by the one-dot chain line A1 - A2 in A. Also, in each of FIGS. 12 to 34, C in the figure is a cross-sectional view of the part indicated by the one-dot chain line A3 - A4 in A. Further, FIG. 25D is an enlarged cross-sectional view of the portion surrounded by the one-dot chain line in FIG. 25B. In this manufacturing method, one memory string 120 having two memory elements MC (also referred to as "two stages") is exemplified, but the present embodiment is not limited to this. The memory string 120 may have three or more memory elements MC. For example, the memory string 120 may have 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0149] First, a layer 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the layer 122 (see FIGS. 12A to 12C).

[0150] First, a conductive film is formed, and the conductive film is processed using a lithography method to form the layer 122. Next, an insulating film is formed on the substrate 121 so as to cover the layer 122. Next, it is preferable to perform a planarization process on the insulating film. In the planarization process, it is preferable to polish the insulating film until the surface of the layer 122 is exposed. By the above method, the insulator 132 can be formed, however, the formation methods of the layer 122 and the insulator 132 are not limited to this. The insulator 132 may be formed on the substrate 121, and grooves and openings may be formed by removing unnecessary portions of the insulator 132, and the layer 122 may be formed so as to be embedded in the grooves and the openings. Such a method for forming a conductor is sometimes referred to as a damascene method (single damascene method, dual damascene method). By the above method, the structure of the layer 122 and the insulator 132 shown in FIGS. 12A to 12C can be obtained.

[0151] The formation of the layer 122 and the insulator 132 can be carried out using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0152] Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method that utilizes plasma, a thermal CVD (TCVD) method that utilizes heat, a photo CVD method that utilizes light, and the like. Further, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on the raw material gas used.

[0153] In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Also, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charge-up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0154] Also, the ALD method is also a film formation method capable of reducing plasma damage to the object to be processed. Also, since plasma damage does not occur during film formation in the ALD method, a film with few defects can be obtained.

[0155] Unlike film deposition methods in which particles emitted from a target or the like are deposited, the CVD method and the ALD method are film deposition methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is a film deposition method that is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film deposition rate, it may be preferable to use it in combination with other film deposition methods such as the CVD method with a high film deposition rate.

[0156] The composition of the obtained film can be controlled by the flow rate ratio of the source gases in the CVD method and the ALD method. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while depositing the film. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened by the time required for transfer and pressure adjustment compared to the case of using a plurality of film deposition chambers. Therefore, the productivity of semiconductor devices may be increased.

[0157] In the lithography method, first, a resist is exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique can be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam can be used. Note that when using an electron beam or an ion beam, a photomask is not required. For removing the resist mask, a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process can be performed.

[0158] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductive film, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material.

[0159] This processing can use a dry etching method or a wet etching method. Processing by the dry etching method is suitable for microfabrication.

[0160] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power source to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency power sources to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power sources of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0161] When a hard mask is used for etching the conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film. On the other hand, when the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

[0162] As the layer 122, for example, a conductive film containing a metal element formed by a sputtering method can be used. Further, the conductive film can also be formed by using a CVD method. The layer 122 may be a semiconductor. For example, when performing a gettering process related to a crystallinity improvement process (also referred to as "catalytic crystallization") using a catalyst element described later, it is preferable to use a conductive film having many crystal defects as the layer 122. Note that the layer 122 can also be referred to as a "gettering layer".

[0163] Also, when performing the gettering process described later more effectively, it is preferable that the layer 122 contains impurity elements. As the impurity elements, for example, group 15 elements such as phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb), and bismuth (Bi) may be used. In addition to group 15 elements, group 13 elements (typically, boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) may be used. The concentration of the impurity contained in the layer 122 is 1×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less. Note that the addition of impurity elements to the layer 122 for the gettering process is not essential. Also, as the impurity elements contained in the layer 122, group 18 elements (typically, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc.) may be used. As the impurity elements contained in the layer 122, group 15 elements, group 13 elements, and group 18 elements may be used in combination.

[0164] In the present embodiment, amorphous silicon containing phosphorus is used as the layer 122. For example, after forming the amorphous silicon film, phosphorus may be introduced into the amorphous silicon film by a plasma doping method or an ion implantation method. Also, when forming the layer 122 by a CVD method or the like, a gas containing an impurity element may be mixed into the source gas.

[0165] The surface of the insulator 132 is preferably subjected to a planarization process as necessary. For the planarization process, a chemical mechanical polishing (CMP) method or a reflow method can be used.

[0166] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately laminated on the layer 122 and the insulator 132. In the present embodiment, an example is shown in which an insulating film 123A is formed on the insulator 132, a conductive film 134A is formed on the insulating film 123A, an insulating film 123A is formed on the conductive film 134A, and a conductive film 136A is formed on the insulating film 123A (see FIGS. 12A to 12C). For the formation of the conductive film 134A, the conductive film 136A, and the insulating film 123A, a CVD method can be used. Also, a sputtering method may be used.

[0167] As the conductive film 134A and the conductive film 136A, the aforementioned conductors can be used. Since the conductive film 136A needs to be selectively etched with respect to the layer 122 and the conductive film 134A in a later process, it is preferably made of a material different from that of the layer 122 and the conductive film 134A. On the other hand, the layer 122 and the conductive film 134A may be made of the same material or different materials. The layer 122, the conductive film 134A, and the conductive film 136A may be conductors having different crystallinities.

[0168] As the insulator 132 and the insulating film 123A, the aforementioned insulators can be used. For example, oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties can be used.

[0169] Also, in the present embodiment, an example is shown in which 6 layers of the insulating film 123A, 3 layers of the conductive film 134A, and 2 layers of the conductive film 136A are formed, but the number of laminated layers is not limited to this. They can be formed respectively according to the required performance of the semiconductor device. Here, if the number of laminated layers of the conductive film 134A is m (m is an integer of 2 or more), the number of laminated layers of the insulating film 123A is 2×m, and the number of laminated layers of the conductive film 136A is m - 1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and still more preferably 257 or more.

[0170] Next, a mask is formed on the insulating film 123A (not shown), and the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed using a lithography method to form a first opening 141 so as to expose the layer 122 (see FIGS. 13A to 13C).

[0171] Next, isotropic etching is performed on the conductive film 136A to recess the side surface of the conductive film 136A in the first opening 141 behind the side surfaces of the insulating film 123A and the conductive film 134A (see FIGS. 14A to 14C). By this process, the diameter of the first opening 141 that overlaps the conductive film 136A in the direction perpendicular to the Z direction becomes larger than the diameter of the first opening 141 that overlaps the insulating film 123A and the diameter of the first opening 141 that overlaps the conductive film 134A in the direction perpendicular to the Z direction. Therefore, irregularities are formed on the side surface of the first opening 141. For such processing, isotropic etching by dry etching using a gas, radical, plasma, etc. or isotropic etching by wet etching using a liquid can be used. The liquid used for wet etching is sometimes referred to as an etchant. When performing isotropic etching using dry etching, a gas, radical, plasma, etc. containing at least one of chlorine, bromine, and fluorine can be used. Isotropic etching is preferably performed without removing the mask used for the formation of the first opening 141.

[0172] Next, an insulating film 124A is formed on the insulating film 123A and inside the first opening 141 (see FIGS. 15A to 15C). Although not shown, the insulating film 124A may have a laminated structure. The insulating film 124A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for a groove or opening with a large aspect ratio, which is preferable. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. When the insulating film 124A has a laminated structure, each insulating film may be formed by the same film-forming apparatus or different film-forming apparatuses.

[0173] The insulating film 124A formed by the above method has good coverage and can be formed on the uneven shape of the side surface of the first opening 141. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of the insulating film 123A, the conductive film 134A, and the conductive film 136A, but also a part of the upper surface and a part of the lower surface of the insulating film 123A.

[0174] Next, the insulating film 124A formed at the bottom of the first opening 141 is removed to obtain the insulator 124. It is preferable to use anisotropic etching for removing the insulating film 124A. At this time, since the insulating film 124A on the insulating film 123A is also removed, the insulator 124 is provided only on the sidewall of the first opening 141 (see FIGS. 16A to 16C). By removing the insulating film 124A at the bottom of the first opening 141, the layer 122 is exposed again.

[0175] Next, a semiconductor film 125A and an insulating film 126A are formed inside the first opening (see FIGS. 17A to 17C).

[0176] The semiconductor film 125A and the insulating film 126A can be formed using the CVD method or the ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves or openings with a large aspect ratio, which is preferable. Alternatively, the semiconductor film 125A and the insulating film 126A may be formed by combining the ALD method and the CVD method. Also, different film formation methods or different film formation apparatuses may be used for each film to be formed.

[0177] In this embodiment, amorphous silicon is formed as the semiconductor film 125A, and silicon oxynitride is formed as the insulating film 126A.

[0178] Next, a part of the insulating film 126A is removed, leaving the region where the insulating film 126A overlaps with the first opening 141 and the vicinity thereof (see FIGS. 18A to 18C). In the present embodiment, a part of the insulating film 126A is removed so that, when viewed from the Z direction, the region overlapping with the first opening 141 and the portion overlapping with the region that will later function as the transistor STr2 remain. In the region where the insulating film 126A is removed, the semiconductor film 125A is exposed. This region is also referred to as the "catalyst element addition region".

[0179] Subsequently, a catalyst layer 185 containing a catalyst element is formed on the semiconductor film 125A and the insulating film 126A (see FIGS. 19A to 19C). The catalyst layer 185 may be formed using a sputtering method, a CVD method, an ALD method, or the like, or may be formed by a coating method in which a solution containing a catalyst element is applied by a spin coating method or the like. The catalyst layer 185 may be, for example, a silicide containing a catalyst element.

[0180] As the catalyst element, an element selected from metal elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge) may be used.

[0181] In the present embodiment, nickel is used as the catalyst element. When the catalyst layer 185 is formed by a coating method, a solution having a nickel salt such as nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, or nickel sulfate as a solute and water, alcohol, an acid, or ammonia as a solvent can be used. Alternatively, a solution having nickel element as a solute and a solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform, and ether can be used. Or, even if nickel is not completely dissolved, a material such as an emulsion in which nickel is dispersed in a medium may be used.

[0182] Next, in order to diffuse the catalyst element from the catalyst layer 185 containing the catalyst element into the semiconductor film 125A, heat treatment is performed under the conditions of 450 °C or higher and 650 °C or lower for 4 hours or longer and 24 hours or shorter. Note that prior to the heat treatment, a dehydrogenation treatment may be performed at 450 °C for about 1 hour. By performing the dehydrogenation treatment, the hydrogen concentration in the semiconductor film 125A is reduced. By reducing the hydrogen concentration by heat treatment, silicide is likely to be formed.

[0183] Silicon in contact with the catalyst element binds to the catalyst element to form silicide. The catalyst element is likely to bind to a site with many defects such as an amorphous state. Therefore, the catalyst element contained in the silicide reacts with the amorphous silicon to form a new silicide. In this way, crystallization proceeds while the silicide moves. This is because the interatomic distance between the catalyst element and silicon is very close to the interatomic distance of single-crystal silicon, and the Ni-Si distance is closest to the single-crystal Si-Si distance and is about 0.6% shorter. By performing crystallization using the catalyst element, the crystal grain size increases and defects in the semiconductor are reduced.

[0184] Figs. 20 and 21 show how the silicide 188 moves from the catalyst element addition region to the semiconductor film 125A. Fig. 20 shows the state at the initial stage of the heat treatment. First, silicide is formed in the semiconductor film 125A in contact with the catalyst element addition region. Since the insulating film 126A functions as a mask, the catalyst element is not added to the semiconductor film 125A in the region overlapping the insulating film 126A. As the heat treatment progresses, the silicide 188 moves in a direction away from the catalyst element addition region. In the semiconductor film 125A, the site where catalyst crystallization has occurred (the site where the crystallinity has been enhanced by the catalyst element) is denoted as the semiconductor film 125Ac. The amorphous semiconductor film 125A changes to a crystalline semiconductor as the silicide 188 passes through it.

[0185] FIG. 21 shows the state in the middle of the heat treatment. As the heat treatment progresses, the silicide 188 moves toward the layer 122. In the present embodiment, since amorphous silicon containing phosphorus is used as the layer 122, when the silicide 188 reaches the layer 122 during the heat treatment period, the crystallinity of the layer 122 is also promoted.

[0186] Finally, the catalyst element contained in the silicide 188 is contained in the layer 122 (gettering treatment). By containing an impurity element such as a group 15 element or a group 13 element in the layer 122, re-diffusion of the catalyst element that has moved to the layer 122 can be reduced.

[0187] The concentration of the catalyst element remaining in the semiconductor film 125Ac is 5×10 17 atoms / cm 3 The following is preferable. When an impurity element such as a group 15 element is contained in the layer 122, after the heat treatment of the semiconductor film 125A using the catalyst element is completed, by performing the heat treatment at a higher temperature, the catalyst element remaining in the semiconductor film 125Ac can be moved (absorbed) to the layer 122. By containing an impurity element in the layer 122, the effect of the gettering treatment can be enhanced.

[0188] Next, the catalyst layer 185 is removed (see FIGS. 22A to 22C), and a semiconductor film 127A and a conductive film 128A are formed inside the first opening 141 (see FIGS. 23A to 23C).

[0189] The semiconductor film 127A and the conductive film 128A can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for a groove or an opening with a large aspect ratio, which is preferable. Alternatively, the semiconductor film 127A and the conductive film 128A may be formed by combining the ALD method and the CVD method. Also, for each film to be formed, a different film formation method or a different film formation apparatus may be used.

[0190] The conductive film 128A only needs to be formed so as to fill the recess (the intersection of the first opening 141 and the conductive film 136A in the direction perpendicular to the Z direction) on the side surface of the first opening 141 through at least the insulator 124, the semiconductor film 125Ac, the insulating film 126A, and the semiconductor film 127A, and it is not necessarily required to fill the entire inside of the first opening. The conductive film 128A can be formed using the CVD method or the ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for grooves or openings with a large aspect ratio, which is preferable. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0191] The semiconductor film 127A is preferably an oxide semiconductor. As the oxide semiconductor used for the semiconductor film 127A, oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used.

[0192] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 24A to 24C). Isotropic etching or anisotropic etching can be used for processing the conductive film 128A. In the formation of the conductive film 128A, when the conductive film 128A fills the recess on the side surface of the first opening 141 but the first opening 141 is not completely filled (see FIG. 23), it is preferable to use isotropic etching for processing the conductive film 128A. On the other hand, when the conductive film 128A is formed so as to completely fill the first opening 141, it is preferable to use anisotropic etching. Through the above-described processing, the conductor 128 can be formed in the recess on the side surface of the first opening 141.

[0193] Next, an insulating film 129A is formed inside the semiconductor film 127A and the conductor 128. Subsequently, using the conductor 128 as a mask, a part of the semiconductor film 127A is made to have a high resistance to form a high-resistance region (type I region) (see FIGS. 25A to 25D). As a method for forming the high-resistance region, there is a method of irradiating the semiconductor film 127A with microwaves 144 through the insulating film 129A to remove hydrogen contained in the semiconductor film 127A. It is preferable to perform the irradiation of the microwaves 144 in an atmosphere containing oxygen because oxygen is supplied to the semiconductor film 127A. In the present embodiment, in an atmosphere containing oxygen and argon, a part of the semiconductor film 127A is irradiated with microwaves 144 through the insulating film 129A to make a region 146, which is a part of the semiconductor film 127A, have a high resistance (see FIG. 25D).

[0194] Here, heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at 200°C or higher and 500°C or lower, more preferably 300°C or higher and 400°C or lower. The atmosphere for performing the heat treatment is not limited to the above, and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. Further, the heat treatment may be performed in a reduced-pressure atmosphere or an atmospheric-pressure atmosphere.

[0195] By the heat treatment, the semiconductor film 127A in contact with the conductor 128 can be made to have a low resistance, and a low-resistance region (N-type region) can be formed in the region 148. When the heat treatment is performed with the semiconductor film 127A and the conductor 128 in contact with each other, a metal compound layer containing a metal element of the conductor 128 and a component of the semiconductor film 127A may be formed at the interface between the conductor 128 and the semiconductor film 127A. The formation of the metal compound layer is preferable because the resistance of the semiconductor film 127A is reduced in the region in contact with the conductor 128. Further, the conductor 128 may absorb oxygen contained in the semiconductor film 127A. When the heat treatment is performed with the semiconductor film 127A and the conductor 128 in contact with each other, the semiconductor film 127A has a lower resistance. The heat treatment may be performed before the microwave treatment. Since the region 148 having a reduced resistance by the heat treatment is covered with the conductor 128, it is not affected by the microwaves 144 and can maintain a low resistance value even after the microwave treatment.

[0196] The carrier concentration of the region 146 after the above-mentioned microwave treatment and heat treatment is less than 1×10 18 / cm 3 , preferably less than 1×10 17 / cm 3 , more preferably less than 1×10 16 / cm 3 . Also, the carrier concentration of the region 148 is preferably 1×10 18 / cm 3 or more, preferably 1×10 19 / cm 3 or more, more preferably 1×10 20 / cm 3 or more.

[0197] Next, a conductive film 130A is formed (see FIGS. 26A to 26C). The conductive film 130A can be formed using a CVD method or an ALD method. In particular, using the ALD method is preferable because a film with a uniform thickness can be formed even for grooves or openings with a large aspect ratio. Alternatively, it may be formed by combining the ALD method and the CVD method.

[0198] Next, a heat treatment is performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at 200°C or higher and 500°C or lower, more preferably at 300°C or higher and 400°C or lower. The atmosphere for performing the heat treatment is not limited to the above, and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. Also, the heat treatment may be performed in a reduced-pressure atmosphere or an atmospheric-pressure atmosphere.

[0199] Next, the conductive film 130A is removed using a CMP method or the like until the surface of the insulating film 129A is exposed to obtain a conductor 130 (see FIGS. 27A to 27C). Note that the above-mentioned heat treatment may be performed after the conductor 130 is formed.

[0200] Next, the semiconductor film 125A, the insulating film 126A, the semiconductor film 127A, and the insulating film 129A are processed to obtain a semiconductor 125, an insulator 126, an oxide film 127B, and an insulating film 129B (see FIGS. 28A to 28C). For this processing, a dry etching method or a wet etching method can be used.

[0201] Next, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form an insulator 123B, a conductor 134B, and a conductor 136B that overlap stepwise at the ends as shown in FIG. 29B (see FIGS. 29A to 29C). In processing the insulating film 123A, the conductive film 134A, and the conductive film 136A, by alternately performing etching of the insulating film 123A, the conductive film 134A, and the conductive film 136A and trimming of the mask, a stepped end portion can be formed.

[0202] Next, an insulator 150 is formed (see FIG. 29). The insulator 150 can be formed using a CVD method. Preferably, the surface of the insulator 150 is planarized using a CMP method or a reflow method.

[0203] Next, the insulator 150, the insulator 123B, the conductor 134B, and the conductor 136B are processed to form an insulator 123, a conductor 134, and a conductor 136 (see FIGS. 30A to 30C).

[0204] Next, an insulator 152 is formed so as to fill the portions removed during the formation of the insulator 123, the conductor 134, and the conductor 136 (see FIG. 30). The insulator 152 can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with a uniform thickness can be formed even for a groove or an opening with a large aspect ratio, which is preferable. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. Preferably, the insulator 152 is planarized using a CMP method or a reflow method.

[0205] Next, the oxide film 127B and the insulating film 129B are processed using a lithography method to obtain the semiconductor 127 and the insulator 129 (see FIGS. 31A to 31C). This processing can use a dry etching method or a wet etching method. At this time, a part of the insulator 126 is exposed.

[0206] Next, a conductor 154 is formed so as to overlap a part of the semiconductor 125 via the insulator 126 (see FIGS. 32A to 32C). The conductor 154 is obtained by forming a conductive film on the insulator 126, the insulator 150, and the insulator 152 and processing the conductive film using a lithography method. In FIG. 32A, the conductor 154 does not exist on the one-dot chain line of A1 - A2, but in FIG. 32B, the conductor 154 is shown by a broken line. The conductor 154 is similarly shown in FIGS. 33 and 34 described later.

[0207] Next, an insulator 156 is formed so as to cover the conductor 154, the insulator 126, the insulator 150, and the insulator 152 (see FIGS. 33A to 33C). The insulator 156 can be formed using a CVD method, an ALD method, a sputtering method, or the like.

[0208] Next, the insulator 156, the insulator 126, the insulator 129, the semiconductor 127, and the insulator 150 are processed using a lithography method to form a second opening so as to expose the conductor 134, the conductor 136, the conductor 130, the conductor 154, and the semiconductor 125. The second opening is formed for each of the conductor 134 and the conductor 136 formed in a stepped shape (see FIG. 33).

[0209] Next, conductors 161 electrically connected to conductor 134, conductor 162 electrically connected to conductor 136, conductor 163 electrically connected to conductor 130, conductor 164 electrically connected to conductor 154, conductor 165 electrically connected to semiconductor 125, and conductor 166 electrically connecting semiconductor 125 and semiconductor 127 are formed so as to be embedded in the second opening (see FIGS. 34A to 34C). Conductors 161, 162, 163, 164, 165, and 166 can be formed using a CVD method or an ALD method. In particular, by using the ALD method, a film with uniform thickness can be formed even for grooves or openings with a large aspect ratio, which is preferable. Alternatively, the above conductors may be formed by combining the ALD method and the CVD method. Also, conductors 161, 162, 163, 164, 165, and 166 may have a laminated structure composed of a plurality of layers. Conductors 161, 162, 163, 164, 165, and 166 can be formed by forming a conductive film on insulator 156 and inside the second opening, and removing the unnecessary conductive film using CMP or the like.

[0210] Next, conductors 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 173 electrically connected to conductor 163, conductor 174 electrically connected to conductor 164, and conductor 175 electrically connected to conductor 165 are formed (see FIG. 34). Conductors 171, 172, 173, 174, and 175 can be formed by forming a conductive film on insulator 156 and processing it using a lithography method. The processing can use a dry etching method or a wet etching method.

[0211] The conductor 171, the conductor 161, and the conductor 134 function as the conductor SG or the conductor WWL. The conductor 172, the conductor 162, and the conductor 136 function as the conductor RWL. The conductor 173, the conductor 163, and the conductor 130 function as the conductor BG. The conductor 174, the conductor 164, and the conductor 154 function as the conductor SEL. The conductor 175 and the conductor 165 function as the BL. Through the above steps, a memory device can be manufactured.

[0212] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0213] (Embodiment 2) In this embodiment, the circuit configuration and operation of the memory string 120, which is a memory device, will be described. FIG. 35 shows an example of the circuit configuration of the memory string 120.

[0214] <Example of Circuit Configuration of Memory String> FIG. 35 shows an example of the circuit configuration when the number n of memory elements MC included in the memory string 120 is 5. As described in the above embodiment, the memory element MC has a transistor WTr and a transistor RTr.

[0215] In an equivalent circuit diagram or the like, in order to clarify that a transistor is an OS transistor, "OS" may be appended to the circuit symbol of the transistor. Similarly, in order to clarify that a transistor is a Si transistor (a transistor using silicon for the semiconductor layer in which a channel is formed), "Si" may be appended to the circuit symbol of the transistor. FIG. 35 shows that the transistor WTr is an OS transistor and the transistor RTr is a Si transistor.

[0216] Fig. 36 shows an equivalent circuit diagram of the memory element MC. As shown in Fig. 36, the transistor WTr can be replaced by a capacitor Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor WWL via the capacitor Cs. The memory element MC exemplified in this embodiment is a "2Tr1C type" memory cell composed of two transistors and one capacitor.

[0217] In Fig. 35, the transistor WTr included in the memory element MC_1 is denoted as transistor WTr_1, and the transistor RTr included in the memory element MC_1 is denoted as transistor RTr_1. Therefore, the memory string 120 shown in Fig. 35 has transistors WTr_1 to WTr_5 and transistors RTr_1 to RTr_5. Also, the memory string 120 shown in Fig. 35 has transistors STr1 and STr2. The memory string 120 is a NAND type memory device.

[0218] A NAND type memory device including an OS memory is also referred to as an "OS NAND type" or an "OS NAND type memory device". Also, a 3D OS NAND type memory device having a configuration in which a plurality of OS memories are stacked in the Z direction is also referred to as a "3D OS NAND type" or a "3D OS NAND type memory device".

[0219] One of the source or drain of transistor RTr_1 is electrically connected to one of the source or drain of transistor STr1, and the other is electrically connected to one of the source or drain of transistor RTr_2. One of the source or drain of transistor WTr_1 is electrically connected to the gate of transistor RTr_1, and the other is electrically connected to one of the source or drain of transistor WTr_2. The back gate of transistor RTr_1 is electrically connected to conductor RWL_1. The gate of transistor WTr_1 is electrically connected to conductor WWL_1. Also, the back gate of transistor WTr_1 is electrically connected to conductor BG. Also, the other of the source or drain of transistor STr1 is electrically connected to layer 122, and the gate is electrically connected to conductor SG.

[0220] Also, one of the source or drain of transistor RTr_5 is electrically connected to the other of the source or drain of transistor RTr_4, and the other is electrically connected to one of the source or drain of transistor STr2. The gate of transistor RTr_5 is electrically connected to one of the source or drain of transistor WTr_5. The other of the source or drain of transistor WTr_5 is electrically connected to one of the source or drain of transistor STr2. The back gate of transistor RTr_5 is electrically connected to conductor RWL_5. The gate of transistor WTr_5 is electrically connected to conductor WWL_5. Also, the back gate of transistor WTr_5 is electrically connected to conductor BG. Also, the other of the source or drain of transistor STr2 is electrically connected to conductor BL, and the gate is electrically connected to conductor SEL.

[0221] When the memory string 120 includes n memory cells MC, in the i-th memory cell MC_i (where i is an integer from 1 to n, excluding the first and n-th memory cells MC), one of the source or drain of the transistor RTr_i is electrically connected to the other of the source or drain of the transistor RTr_i - 1, and the other is electrically connected to one of the source or drain of the transistor RTr_i + 1. The gate of the transistor RTr_i is electrically connected to one of the source or drain of the transistor WTr_i. The other of the source or drain of the transistor WTr_i is electrically connected to one of the source or drain of the transistor WTr_i + 1. The back gate of the transistor RTr_i is electrically connected to the conductor RWL_i. The gate of the transistor WTr_i is electrically connected to the conductor WWL_i. Also, the back gate of the transistor WTr_i is electrically connected to the conductor BG.

[0222] Also, let the node where the gate of the transistor RTr and one of the source or drain of the transistor WTr are electrically connected be the node ND. That is, let the node where the gate of the transistor RTr_i and one of the source or drain of the transistor WTr_i are electrically connected be the node ND_i. In FIG. 35, the node ND included in the memory cell MC_1 is shown as the node ND_1.

[0223] The transistors STr1 and STr2 may be, for example, OS transistors or Si transistors. One of the transistors STr1 and STr2 may be an OS transistor and the other may be an Si transistor.

[0224] As shown in FIG. 37, depending on the purpose or application, etc., an Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr. Also, in FIG. 37, an example of using OS transistors for the transistors STr1 and STr2 is shown.

[0225] Also, depending on the purpose, application, etc., as shown in FIG. 38, the transistor WTr may be configured without a back gate. Further, FIG. 38 shows an example in which OS transistors are used for the transistors STr1 and STr2.

[0226] <Operation Example of Memory String> Subsequently, an operation example of the memory string 120 shown in FIG. 35 will be described.

[0227] [Write Operation] In the present embodiment, an operation example in the case where an H potential is written to the memory elements MC_1 and MC_3 and an L potential is written to the other memory elements MC will be described. FIG. 39 is a timing chart for explaining the write operation. FIGS. 40A to 43B are circuit diagrams for explaining the write operation. Note that symbols and the like not described in FIGS. 40A to 43B may be referred to in FIG. 35 and the like.

[0228] As an initial state, it is assumed that L potentials are written to the memory elements MC_1 to MC_5. Also, it is assumed that L potentials are supplied to the conductors WWL_1 to WWL_5, the conductors RWL_1 to RWL_5, the conductor SEL, the conductor BG, the conductor BL, the conductor SG, and the layer 122. Note that the threshold value of the transistor RTr can be controlled by adjusting the potential supplied to the conductor BG. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on type transistor.

[0229] [Period T1] In period T1, H potentials are supplied to the conductors WWL_1 to WWL_5, the conductor BL, and the conductor SEL (see FIG. 40A). Then, the potentials of the nodes ND_1 to ND_5 become H potentials.

[0230] [Period T2] During period T2, an L potential is supplied to the conductor WWL_1 (see Fig. 40B). Then, the transistor WTr_1 turns off, and the charge written to the node ND_1 is retained. Here, the charge corresponding to the H potential is retained.

[0231] [Period T3] During period T3, an L potential is supplied to the conductor BL (see Fig. 40B). Then, the potentials of nodes ND_2 to ND_5 become the L potential. In this case, although the gates of transistors RTr_2 to RTr_5 also become the L potential, since transistor RTr is a normally-on type transistor, transistors RTr_2 to RTr_5 do not turn off.

[0232] [Period T4] During period T4, an L potential is supplied to the conductor WWL_2 (see Fig. 41A). Then, the transistor WTr_2 turns off, and the charge written to the node ND_2 is retained. Here, the charge corresponding to the L potential is retained.

[0233] [Period T5] During period T5, an H potential is supplied to the conductor BL (see Fig. 41B). Then, the potentials of nodes _3 to _5 become the H potential.

[0234] [Period T6] During period T6, an L potential is supplied to the conductor WWL_3 (see Fig. 42A). Then, the transistor WTr_3 turns off, and the charge written to the node ND_3 is retained. Here, the charge corresponding to the H potential is retained.

[0235] [Period T7] During period T7, an L potential is supplied to the conductor BL (see Fig. 42B). Then, the potentials of nodes ND_4 and ND_5 become the L potential.

[0236] [Period T8] During period T8, supply the L potential to the conductor WWL_4 (see Fig. 43A). Then, the transistor WTr_4 turns off, and the charge written to the node ND_4 is retained. Here, the charge corresponding to the L potential is retained.

[0237] [Period T9] During period T9, keep the conductor BL at the L potential. Thus, the potential of the node ND_5 also remains at the L potential.

[0238] [Period T10] During period T10, supply the L potential to the conductor WWL_5 (see Fig. 43B). Then, the transistor WTr_5 turns off, and the charge written to the node ND_5 is retained. Here, the charge corresponding to the L potential is retained. Also, supply the L potential to the conductor SEL.

[0239] In this way, information can be written to the memory element MC.

[0240] Note that when writing information to the i-th (excluding i = 1) memory element MC among a plurality of memory elements MC, the information writing operation for the memory elements MC up to the (i - 1)-th can be omitted. For example, when wanting to write information to the memory element MC_4, the information writing operations for the memory elements MC_1 to MC_3 do not have to be performed. In other words, the writing operations from period T1 to period T6 shown in this embodiment can be omitted. Thus, the time and power consumption related to the writing operation of the memory device can be reduced.

[0241] [Read operation] An example of the read operation of the memory string 120 with the above circuit configuration will be described. As an initial state, it is assumed that the H potential is held in the memory element MC_1 and the memory element MC_3, and the L potential is held in the memory element MC_2, the memory element MC_4, and the memory element MC_5. Also, it is assumed that the L potential is supplied to the conductors WWL_1 to WWL_5, the conductors RWL_1 to RWL_5, the conductor SEL, the conductor BG, the conductor BL, the conductor SG, and the layer 122. FIGS. 44A and 44B are timing charts for explaining the read operation. FIGS. 45A, 45B, and 46 are circuit diagrams for explaining the read operation. Note that for symbols not shown in FIGS. 45A, 45B, and 46, reference may be made to FIG. 35 and the like.

[0242] <<When the holding potential is the H potential>> First, the read operation of the memory element MC_3 in which the H potential is held will be described.

[0243] [Period T11] In period T11, an H potential is supplied to the conductors RWL_1 to RWL_5 and the conductor SEL (see FIG. 45A). Then, the transistor STr2 is turned on, and the semiconductor 125 included in the transistor RTr and the conductor BL are brought into a conductive state. In this state, the H potential is precharged to the conductor BL and the semiconductor 125, and both are brought into a floating state.

[0244] Here, the Id-Vg characteristics of the transistor will be described. FIGS. 47A and 47B are diagrams for explaining the Id-Vg characteristics of the transistor. The horizontal axis in FIGS. 47A and 47B indicates the gate voltage (Vg), and the vertical axis indicates the drain current (Id). FIG. 47A shows the Id-Vg characteristics of a normally-off type transistor, and FIG. 47B shows the Id-Vg characteristics of a normally-on type transistor.

[0245] The H potential is higher than the L potential. If the L potential is set to 0 V, the H potential is a positive voltage. In a normally-off type transistor, when Vg is at the L potential (0 V), the channel resistance value (the resistance value between the source and the drain) is extremely large and almost no Id flows. Also, when Vg becomes the H potential, the channel resistance value decreases and Id increases (see Fig. 47A).

[0246] In a normally-on type transistor, even when Vg is at the L potential, the channel resistance value is small and more Id flows compared to a normally-off type transistor. Also, when Vg becomes the H potential, the channel resistance value becomes even smaller and Id further increases (see Fig. 47B).

[0247] Since the transistor RTr is a normally-on type transistor, precharging to the semiconductor 125 is possible even when the potential of the conductor RWL remains at the L potential. However, by supplying the H potential to the conductor RWL, the channel resistance value of the transistor RTr becomes even smaller. Therefore, the time and power consumption required for precharging can be reduced.

[0248] [Period T12] During period T12, supply the L potential to the conductor RWL_3 (see Fig. 45B). The H potential is held at the node ND_3. Therefore, even when the potential of the conductor RWL_3 becomes the L potential, the channel resistance value of the transistor RTr_3 is smaller than when the L potential is held at the node ND_3.

[0249] [Period T13] During period T13, an H potential is supplied to the conductor SG to turn on the transistor ST r1 (see Fig. 46A). Then, the conductor BL and the layer 122 are brought into a conductive state. At this time, since an H potential is supplied to the conductors RWL_1, RWL_2, RWL_4, and RWL_5, the channel resistance values of the transistors RTr_1, RTr_2, RTr_4, and RTr_5 become small regardless of the potential of the node ND. Also, as described above, although an L potential is supplied to the conductor RWL_3, since an H potential is held at the node ND_3, the channel resistance value of the transistor RTr_3 is small. Therefore, the potential of the floating conductor BL changes rapidly from the H potential to the L potential (see Fig. 44A).

[0250] [Period T14] During period T14, an L potential is supplied to the conductors SEL, RWL, and SG (see Fig. 46B).

[0251] [[When the held potential is the L potential]] Next, the read operation of the memory element MC_2 holding the L potential will be described. When reading the information (potential) held in the memory element MC_2, in period T12, the potential of the conductor RWL_2 is set to the L potential (see Fig. 44B). At this time, since an L potential is held at the node ND_2, the channel resistance value of the transistor RTr_2 is larger than when an H potential is held at the node ND_2.

[0252] Subsequently, in period T13, an H potential is supplied to the conductor SG to bring the conductor BL and the layer 122 into a conductive state. At this time, since the channel resistance value of the transistor RTr_2 is large, the potential of the conductor BL changes gently from the H potential toward the L potential.

[0253] In this way, in period T13, by setting the potential of the conductor RWL corresponding to the memory element MC to be read to the L potential and detecting the potential change of the conductor BL, the information held in the memory element MC can be known.

[0254] Also, during periods other than the writing operation, it is preferable to supply a potential lower than the L potential (also referred to as "LL potential") to the conductor BG. By supplying the LL potential to the conductor BG, the transistor WTr can be more surely turned off. Therefore, the information written to the node ND can be retained for a longer period.

[0255] Also, during the writing operation, a potential higher than the L potential may be supplied to the conductor BG. For example, the H potential may be supplied to the conductor BG during the writing operation. By supplying the H potential to the conductor BG during the writing operation, the resistance value of the semiconductor 127 becomes smaller, and the writing speed can be increased.

[0256] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0257] (Embodiment 3) In this embodiment, a configuration example of the semiconductor device 200 including the memory device 100 will be described.

[0258] FIG. 48 shows a block diagram showing a configuration example of a semiconductor device 200 which is an aspect of the present invention. The semiconductor device 200 shown in FIG. 48 has a drive circuit 210 and a memory array 220. The memory array 220 has one or more memory devices 100. FIG. 48 shows an example in which the memory array 220 has a plurality of memory devices 100 arranged in a matrix.

[0259] The drive circuit 210 has a PSW241 (power switch), a PSW242, and a peripheral circuit 215. The peripheral circuit 215 has a peripheral circuit 211 (Row Decoder), a control circuit 212 (Control Circuit), and a voltage generation circuit 228. Note that the semiconductor device 200 has elements or circuits having various functions such as the memory array 220, the PSW241, 242, the peripheral circuit 211, the control circuit 212, and the voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or a subsystem.

[0260] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0261] Also, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. Note that the signals PON1 and PON2 may be generated by the control circuit 212.

[0262] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0263] The voltage generation circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0264] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 includes a row decoder 221 (Row Decoder), a column decoder 222 (Column Decoder), a row driver 223 (Row Driver), a column driver 224 (Column Driver), an input circuit 225 (Input Cir.), an output circuit 226 (Output Cir.), and a sense amplifier 227 (sense amplifier).

[0265] The row decoder 221 and the column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying the row to be accessed, and the column decoder 222 is a circuit for specifying the column to be accessed. The row driver 223 has the function of selecting the wiring specified by the row decoder 221. The column driver 224 has functions such as writing data to the memory device 100, reading data from the memory device 100, and holding the read data.

[0266] The input circuit 225 has the function of holding the signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is the data (Din) to be written to the memory device 100. The data (Dout) read by the column driver 224 from the memory device 100 is output to the output circuit 226. The output circuit 226 has the function of holding Dout. Also, the output circuit 226 has the function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is the signal RDA.

[0267] PSW241 has a function of controlling the supply of VDD to the peripheral circuit 215. PSW242 has a function of controlling the supply of VHM to the row driver 223. Here, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW241 is controlled by the signal PON1, and the on / off of PSW242 is controlled by the signal PON2. In FIG. 48, in the peripheral circuit 215, the number of power supply domains to which VDD is supplied is set to 1, but it can also be plural. In this case, a power switch may be provided for each power supply domain.

[0268] The drive circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in FIG. 49A, the drive circuit 210 and the memory array 220 may be provided overlapping each other. By providing the drive circuit 210 and the memory array 220 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 49B, a plurality of memory arrays 220 may be provided stacked on the drive circuit 210.

[0269] Also, as shown in FIG. 49C, the memory array 220 may be provided in the upper layer and the lower layer of the drive circuit 210. FIG. 49C shows an example in which one layer of the memory array 220 is provided in each of the upper layer and the lower layer of the drive circuit 210. By arranging so that the drive circuit 210 is sandwiched between a plurality of memory arrays 220, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 220 stacked in the upper layer of the drive circuit 210 and the number of layers of the memory array 220 stacked in the lower layer of the drive circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked in the upper layer of the drive circuit 210 is equal to the number of memory arrays 220 stacked in the lower layer of the drive circuit 210.

[0270] <Cross-sectional configuration example of the semiconductor device> FIG. 50 shows a cross-sectional configuration example of the semiconductor device 200 shown in FIG. 49A. FIG. 50 shows a part of the semiconductor device 200 shown in FIG. 49A.

[0271] In FIG. 50, transistors 301, 302, and 303 included in the drive circuit 210 are shown. Note that transistors 301 and 302 function as part of the sense amplifier 304. Also, transistor 303 functions as a column selection switch. Specifically, the conductor BL included in the memory array 220 is electrically connected to one of the source and drain of transistor 301, the gate of transistor 301 is electrically connected to one of the source and drain of transistor 302, and the gate of transistor 302 is electrically connected to the other of the source and drain of transistor 301. Also, one of the source and drain of transistor 301 and the other of the source and drain of transistor 302 are electrically connected to one of the source and drain of transistor 303 that functions as a column selection switch. Thereby, the layout area of the semiconductor device 200 can be reduced. Note that FIG. 50 shows an example in which seven memory elements MC are provided per one memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of memory elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0272] The conductor BL of the memory array 220 is electrically connected to the sense amplifier 304 and the transistor 303 that functions as a column selection switch via a conductor 752 formed to be embedded in insulators 726 and 722, a conductor 705, a conductor 714, and a conductor 715. Note that the circuits and transistors included in the drive circuit 210 are an example and are not limited to the circuit configuration and transistor structure thereof. In addition to the above, appropriate circuits and transistors can be provided according to the configuration of the semiconductor device 200 and its driving method, such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit.

[0273] Transistors 301, 302, and 303 are provided on substrate 311 and each have a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. Note that, as shown in FIG. 50, one low-resistance region may be shared as one of the source regions or drain regions of transistors 301 and 302 and the other source region or drain region.

[0274] Transistors 301, 302, and 303 have a semiconductor region 313 (a part of the substrate 311) in which a channel is formed and has a convex shape. Also, the side surface and the upper surface of the semiconductor region 313 are provided to be covered with the conductor 316 via the insulator 315. Note that the conductor 316 may be formed of a material that adjusts the work function. Since such transistors 301, 302, and 303 utilize the convex portions of the semiconductor substrate, they are also called FIN-type transistors. Note that an insulator that functions as a mask for forming the convex portions may be in contact with the upper portions of the convex portions. Here, a case in which a part of the semiconductor substrate is processed to form the convex portions has been described, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0275] Transistors 301, 302, and 303 may each be either a p-channel type or an n-channel type, but it is preferable that transistors 301 and 302 have different polarities.

[0276] In regions where the channel of the semiconductor region 313 is formed, regions in the vicinity thereof, source regions, or drain regions such as the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, by using GaAs, GaAlAs, etc., the transistors 301, 302, and 303 may be HEMTs (High Electron Mobility Transistors).

[0277] The low-resistance regions 314a and 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron.

[0278] The insulator 315 functions as a gate insulating film for the transistors 301, 302, and 303.

[0279] The conductor 316 that functions as a gate electrode can use a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0280] Note that since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0281] Also, it is preferable that an insulator 317 that functions as an etch stopper is provided above the conductor 316. Further, it is preferable that an insulator 318 that functions as a spacer is provided on the side surface of the insulator 315. By providing the insulator 317 and the insulator 318, the low resistance regions 314a and 314b and the region where the conductor 328 is electrically connected can be self-alignedly defined. Therefore, even if an alignment deviation occurs when forming an opening for exposing a part of the low resistance region 314a and the low resistance region 314b, an opening for exposing the intended region can be formed. By forming the conductor 328 in the opening thus formed, a good contact with reduced contact resistance can be obtained between the low resistance region 314a, the low resistance region 314b, and the conductor 328. The contact between the low resistance region 314a and the low resistance region 314b and the conductor 328 formed in this way may be referred to as a self-aligned contact. Further, a conductor 329 that is electrically connected to the conductor 316 may be provided so as to be embedded in the insulator 317 and the insulator 322.

[0282] Over the transistors 301, 302, and 303, insulators 320, 322, 324, 326, and 327 are sequentially stacked and provided.

[0283] As the insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxynitride, nitrided silicon oxide, silicon nitride, aluminum oxide, aluminum oxynitride, nitrided aluminum oxide, aluminum nitride, etc. may be used.

[0284] The insulator 322 may have a function as a planarization film that planarizes the step formed by the transistor 301 or the like provided below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0285] In addition, for the insulator 324, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing into the region where the memory array 220 is provided, such as the substrate 311 or the transistor 301.

[0286] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the memory element MC, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0287] The amount of hydrogen desorption can be analyzed using, for example, temperature programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 10×10 15 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm 2 or less is sufficient.

[0288] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulators 326 and 327 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0289] In addition, conductors 328, 329, and 330, etc., which are electrically connected to the memory array 220, are embedded in the insulators 320, 322, 324, 326, and 327. Note that the conductors 328, 329, and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Further, in this specification, etc., a wiring and a plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0290] As materials for each plug and wiring (conductors 328, 329, and 330, etc.), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in a stacked manner. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0291] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in FIG. 50, the insulators 350, 352, and 354 are stacked in order. Also, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 has a function as a plug or a wiring. Note that the conductor 356 can be provided using the same material as the conductors 328, 329, and 330.

[0292] Note that, for example, as with the insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 301 or the like and the memory element MC can be separated by a barrier layer, and diffusion of hydrogen from the transistor 301 or the like to the memory element MC can be suppressed.

[0293] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 301 or the like can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0294] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 50, the insulators 360, 362, and 364 are sequentially laminated and provided. Further, a conductor 366 is formed in the insulators 360, 362, and 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same materials as the conductors 328, 329, and 330.

[0295] Note that, for example, as with the insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 360. Further, the conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 301 or the like and the memory element MC can be separated by a barrier layer, and diffusion of hydrogen from the transistor 301 or the like to the memory element MC can be suppressed.

[0296] An insulator 722 is provided on the insulator 364 and the conductor 366, and a memory array 220 is provided above the insulator 722. A barrier film made of the same material as the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0297] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0298] (Embodiment 4) In this embodiment, an application example of a semiconductor device using the memory device shown in the previous embodiment will be described. The memory device shown in the previous embodiment can be applied to various removable storage devices such as a memory card (e.g., SD card), a USB memory, and an SSD (solid state drive). Some configuration examples of the removable storage device are schematically shown in FIGS. 51A to 51E. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0299] FIG. 51A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The memory device or semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like.

[0300] FIG. 51B is a schematic diagram of the appearance of an SD card, and FIG. 51C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. A storage device or a semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 or the like.

[0301] FIG. 51D is a schematic diagram of the appearance of an SSD, and FIG. 51E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A storage device or a semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 or the like.

[0302] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0303] (Embodiment 5) FIGS. 52A to 52G show specific examples of electronic devices equipped with a storage device or a semiconductor device according to an aspect of the present invention.

[0304] <Electronic device / system> A memory device or semiconductor device according to an aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book terminals, television devices, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, audio playback devices, and the like. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large computers such as server systems.

[0305] An electronic device according to an aspect of the present invention may have an antenna. By receiving a signal with the antenna, it is possible to display video, information, etc. on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0306] An electronic device according to an aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0307] An electronic device according to an aspect of the present invention can have various functions. For example, it can have functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, and the like.

[0308] [Information terminal] Using the memory device or semiconductor device according to one aspect of the present invention, a memory device for holding a program of a microcontroller can be formed. Therefore, according to one aspect of the present invention, the microcontroller chip can be miniaturized.

[0309] FIG. 52A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided in the display unit 5102, and buttons are provided in the housing 5101. By using the miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Also, a memory device according to one aspect of the present invention may be used for the storage of the mobile phone. Thereby, the storage capacity per unit area of the storage can be increased.

[0310] FIG. 52B shows a notebook information terminal 5200. The notebook information terminal 5200 has a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using the miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook information terminal can be effectively utilized. Also, a memory device according to one aspect of the present invention may be used for the storage of the notebook information terminal. Thereby, the storage capacity per unit area of the storage can be increased.

[0311] In the above description, a smartphone and a notebook information terminal are illustrated in FIGS. 52A and 52B as examples of electronic devices, respectively. However, information terminals other than smartphones and notebook information terminals can be applied. Examples of information terminals other than smartphones and notebook information terminals include, for example, PDAs (Personal Digital Assistants), desktop information terminals, workstations, and the like.

[0312] [Game console] FIG. 52C shows a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided on the housing 5301 to another housing (not shown), the video output to the display unit 5304 can be output to another video device (not shown). At this time, the housing 5302 and the housing 5303 can each function as an operation unit. Thereby, a plurality of players can play games simultaneously. A storage device or a semiconductor device according to an aspect of the present invention can be incorporated into chips etc. provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0313] Further, FIG. 52D shows a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0314] By using a miniaturized microcontroller according to an aspect of the present invention in game machines such as the portable game machine 5300 and the stationary game machine 5400, the limited space inside the game machine can be effectively utilized. Also, a storage device or a semiconductor device according to an aspect of the present invention may be used for the storage of the portable game machine. Thereby, the storage capacity per unit area of the storage can be increased.

[0315] In FIGS. 52C and 52D, a portable game machine and a stationary game machine are illustrated as examples of game machines, but the game machines to which the microcontroller according to an aspect of the present invention is applied are not limited thereto. Examples of game machines to which the microcontroller according to an aspect of the present invention is applied include, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), and pitching machines for batting practice installed in sports facilities.

[0316] [Large computer] A memory device, a semiconductor device, or the like according to one aspect of the present invention can be applied to a large computer.

[0317] FIG. 52E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 52F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0318] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of substrates 5504, and a microcontroller according to one aspect of the present invention can be mounted on the substrate. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space of the large computer can be effectively utilized. Further, a memory device, a semiconductor device, or the like according to one aspect of the present invention may be used for the storage of the large computer. Thereby, the storage capacity per unit area of the storage can be increased.

[0319] In FIGS. 52E and 52F, a supercomputer is illustrated as an example of a large computer, but the large computer to which the microcontroller according to one aspect of the present invention is applied is not limited thereto. Examples of the large computer to which the microcontroller according to one aspect of the present invention is applied include, for example, a computer (server) that provides services and a large general-purpose computer (mainframe).

[0320] [Household Appliance] FIG. 52G shows an electric refrigerator-freezer 5800, which is an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0321] A memory device, a semiconductor device, or the like according to an aspect of the present invention can also be applied to an electric refrigerator 5800. For example, by applying the miniaturized microcontroller according to an aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0322] Although an electric refrigerator has been described as an example of an electric appliance, other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating and cooling appliance including an air conditioner, a washing machine, a dryer, and audio-visual equipment.

[0323] The electronic device, the function of the electronic device, the effect, etc. described in the present embodiment can be appropriately combined with the description of other electronic devices.

[0324] The present embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

Description of Reference Numerals

[0325] 100: Memory device, 105: Region, 110: Memory cell array, 120: Memory string, 121: Substrate, 122: Layer, 123: Insulator, 124: Insulator, 125: Semiconductor, 126: Insulator, 127: Semiconductor, 128: Conductor, 129: Insulator, 130: Conductor, 132: Insulator, 134: Conductor, 136: Conductor

Claims

1. A structure extending in a first direction, A plurality of first conductors extending in a second direction intersecting the first direction, A plurality of second conductors extending in the second direction, comprising: The structure includes A third conductor, A first insulator, A plurality of fourth conductors, A first semiconductor, A second insulator, A second semiconductor, A third insulator, In a first region corresponding to each intersection of the plurality of first conductors and the structure, Outside the third conductor, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged in this order, In the first region, a part of the first conductor functions as a first gate electrode of a first transistor, a channel of the first transistor is formed in the first semiconductor, and a part of the third conductor functions as a second gate electrode of the first transistor, In a second region corresponding to each intersection of the plurality of second conductors and the structure, Outside the third conductor, the first insulator, any one of the plurality of fourth conductors, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged in this order, and any one of the plurality of fourth conductors is in contact with the first semiconductor, In the second region, a part of the second conductor functions as a first gate electrode of a second transistor, a channel of the second transistor is formed in the second semiconductor, and a part of any one of the plurality of fourth conductors functions as a second gate electrode of the second transistor, The first semiconductor includes an oxide semiconductor, The second semiconductor includes silicon, The second semiconductor has a region in contact with the first layer, The semiconductor device, wherein the first layer contains a first metal element.

2. In claim 1, The semiconductor device, wherein the first metal element is nickel.

3. In claim 1 or claim 2, The semiconductor device, wherein the first layer contains silicon and phosphorus.

4. In any one of claims 1 to 3, The semiconductor device, wherein the oxide semiconductor contains at least one of indium and zinc.

5. In any one of claims 1 to 4, The semiconductor device, wherein the oxide semiconductor contains CAAC-OS, nc-OS, or a-like OS.

Images