Written mask latch bit cell

Abstract

The SRAM write masked latch bitcell includes a write mask circuit that forces the value of the write data node to a first value in response to assertion of a first write mask signal and forces the value of the write data node to a second value in response to assertion of a second write mask signal. A pass gate provides data on the write data node to an internal node of the bitcell in response to a write word line signal being asserted. A keeper circuit maintains the value of the first node regardless of the value of the write word line signal while the first write mask signal and the second write mask signal are deasserted.

Description

Technical Field

[0001] This application relates to SRAM and SRAM bit cells. Selectively writing to bit cells within SRAM enables more efficient overall operation of the SRAM. It is desirable to continue to improve the impact on the area of masked writes to SRAM cells so as to help provide improved system performance.

Summary of the Invention

Means for Solving the Problems

[0002] (Disclosure of Embodiments of the Invention) Accordingly, in one embodiment, an apparatus includes a write-masked latch bit cell including a write portion. The write portion includes a write mask circuit that sets the value of a write data node to a first value in response to the assertion of a first write mask signal and causes the write data node to have a second value in response to the assertion of a second write mask signal. A pass gate is coupled to the write data node and supplies the value on the write data node to a first node in response to the assertion of a write word line signal. A keeper circuit is configured to maintain the value of the first node regardless of the value of the write word line signal while the first write mask signal and the second write mask signal are deasserted.

[0003] In another embodiment, a method includes setting a write data node in a write-masked latch bit cell to a first value in response to the assertion of a first write mask signal and setting the write data node to a second value in response to the assertion of a second write mask signal. The method includes coupling the write data node to a first node in response to the assertion of a write word line signal. Data on the first node is maintained by a keeper circuit regardless of the value of the write word line signal while the first write mask signal and the second write mask signal are deasserted.

[0004] In another embodiment, the method includes writing a write-masked latch bit cell in response to a write word line (WWL) signal and an active low write word line (WWLX) signal being asserted in combination with either a first write mask signal or a second write mask signal being asserted. The state of the write-masked latch bit cell is maintained while the WWL signal and the WWLX signal are asserted and the first write mask signal and the second write mask signal are de-asserted.

[0005] The present invention can be better understood by reference to the accompanying drawings, and its various objects, features, and advantages will become apparent to those skilled in the art.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12A

Figure 12B

Figure 12C

Figure 13

Figure 14

Figure 15

Figure 16

[0007] The use of the same reference numerals in different drawings indicates similar or identical items.

[0008] An 8-transistor (8T) static random access memory (SRAM) array does not scale well in terms of area within newer technology nodes. However, circuits built with standard cell design rules continue to scale relatively well within newer technology nodes. Building an SRAM array with standard cell design rules enables the use of a smaller area even when there are more transistors. FIG. 1 shows an SRAM bit cell implemented as a latch bit cell 100 with individual read and write ports. The latch bit cell 100 uses 12 transistors per bit as compared to the 8 transistors of an 8T SRAM bit cell, but due to the use of standard cell design rules, it is noted that in certain manufacturing technologies, it still uses less area. A major difference between the latch-type bit cell and the classical 6T / 8T SRAM bit cell is that the latch bit cell invalidates feedback during writing. In contrast, in a 6T / 8T bit cell, the pass gate has to fight the pull-up to perform a write. The latch bit cell does not have such contention during writing.

[0009] The approach of FIG. 1 implemented using standard cell design rules means that there is no overhead required for the use of a custom SRAM macro, thereby reducing the area. For example, the use of standard cell layout rules enables adjacent to the standard cell logic with a 0-connected poly pitch (CPP) (horizontal distance between transistors). More traditional approaches to SRAM have boundary cells and edge cells required for lithography purposes. Since the standard cell design rules scale well, implementing an SRAM cell based on the latch bit cell 100 and the standard cell design rules enables the SRAM design to scale in terms of area similar to future standard architectures.

[0010] The latch bit cell shown in FIG. 1 amortizes the local inverters normally present in the latch over more cells. The latch bit cell shown in FIG. 1 removes the local inverters conventionally used for the inputs to the latch, including the write bit line (WBL), write word line (WWL), active low write word line (WWLX), read word line (RWL), and active low read word line (RWLX). In more traditional latch arrays, CMOS combinational stages are used between latches. The latch bit cell 100 uses a tri-state output for RBL101. The use of the tri-state driver by the latch bit cell enables the outputs (read bit lines) of several cells, e.g., 16 cells, to be combined together using a tri-state output driver to avoid any additional combinational stages (NOR / NANDing, etc.) of the output data.

[0011] Figure 2 shows a stick layout of a latch bit cell 100 showing seven transistors in the horizontal direction. The boxes indicate the source / drain connections of the transistors. The gate regions of the transistors are shown as vertical lines having the same markings as the transistors in FIG. 1. The long vertical line 201 indicates, for example, the shared gate connections by transistors PFBO and NFBO, and transistors PINV and NINV. If there is a blank in the box, there are nodes that are not named in FIG. 1, but the unidentified source / drain connections and gate connections can be easily seen in FIG. 1. The layout includes dummy cell (DUM) transistors. A dummy is a transistor that is formed but not connected. The use of dummy transistors provides an efficient way to provide separation between other transistors. Also, the use of dummy transistors provides an advantage in the ability to change the type of transistors used with respect to the threshold voltage (Vt). In an embodiment, the write part of the latch (transistors PPG, NPG, PINV, NINV, NFB1, NFB0, PFB0, PFB1) does not require high performance, while the read part of the latch (transistors PRP1, PRP0, NRP0, NRP1) requires high performance. Note that the first letter of the transistor name indicates the type of transistor (N or P), and the remaining letters indicate its function (PG pass gate, INV inverter, FB feedback, RP read port).

[0012] Referring to FIG. 3, the read portion 301 of the latch bit cell 100 including transistors PRP0, PRP1, NRP0, and NRP1 enables implementation using transistors with a lower Vt (such as ultra low Vt (ulvt)), thereby providing the required high performance. On the other hand, the write portion 303 of the latch bit cell 100 on the left side of the dummy transistor in FIG. 3 is implemented with a higher threshold voltage transistor (such as a low Vt (lvt) transistor). Transistors with a higher Vt provide lower performance but also less leakage, and transistors with a lower Vt are utilized only when required for performance. Thus, the layout option enables different threshold voltages to be utilized on read ports and write ports with different performance requirements, thereby reducing leakage current compared to the case where lower Vt devices must be used for all devices to meet the performance requirements for only a portion of the bit cell. The transistors within the read port and write port share diffusion between adjacent cells and, if possible, reduce the xtor (transistor) load by half for a non-optimized design.

[0013] Referring again to FIG. 1, the operation of the latch bit cell 100 will be described. The data written to the cell on the write bit line WBL102 (also referred to herein as write data (WD)) is supplied to a pass gate 103 formed from transistors NPG and PPG. The gates or those transistors are respectively coupled to a write word line (WWL) and a write word line X (WWLX), where "X" indicates that the signal is active low. When WWL and WWLX are asserted, the data on the WBL is passed as data "D" to an inverter 104 formed by transistors PINV and NINV. Transistors NFB1 and PFB1 turn off when WWL and WWLX are asserted. The gates of NFB0 and PFB0 in the feedback portion of the bit latch cell 100 receive the output D_X (the inverted value of "D") from the inverter. The gates of PRP1 and NRP1 in the read portion 106 of the latch also receive D_X. When WWL and WWLX are de-asserted, the pass gate 103 is blocked, transistors NFB1 and PFB1 turn on, and D_X turns on either transistor NFB0 or PFB0 to enable the supply of "D" as a feedback signal. Transistors NFB1, NFB0, PFB0, and PFB1 function as a keeper circuit 108 and, together with the inverter formed by transistors PINV and NINV, ensure that the data on node D is maintained when WWL and WWLX are de-asserted. In this way, the value of D is maintained in the write portion of the latch bit cell 100 and is available when the latch is read. In the latch bit cell 100, the PMOS transistors PINV, PFB1, and PRP1 are coupled to the power supply voltage (VDD) at their sources. The NMOS transistors NINV, NFB1, and NRP1 are coupled to the second power supply voltage (ground) at their sources.

[0014] To read the latch bit cell, the read word line (RWL) and RWLX are asserted, turning on NRP0 and PRP0 respectively. Note that "X" indicates an active low signal. The assertion of RWL and RWLX enables the value of D_X to determine the value of the output signal read bit line (RBL) 101, which is also referred to herein as read data (RD). When RWL and RWLX are de-asserted, RBL is set to high impedance, allowing other SRAM cells to drive RBL when they are selected to be read.

[0015] Figure 4 shows an embodiment in which a group of 32 latch bit cells is formed within two groups of latch bit cells (bits <31:16> and bits <15:0>). Each group of latch bit cells supplies bits to multiplexer 401, which selects bits from either bits <31:16> or bits <15:0> and supplies the selected bits on rdData 403. In the embodiment of Figure 4, the three-state driver on the read side of the latch bit cell enables 16 bits (only one active at a time) to drive the same RBL that is supplied to multiplexer 401. Thus, only one RWL / RWLX is turned on at a time within each group [31:16] and [15:0] to ensure that multiple latch bit cells do not drive RBL simultaneously, causing a high current situation. It is also important to ensure that either one of the RWL / RWLX signals is active and that one of the bit cells drives a high or low logic level on RBL. All de-asserted RWL / RWLX pairs result in a floating node on RBL, which can cause high current draw in downstream CMOS gates that receive a signal intermediate between VDD and VSS.

[0016] FIG. 5 shows a block diagram of an embodiment having bit cells of 64 rows and 2 columns, where multiplexer 501 selects 1 bit from 64 rows and 2 columns. Although not shown in FIG. 5 for ease of explanation, the embodiment shown in FIG. 5 also requires a write column multiplexer function. One way to achieve this is to supply the WWL / WWLX pair to the even physical columns and another WWL / WWLX pair to the odd physical columns. In this way, every other cell can be written to. Another way to achieve the write multiplexer function is to use a write mask, as will be further described herein.

[0017] During a write operation, when a particular word line is asserted, all the bits within the word line may change state. Instead of changing the state of all the bits within the word line, it is advantageous to write only to the selected cells of the word line, which helps to make the write operation more efficient. Thus, in another embodiment shown in FIG. 6, the latch bit cell 600 includes a write mask. The write mask utilizes signals write one (WRONEX) (where "X" indicates that the signal is active low) and write zero (WRZERO). The write mask circuit is formed by transistors PWD601 and NWD603, where WD represents write data. When WRONEX is asserted (active low), the write data (WD) node is pulled high through transistor PWD, and when WRZERO is asserted, the WD node is pulled low through transistor NWD. The write mask enables a write word line of one row of cells to be asserted without changing the state of all the cells. For example, only one byte or several bits on the word line can change by asserting the word line and using the write mask to ensure that only the targeted cells are written. In addition to the transistors PWD and NWD used to determine the value of WD, the write-masked latch bit cell 600 includes transistors NFB2 and PFB2 used in the keeper circuit 605. These transistors are used to ensure that the feedback function of the keeper circuit continues to operate so that the latch bit cell maintains its state even when WWL and WWLX are asserted. When WWLX is asserted, NFB1 turns off, and when WWL is asserted, PFB1 turns off. Transistors NFB2 and PFB2 ensure that when the bit has a write mask that effectively blocks writing to the latch bit cell, the keeper circuit drives "D" with the correct value from the node between NFB0 and PFB0 when WWL and WWLX are asserted. Note that when WRONEX and WRZERO are de-asserted, WD floats.By incorporating the PWD and NWD transistors into the bit cell itself, the capacitance on the intermediate node WD is kept low enough to avoid cell stability issues when WWL / WWLX is asserted. The keeper stack (KSTK) nodes PKSTK602 and NKSTK604 are labeled in FIG. 6.

[0018] FIG. 7 shows a bar chart of the layout of the write-masked latch bit cell 600 shown in FIG. 6. It should be noted that the solution in FIG. 6 increases the cell size by four transistors and includes extra dummy cells compared to the layout shown in FIG. 2. Thus, the write-masked latch bit cell 600 (FIG. 6) shows an increase from 3CPP to 10CPP compared to the layout of FIG. 2 (7CPP) for the latch bit cell 100 shown in FIG. 1.

[0019] FIG. 8 shows a more efficient embodiment of the write-masked latch bit cell 800 as compared to the write-masked latch bit cell 600 of FIG. 6. Note that the additional transistors NFB2 and PFB2 coupled to the keeper stack node in the write-masked latch bit cell 600 replace NFB1 and PFB1 in the write-masked latch bit cell 800. The write-masked latch bit cell 800 does not disable the keeper circuit 805 by turning off NFB1 and PFB1 when WWL and WWLX are asserted (see FIGS. 1 and 6). Instead, the write-masked latch bit cell 800 only disables the keeper in response to WRONEX or WRZERO being asserted. This ensures that the latch bit cell 800 retains its state when the latch bit cell 800 is masked. Note that WWL and WWLX are coupled only to the passgate transistors PPG and NPG in the write-masked latch bit cell 800. When WRONEX is asserted (active low), the transistor NFB2 turns off, and when WRZERO is asserted, the transistor PFB2 turns off. Assuming WWLX and WWL are asserted, when WRONEX is asserted, node WD goes high and node D goes high, and when WRZERO is asserted (active low), node WD goes low and node D goes low. When each mask line (WRONEX and WRZERO) is de-asserted, both NFB2 and PFB2 are on, and the keeper circuit maintains the value of node D according to the value of D_X provided by the inverter formed by transistors PINV and NINV. D_X turns on transistor NFB0 to maintain a low value with respect to node D, or turns on PFB0 to maintain a high value with respect to node D. The write mask circuit is formed by transistors PWD801 and NWD803 and is the same as the embodiment shown in FIG. 6.The read side of the write-masked latch bit cell 800 formed by transistors PRP1, PRP0, NRP0, and NRP1 is the same as the previous latch bit cell embodiments 100 and 600 shown in FIGS. 1 and 6, respectively.

[0020] Whenever either WRONEX or WRZERO is asserted, all the bit cells within the column coupled to WRONEX and WRZERO disable their keeper circuits because asserting WRONEX turns NFB2 off and prevents D_X from being pulled to VSS through NFB0 and NFB2, and asserting WRZERO turns PFB2 off and prevents D_X from being pulled to BDD through PFB0 and PBF2. Thus, node D floats in response to the assertion of WRONEX or WRZERO. If the assertion of WRONEX or WRZERO is long enough, at least a portion of the keeper circuits turn off due to NFB1 or PFB1 being disabled by the assertion of WRONEX or WRZERO, so the cells along the column can change state. Thus, WRONEX and WRZERO should be asserted as pulse writes. Thus, these signals should be asserted as self-timing pulses with a length of several inverter delays, e.g., 50 ps. The pulse can be generated using, for example, nine inverters. The number of inverters depends on the technology used. FIG. 9 shows embodiments of a pulse circuit 901 for WRZERO and a pulse circuit 903 for WRONEX. Note that in each of the pulse circuits shown in FIG. 9, an odd number of inverters are used. In FIG. 9, the inputs (write 0 and write 1) to the logic gates are assumed to be active high. Many other pulse generator circuits suitable for WRONEX and WRZERO are known to those skilled in the art. The pulse should be long enough to write one cell but short enough so that other cells along the column do not lose their state due to node D floating during the pulse, and thus the area penalty for additional write mask capabilities is relatively small compared to the write mask latched bit cell shown in FIG. 6.

[0021] FIG. 10 shows an example of the layout of the circuit of FIG. 8. Note that only one dummy transistor is required for the latch bit cell 800. The layout of the latch bit cell 800 shown in FIG. 10 has only one extra CPP with respect to the baseline latch bit cell 100 shown in FIG. 2.

[0022] FIG. 11 shows a latch array column of the latch shown in FIG. 1 formed in a single standard cell row. Note that the term "single standard cell row" refers to a physical row of an integrated circuit and not to a logical row of an SRAM. In a standard design with non-hybrid standard cell library rules, all devices typically have the same number of fins. In a conventional standard cell architecture, all rows of devices have the same height. In the world of FinFETs, this generally also means that the number of fins per finger is the same. FIG. 12A shows a conventional standard cell architecture of a PFET and an NFET having two fins per finger. Each standard cell is uniform within the row and has P and N transistors.

[0023] A hybrid standard cell architecture utilizes alternating rows of high-performance and high-density (but lower-performance) standard cells. For example, in one embodiment, it means that the high-performance cells and the cells with two fins per transistor finger for lower performance have one fin per transistor finger. As shown in FIG. 12B, it results in alternating rows of higher and lower cells, and shorter rows. The advantage of the hybrid standard cell architecture is smaller area and reduced power, but the shorter cell height results in a performance degradation compared to the larger two-fin cells. FIG. 12C shows an exemplary one fin per transistor finger device 1201 and two fins per transistor finger device 1203.

[0024] FIG. 13 shows that when constructing a standard cell latch array by moving from a conventional standard cell library to a hybrid standard cell library approach, there may be unbalanced performance between adjacent bits. For example, the bit cells in column 1301 are formed from, for example, "fast" standard cells having two fins per finger. The logic SRAM column 1301 is within a physical fast row of the hybrid row architecture in the illustrated embodiment. The bit cells in column 1303 are, for example, "slow" cells having one fin per finger. Thus, reading Rddata[1] 1302 from any of the bit cells in column 1301 is done faster than reading Rddata[0] 1304 from column 1302. Thus, adjacent bits are read at different timings (one fast and the other slow), which is undesirable.

[0025] To provide more balanced performance between high-speed cells and low-speed cells, the embodiment shown in FIG. 14 uses a group of bit cells from one column, e.g., bit cells within column 1401 (high-speed physical row) or 1403 (low-speed physical row), but uses a multiplexer circuit from other rows. For example, low-speed multiplexer 1407 selects one bit from 32 high-speed bit cells. The 32 high-speed bit cells are high-speed bit cell 1404 (only any one of bits <15:0> is shown) and high-speed bit cell 1406 (only any one of bits <31:16> is shown). High-speed multiplexer 1415 selects one bit from 32 low-speed bit cells. The 32 low-speed bit cells are low-speed bit cell 1409 (only any one of bits <15:0> is shown) and low-speed bit cell 1411 (only any one of bits <31:16> is shown). Similarly, high-speed bit cells 1421 and 1423 use low-speed multiplexer 1425, and low-speed bit cells 1427 and 1429 use high-speed multiplexer 1431. The read data (Rddata[1]) supplied by high-speed multiplexer 1435 has a high-speed multiplexer (2 fins) but has low-speed bit cells (1 fin), and the read data (Rddata[0]) has a low-speed multiplexer (1 fin) but has high-speed bit cells (2 fins). Thus, one logical SRAM column has high-speed bit cells and low-speed multiplexer stages, while an adjacent SRAM logical column has low-speed bit cells and high-speed multiplexer stages. This provides an improved performance balance compared to an array where every other bit has significantly different timings - high and low.

[0026] FIG. 15 shows a high-level block diagram of an array of bit cells. FIG. 14 shows the latch bit cell of FIG. 1 used as bit cells within columns 1401 and 1403, although in other embodiments, other bit cells can be used. FIG. 16 shows an embodiment in which the masked write latch bit cell 600 of FIG. 6 or the masked write latch bit cell 800 of FIG. 8 is utilized. FIG. 16 shows how the mask signal WRONEX and the WRZERO signal are distributed to the bit cells.

[0027] The write-masked SRAM bit cell has been described above. The description of the invention set forth in this specification is exemplary and is not intended to limit the scope of the invention as set forth in the following claims. Modifications and variations of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the following claims.

Claims

1. An apparatus, comprising a latched bit cell masked for writing, the latched bit cell masked for writing including a write portion of the latched bit cell masked for writing, the write portion, a write mask circuit that sets the value of a write data node to a first value in response to an assertion of a first write mask signal and sets the value of the write data node to a second value in response to an assertion of a second write mask signal, a pass gate coupled to the write data node that supplies the value of the write data node to a first node in response to an assertion of a write word line signal, and a keeper circuit configured to maintain the value of data on the first node independent of the value of the write word line signal while the first write mask signal and the second write mask signal are deasserted. An apparatus.

2. The write data node floats in response to deassertion of the first write mask signal and the second write mask signal. The apparatus of claim 1.

3. The write mask circuit, includes a first write data transistor coupled between a first power supply node and the write data node, the first write data transistor having a gate coupled to the first write mask signal, and a second write data transistor coupled between the write data node and a second power supply node, the second write data transistor having a gate coupled to the second write mask signal. The apparatus of claim 2.

4. The apparatus, An inverter coupled to the first node to supply inverted data, The keeper circuit, Comprises a keeper stack including a first keeper transistor, a second keeper transistor, a third keeper transistor, and a fourth keeper transistor, The first keeper transistor has a first gate coupled to the first write mask signal and a first conduction terminal coupled between the second power supply node and the second keeper transistor, The second keeper transistor has a second gate coupled to the inverted data and a second conduction terminal coupled between the first keeper transistor and the first node, The third keeper transistor has a third gate coupled to the inverted data and a third conduction terminal coupled between the first node and the fourth keeper transistor, The fourth keeper transistor has a fourth gate coupled to the second write mask signal and a fourth conduction terminal coupled between the third keeper transistor and the first power supply node, The apparatus of claim 3.

5. The apparatus, Comprises an inverter coupled to the first node to supply inverted data, The keeper circuit, Comprises a keeper stack including a first keeper transistor, a second keeper transistor, a third keeper transistor, and a fourth keeper transistor, The first keeper transistor has a first gate coupled to the active low write word line signal and a first conduction terminal coupled between the second power supply node and the second keeper transistor, The second keeper transistor has a second gate coupled to the inverted data and a second conduction terminal coupled between the first keeper transistor and the first node, The third keeper transistor has a third gate coupled to the inverted data and a third conduction terminal coupled between the first node and the fourth keeper transistor. The fourth keeper transistor has a fourth gate coupled to the write word line signal and a fourth conduction terminal coupled between the third keeper transistor and the first power supply node. The write word line signal includes the write word line signal and the active low write word line signal. The apparatus of claim 3.

6. The keeper circuit A fifth keeper transistor coupled between the second power supply node and a first keeper node between the first keeper transistor and the second keeper transistor, the fifth keeper transistor having a fifth gate coupled to the first write mask signal; A sixth keeper transistor coupled between the first power supply node and a second keeper node between the third keeper transistor and the fourth keeper transistor, the sixth keeper transistor having a sixth gate coupled to the second write mask signal. The apparatus of claim 5.

7. A first pulse generation unit that generates the first write mask signal; A second pulse generation unit that generates the second write mask signal. The apparatus of claim 1.

8. Comprising a read portion of the written masked latch bit cell; The read portion receives a read word line signal and is coupled to supply output data on an output node of the read portion of the written masked latch bit cell in response to an assertion of the read word line signal. The output data corresponds to the data on the first node. The apparatus of claim 1.

9. The read portion of the written mask latch bit cell is configured to put the output node in a high impedance state in response to deassertion of the read word line signal. The apparatus of claim 8.

10. A method comprising: setting a write data node in a written mask latch bit cell to a first value in response to assertion of a first write mask signal; setting the write data node to a second value in response to assertion of a second write mask signal; coupling the write data node to a first node in response to assertion of a write word line signal; while the first write mask signal and the second write mask signal are deasserted, using a keeper circuit to maintain data on the first node regardless of the value of the write word line signal. A method.

11. comprising floating the write data node in response to deassertion of the first write mask signal and the second write mask signal. The method of claim 10.

12. supplying the first write mask signal to a gate of a first write data transistor; setting the write data node to the first value by coupling a first power supply node to the first node through the first write data transistor in response to assertion of the first write mask signal; supplying the second write mask signal to a gate of a second write data transistor; Setting the write data node to the second value by coupling a second power supply node to the first node via the second write data transistor in response to assertion of the second write mask signal. The method of claim 10. **Claim 13** Inverting data on the first node and supplying the inverted data to the keeper circuit. Enabling the keeper circuit in response to de-assertion of the first write mask signal and the second write mask signal. Disabling the keeper circuit in response to assertion of the first write mask signal and the second write mask signal. The method of claim 10. **Claim 14** Supplying the first write mask signal to a first gate of a first keeper transistor and enabling the first keeper transistor in response to de-assertion of the first write mask signal. Supplying the inverted data to a second gate of a second keeper transistor. Supplying the inverted data to a third gate of a third keeper transistor. Supplying the second write mask signal to a fourth gate of a fourth keeper transistor and enabling the fourth keeper transistor in response to de-assertion of the second write mask signal. The method of claim 13. **Claim 15** Supplying an active low write word line signal to a first gate of a first keeper transistor. Supplying the inverted data to a second gate of a second keeper transistor. Supplying the inverted data to a third gate of a third keeper transistor. Supplying a write word line signal to a fourth gate of a fourth keeper transistor, wherein the write word line signal includes the write word line signal and the active low write word line signal, Supplying the first write mask signal to a first gate of a fifth keeper transistor, and activating the fifth keeper transistor in response to deassertion of the first write mask signal, Supplying the second write mask signal to a sixth gate of a sixth keeper transistor, and activating the sixth keeper transistor in response to deassertion of the second write mask signal, The method of claim 13.

16. Generating the first write mask signal as a first pulse, Generating the second write mask signal as a second pulse, The method of claim 10.

17. The first pulse is short enough such that when the first pulse write mask signal is asserted and the write word line signal is not asserted, the state of the data on the first node is not changed. The method of claim 16.

18. The second pulse is short enough such that when the first pulse write mask signal is asserted and the write word line signal is not asserted, the state of the data on the first node is not changed. The method of claim 16.

19. Supplying output data to an output node of a read portion of the write masked latch bit cell in response to assertion of a read word line signal, Setting the output node to a high impedance state in response to deassertion of the read word line signal, The method of claim 10. Claim 20 A method comprising: writing a masked latch bit cell in response to a write word line (WWL) signal and an active low write word line (WWLX) signal being asserted in combination with either a first write mask signal or a second write mask signal being asserted; maintaining the state of the masked latch bit cell while the WWL signal and the WWLX signal are asserted and the first write mask signal and the second write mask signal are de-asserted. A method.

Images