Substrate and mounting substrate

Abstract

To provide a substrate capable of suppressing the generation of a solder ball in a connection part between a wiring and a center pad.SOLUTION: A substrate comprises: a base material having a main surface; a center pad part that is arranged on the main surface; a peripheral pad part existed in the circumference of the center pad part; a conductor pattern that has a wiring connecting an outer peripheral edge of the center pad part and the peripheral pad part; and a solder resist that is arranged on the main surface so as to cover the conductor pattern, and forms a first open making the center pad part expose and a second open making the peripheral pad part expose. The solder resist covers a connection part with the center pad part of the wiring.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a substrate and a mounting substrate.

Background Art

[0002] For example, Japanese Unexamined Patent Application Publication No. 2016-18846 (Patent Document 1) describes a semiconductor package. The semiconductor package described in Patent Document 1 is a QFN (Quad Flat Non-leaded) package. From the back surface of the semiconductor package of Patent Document 1, a central electrode and a plurality of peripheral electrodes are exposed. The central electrode is at the center of the back surface. The peripheral electrodes are around the central electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The semiconductor package described in Patent Document 1 is mounted on a substrate. The substrate has, for example, a base material, a conductor pattern, and a solder resist. The conductor pattern is disposed on the main surface of the base material and has a central pad, a plurality of peripheral pads, and wirings. The peripheral pads are around the central pad. The wirings connect the outer peripheral edge of the central pad and the peripheral pads. The solder resist is disposed on the main surface of the base material so as to cover the conductor pattern. In the solder resist, a first opening for exposing the central pad and a plurality of second openings for exposing the peripheral pads are formed.

[0005] The semiconductor package described in Patent Document 1 is mounted on the substrate by joining the central electrode to the central pad with a solder alloy and joining the peripheral electrodes to the peripheral pads with a solder alloy.

[0006] The first opening may be located outside the outer peripheral edge of the central pad in a plan view. That is, the connection portion between the wiring and the outer peripheral edge of the central pad is exposed from the first opening. As a result, when the solder alloy is melted to join the central electrode and the central pad, a part of the melted solder alloy may become a solder ball at the connection portion between the wiring and the outer peripheral edge of the central pad. The solder ball may cause a short circuit between adjacent peripheral pads.

[0007] The present invention has been made in view of the problems of the prior art as described above. More specifically, the present invention provides a substrate and a mounting substrate capable of suppressing the generation of solder balls at the connection portion between the wiring and the central pad.

Means for Solving the Problems

[0008] The substrate of the present invention includes a base material having a main surface, a conductor pattern disposed on the main surface and having a central pad portion, a peripheral pad portion around the central pad portion, and wiring connecting the outer peripheral edge of the central pad portion and the peripheral pad portion, and a solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening for exposing the central pad portion and a second opening for exposing the peripheral pad portion formed therein. The solder resist covers the connection portion between the wiring and the central pad portion.

[0009] In the above substrate, the first opening may be located inside the outer peripheral edge of the central pad portion in a plan view.

[0010] The above substrate may further include an annular wall disposed on the solder resist. The annular wall may be disposed outside the first opening and inside the peripheral pad portion in a plan view. The annular wall may be formed of a resin material different from the solder resist. In the above substrate, the annular wall may be formed of a resin ink colored in a color different from the solder resist. In the above substrate, the thickness of the conductor pattern may be larger than the thickness of the solder resist.

[0011] The mounting substrate of the present invention includes a substrate, a semiconductor package having a back surface, and a solder alloy. The substrate is the above-described substrate. The semiconductor package has, on the back surface, a central electrode facing the central pad portion and peripheral electrodes that are around the central electrode and face the peripheral pad portion. The solder alloy joins the central electrode and the central pad portion and also joins the peripheral electrode and the peripheral pad portion. In the above-described mounting substrate, the semiconductor package may be a QFN package.

Effects of the Invention

[0012] According to the substrate of the present invention and the mounting substrate of the present invention, it is possible to suppress the generation of solder balls at the connection portion between the wiring and the central pad.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

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Figure 8

Embodiments for Carrying Out the Invention

[0014] Details of the embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0015] (First Embodiment) The substrate according to the first embodiment will be described. Hereinafter, the substrate according to the first embodiment will be referred to as substrate 100.

[0016] <Configuration of Substrate 100> The configuration of substrate 100 will be described below.

[0017] FIG. 1 is a plan view of substrate 100. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. As shown in FIGS. 1 and 2, substrate 100 has a base material 10, a conductor pattern 20, and a solder resist 30.

[0018] The base material 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are end faces in the thickness direction of the base material 10. The second main surface 10b is the opposite surface of the first main surface 10a. The base material 10 is formed of an electrically insulating material. The base material 10 is formed of, for example, glass epoxy. However, the electrically insulating material used for the base material 10 is not limited to this.

[0019] The conductor pattern 20 is disposed on the first main surface 10a. The conductor pattern 20 is formed of an electrically conductive material. The conductor pattern 20 is formed of, for example, copper. However, the electrically conductive material used for the conductor pattern 20 is not limited to this.

[0020] The conductor pattern 20 has a central pad 21 and a plurality of peripheral pads 22. The central pad 21 is, for example, rectangular in plan view. More specifically, the central pad 21 is square in plan view. The peripheral pads 22 are arranged around the central pad 21. The peripheral pads 22 are, for example, rectangular in plan view. More specifically, the peripheral pads 22 are rectangular in plan view. The peripheral pads 22 are arranged spaced apart from the outer peripheral edge (outer peripheral edge 21a) of the central pad 21. The short sides of the peripheral pads 22 in plan view face the outer peripheral edge 21a with a gap therebetween. A plurality of peripheral pads 22 facing one side of the outer peripheral edge 21a are arranged in a row along the direction of that side.

[0021] A part of the plurality of peripheral pads 22 (referred to as peripheral pad 22a) is connected to the outer peripheral edge 21a by a wiring 23.

[0022] The base material 10 has a through hole 10c formed therein. The through hole 10c penetrates the base material 10 in the thickness direction. The through hole 10c is formed at a position overlapping the central pad 21 in plan view. A conductor layer 24 is disposed on the inner wall surface of the through hole 10c. The conductor layer 24 is connected to the central pad 21. The conductor layer 24 is also disposed on the second main surface 10b around the through hole 10c. The conductor layer 24 is formed of an electrically conductive material (for example, copper).

[0023] The solder resist 30 is disposed on the first main surface 10a so as to cover the conductor pattern 20. The solder resist 30 is also disposed on the second main surface 10b. The solder resist 30 covers a conductor pattern (not shown) disposed on the second main surface 10b. The solder resist 30 is formed of an electrically insulating material. The solder resist 30 is formed of, for example, an epoxy resin. However, the electrically insulating material used for the solder resist 30 is not limited to this. The solder resist 30 may be colored.

[0024] The solder resist 30 is formed with a first opening 31 and a plurality of second openings 32. The first opening 31 and the second openings 32 penetrate the solder resist 30 in the thickness direction. The central pad 21 is exposed from the first opening 31. The peripheral pads 22 are exposed from the second openings 32.

[0025] The first opening 31 is rectangular in plan view. More specifically, the first opening 31 is square in plan view. The first opening 31 is inside the outer peripheral edge 21a in plan view. In other words, the outer peripheral edge portion of the central pad 21 and the connection portion between the outer peripheral edge 21a and the wiring 23 are covered by the solder resist 30.

[0026] The second opening 32 is rectangular in plan view. More specifically, the second opening 32 is rectangular in plan view.

[0027] Let the thickness of the conductor pattern 20 be thickness T1, and the thickness of the solder resist 30 be thickness T2. It is preferable that the thickness T1 is greater than the thickness T2.

[0028] <Configuration of the mounting substrate 200> The configuration of the mounting substrate 200 will be described below.

[0029] FIG. 3 is a cross-sectional view of the mounting substrate 200. As shown in FIG. 3, the mounting substrate 200 has a substrate 100 and a semiconductor package 300.

[0030] The semiconductor package 300 is, for example, a QFN package. However, the semiconductor package 300 is not limited thereto. The semiconductor package 300 may be, for example, an LGA (Lead Grid Array) package. The semiconductor package 300 has a lead frame 310, a semiconductor chip 320, bonding wires 330, and a sealing resin 340.

[0031] The lead frame 310 has a die pad portion 311 and a plurality of lead portions 312. The plurality of lead portions 312 are arranged around the die pad portion 311. The lead frame 310 is formed of an electrically conductive material. The lead frame 310 is formed of, for example, a copper alloy. However, the electrically conductive material used for the lead frame 310 is not limited to this.

[0032] The semiconductor chip 320 has a front surface 320a and a back surface 320b. The front surface 320a and the back surface 320b are end faces in the thickness direction of the semiconductor chip 320. The back surface 320b is the opposite surface of the front surface 320a. The semiconductor chip 320 is arranged on the die pad portion 311. More specifically, the back surface 320b is connected to the die pad portion 311 by a solder alloy (not shown), a conductive adhesive (not shown), or the like. Although not shown, bonding pads are formed on the front surface 320a.

[0033] The bonding wire 330 is connected to the bonding pad of the semiconductor chip 320 at one end and to the lead portion 312 at the other end. The bonding wire 330 is formed of an electrically conductive material such as gold or copper. The encapsulating resin 340 encapsulates the lead frame 310, the semiconductor chip 320, and the bonding wire 330. The encapsulating resin 340 is formed of, for example, an epoxy resin. However, the resin material used for the encapsulating resin 340 is not limited to this.

[0034] The semiconductor package 300 has a front surface 300a and a back surface 300b. The front surface 300a and the back surface 300b are end faces in the thickness direction of the semiconductor package 300. FIG. 4 is a bottom view of the semiconductor package 300. As shown in FIG. 4, the die pad portion 311 and the lead portion 312 are exposed from the encapsulating resin 340 on the back surface 300b. The die pad portion 311 and the lead portion 312 that are exposed from the encapsulating resin 340 on the back surface 300b respectively become the central electrode 300c and the peripheral electrode 300d of the semiconductor package 300. The peripheral electrode 300d is arranged around the central electrode 300c.

[0035] As shown in FIG. 3, the semiconductor package 300 is mounted on the substrate 100. More specifically, the solder alloy 210 joins the central pad 21 and the central electrode 300c and also joins the peripheral pad 22 and the peripheral electrode 300d. The solder alloy 210 is formed of, for example, a tin alloy.

[0036] In mounting the semiconductor package 300 on the substrate 100, first, cream solder is applied on the central pad 21 and the peripheral pad 22. The cream solder is a paste in which an organic solvent, a flux, and particles of the solder alloy 210 are mixed. The cream solder is applied, for example, near the four corners in a plan view of the central pad 21 exposed from the first opening 31.

[0037] Second, the semiconductor package 300 is mounted on the substrate 100. At this time, the central pad 21 faces the central electrode 300c with the cream solder interposed therebetween, and the peripheral pad 22 faces the peripheral electrode 300d with the cream solder interposed therebetween. When the semiconductor package 300 is mounted on the substrate 100, the cream solder applied on the central pad 21 is spread.

[0038] Thirdly, the substrate 100 on which the semiconductor package 300 is mounted is loaded into a reflow furnace. As a result, the solder alloy 210 melts and spreads by wetting between the central pad 21 and the central electrode 300c and between the peripheral pad 22 and the peripheral electrode 300d, and the bonding between the central pad 21 and the central electrode 300c and the bonding between the peripheral pad 22 and the peripheral electrode 300d are performed. As described above, the semiconductor package 300 is mounted on the substrate 100, and the mounting substrate 200 is obtained.

[0039] Note that the gas generated when the flux and the organic solvent volatilize from the cream solder is discharged through the through hole 10c. That is, the through hole 10c is a gas vent hole during reflow.

[0040] <Effect of the substrate 100> The effects of the substrate 100 will be described below while comparing with the substrate according to the comparative example. The substrate according to the comparative example is referred to as substrate 100A.

[0041] FIG. 5 is a plan view of the substrate 100A. As shown in FIG. 5, the substrate 100A has a base material 10 (not shown in FIG. 5), a conductor pattern 20, and a solder resist 30. In the substrate 100A, the conductor pattern 20 has a central pad 21, a plurality of peripheral pads 22, and a wiring 23. In these respects, the configuration of the substrate 100A is common to the configuration of the substrate 100.

[0042] In the substrate 100A, the first opening 31 is outside the outer peripheral edge 21a in a plan view. As a result, the connection portion between the outer peripheral edge 21a and the wiring 23 is exposed from the first opening 31. That is, the connection portion between the outer peripheral edge 21a and the wiring 23 is not covered with the solder resist 30. In these respects, the configuration of the substrate 100A is different from the configuration of the substrate 100.

[0043] When the semiconductor package 300 is mounted on the substrate 100A, the cream solder applied on the central pad 21 is spread, and spreads onto the connection portion between the outer peripheral edge 21a and the wiring 23. In the substrate 100A, the heat of the solder alloy 210 melted on the connection portion between the outer peripheral edge 21a and the wiring 23 is also dissipated from the peripheral pad 22 through the wiring 23. Therefore, the solder alloy 210 melted on the connection portion between the outer peripheral edge 21a and the wiring 23 is more likely to solidify than the solder alloy 210 melted on the central pad 21. As a result, the solder alloy 210 solidified on the connection portion between the outer peripheral edge 21a and the wiring 23 is separated from the unsolidified solder alloy 210 on the central pad 21 and becomes solder balls.

[0044] On the other hand, in the substrate 100, since the connection portion between the outer peripheral edge 21a and the wiring 23 is covered with the solder resist 30, unlike the substrate 100A, solder balls are less likely to be generated.

[0045] Also, in the substrate 100A, due to the mounting of the semiconductor package 300, the cream solder applied on the central pad 21 also spreads onto the solder resist 30 around the first opening 31. The solder alloy 210 melted on the solder resist 30 tends to flow toward the central pad 21 because the interfacial energy at the interface with the solder resist 30 is greater than the interfacial energy at the interface with the central pad 21.

[0046] However, when the thickness T1 is greater than the thickness T2, there is a step where the side of the solder resist 30 is lower between the solder resist 30 around the first opening 31 and the central pad 21. Therefore, the solder alloy 210 melted on the solder resist 30 around the first opening 31 may not be able to overcome the step and become solder balls.

[0047] On the other hand, in the substrate 100, the solder resist 30 and the central pad 21 overlap around the first opening 31. As a result, there is a step where the solder resist 30 side is higher between the solder resist 30 around the first opening 31 and the central pad 21 exposed from the first opening 31. Therefore, on the solder resist 30 around the first opening 31 of the substrate 100, the molten solder alloy 210 can easily flow toward the central pad 21 exposed from the first opening 31, and solder balls are less likely to be generated.

[0048] (Second Embodiment) The substrate according to the second embodiment will be described. Hereinafter, the substrate according to the second embodiment will be referred to as substrate 100B. Here, the points different from the substrate 100 will be mainly described, and repeated descriptions will not be repeated.

[0049] <Configuration of Substrate 100B> The configuration of the substrate 100B will be described below.

[0050] FIG. 6 is a plan view of the substrate 100B. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6. As shown in FIGS. 6 and 7, the substrate 100B has a base material 10, a conductor pattern 20, and a solder resist 30. In this regard, the configuration of the substrate 100B is common to the configuration of the substrate 100. The substrate 100B further has an annular wall 40. In this regard, the configuration of the substrate 100B is different from the configuration of the substrate 100.

[0051] The annular wall 40 is annular in plan view. More specifically, the annular wall 40 is rectangular annular in plan view. The annular wall 40 is disposed outside the first opening 31 and inside the peripheral pad 22 in plan view. The annular wall 40 is disposed on the solder resist 30.

[0052] The annular wall 40 is formed of a resin material different from the solder resist 30. The annular wall 40 is formed of, for example, resin ink. The resin ink is, for example, silk ink. This resin ink is preferably colored in a color different from that of the solder resist 30. For example, when the solder resist 30 is colored green, the annular wall 40 is formed of resin ink colored white.

[0053] Although not shown, characters are drawn on the solder resist 30 with the same resin ink as that used for the annular wall 40. This character shows, for example, information necessary when mounting components on the substrate 100B and information regarding the handling of the substrate 100B.

[0054] <Effect of the substrate 100B> The effect of the substrate 100B will be described below.

[0055] In the substrate 100B, the annular wall 40 is disposed outside the first opening 31 and inside the peripheral pad 22. Therefore, even if solder balls are generated, it is possible to suppress the solder balls from moving between two adjacent peripheral pads 22 and causing a short circuit between these two peripheral pads 22.

[0056] Also, in the manufacturing process of the substrate 100B, characters for displaying various information on the solder resist 30 are drawn using resin ink colored in a color different from that of the solder resist 30. In the substrate 100B, since the annular wall 40 is formed using the same ink as that used for drawing the above characters, the annular wall 40 can be formed within this process, and there is no need to add a new process for forming the annular wall 40.

[0057] (Third Embodiment) The substrate according to the third embodiment will be described. In the following, the substrate according to the third embodiment is referred to as the substrate 100C. Here, the differences from the substrate 100B will be mainly described, and repeated descriptions will not be repeated.

[0058] <Configuration of Substrate 100C> The configuration of substrate 100C will be described below.

[0059] FIG. 8 is a plan view of substrate 100C. As shown in FIG. 8, substrate 100C has a base material 10 (not shown in FIG. 8), a conductor pattern 20, a solder resist 30, and an annular wall 40. In this regard, the configuration of substrate 100C is common to the configuration of substrate 100B. In substrate 100C, the first opening 31 is outside the outer peripheral edge 21a in a plan view. That is, in substrate 100C, the connection portion between the outer peripheral edge 21a and the wiring 23 is not covered by the solder resist 30. In this regard, the configuration of substrate 100C is different from the configuration of substrate 100B.

[0060] <Effect of Substrate 100C> In substrate 100C, since the connection portion between the outer peripheral edge 21a and the wiring 23 is not covered by the solder resist 30, solder balls may be generated on the connection portion between the outer peripheral edge 21a and the wiring 23. However, in substrate 100C, since the annular wall 40 is disposed outside the first opening 31 and inside the peripheral pad 22, the generated solder balls are moved between two adjacent peripheral pads 22, and it is suppressed that a short circuit occurs between these two peripheral pads 22.

[0061] Although the embodiments of the present invention have been described as above, it is also possible to variously modify the above-described embodiments. Further, the scope of the present invention is not limited to the above-described embodiments. The scope of the present invention is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Description of Reference Numerals

[0062] 10 Substrate, 10a First main surface, 10b Second main surface, 10c Through-hole, 20 Conductor pattern, 21 Central pad, 21a Outer peripheral edge, 22, 22a Peripheral pads, 23 Wiring, 24 Conductor layer, 30 Solder resist, 31 First opening, 32 Second opening, 40 Annular wall, 100, 100A, 100B, 100C Substrate, 200 Mounting substrate, 210 Solder alloy, 300 Semiconductor package, 300a Surface, 300b Back surface, 300c Central electrode, 300d Peripheral electrode, 310 Lead frame, 311 Die pad portion, 312 Lead portion, 320 Semiconductor chip, 320a Surface, 320b Back surface, 330 Bonding wire, 340 Encapsulating resin, T1, T2 Thickness.

Claims

1. A substrate having a main surface, A conductor pattern disposed on the main surface and having a central pad portion, a peripheral pad portion around the central pad portion, and a wiring connecting the outer peripheral edge of the central pad portion and the peripheral pad portion, A solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening exposing the central pad portion and a second opening exposing the peripheral pad portion, The solder resist covers a connection portion of the wiring with the central pad portion. A substrate.

2. The first opening is inside the outer peripheral edge of the central pad portion in a plan view. The substrate according to claim 1.

3. Further comprising an annular wall disposed on the solder resist, The annular wall is disposed outside the first opening and inside the peripheral pad portion in a plan view, The annular wall is formed of a resin material different from the solder resist. The substrate according to claim 1 or claim 2.

4. The annular wall is formed of a resin ink colored in a color different from the solder resist. The substrate according to claim 3.

5. The thickness of the conductor pattern is greater than the thickness of the solder resist. The substrate according to any one of claims 1 to 4.

6. The substrate according to any one of claims 1 to 5, A semiconductor package having a back surface, And a solder alloy, The semiconductor package has a central electrode facing the central pad portion and a peripheral electrode around the central electrode and facing the peripheral pad portion on the back surface, The solder alloy is a mounting substrate that joins the central electrode and the central pad portion, and also joins the peripheral electrode and the peripheral pad portion.

7. The semiconductor package is a QFN package, and the mounting substrate according to claim 6.

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