Semiconductor integrated circuit

Abstract

To provide a semiconductor integrated circuit capable of detecting occurrence of an open state or a short state in any of a plurality of output terminals.SOLUTION: A semiconductor integrated circuit comprises a plurality of first current control elements respectively connected between an input terminal and a plurality of output terminals, a control circuit controlling the first current control elements, an abnormality detection circuit including a plurality of voltage comparison circuits and detecting an open or short state of each of the plurality of output terminals, and a voltage conversion circuit generating a threshold value voltage according to a voltage generated by applying a current to an external resistor. The abnormality detection circuit comprises a plurality of second current control elements applying a proportionally reduced current to a current flowing to each of a plurality of first current control elements, and a plurality of current-voltage conversion elements converting a current flowing to the second current control elements to a voltage. The plurality of voltage comparison circuits compare the voltages converted by the plurality of current-voltage conversion elements and a common threshold value voltage, and output the comparison results.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit having a current control element connected between an input terminal and an output terminal, and more particularly to a semiconductor integrated circuit for power supply (power supply IC) that constitutes a voltage regulator or a DC-DC converter for converting a DC voltage, which is used to detect an open abnormality or a short abnormality of a plurality of output terminals to which a load is connected or the load. The present invention relates to an effective technique.

Background Art

[0002] There is a series regulator (hereinafter abbreviated as a regulator) as a power supply device that controls a transistor provided between a DC voltage input terminal and an output terminal to output a DC voltage of a desired potential. In an automobile equipped with a terrestrial digital (terrestrial digital television broadcast) tuner, power is supplied to in-vehicle electronic devices such as a terrestrial digital antenna by an in-vehicle regulator. Further, in a full-segment compatible in-vehicle terrestrial digital tuner, reception sensitivity adjustment and full-segment / one-segment switching are performed by the tuner, and in order to optimize the reception status, a diversity antenna, which is a 4-channel equivalent antenna, is generally used as the terrestrial digital antenna.

[0003] On the other hand, in-vehicle tuners and antennas are connected to an in-vehicle regulator via a connector, so the connector may become disconnected due to vehicle body vibration, causing the output terminal of the power supply to become open, or a disconnection or short circuit may occur inside the load. Therefore, some in-vehicle regulators are equipped with a function to detect such abnormal states. Note that there are inventions described in Patent Documents 1 and 2 regarding a semiconductor integrated circuit for a regulator (regulator IC) configured to provide an open abnormality detection comparator for detecting an open state of an output terminal and a short abnormality detection comparator for detecting a short state, generate an abnormality detection signal, and output it from the output terminal.

Prior Art Documents

Patent Document

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] Conventionally, in an in-vehicle digital system equipped with a plurality of antennas, it has been common to supply power from a common regulator to the plurality of antennas. In this case, even if one channel antenna becomes open, since reception is performed on other channels, it operates without detecting an abnormality. On the other hand, in order to be able to detect that one channel antenna has become open, it is also conceivable to provide a regulator having an open abnormality detection function for each antenna as a load. However, if done in this way, since a plurality of regulators are required, there is a problem of a significant cost increase and an increase in the mounting area.

[0006] Therefore, as shown in FIG. 4, it is conceivable to provide two series regulators (LDOs) and two output terminals in one IC chip to enable power supply to two loads, and to be configured to be able to detect an open abnormality or a short abnormality at the output terminal of each regulator. The power supply IC shown in FIG. 4 is considered by the inventor by applying the open abnormality and short abnormality detection circuits in the power supply IC described in Patent Document 2 and is not a known one. Also, the regulator ICs and semiconductor devices described in Patent Document 1 and 2 are assumed to have one load connected.

[0007] The power supply IC shown in FIG. 4 has the advantage that it can detect either an open abnormality or a short abnormality with different thresholds for each of the two output terminals. However, when used in a regulator that supplies power to two antennas in an in-vehicle digital system, if two loads with the same characteristics, such as diversity antennas, are connected to the two output terminals, there is no need to individually set different thresholds for each output terminal. Therefore, there is waste in the number of terminals and external resistors, which poses a problem of being a disadvantage for miniaturization and cost reduction of the IC.

[0008] The present invention has been made paying attention to the above problems, and an object thereof is to be able to output a signal that detects an open state or a short state in any of a plurality of loads and notifies an abnormality in a semiconductor integrated circuit having a plurality of output terminals to which the plurality of loads are connected.

Means for Solving the Problems

[0009] To achieve the above object, the present invention In a semiconductor integrated circuit including one input terminal, a plurality of output terminals, a plurality of first current control elements respectively connected between the input terminal and the plurality of output terminals, and a control circuit for controlling the plurality of first current control elements, It has a plurality of voltage comparison circuits that compare a voltage proportional to the voltage of the plurality of output terminals with a predetermined threshold voltage, and an abnormality detection circuit that detects an open state or a short state of each of the plurality of output terminals, An external terminal for connecting an external resistor, A voltage conversion circuit that generates the predetermined threshold voltage that is commonly applied to one input terminal of the plurality of voltage comparison circuits in response to the voltage of the external terminal generated by flowing a current through the external resistor, A detection result output terminal for outputting the detection result by the abnormality detection circuit to the outside, It is configured to include.

[0010] According to the semiconductor integrated circuit having the above-described configuration, it is possible to supply current to loads connected to each of a plurality of voltage output terminals. If the plurality of loads connected to the plurality of voltage output terminals have the same characteristics, only one external terminal for connecting an external resistor is provided, and when an open state or a short state occurs in any of the output terminals or loads, it can detect this and output a signal notifying an abnormality. Further, by appropriately selecting the resistance value of the external resistor connected to the external terminal, it is possible to easily change the threshold for discriminating between the open state and the short state.

Effects of the Invention

[0011] According to the present invention, in a semiconductor integrated circuit including a plurality of output terminals to which a plurality of loads are connected, when an open state or a short state occurs in any of the plurality of loads, there is an effect that it can detect this and output a signal notifying an abnormality.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Modes for Carrying Out the Invention

[0013] Hereinafter, preferred embodiments of the present invention will be described based on the drawings. FIG. 1 shows an embodiment when the present invention is applied to a series regulator as a DC power supply device as an example. In FIG. 1, the portion surrounded by the dashed-dotted line is formed as a semiconductor integrated circuit (hereinafter referred to as a regulator IC) 10 on a semiconductor chip such as a single crystal silicon.

[0014] In the regulator IC 10 of the present embodiment, as shown in FIG. 1, one voltage input terminal IN to which a DC voltage VDD is applied and two output terminals OUT1 and OUT2 are provided as external terminals, and P-channel MOS transistors Q11 and Q21 are respectively connected between the voltage input terminal IN and each of the output terminals OUT1 and OUT2. Capacitors Co1 and Co2 are connected to the output terminals OUT1 and OUT2, and it functions as a DC power supply device that supplies two stable DC output voltages Vout1 and Vout2 to the outside. LD1 and LD2 represent load devices such as antennas connected to the output terminals OUT1 and OUT2.

[0015] Also, between the output terminals OUT1 and OUT2 and the ground line to which the ground potential GND is applied, bleeder resistors R11 and R12 and resistors R21 and R22 that divide the output voltages Vout1 and Vout2 respectively are connected in series. When an external terminal connected to the midpoint between R11 and R12 or the midpoint between R21 and R22 is provided separately, R11, R12, R21, and R22 can be provided outside the regulator IC 10. The voltage VFB1 divided by the resistors R11 and R12 for output voltage division is fed back to the non-inverting input terminal of an error amplifier 11A as an error amplification circuit that controls the gate terminal of the transistor Q11, and the voltage VFB2 divided by the resistors R21 and R22 is fed back to the non-inverting input terminal of an error amplifier 11B that controls the gate terminal of the transistor Q21. Then, the error amplifiers 11A and 11B control the transistors Q11 and Q21 according to the potential difference between the feedback voltages VFB1 and VFB2 of the output and a predetermined reference voltage Vref, and control the current flowing according to the load so that the output voltages Vout1 and Vout2 become desired potentials. Thereby, the transistors Q11 and Q21 function as current control elements and voltage control elements.

[0016] Furthermore, the regulator IC10 of the present embodiment is provided with a reference voltage circuit 12 for generating the reference voltage Vref applied to the inverting input terminals of the error amplifiers 11A and 11B, and a bias circuit 13 for flowing an operating current to the error amplifiers 11A and 11B and the reference voltage circuit 12. The reference voltage circuit 12 can be composed of a bandgap reference circuit, a series resistor, a Zener diode, and the like.

[0017] Furthermore, in the regulator IC10 of the present embodiment, transistors Q12 and Q22 that form current mirror circuits with Q11 and Q21 respectively are provided in parallel with the transistors Q11 and Q21 for current control, and the same voltage as the voltage applied to the gate terminals of the transistors Q11 and Q21, that is, the output voltages of the error amplifiers 11A and 11B, is applied to the gate terminals as the control terminals of these transistors Q12 and Q22. Thereby, a current (1 / N of the current) proportional to the drain current of Q11 and Q21 flows through Q12 and Q22 according to the element size ratio N. When the transistors Q11 and Q21 are configured by connecting N transistors of the same size in parallel, and Q12 and Q22 are each configured by one transistor, it is set so that a current proportional to the number of elements flows.

[0018] Furthermore, in the regulator IC 10 of the present embodiment, resistors R13 and R23, which are current-voltage conversion elements connected in series with the current mirror transistors Q12 and Q22 respectively, are provided to convert the current flowing through Q12 and Q22 into a voltage. Also, an external terminal P1 for connecting a resistor Rdet for voltage-current conversion outside the chip, a voltage converter 14 for generating a voltage Vth corresponding to the voltage Vdet generated at the external terminal P1, and a comparator CMP1 and a comparator CMP2 for comparing the voltage Vth generated by the voltage converter 14 with the voltages converted by the resistors R13 and R23 to detect any abnormality such as an open abnormality or a short abnormality of the output terminals OUT1 and OUT2 are provided. Therefore, the voltage Vth serves as a threshold for determining an open abnormality or a short abnormality.

[0019] When the output terminal OUT1 or OUT2 is open, almost no current flows through the transistors Q11 or Q21 and Q12 or Q22, so the voltage across the resistor R13 or R23 also becomes low. Therefore, when the comparators CMP1 and CMP2 are to function as open abnormality detection means, a resistor Rdet with a large resistance value is connected to the external terminal P1 to generate a relatively low voltage Vtho for detecting an open abnormality by the voltage converter 14. On the other hand, when the output terminal OUT1 or OUT2 is shorted, a current larger than the load current flows through the transistors Q11 or Q21 and Q12 or Q22, so the voltage across the resistor R13 or R23 becomes high. Therefore, when the comparators CMP1 and CMP2 are to function as short abnormality detection means, a resistor Rdet with a small resistance value is connected to the external terminal P1 to generate a relatively high voltage Vths (>Vtho) for detecting a short abnormality by the voltage converter 14.

[0020] Also, when the comparators CMP1 and CMP2 function as open-circuit detection means, a voltage is generated by flowing the currents Iout1’ and Iout2’ of Q12 and Q22 through the resistors R13 and R23 to one input terminal (+ or -) of the comparators CMP1 and CMP2, and a threshold voltage Vtho is generated at the other input terminal (- or +). On the other hand, when the comparators CMP1 and CMP2 function as short-circuit detection means, a voltage is generated by flowing the currents Iout1’ and Iout2’ of Q12 and Q22 through the resistors R13 and R23 to one input terminal (- or +) of the comparators CMP1 and CMP2, and a threshold voltage Vths is generated at the other input terminal (+ or -). Note that the inverting / non-inverting input terminals (- or +) of the comparators CMP1 and CMP2 for generating Vtho or Vths can be either according to the logic of the subsequent logic circuit. And the above input switching can be realized, for example, by configuring the input signal wiring or the logic circuit to be switchable with a mask option. Also, it is preferable to use comparators CMP1 and CMP2 having a hysteresis characteristic.

[0021] Furthermore, the regulator IC10 of the present embodiment is provided with a logic circuit 15 that takes the outputs of the above abnormal detection comparators CMP1 and CMP2 as inputs. Also, an N-channel MOS transistor Q5 whose output of the logic circuit 15 is input to the gate terminal is provided, and an external terminal P3 for outputting an abnormal detection signal Err to an external CPU or the like in an open-drain format is provided, and the drain terminal of the transistor Q5 is connected to the external terminal P3. Instead of the open-drain type transistor Q5, an output circuit composed of a CMOS inverter may be provided.

[0022] When the outputs of the abnormality detection comparators CMP1 and CMP2 are at the high level, the logic circuit 15 is configured as a circuit having an OR logic function, indicating an abnormal state respectively and outputting it as a low-level abnormality detection signal ERR. When the outputs of the abnormality detection comparators CMP1 and CMP2 are at the low level, indicating an abnormal state and outputting it as a low-level abnormality detection signal ERR, it is configured as a circuit having a NAND logic function. Also, when the outputs of CMP1 and CMP2 are at the low level, indicating an abnormal state and outputting it as a high-level abnormality detection signal ERR, it is configured as a circuit having a NOR logic function.

[0023] Furthermore, two external terminals for outputting an abnormality detection signal may be provided to output 2-bit abnormality detection signals corresponding to the outputs of the comparators CMP1 and CMP2 to the outside respectively. In that case, the logic circuit 15 can be configured as a delay circuit, for example. Also, in the above description, according to whether detecting an open abnormality or a short abnormality of the output terminals OUT1 and OUT2, the input signal wiring of the comparators CMP1 and CMP2 is configured to be switchable with a mask option. However, instead of switching the input signal wiring of the comparators CMP1 and CMP2, the logic configuration of the logic circuit 15 may be configured to be switchable with a mask option.

[0024] As shown in FIG. 1, the voltage converter 14 includes a current buffer 14a composed of an amplifier AMP with an inverting input terminal connected to the external terminal P1 to which the resistor Rdet is connected, a reference voltage Vdet_in applied to the non-inverting input terminal, and an N-channel MOS transistor Qa with a source terminal connected to the external terminal P1 and a gate terminal to which the output voltage of the amplifier AMP is applied; a current mirror circuit 14b that folds back the current Idet flowing through the resistor Rdet generated by the current buffer 14a; and a resistor Rth that converts the current (transfer current) Idet' on the secondary side of the current mirror circuit 14b into a voltage. The voltage converted by the resistor Rth is supplied to the comparators CMP1 and CMP2 as a comparison reference voltage Vth.

[0025] The current buffer 14a of the voltage converter 14 is connected such that the output terminal of the amplifier AMP is connected to the gate terminal of the transistor Qa, and the source terminal of the transistor Qa is connected to the inverting input terminal of the amplifier AMP. As a result, the amplifier AMP functions as a voltage follower and operates the transistor Qa so that the source voltage of the transistor Qa (the potential of the external terminal P1) becomes equal to the input voltage (reference voltage Vdet_in) of the non-inverting input terminal.

[0026] As the amplifier AMP, for example, as shown in FIG. 2, it is composed of a differential amplifier circuit including differential input transistors Q31 and Q32, active load transistors Q33 and Q34, and a constant current source CC1 to which the reference voltage Vdet_in and the voltage Vdet of the external terminal P1 are input to the gate terminals. The gate terminal of the transistor Qa is connected to the connection node N1 between the transistors Q32 and Q34, thereby operating as a current buffer that passes a predetermined drain current through the transistor Qa. Note that the circuit shown in FIG. 2 is an example and is not limited to a circuit having such a configuration.

[0027] Here, the characteristics of the voltage converter 14 will be described. In the voltage converter 14 of the present embodiment, due to the function of the current buffer 14a, the voltage Vdet of the external terminal P1 is equal to the reference voltage Vdet_in, that is, Vdet = Vdet_in. Therefore, the current Idet flowing through the external resistor Rdet by the current buffer 14a is Idet = Vdet / Rdet = Vdet_in / Rdet Thus, the comparison reference voltage Vth generated by being converted by the resistor Rth through which the current Idet' folded back by the current mirror circuit 14b flows is, assuming the current mirror ratio is m, the following equation (1) Vth = Rth*Idet' = Rth*Idet / m ……(1) is represented by.

[0028] On the one hand, the output current Iout1 of the output terminal OUT1 is converted into a voltage Vout1' by flowing the current Iout1' generated by the current mirror (n) of the transistors Q11 and Q12 through the resistor R13. Therefore, if the ratio of Q11 and Q12 is n, the following equation (2) Vout1' = R13 * Iout1' = R13 * Iout1 / n ……(2) will be represented by it. The comparator CMP1 compares the voltage given by the above equation (1) with the voltage given by equation (2), and determines that it is open when Vout1' ≤ Vtho, and determines that it is short when Vout1' ≥ Vths. Therefore, by connecting an external resistor Rdet having a resistance value such that Vth = Vtho to the external terminal P1, the comparator CMP1 can function as an open abnormality detection means, and by connecting an external resistor Rdet having a resistance value such that Vth = Vths to the external terminal P1, the comparator CMP1 can function as a short abnormality detection means.

[0029] Here, since both the internal resistors R13 and Rth of the IC are on-chip elements, the relative ratio is good (about ±0.5%), and the variation in temperature characteristics due to manufacturing variations is canceled. On the other hand, the reference voltage Vdet_in of the voltage converter 14 can generate a high-precision reference voltage by means of a bandgap or the like, and the external resistor Rdet that generates Idet is a discrete component with good accuracy and temperature characteristics and can be manufactured or obtained with high precision (resistance accuracy is about ±1%, temperature characteristics are about ±100 ppm / °C). Therefore, a high-precision comparison reference voltage Vth can be set, and the accuracy of open abnormality detection or short abnormality detection can be improved.

[0030] The output current Iout2 of the output terminal OUT2 is the same as above. With the voltage converter 14 and the comparator CMP2, high-precision open-fault detection or short-circuit fault detection can be performed. Also, if the loads connected to the output terminals OUT1 and OUT2 have the same characteristics and conduct the same current, the same comparison reference voltage Vth can be used by the comparators CMP1 and CMP2. Therefore, the voltage converter 14 can be shared as in the regulator IC10 of this embodiment, and the comparison reference voltage Vth can be set by providing one external terminal P1 and one external resistor Rdet.

[0031] As described above, in the regulator IC10 of this embodiment, when loads equivalent to the output terminals OUT1 and OUT2 are connected, an open fault or a short-circuit fault can be detected by simply providing one external terminal for connecting the external resistor Rdet. Therefore, the chip size can be reduced. Also, due to the reduction of terminals and components, a small and inexpensive package can be used, achieving space saving and cost reduction of the power supply device. Also, by changing the resistance value of the external resistor Rdet, the threshold for easily detecting an open fault or a short-circuit fault can be changed, so the applications of the IC can be expanded.

[0032] Although not shown in FIG. 1, a current limit circuit connected to the gate terminals of the transistors Q11 and Q21 to limit the output current, and a thermal shutdown circuit that stops the operation of the error amplifiers 11A and 11B and turns off the transistors Q11 and Q21 when the temperature of the chip rises above a predetermined temperature may be provided. The operation signals of the current limit circuit and the thermal shutdown circuit are also supplied to the logic circuit 15, and the logic with the output signals of the comparators CMP1 and CMP2 is taken to generate, for example, a 2-bit or 3-bit fault detection signal Err and output it to the outside of the chip. In addition, the regulator IC10 may be provided with an external terminal CE to which a signal for turning on / off the operation of the IC is input, and the bias circuit 13 may be provided with a function of supplying or cutting off the bias current to the error amplifiers 11A and 11B according to a control signal input to the external terminal CE from an external microcomputer (CPU) or the like.

[0033] (Modification example) Next, a modification example of the regulator IC of the above embodiment will be described with reference to FIG. 3. In the regulator IC (FIG. 1) of the above embodiment, one external terminal P1 for connecting the external resistor Rdet and one voltage converter 14 are provided, and the two comparators CMP1 and CMP2 are configured to detect either an open or a short of the two output terminals OUT1 and OUT2. On the other hand, in the regulator IC (FIG. 3) of this modification example, two external terminals for connecting the external resistor Rdet and two voltage converters 14 are provided, and the four comparators CMP1 to CMP4 are configured to detect both an open and a short of the two output terminals OUT1 and OUT2, and output a 2-bit abnormality detection signal Err from the logic circuit 15.

[0034] Specifically, two output current detection transistors Q12 and Q13 connected in a current mirror with the output current control transistor Q11 connected to the output terminal OUT1, and two output current detection transistors Q22 and Q23 connected in a current mirror with the output current control transistor Q21 connected to the output terminal OUT2 are provided, and on-chip resistors R13, R14, R23, and R24 for current-voltage conversion are connected in series with the transistors Q12, Q13 and the transistors Q22, Q23.

[0035] In addition, external terminals P1 and P2 to which resistors Rdet1 and Rdet2 are connected, and voltage converters 14A and 14B are provided. Four comparators CMP1 to CMP4 are provided. In comparators CMP1 and CMP3, a short detection reference voltage Vths generated by voltage converter 14A is compared with the voltages converted by resistors R13 and R23. In comparators CMP2 and CMP4, an open detection reference voltage Vtho generated by voltage converter 14B is compared with the voltages converted by resistors R14 and R24.

[0036] Furthermore, two open-drain output transistors Q5 and Q6 for outputting an abnormality detection signal and external terminals P3 and P4 are provided. Logic circuit 15 receives the output signals of comparators CMP1 to CMP4, detects a one-channel open state, a two-channel open state, a one-channel short state, and a two-channel short state, and is configured to distinguish and output them by two-bit abnormality detection signals Err_1 and Err_2. In this modification example as well, a current limit circuit for connecting to the gate terminals of transistors Q11 and Q21 to limit the output current and a thermal shutdown circuit may be provided. The operation signals of the current limit circuit and the thermal shutdown circuit are also supplied to logic circuit 15, and the logic with the output signals of comparators CMP1 to CMP4 may be taken to generate a three-bit abnormality detection signal and output it to the outside of the chip.

[0037] The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments. For example, in the above embodiments, MOS transistors are used as the transistors constituting the internal circuit of regulator IC10, but bipolar transistors may be used instead of MOS transistors.

[0038] Furthermore, in the regulator IC of the above embodiment, although the case where it is configured as an in-vehicle terrestrial digital power supply device with an antenna connected to the output terminal OUT as a load has been described, the load is not limited to the antenna, and it can also be applied to a power supply device to which two or more loads with the same current consumption are connected. Also, in the above embodiment, the case where the present invention is applied to a regulator IC has been described. However, the present invention is not limited to a regulator IC, and it can also be applied to an IC constituting a switching regulator type DC-DC converter or a high-side switch IC.

Explanation of Reference Numerals

[0039] 10... Regulator IC, 11... Error amplifier, 12... Reference voltage circuit, 13... Bias circuit, 14, 14A, 14B... Voltage converter, 14a... Current buffer (voltage-current conversion circuit), 14b... Current mirror circuit, 15...... Logic circuit, CMP1, CMP2... Comparators for open / short abnormality detection, Q11, Q21... Current control transistors, Q12, Q13, Q22, Q23... Current mirror transistors, Q5, Q6... Transistors for outputting abnormality detection signals, P1, P2... External terminals (resistance connection terminals), P3, P4... External terminals (detection result output terminals)

Claims

1. A semiconductor integrated circuit comprising one input terminal, a plurality of output terminals, a plurality of first current control elements respectively connected between the input terminal and the plurality of output terminals, and a control circuit for controlling the plurality of first current control elements, having a plurality of voltage comparison circuits for comparing a voltage proportional to the voltage of the plurality of output terminals with a predetermined threshold voltage, and an abnormality detection circuit for detecting an open state or a short state of each of the plurality of output terminals, an external terminal for connecting an external resistor, a voltage conversion circuit for generating the predetermined threshold voltage commonly applied to one input terminal of the plurality of voltage comparison circuits in response to the voltage of the external terminal generated by flowing a current through the external resistor, a detection result output terminal for externally outputting a detection result by the abnormality detection circuit, and characterized by comprising the above.

2. The abnormality detection circuit has a plurality of second current control elements that flow currents proportional to and reduced from the currents flowing through the plurality of first current control elements, and a plurality of current-voltage conversion elements that convert the currents flowing through the second current control elements into voltages. The plurality of voltage comparison circuits compare the voltages converted by the plurality of current-voltage conversion elements with the predetermined threshold voltage and output a magnitude result. The semiconductor integrated circuit according to claim 1, characterized in that.

3. The voltage conversion circuit includes a voltage-current conversion circuit that generates a current corresponding to the voltage of the external terminal or an external resistor connected to the external terminal, a current mirror circuit that transfers the current generated by the voltage-current conversion circuit, and a current-voltage conversion element that converts the output current of the current mirror circuit into a voltage. The semiconductor integrated circuit according to claim 1, characterized in that.

4. The voltage-current conversion circuit is, a differential amplifier circuit in which the voltage of the external terminal is applied to the inverting input terminal and a predetermined constant voltage is applied to the non-inverting input terminal, A transistor in which a drain terminal is connected to the external terminal, an output voltage of the differential amplifier circuit is applied to a gate terminal, and the current mirror circuit is connected to the drain terminal; The semiconductor integrated circuit according to claim 3, characterized by comprising .

5. Comprising two of the external terminals and two of the voltage conversion circuits respectively; One of the voltage conversion circuits generates the threshold voltage for detecting an open state of the plurality of output terminals; The semiconductor integrated circuit according to any one of claims 1 to 4, characterized in that the other voltage conversion circuit generates the threshold voltage for detecting a short state of the plurality of output terminals.

6. Comprising a plurality of detection result output terminals, and receiving output signals of the plurality of voltage comparison circuits, The semiconductor integrated circuit according to any one of claims 1 to 5, characterized by comprising a logic circuit that generates a multi-bit output signal for distinguishing an open state or a short state of each of the plurality of output terminals and outputting the signal to the outside from the plurality of detection result output terminals.

7. The control circuit comprises a plurality of error amplifiers that respectively generate output voltages for controlling the plurality of first current control elements according to a feedback voltage of an output; The semiconductor integrated circuit is a semiconductor integrated circuit for power supply that constitutes a DC power supply device; The semiconductor integrated circuit according to any one of claims 1 to 6, characterized in that a load connected to the plurality of output terminals is an antenna connected to a television broadcast tuner mounted on a vehicle.

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