Method for Removal of Elements Using Grooves

Abstract

To provide a method for removing bars of devices from a substrate using a trench, and devices fabricated by the method.SOLUTION: In an opto-electronic device 114, an epitaxial lateral overgrowth (ELO) layer 105 is grown on an opening area of a substrate 101, where the ELO layer is higher than a surface of a trench 109 in the substrate. The trench is apt to form a symmetric shape of the ELO layer, which renders it suitable for flip-chip bonding. The shape of the ELO layer has a depressed surface region 107 at a back side of a bar formed by the ELO layer. A cleaving point 112 is located higher than the bottom of the ELO layer so that a force can be efficiently applied to the cleaving point for removing the bar of the device 114.SELECTED DRAWING: Figure 1a

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit under 35 U.S.C. Section 119(e) (Title 35, United States Code, Section 119(e)) of the following co - pending application that has been assigned to the assignee of the present invention. U.S. Provisional Application No. 62 / 793,253, filed on January 16, 2019, Attorney Docket No. G&C 30794.0713USP1(UC 2019 - 398 - 1), entitled "METHOD FOR REMOVAL OF DEVICES USING A TRENCH" by Takeshi Kamikawa, Srinivas Gandrothula, and Masahiro Araki. That application is incorporated herein by reference.

[0002] This application is related to the following co - pending application that has been assigned to the assignee of the present invention. The application entitled "METHOD OF REMOVING A SUBSTRATE" by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen, filed on May 5, 2017, U.S. Provisional Patent Application No. 62 / 502,205, Attorney Docket No. 30794.0653USP1(UC 2017 - 621 - 1), which claims the benefit under 35 U.S.C. Section 119(e) (Title 35, United States Code, Section 119(e)) of the present invention; and the PCT International Patent Application No. PCT / US18 / 31393, filed on May 7, 2018, Attorney Docket No. 30794.0653WOU1(UC 2017 - 621 - 2), entitled "METHOD OF REMOVING A SUBSTRATE" by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li, and Daniel A. Cohen. This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Patent Application No. 62 / 559,378, filed on September 15, 2017, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE", naming Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li as inventors, and assigned to the assignee of the present invention (Attorney Docket No. 30794.0659USP1(UC 2018-086-1)), and PCT International Patent Application No. PCT / US18 / 51375, filed on September 17, 2018, entitled "METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE", naming Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li as inventors, and assigned to the assignee of the present invention (Attorney Docket No. 30794.0659WOU1(UC 2018-086-2)). This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Patent Application No. 62 / 650,487, filed Mar. 30, 2018, entitled "METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES BY USING LATERAL OVERGROWTH," naming Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li as inventors, and assigned to the assignee of the present invention (Attorney Docket No. G&C 30794.0680USP1(UC 2018-427-1)), and PCT International Patent Application No. PCT / US19 / 25187, filed Apr. 1, 2019, entitled "METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH," naming Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li as inventors, and assigned to the assignee of the present invention (Attorney Docket No. 30794.0680WOU1(UC 2018-427-2)). This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Application No. 62 / 672,913, filed May 17, 2018, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES," naming Takeshi Kamikawa and Srinivas Gandrothula as inventors, and assigned to the assignee of the present invention (Attorney Docket No. G&C 30794.0682USP1(UC 2018-605-1)), and PCT International Patent Application No. PCT / US19 / 32936, filed May 17, 2019, entitled "METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES," naming Takeshi Kamikawa and Srinivas Gandrothula as inventors, and assigned to the assignee of the present invention (Attorney Docket No. 30794.0681WOU1(UC 2018-605-2)). This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Application No. 62 / 677,833, filed May 30, 2018, entitled "METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE," attorney docket number G&C 30794.0682USP1(UC 2018-614-1), which is co-pending and assigned to the assignee of the present invention, and PCT International Patent Application No. PCT / US19 / 34686, filed May 30, 2019, entitled "METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE," attorney docket number 30794.0682WOU1(UC 2018-614-2). This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Application No. 62 / 753,225, filed October 31, 2018, entitled "METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH," attorney docket number G&C 30794.0693USP1(UC 2019-166-1), which is co-pending and assigned to the assignee of the present invention, and PCT International Patent Application No. PCT / US19 / 59086, filed October 31, 2019, entitled "METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH," attorney docket number 30794.0693WOU1(UC 2019-166-2). All of that application is incorporated herein by reference.

[0003] 1. Field of the Invention The present invention relates to a method for removing elements using grooves. BACKGROUND OF THE INVENTION

[0004] 2. Description of the Related Art Many device manufacturers use self-supporting bulk gallium nitride (GaN) substrates to produce laser diodes (LDs) and light emitting diodes (LEDs) for lighting, optical memory, and other purposes. GaN substrates are attractive in that it is easy to obtain high-quality group III nitride semiconductor layers with a low defect density by homoepitaxial growth on GaN substrates.

[0005] However, typically, GaN substrates, which are produced using hydride vapor phase epitaxy (HVPE), are very expensive. Also, nonpolar and semipolar GaN substrates are more expensive than polar (c-plane) GaN substrates. As a result, researchers have investigated removing group III nitride semiconductor layers from GaN substrates after the devices are fabricated. Such techniques would result in reusable GaN substrates, which would provide very inexpensive and high-quality GaN substrates and group III nitride devices to customers.

[0006] As a result, there is a need for techniques to easily remove group III nitride semiconductor layers from group III nitride substrates or layers and hetero-substrates with group III nitride layers.

[0007] In one previous technique, the GaN layer is spalled by a metal stressor layer under tensile strain. See, for example, Applied Physics Express 6 (2013) 112301 and U.S. Patent No. 8,450,184, both of which are incorporated herein by reference. Specifically, this technique uses spalling in the middle of the GaN layer.

[0008] However, the surface morphology on the polishing surface is rough and cannot be controlled at the polishing position. Also, this removal method can damage the semiconductor layer due to excessive bending in the layer being removed, which can lead to cracks in unintended directions. Therefore, it is necessary to reduce any such damage and surface roughness.

[0009] Another conventional technique is the use of photoelectrochemical (PEC) etching of a sacrificial layer to remove the device structure from a GaN substrate, but this is time-consuming and involves several complex processes. Also, the yield from these processes has not met industry expectations.

[0010] Therefore, there is a need in the art for an improved method of removing a group III nitride substrate from a group III nitride semiconductor layer. The present invention meets this need. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] (SUMMARY OF THE INVENTION) To overcome the limitations in the prior art described above and other limitations that will become apparent upon a thorough reading and understanding of this specification, the present invention discloses a method for removing a bar of a device from a substrate using a groove, and a device resulting from the processing by this method. MEANS FOR SOLVING THE PROBLEM

[0012] Specifically, the present invention includes the following steps: etching a substrate to form grooves on the surface of the substrate; depositing a growth-limiting mask on the substrate, optionally on or in the grooves and at least partially on at least a portion of the remaining surface area of the substrate, the growth-limiting mask having an open area where the surface of the substrate is exposed; growing a group-III nitride ELO layer on the substrate using the growth-limiting mask, the group-III nitride ELO layer having discrete regions with depressions formed by the grooves in the substrate and the group-III nitride ELO layers not fusing and remaining separated from each other; optionally removing the growth-limiting mask by wet or dry etching; growing a group-III nitride semiconductor element layer on the group-III nitride ELO layer to produce an island-shaped group-III nitride semiconductor layer on which optoelectronic elements such as LEDs and LDs are processed; removing bars of the element from the substrate; and then dividing the bars into separate elements. The present invention provides, for example, the following items. (Item 1) A method comprising: etching a substrate to form one or more grooves on the surface of the substrate; depositing a growth-limiting mask on or above the substrate, at least partially on or in the grooves, the growth-limiting mask having one or more open areas where the surface of the substrate is exposed; growing one or more group-III nitride epitaxial lateral overgrowth (ELO) layers on the surface of the substrate in the open area of the growth-limiting mask, the group-III nitride ELO layer having discrete regions with depressions formed by the grooves in the substrate; growing one or more group-III nitride semiconductor element layers on the group-III nitride ELO layer to produce one or more island-shaped group-III nitride semiconductor layers on which one or more optoelectronic elements are processed; removing the optoelectronic element from the substrate using the grooves; and including the above steps. (Item 2) The growth-limiting mask deposited in the groove is the method according to item 1, which has one or more of the open areas in the groove. (Item 3) The method according to item 2, wherein the group III nitride ELO layer is grown in the open area in the groove. (Item 4) The method according to item 1, wherein the etching of the substrate to form the groove on the surface of the substrate results in one or more residual surface regions of the substrate. (Item 5) The method according to item 4, wherein the growth-limiting mask is deposited on at least a part of the residual surface region. (Item 6) The method according to item 5, wherein a part of the residual surface region has an edge of the residual surface region. (Item 7) The method according to item 5, wherein the growth-limiting mask deposited on a part of the residual surface region determines a place where cleavage should be initiated to remove the element from the substrate. (Item 8) The method according to item 1, wherein the group III nitride ELO layer is grown from the open area of the growth-limiting mask without fusion, leaving a non-growth region between separate islands of the group III nitride ELO layer. (Item 9) The method according to item 8, wherein the groove provides a symmetric shape for separate islands of the group III nitride ELO layer, and the symmetric shape for separate islands of the group III nitride ELO layer results in an element suitable for flip-chip bonding. (Item 10) The surface of the separate region with the depression is higher than the bottom of the group III nitride ELO layer. The method according to item 1. (Item 11) The method according to item 10, wherein one or more cleavage points are located higher than the bottom of the group III nitride ELO layer such that a force is applied to the cleavage points for removal of the element from the substrate. (Item 12) An element processed by the method according to item 1. (Item 13) A structure comprising: a substrate etched to form one or more grooves on a surface of the substrate; a growth-limiting mask deposited on or above the substrate, at least partially covering the grooves, the growth-limiting mask having an open area where the surface of the substrate is exposed; one or more group-III nitride epitaxial lateral overgrowth (ELO) layers grown on the surface of the substrate in the open area of the growth-limiting mask, the group-III nitride ELO layers having distinct regions with depressions formed by the grooves in the substrate; one or more group-III nitride semiconductor device layers grown on the group-III nitride ELO layers to form island-shaped group-III nitride semiconductor layers on which one or more optoelectronic devices are fabricated. A structure as described above. (Item 14) The element according to item 13, wherein the grooves provide a symmetric shape with respect to distinct islands of the group-III nitride ELO layer, and the symmetric shape with respect to the distinct islands of the group-III nitride ELO layer results in the element being suitable for flip-chip bonding. (Item 15) The element according to item 13, wherein the surface of the distinct region with depressions is higher than the bottom of the group-III nitride ELO layer. (Item 16) The element according to item 15, wherein one or more cleavage points are located higher than the bottom of the group-III nitride ELO layer such that a force is applied to the cleavage points for removal of the element from the substrate. (Item 17) An element comprising: One or more group-III nitride epitaxial lateral overgrowth (ELO) layers grown on the surface of a substrate in one or more open areas of a growth-limiting mask, wherein the substrate includes one or more grooves on the surface of the substrate, and the group-III nitride ELO layer has a separate region with depressions formed by the grooves in the substrate, one or more group-III nitride epitaxial lateral overgrowth (ELO) layers One or more group-III nitride semiconductor device layers grown on the group-III nitride ELO layer to form an island-shaped group-III nitride semiconductor layer on which one or more optoelectronic devices are fabricated An element comprising (Item 18) The element according to item 17, wherein the grooves provide a symmetric shape with respect to separate islands of the group-III nitride ELO layer, and the symmetric shape with respect to the separate islands of the group-III nitride ELO layer results in the element being suitable for flip-chip bonding. (Item 19) The element according to item 17, wherein the surface of the separate region with depressions is higher than the bottom of the group-III nitride ELO layer. (Item 20) The element according to item 19, wherein one or more cleavage points are located higher than the bottom of the group-III nitride ELO layer such that a force is applied to the cleavage points for removal of the element from the substrate.

Brief Description of the Drawings

[0013] Reference is made to the drawings, where like reference numerals represent corresponding parts throughout.

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Embodiments for Carrying Out the Invention

[0015] (Detailed Description of the Invention) In the following description of the preferred embodiments, specific embodiments in which the present invention may be practiced are referred to. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0016] Overview The present invention discloses a method for removing one or more elements formed on a substrate using grooves. The elements may comprise a light emitting diode (LED), a laser diode (LD), a Schottky barrier diode (SBD), or a metal oxide semiconductor field effect transistor (MOSFET).

[0017] Figures 1(a) and 1(b) illustrate a structure processed in accordance with the present invention, which includes a substrate 101, a growth-limiting mask 102, an open area 103, a non-growth region 104, a group III nitride ELO layer 105, a group III nitride semiconductor element layer 106, a flat surface region 107, a layer bending region 108, a groove 109, an island-shaped group III nitride semiconductor layer 110, a separate recessed region 111, a cleavage point 112, and a group III nitride template layer 113, and the structure comprises one or more optoelectronic elements 114.

[0018] In an alternative embodiment, a group III nitride substrate 101 such as GaN or a hetero-substrate 101 such as sapphire, Si, GaAs, SiC, etc. may be used. As shown in Figure 1(b), a GaN template 113 or other group III nitride-based semiconductor layer 113 may be grown on the hetero-substrate 101 prior to the deposition or growth of other layers.

[0019] A plurality of grooves 109 are formed in the substrate 101, and the growth-limiting mask 102 is deposited on or above the substrate 101, and the growth-limiting mask 102 is deposited at least partially on or in the grooves 109.

[0020] The Group-III nitride ELO layer 105 is grown from the opening area 103 of the growth-limiting mask 102 without coalescing, leaving a non-growth region 104 between separate islands of the Group-III nitride ELO layer 105. The trench 109 provides a symmetric shape for each island of the Group-III nitride ELO layer 105, and the symmetric shape provides an element 114 that is suitable for flip-chip bonding.

[0021] The Group-III nitride semiconductor element layer 106, which includes a flat surface region 107 and a layer bending region 108, is grown on the Group-III nitride ELO layer 105, resulting in an island-shaped Group-III nitride semiconductor layer 110, which is used to form one or more elements 114. The width of the opening area 103 is narrower than the width of the island-shaped Group-III nitride semiconductor layer 110. The island-shaped Group-III nitride semiconductor layer 110 is generally bonded to the substrate 101 only in the opening area 103. The strength of the bond between the growth-limiting mask 102 and the island-shaped Group-III nitride semiconductor layer 110 is typically weak.

[0022] The trench 109 provides a separate recessed region 111 on the bottom of each island of the Group-III nitride ELO layer 105, and the surface of the separate recessed region 111 is higher than the bottom of the Group-III nitride ELO layer 105. The cleavage point 112 is located higher than the bottom of the Group-III nitride ELO layer 105, and a force can be efficiently applied to the cleavage point 112 for the removal of the bar of the element 114 formed by the island-shaped Group-III nitride semiconductor layer 110. As a result, the trench 109 helps to remove the element 114 from the substrate 101.

[0023] Formation of trenches in the substrate The following is an explanation of a method by which the substrate 101 is processed in order to fabricate the element 114 thereon according to the present invention. Specifically, FIGS. 2(a)-2(k) illustrate the steps used to form the trench 109 in the substrate 101 when fabricating the element 114 to facilitate the removal of the element 114 from the substrate 101.

[0024] 1. As shown in FIG. 2(a), the substrate 101 is prepared. In one embodiment, the substrate 101 is a self-standing m-plane GaN substrate 101 having a misorientation of -1 degree with respect to the c-axis.

[0025] 2. As shown in FIG. 2(b), the SiO2 mask 201 is deposited on the substrate 101 prior to forming the groove 109 in the substrate 101. Alternatively, a photoresist mask 201 may be used instead of the SiO2 mask 201.

[0026] 3. As shown in FIG. 2(c), the groove 109 is formed by wet or dry etching or another method. In this embodiment, the width W of the groove 109 is about 50 μm, and the depth D of the groove 109 in the substrate 101 is about 1 μm. The mask 201 that covers the remaining surface region 202 of the substrate 101 having a width L of about 50 μm is then removed.

[0027] 4. As shown in FIG. 2(d), the growth-limiting mask 102 is optionally formed on or in the groove 109 and at least partially on the remaining surface region 202. The width B of the open area 103 in the growth-limiting mask 102 is about 50 μm, the width C of the growth-limiting mask 102 that covers the remaining surface region 202 is about 5 μm, and the thickness of the growth-limiting mask 102 is about 0.2 μm.

[0028] 5. As shown in FIG. 2(e), the group III nitride ELO layer 105 is grown on the substrate 101 with the groove 109. By doing so, the group III nitride ELO layer 105 has a separate region 111 with a depression.

[0029] 6. Also, as shown in FIG. 2(e), after the growth of the group III nitride ELO layer 105, the substrate 101 may be removed from the MOCVD reactor, and the growth-limiting mask 102 may be removed by wet or dry etching or another method.

[0030] 7. The group-III nitride semiconductor element layer 106 is grown by metalorganic chemical vapor deposition (MOCVD) on the group-III nitride ELO layer 105, resulting in island-shaped group-III nitride semiconductor layers 110 as shown in Fig. 2(f). At the same time, the group-III nitride semiconductor layer 106 may also be grown on the grooves 109 in the substrate 101.

[0031] 8. Device processing is carried out on the island-shaped group-III nitride semiconductor layers 110 as shown in Fig. 2(g), resulting in devices 114. This processing may particularly include the formation of a raised stripe structure, deposition of a p-electrode, etc.

[0032] 9. A polymer film 203 is attached to the upper surface of the device 114 as shown in Fig. 2(h). The polymer film 203 may be a multilayer film 203.

[0033] 10. As shown in Fig. 2(i), a pressure 204 is applied to the polymer film 203, which pushes the bottom portion 205 of the polymer film 203 into the grooves 109. The bottom portion 205 of the polymer film 203 may be located at a distance K below the upper surface of the device 114 as represented by 206A in Fig. 2(i). Alternatively, the bottom portion 205 of the polymer film 203 may contact the bottom of the grooves 109 as represented by 206B and 206C in Fig. 2(i).

[0034] 11. As shown in Figs. 2(i) and 2(j), the cleavage point 112 is located higher than the bottom portion of the group-III nitride ELO layer 105 of the device 114, which means that a force 207 can be efficiently applied to the polymer film 203 and thus to the cleavage point 112 in order to remove the device 114 from the substrate 101 using the polymer film 203.

[0035] 12. As shown in Fig. 2(k), depicting the inverted device 114 and the polymer film 203, the width of the remaining surface region 202 of the substrate 101 exceeds the width of the open area 103, and the difference is the width of the growth-limiting mask 102 on the remaining surface region 202.

[0036] 13. Once the element 114 is removed from the substrate 101 but still attached to the polymer film 203, further processing can be carried out as will be described in more detail below. This further processing may include steps of forming a support structure for cleavage at the side facets and flat surface regions 107 of the element 114, processing an n - electrode on the element 114, decomposing the bars of the element 114 into separate elements 114, coating the facets of the laser diode element 114, screening the element 114, and mounting the element 114 on or in a package.

[0037] Element processing process A more detailed description of the steps used in processing the element 114 according to the present invention is provided below.

[0038] Step 1: Form a groove 109 on the substrate 101, where the substrate 101 is a group - III nitride substrate 101 or a hetero - substrate 101 on which a group - III nitride template 113 is deposited.

[0039] Step 2: Deposit a growth - limiting mask 102 on the substrate 101, at least partially covering or within the groove 109, such that the remaining surface region 202 of the substrate 101 is exposed by the striped open area 103 within the growth - limiting mask 102.

[0040] Step 3: Grow a group - III nitride ELO layer 105 in a direction parallel to the striped open area 103 of the growth - limiting mask 102, and grow the group - III nitride ELO layer 105 on or above the substrate 101 in a MOCVD reactor using the growth - limiting mask 102 so that the group - III nitride ELO layer 105 does not coalesce.

[0041] Step 4: Remove the substrate 101 with the group-III nitride ELO layer 105 from the MOCVD reactor, and the growth-limiting mask 102 is removed by dry or wet etching using an etching solution such as hydrogen fluoride (HF) or buffered HF (BHF) acid.

[0042] Step 5: Grow a group-III nitride semiconductor element layer 106 on the group-III nitride ELO layer 105 and on the surface of the substrate 101 between the islands of the group-III nitride ELO layer 105.

[0043] Step 6: Process one or more elements 114 in the flat surface region 107 by a conventional method, and a raised stripe structure, a p-electrode, etc. are arranged on each of the island-shaped group-III nitride semiconductor layers 110 at predetermined positions.

[0044] Step 7: Form a support structure for cleavage in the side facets of the element 114 and in the flat surface region 107.

[0045] Step 8: Remove the bar of the element 114 from the substrate 101 as follows. Step 8.1: Attach the polymer film 203 to the bar. Step 8.2: Apply a pressure 204 to the polymer film 203 and the substrate 101. Step 8.3: Reduce the temperature of the polymer film 203 and the substrate 101 while the pressure is applied. Step 8.4: Utilize the difference in the thermal coefficients between the polymer film 203 and the substrate 101 to remove the bar.

[0046] Step 9: Process an n-electrode on the bar.

[0047] Step 10: Decompose the bar into separate elements 114.

[0048] Step 11: Mount the element 114 on a heat sink plate.

[0049] Step 12: Coat the facets of each laser diode element 114.

[0050] Step 13: Divide the heat sink plate and the element 114.

[0051] Step 14: Screen the element 114.

[0052] Step 15: Mount the element 114 on or in the package.

[0053] These steps are described in more detail below.

[0054] Step 1: Form grooves on the substrate The grooves 109 in the substrate 101 may be formed by dry etching, wet etching, or other methods. In one embodiment, as shown in FIGS. 3(a)-3(b), the width W of each groove 109 is about 50 μm, the depth D of each groove 109 is about 1 μm, the width L of each remaining surface region 202 of the substrate 101 between the grooves 109 is about 50 μm, and the width C of the overlapping region of the growth-limiting mask 102 on the remaining surface region 202 is about 5 μm. In this case, the shapes of the open area 103, the grooves 109, and the remaining surface region 202 are stripes, as shown in FIG. 3(b).

[0055] Step 2: Deposit a growth-limiting mask on the substrate, at least partially covering or within the grooves The substrate 101 is patterned using a SiO2 layer, and the patterned SiO2 layer is the growth-limiting mask 102. The growth-limiting mask 102 shown in FIGS. 3(a) and 3(b) is periodically arranged at intervals p, and is arranged in a first direction parallel to the 11-20 direction of the group III nitride-based semiconductor substrate 101 oriented in the (1-100) plane and a second direction parallel to the 0001 direction of the group III nitride-based semiconductor substrate 101, and includes a plurality of open areas 103 extending in the second direction. The growth-limiting mask 102 may or may not partially cover the remaining surface region 202.

[0056] In one embodiment, the length A of the opening area 103 is about 200 to 35,000 μm, the width B of the opening area 103 is about 2 to 180 μm, and the growth-limiting mask 102 has a thickness of about 0.05 to 3 μm. In addition, the spacing P between the opening areas 103 is about 100 to 1,000 μm.

[0057] Step 3: Growing a group III nitride ELO layer on a substrate using a growth-limiting mask The epitaxial GaN layer 105 is grown by ELO on the substrate 101 using the growth-limiting mask 102. By doing so, the group III nitride ELO layer 105 is formed on the remaining surface region 202 of the substrate 101 and grows only on the opening area 103. Also, the group III nitride ELO layer 105 does not fuse on top of the growth-limiting mask 102.

[0058] In one embodiment, MOCVD is used for the epitaxial growth of the group III nitride ELO layer 105. Trimethylgallium (TMGa) is used as the group III element source. Ammonia (NH3) is used as the raw gas for supplying nitrogen. Hydrogen (H2) and nitrogen (N2) are used as the carrier gases for the group III element source. It is important to include hydrogen in the carrier gas to obtain a smooth surface epi-layer. In one embodiment, the thickness of the group III nitride ELO layer 105 is about 3 to 100 μm. Also, the group III nitride ELO layer 105 may include a GaN or AlGaN layer to obtain a smooth surface.

[0059] Step 4: Removing the growth-limiting mask After the group III nitride ELO layer 105 is grown, the substrate 101 may be removed from the MOCVD reactor to remove the growth-limiting mask 102 by wet etching, dry etching, or other methods. This is an optional step to increase the growth area on the substrate 101.

[0060] Removing the growth-limiting mask 102 before the growth of the group-III nitride semiconductor element layer 106 also reduces the excessive supply gas to the side facets of the group-III nitride ELO layer 105. Reducing the excessive supply gas to the side facets can avoid edge growth in the edge region of the group-III nitride ELO layer 105. This can make it easier to obtain a smooth surface and uniform light emission from the active layer within the group-III nitride semiconductor element layer 106.

[0061] However, if the growth-limiting mask 102 is not removed before the growth of the group-III nitride semiconductor element layer 106, other benefits can exist. As shown in FIGS. 4(a)-4(e), flakes 401 are often deposited on the growth-limiting mask 102 during the growth of thick In-containing AlGaN and InGaN layers within the group-III nitride semiconductor element layer 106. In some situations, two of the island-shaped group-III nitride semiconductor layers 110 may be connected by the flakes 401. Subsequently, the flakes 401 can be removed by ultrasonic cleaning, wet etching, or another method. However, sometimes this leads to a reduction in yield in a mass production environment.

[0062] As shown in FIGS. 4(a)-4(h), the growth-limiting mask 102 may be deposited on or in the trench 109. The amount of supply gas is less at the edge of the trench 109, which reduces the amount of flakes 401. Ultimately, this effect avoids the connection of the flakes 401 and the island-shaped group-III nitride semiconductor layer 110.

[0063] As shown in FIGS. 4(a)-4(d), 4(e), and 4(f)-4(h), several different types of mask 102 shapes exist. In FIGS. 4(f)-4(h), the growth-limiting mask 102 within the trench 109 has one or more open areas 103 near the center of the trench 109. In FIG. 4(h), the group-III nitride ELO layer 105 is grown in the open area 103 within the trench 109.

[0064] Another difference between FIGS. 4(f) and 4(g) exists, where FIG. 4(f) shows the growth-limiting mask 102 on the residual surface region 202, while FIG. 4(g) does not. In FIG. 4(f), the growth-limiting mask 102 exists on the edge of the residual surface region 202, while FIG. 4(g) shows the growth-limiting mask 102 only within the groove 109. The presence of the growth-limiting mask 102 on the residual surface region 202 is important in determining where cleavage should be initiated, which helps to increase the yield in a mass production environment. However, as shown in FIG. 4(g), it is easy to remove the bar of the element even without the growth-limiting mask 102 on the residual surface region 202.

[0065] Step 5: Growing a Group III Nitride Semiconductor Element Layer The substrate 101 is loaded into the MOCVD reactor for the growth of the Group III nitride semiconductor element layer 106, resulting in the island-like Group III nitride semiconductor layer 110. Trimethylgallium (TMGa), trimethylindium (TMIn), and trimethylaluminum (TMAl) are used as Group III element sources. Ammonia (NH3) is used as the raw gas to supply nitrogen. Hydrogen (H2) and nitrogen (N2) are used as carrier gases for the Group III element sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface epitaxial layer.

[0066] Physiological saline and bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants. The pressure setting is typically 50 - 760 Torr. The Group III nitride-based semiconductor layer is generally grown in a temperature range of 700 - 1,250 °C.

[0067] For example, the growth parameters include the following: namely, TMG is 12 sccm, NH3 is 8 slm, the carrier gas is 3 slm, SiH4 is 1.0 sccm, and the V / III ratio is about 7,700. These growth conditions are only one example and can be changed and optimized for each layer described above.

[0068] Step 6: Fabricate the element on the flat surface area The element 114 is fabricated on the flat surface area 107 and may include a raised stripe structure, a p electrode, etc. Conventional methods can be used to fabricate the raised stripe structure, the p electrode, etc.

[0069] Step 7: Form a support structure for cleavage in the side facet and the flat surface area As shown in FIGS. 5(a) and 5(b), the goal of this step is to prepare to divide the bar 501 of the element 114 before the bar 501 of the element 114 is removed from the substrate 101. The division support region 502 is formed at a periodic length, and each period is determined by the length of the element 114. For example, in the case of the laser diode element 114, one period is set to be 300 to 1,200 μm.

[0070] The division support region 502 is a line engraved by a scriber with a diamond tip or a laser scriber as shown in FIG. 5(a), or a groove formed by dry etching such as RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma) as shown in FIG. 5(b), but is not limited to those methods. The division support region 502 may be formed on both sides of the bar 501 or on one side of the bar 501. The depth of the division support region 502 is preferably 1 μm or more.

[0071] Since the division support region 502 is weaker than any other part, in both cases, the bar 501 can be divided into separate elements 114 in the division support region 502. The division support region 502 avoids decomposing the bar 501 at an unintended position so that it can precisely determine the length of the element 114.

[0072] The division support region 502 is generated in the flat surface area 107 in a manner that avoids the current injection region 503, the p electrode 504, and the layer bending region 108 within the raised stripe structure, which may include at least a part of the SiO2 current limiting layer 505.

[0073] The division support regions 502 are formed in a first facet 506, optionally a second facet 507, which are easy to process because they are flattened areas. A third facet 508 may be avoided.

[0074] As shown in FIG. 5(b), it may be preferable for the division support regions 502 to be formed only in the second facet 506, in which case a small width of the island III-nitride semiconductor layer 110 has to be used. In this case, this enables the bar 501 of the element 114 to be precisely divided.

[0075] Also, the p-electrode 504, the dielectric layer 505, the p-pad for wire bonding, etc. can avoid the division support regions 502.

[0076] By doing so, the shape of the division support regions 502 is formed uniformly. It is much more preferable for the blade for disassembling the bar 501 to contact the back side of the bar 501. By doing so, the cleavage starts from the division support regions 502 on the upper surface of the bar 501, but is not limited to this technique.

[0077] Step 8: Removing the bar of the element from the substrate FIGS. 6(a)-6(e) illustrate a method of removing the bar of the element 114 from the substrate 101.

[0078] Step 8.1 includes attaching the polymer film 203 to the upper surface of the element 114 as shown in FIG. 6(a). In one embodiment, the polymer film 203 consists of a base film 601, an adhesive layer 602, and a backing film 603. However, more or fewer layers may be used as well.

[0079] Step 8.2 includes applying pressure 204 to polymer film 203, element 114, and substrate 101 using plate 604 or other means, as shown in FIG. 6(b). The goal of applying pressure 204 is to place polymer film 203 between elements 114. Polymer film 203 is softer than element 114, and thus, polymer film 203 can easily surround element 114. Preferably, polymer film 203 is heated to soften it, which facilitates polymer film 203 covering element 114.

[0080] When the group III nitride ELO layer 105 is very thin, such as less than 10 μm, it is not easy to deposit the group III nitride ELO layer 105. However, in the present invention, the groove 109 formed in the substrate 101 helps polymer film 203 deposit on the group III nitride ELO layer 105. As shown in FIG. 6(c), polymer film 203 is pushed down to cleavage point 112, and since pressure 204 is applied horizontally, element 114 is tilted obliquely downward 605, and it is easier to remove element 114 from substrate 101.

[0081] Without groove 109, the shape of the group III nitride ELO layer 105 is shown in FIG. 7(a), and the cleavage point 112 and the bottom of the group III nitride ELO layer 105 are at the same height. With groove 109, the shape of the group III nitride ELO layer 105 is shown in FIGS. 7(b) and 7(c), and the cleavage point 112 is above the bottom of the group III nitride ELO layer 105.

[0082] In the present invention, the most important thing to facilitate removing bar 501 is that the bottom of the group III nitride ELO layer 105 is below the cleavage point 112, as shown in FIG. 6(d). The height difference between the bottom of the group III nitride ELO layer 105 and the cleavage point 112 is greater than zero.

[0083] In this case, the force from the polymer film 203 is efficiently applied to the cleavage point 112. In other words, the group III nitride ELO layer 105 has a separate recessed region 111, and the surface of the separate recessed region 111 is located higher than the bottom of the group III nitride ELO layer 105. As a result, the groove 109 enables the easier removal of the thinner and wider group III nitride ELO layer 105.

[0084] Step 8.3 includes reducing the temperature of the film 203 and the substrate 101 while maintaining the applied pressure 204. However, it is not necessary to apply the pressure 204 during the temperature change.

[0085] Various methods may be used to reduce the temperature. For example, the substrate 101 and the polymer film 203 can be placed in liquid N2 (e.g., at 77°K) simultaneously with the application of the pressure 204. The temperature of the substrate 101 and the polymer film 203 can also be controlled using a piezoelectric transducer. Also, the plate 604 that applies the pressure 204 to the polymer film 203 can be cooled to a low temperature before and / or during contact with the polymer film 203. By doing so, the polymer film 203 is cooled and can apply the pressure 204 to the element 114 due to its large coefficient of thermal expansion.

[0086] When reducing the temperature, the substrate 101 and the polymer film 203 can be wetted by moisture in the atmosphere. In this case, the temperature reduction can be performed in a dry air atmosphere or a dry N2 atmosphere, which avoids the substrate 101 and the polymer film 203 from getting wet.

[0087] Step 8.4 includes utilizing the difference in the coefficient of thermal expansion between the polymer film 203 and the substrate 101 to remove the element 114 from the substrate 101.

[0088] As shown in FIG. 6(c), the polymer film 203 shrinks as the temperature decreases, and the polymer film 203 applies a horizontal pressure 204 at the side facets of the element 114. As shown in FIG. 6(d), as a result, the bottom 205 of the polymer film 203 is lower than the upper portion 606 of the element 205. As shown in FIG. 6(c), the pressure 204 applied from the side facets enables the element 114 to be effectively removed from the substrate 101 starting at the cleavage point 112.

[0089] Also, the groove 109 makes the pressure 204 applied by the polymer film 203 more effective at the cleavage point 112 near the interface between the substrate 101 and the group III nitride ELO layer 105. The groove 109 defines a separate region 111 with a depression, enabling a thinner and wider group III nitride ELO layer 105 to be more effectively removed from the substrate 101.

[0090] Thereafter, the temperature increases, for example, to room temperature, and the pressure 204 is no longer applied to the polymer film 203. At that point, the element 114 has been removed from the substrate 101, and the polymer film 203 is then separated from the substrate 101. As shown in FIG. 6(e), when using the polymer film 203, particularly the polymer film 203 having the adhesive layer 602, the element 114 can be removed using the polymer film 203 in an easy and rapid manner.

[0091] FIG. 8(a) shows the surface of the substrate 101 with the groove 109 after removal of the bar from the substrate 101 using the present invention. FIG. 8(b) shows the back surface of the bar after removal of the bar from the substrate 101 using the present invention.

[0092] The present invention also provides other advantages. When using the m-plane substrate 101 having a misorientation toward the c-plane as shown in Fig. 9(a), the shape of the group-III nitride ELO layer 105 is often asymmetric. In this case, the m-plane substrate 101 having a misorientation of -1 degree toward the c-plane is used. In the case of an asymmetric shape, there may exist a possibility that the right height is different from the left height with respect to the island-shaped group-III nitride semiconductor layer 110. The substrate 101 with the groove 109 would be very useful in avoiding these different heights.

[0093] Even when using the substrate 101 having the same misorientation, as shown in Fig. 9(b), the present method can obtain a symmetric-shaped layer. It is considered that this phenomenon is caused by the difference in the supply of the material gas to the side facets due to the presence of the groove 109.

[0094] Also, the present method can be adopted for other materials that can implement lateral growth such as GaAs.

[0095] Step 9: Process the n electrode As shown in Fig. 10(a), after removing the bar 501 from the substrate 101, the bar 501 is attached to the polymer film 203 in an upside-down manner. Fig. 10(b) shows the back side of the bar 501 having a separate area 1001 between the divided support regions 502, and cleavage is performed by the cleavage blade 1002 in the divided support region 502.

[0096] As shown in Fig. 10(c), the metal mask 1003 is placed on each of the bars 501 on the polymer film 203, and only the separate region 1001 is shown through the mask 1003. The n electrode 1004 is then disposed on the back side of the bar 501 within the separate area 1001. Generally, the separate area 1001 is kept in a clean and good surface condition so that the n electrode 1004 can obtain a low contact resistivity. Alternatively, the n electrode can be disposed on the upper surface of the element 114.

[0097] Step 10: Decompose the bar into elements After the n electrodes 1004 are arranged, each bar 501 may be divided into one or more elements 114 as shown in FIG. 10(d). The division support region 502 helps to divide the bar 501 into the elements 114. A splitting or decomposition method, and other methods, can be used.

[0098] Step 11: Mount each element on the heat sink plate After step 8, the divided bar 501 is still on the polymer film 203. In one embodiment, the polymer film 203 is a UV-sensitive dicing tape. In this case, the polymer film 203 is exposed to UV (ultraviolet) light 1005, which can reduce the adhesive strength of the polymer film 203 as shown in FIG. 10(e). This facilitates removing the element 114 from the polymer film 203.

[0099] In this case, a heat sink plate 1006 made of AlN is prepared. An Au-Sn solder 1007 is arranged on the heat sink plate 1006, and the element 114 removed from the polymer film 203 is mounted on the heat sink plate 1006 with the Au-Sn solder 1007. At this point, the heat sink plate 1006 heated above the melting temperature of the solder 1007 can mount the element 114. The element 114 can be mounted with either the n electrode 1004 or the p electrode 504 side facing down. FIG. 10(f) shows the element 114 mounted on the heat sink plate 1006 with the n electrode 1004 side facing down and the p electrode 504 side facing up.

[0100] Step 12: Coat the facets of the laser diode element The next step in the processing of the element 114 involves coating the facets of the laser diode element 114. While the laser diode element 114 is lasing, the light within the element 114 that transmits through the facets of the element 114 to the outside of the element 114 is absorbed by the non-radiative recombination centers at the facets such that the facet temperature continuously increases. As a result, the temperature increase can lead to catastrophic optical damage (COD) of the facets.

[0101] Facet coating can reduce non-radiative recombination centers. To prevent COD, it is necessary to coat the facets using dielectric layers such as AlN, AlON, Al2O3, SiN, SiON, SiO2, ZrO2, TiO2, Ta2O5, and equivalents. Generally, the coating film is a multilayer structure composed of the above materials. The structure and thickness of the layers are determined by a predetermined reflectivity.

[0102] As shown in FIG. 10(f), the bar 501 of the element 114 is split in step 10 to obtain the cleaved facets 1008. These facets 1008 can be coated simultaneously on multiple elements 114 in an easy manner. The element 114 is mounted on the heat sink plate 1006 at a low horizontal position.

[0103] As shown in FIG. 11, the heat sink plate 1006 with the element 114 is mounted on the coating bar 1101, which may be installed on a spacer plate, and a plurality of coating bars 1101 and spacer plates are stored in the coating holder 1102. Note that it is not always necessary to use a spacer plate, and it is possible to use the coating bar 1101 alone.

[0104] By doing so, several elements 114 can be coated simultaneously. In one embodiment, the coating is performed at least twice, i.e., once on the front facet 1008 and once on the rear facet 1008. The length of the heat sink plate 1006 is set to be approximately the length of the cavity of the laser diode element 114, which facilitates and speeds up the implementation of the coating process twice. Once the coating bar 1101 is set within the coating holder 1102, both facets 1008 can be coated without resetting the coating bar 1101 within the coating holder 1102 again. In one embodiment, the first coating is performed on the front facet 1008 that emits laser light, and the second coating is performed on the rear facet 1008 that reflects laser light. The coating holder 1102 is reversed before the second coating within the facility for depositing the coating film. This substantially shortens the lead time of the process.

[0105] Step 13: Divide the element As shown in FIG. 12(a), wire bonds 1201 and 1202 are attached to the element 114, and then the heat sink plate 1006 is divided, for example, in the groove 1203 between one or more of the elements 114. FIG. 12(b) is a top view of FIG. 12(a) showing the relative installation and positions of the element 114, the groove 1203, and the wire bonds 1201, 1202. FIG. 12(c) shows the combined use of separate probes 1204 and wire bonds 1205 on the heat sink plate 1006 with the element 114.

[0106] FIGS. 13(a) and 13(b) further show how the heat sink plate 1006 can be divided to separate the element 114, which can be done before or after the attachment of the wire bonds 1002, 1202. By doing so, it is easy to separate the element 114 after the coating process is completed.

[0107] Step 14: Screen the element This step distinguishes between defective element 114 and non-defective element 114. First, various characteristics of element 114 such as output power, voltage, current, resistivity, FFP (far-field pattern), slope efficiency, and equivalents are checked under given conditions. At this point, element 114 is already mounted on heat sink plate 1006, and thus it is easy to check these characteristics.

[0108] Test apparatus 1401 is shown in FIGS. 14(a) and 14(b), and p electrode 504 and solder 1007 having electrical conductivity to n electrode 1004 are contacted by probes 1402, 1403. Then, non-defective element 114 can be selected and screened by an aging test (life test).

[0109] In one embodiment, it is preferable that test apparatus 1401 includes a box or other container so that the aging test can be performed using element 114 sealed in dry air or a nitrogen atmosphere. Also, heat stage 1404 may be used to maintain the temperature of element 114 during the screening test, for example, 60 degrees, 80 degrees, etc. Photodetector 1405 may be used to measure optical output power 1406 for identifying non-defective element 114 having a constant output power or defective element 114.

[0110] In particular, in the case of group III nitride-based semiconductor laser diode element 114, it is known that when the laser diode oscillates in an atmosphere containing moisture, it deteriorates. This deterioration is caused by moisture and siloxane in the air, and thus group III nitride-based semiconductor laser diode element 114 needs to be sealed in dry air during the aging test.

[0111] As a result, as shown in FIG. 15, when the group III nitride-based laser diode 1501 is shipped from the manufacturer, the chip 1502 itself is mounted on the stem 1503, sealed in a dry air atmosphere using the TO-can package 1504, and the package 1504 includes a window 1505 for light emission 1506.

[0112] Generally speaking, screening or aging tests are performed before shipment to eliminate defective elements 114. For example, the screening conditions are carried out according to the specifications of the laser diode element 114 such as high temperature and high power.

[0113] Also, the aging test can be performed with the element 114 mounted on / inside the package 1501 and the package 1501 sealed in dry air and / or dry nitrogen before screening. This fact limits the flexibility of packaging and mounting of the laser element.

[0114] In the prior art, if defective production occurs, the defective product is discarded as a whole TO-CAN package 1501, which is a great loss for production. This makes it difficult to reduce the production cost of the laser diode element 114. There is a need to detect defective elements 114 at an early step.

[0115] In the present invention, coating the facet 1008 of the element 114 using a heat sink plate 1006 on which a plurality of elements 114 can be mounted at a low horizontal position, and then using a groove 1203 to divide the heat sink plate 1006 and the element 114 after the coating process enables the element 114 to be checked in a screening test in a dry air or nitrogen atmosphere with the submount of the heat sink plate 1006.

[0116] When performing the screening test, the element 114 already has two contacts, namely, the p - electrode 504 and the solder 1007 on the heat - sink plate 1006, or in the case of flip - chip bonding, the n - electrode 1004 and the solder 1007 on the heat - sink plate 1006. Also, when the element 114 consists only of a chip and a sub - mount, the present invention can use the screening test to select defective products. Therefore, when discarding defective products, the present invention can reduce losses compared to the prior art, which has great value.

[0117] In the case of screening the high - power laser diode element 114, it may preferably be the case that the heat - sink plate 1006 has two portions of the solder 1007 arranged without electrical conduction. One portion of the solder 1007 is connected to the p - electrode 504 using a wire (not shown), and the other portion of the solder 1007 is connected to the n - electrode 1004 using a wire (not shown). Also, the p - electrode 504 and the n - electrode 1004 may preferably be connected to the solder portion 1007 by two or more wires, as shown in FIG. 12(c) showing the p - electrode 504 connected to the solder 1007 by two or more wires. Thus, the probe 1204 for applying current to the element 114 can avoid direct contact with the p - electrode 504 (or the n - electrode 1004), which is important in the case of screening the high - power laser diode element 114. Specifically, the probe 1204 can damage the contacted portion, especially when applying a high - current density.

[0118] Step 15: Mount the element on or in the package As shown in FIG. 16, the element 114 (including the heat sink plate 1006) may be mounted in the package 1601 using solder or another metal so as to bond the element 114 at the bottom of the package 1601. The pins 1602 of the package 1601 are connected to the element 114 by wires 1603. By doing so, current from an external power supply can be applied to the element 114.

[0119] This is more preferable than the bonding between the package 1601 and the heat sink plate 1006 using metals such as Au - Au, Au - In, etc. This method requires flatness on the surface of the package 1601 and the back side of the heat sink plate 1006. However, without the solder 1007, this configuration achieves high thermal conductivity and low - temperature bonding, which is a great advantage for the element 114 process.

[0120] Thereafter, the lid 1604 may enclose the package 1601. Also, the phosphor 1605 can be set outside and / or inside the package 1601, and the window 1606 enables light emission to be emitted from the package 1601. By doing so, the package 1601 can be used as a light bulb or an automotive headlight.

[0121] As described in this specification, these processes provide an improved method for obtaining the laser diode element 114. In addition, once the element 114 is removed from the substrate 101, the substrate 101 can be recycled several times. This achieves the goals of environmentally friendly production and low - cost modules. These elements 114 may be used as lighting devices such as light bulbs, data storage devices, optical communication devices such as Li - Fi, etc.

[0122] Encapsulating a plurality of different types of laser elements 114 within a single package 1601 is difficult. However, the present method can overcome this problem because it is possible to conduct the aging test without encapsulation. Therefore, it is easy to mount different types of elements 114 within a single package 1601.

[0123] Alternative Embodiment The following is an alternative embodiment for processing the element 114 according to the present invention.

[0124] First Embodiment In the first embodiment, a self-standing m-plane GaN substrate 101 is used, and the substrate 101 has a misorientation with a -1 degree angle with respect to the c-axis.

[0125] Second Embodiment In the second embodiment, the substrate 101 comprises a group III nitride substrate 101 that can include various off-angle substrates, and the group III nitride ELO layer 105 is a GaN layer.

[0126] Third Embodiment In the third embodiment, a different mounting type, namely, the flip-chip method, is used. In the flip-chip method, the area of the element 114 in contact with the heat sink plate 1006 can be large due to the improved thermal conductivity. In addition, due to the substantially symmetric shape of the group III nitride ELO layer 105 formed using the present invention, the upper surface of the element 114 is horizontal and flatter.

[0127] Definition of Terms Group III Nitride Substrate Any GaN substrate 101 sliced on the {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} planes or other planes from bulk GaN and AlN crystals can be used as long as the group III nitride substrate 101 enables the growth of the group III nitride semiconductor layer through the growth-limiting mask 102.

[0128] Hetero-substrate In addition, the present invention can also use a hetero-substrate 101 for the element 114. For example, a GaN template 113 or other group III nitride-based semiconductor layer 113 may be grown on a hetero-substrate 101 such as sapphire, Si, GaAs, SiC, etc. for use in the present invention. The GaN template 113 or other group III nitride-based semiconductor layer 113 is typically grown on the hetero-substrate 101 to a thickness of about 2 - 6 μm, and then a growth-limiting mask 102 is disposed on the GaN template 113 or other group III nitride-based semiconductor layer 113.

[0129] Growth-limiting mask The growth-limiting mask 102 is composed of a dielectric layer such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, or a refractory metal or noble metal such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt. The growth-limiting mask 102 may be a laminated structure selected from the above materials. It may also be a multiple stacking layer structure selected from the above materials.

[0130] The growth-limiting mask 102 is deposited by sputtering, electron beam evaporation, plasma enhanced chemical vapor deposition (PECVD), ion beam deposition (IBD), etc., but is not limited to those methods.

[0131] In one embodiment, the thickness of the growth-limiting mask 102 is about 0.05 - 3 μm. The width of the mask 102 is preferably greater than 20 μm, and more preferably the width is greater than 40 μm.

[0132] The growth-limiting mask 102 shown in FIGS. 3(a) and 3(b) is periodically arranged at intervals p in a first direction parallel to the 11 - 20 direction of the group III nitride-based semiconductor substrate 101 oriented in the (1 - 100) plane and a second direction parallel to the 0001 direction of the group III nitride-based semiconductor substrate 101, and includes a plurality of open areas 103 extending in the second direction.

[0133] The growth-limiting mask 102 may or may not partially cover the residual surface area 202, which helps to remove each bar of the element 114 from the substrate 101. The length C of the covered area of the residual surface area 202 may be 0 to 0.4 μm or more to facilitate the removal of the bars of the element 114.

[0134] Direction of the growth-limiting mask On the m-plane free-standing GaN substrate 101, the striped open areas 103 are arranged periodically at the first interval and the second interval, respectively, in a first direction parallel to the 11-20 direction (a-axis) of the group III nitride semiconductor layers 105, 106, 110 and in a second direction parallel to the 0001 direction (to the c-axis) of the group III nitride semiconductor layers 105, 106, 110, and extend in the second direction.

[0135] On the c-plane free-standing GaN substrate 101, the striped open areas 103 are arranged periodically at the first interval and the second interval, respectively, in a first direction parallel to the 11-20 direction (a-axis) of the group III nitride semiconductor layers 105, 106, 110 and in a second direction parallel to the 1-100 direction (to the m-axis) of the group III nitride semiconductor layers 105, 106, 110, and extend in the second direction.

[0136] On the semi-polar (20-21) or (20-2-1) GaN substrate 101, the open areas 103 are arranged in directions parallel to [-1014] and [10-14], respectively.

[0137] Alternatively, a hetero-substrate 101 can be used. When the c-plane GaN template 113 is grown on the c-plane sapphire substrate 101, the open area 103 is in the same direction as the c-plane free-standing GaN substrate 101, and when the m-plane GaN template 113 is grown on the m-plane sapphire substrate 101, the open area 103 is in the same direction as the m-plane free-standing GaN substrate 101. By doing so, an m-plane cleavage plane can be used to divide the bar 501 of the element 114 with the c-plane GaN template 113, and a c-plane cleavage plane can be used to divide the bar 501 of the element 114 with the m-plane GaN template 113, which is much more preferable.

[0138] The width of the striped open area 103 is typically constant in the second direction, but may be changed in the second direction as needed.

[0139] Group III nitride semiconductor layer The group III nitride ELO layer 105, the group III nitride semiconductor element layer 106, and the island-like group III nitride semiconductor layer 110 can contain In, Al, and / or B, and other impurities such as Mg, Si, Zn, O, C, H, etc.

[0140] The group III nitride semiconductor element layer 106 generally includes more than two layers including at least one layer selected from an n-type layer, an undoped layer, and a p-type layer. Specifically, the group III nitride semiconductor element layer 106 includes a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc.

[0141] The distance between adjacent island-like group III nitride semiconductor layers 110, which is the non-growth region 104, is generally 30 μm or less, preferably 10 μm or less, but is not limited to these numbers.

[0142] Flat surface region and layer bending region The flat surface region 107 is between the layer bending regions 108 at the edges of the group-III nitride ELO layer 105. Further, the flat surface region 107 is on the growth-limiting mask 102.

[0143] The processing of the semiconductor element 114 is mainly carried out on the flat surface region 107. The width of the flat surface region 107 is preferably at least 5 μm, more preferably 10 μm or more. The flat surface region 107 has high thickness uniformity for each of the semiconductor layers 105, 106, 110 within the flat surface region 107.

[0144] When the processing of the semiconductor element 114 is partially formed on the layer bending region 108, there is no problem. More preferably, the layer in the layer bending region 108 is removed by etching. For example, it is better that at least a part of the active layer in the layer bending region 108 is removed using an etching process such as dry etching or wet etching.

[0145] Polymer film In one embodiment, the polymer film 203 is a dicing tape such as a UV-sensitive dicing tape. The polymer film 203 may include a base film 601 material having a thickness of, for example, about 80 μm and made of polyvinyl chloride (PVC), an adhesive layer 602 having a thickness of, for example, about 15 μm and made of an acrylic UV-sensitive adhesive, and a backing film 603 material having a thickness of, for example, about 38 μm and made of polyethylene terephthalate (P.E.T.), and may include a multilayer film 203 such as that shown in FIGS. 6(a), 6(b), and 6(c). When the polymer film 203 is a UV-sensitive dicing tape and is exposed to UV light, the adhesiveness of the adhesive is significantly reduced, facilitating the removal of the element 114 from the polymer film 203.

[0146] Heat sink plate As described above, when removed, bar 501 of element 114 is transferred to heat sink plate 1006, which can be AlN, SiC, Si, Cu, CuW, and equivalents. As shown in FIG. 10(e), solder 1007 for bonding, which can be Au - Sn, Su - Ag - Cu, Ag paste, and equivalents, is placed on heat sink plate 1006. Then, the n - electrode or p - electrode is bonded to solder 1007. Element 114 can also be flip - chip bonded to heat sink plate 1006.

[0147] When bonding LED element 114 to heat sink plate 1006, the size of heat sink plate 1006 is not a problem and can be designed as desired.

[0148] When bonding LD element 114 to heat sink plate 1006, it is preferable that the length of heat sink plate 1006 is the same as or shorter than the length of LD element 114 for the facet coating process. The length of LD element 114 is approximately the same as the length of the laser cavity. By doing so, it is easy to coat both facets 1008 of the laser cavity. If the length of heat sink plate 1006 is longer than the laser cavity, heat sink plate 1006 may interfere with the uniform coating of laser facet 1008.

[0149] Heat sink plate with long width The long width of heat sink plate 1006 makes the process of processing laser diode element 114 more productive. As shown in FIG. 11, heat sink plate 1006 is installed on coating bar 1101, possibly on a spacer plate, and then stacked with other coating bars 1101 and spacer plates in coating holder 1102 to coat a plurality of elements 114 simultaneously. As a result, a single coating process can coat many devices 114.

[0150] Heat sink plate with grooves As shown in FIG. 12(b), it is preferable that the heat sink plate 1006 has a groove 1203 for dividing the element 114. This structure is useful when the heat sink plate 1006 is divided into one or more elements 114, for example, a single element 114 or an array of elements 114, after the faceting coating process. After dividing the heat sink plate 1006, the element 114 can be processed into a module such as an illumination module. The groove 1203 in the heat sink plate 1006 guides the division into the element 114.

[0151] The groove 1203 is formed by a wet etching method and can be mechanically processed before the element 114 is mounted. For example, when the heat sink plate 1006 is made of silicon, wet etching can be used to form the groove 1203. Using the groove 1203 in this way shortens the lead time of the process.

[0152] Heat sink plate with solder As shown in FIG. 10(f), it is preferable that the length of the solder 1007 is shorter than the length of the element 114 on the heat sink plate 1006. This prevents any intrusion of the solder 1007 into the facet 1008 that could cause degradation of the characteristics of the element 114. In particular, the intrusion should be avoided for flip chip mounting.

[0153] As shown in Fig. 12(b), after the coating process, the coating bar has an overhang area, which is the area surrounded by the dashed line. The overhang area has a width W of about 10 - 20 μm. The coating film will coat these areas. Also, it is difficult to avoid coating the solder 1007 using the coating film. Generally, the coating film is selected from one or more dielectric materials, and thus this area has no conductivity. This becomes a problem for both conductivity and adhesiveness when the wire is joined to the solder 1007. Therefore, it is preferable that the wire be installed so as to avoid the overhang area. At least, the location of the wire bonding should be about 25 μm away from the edge of the heat sink plate 1006.

[0154] Semiconductor element The semiconductor element 114 is, for example, a Schottky diode, a light-emitting diode, a semiconductor laser, a photodiode, a transistor, etc., but is not limited to these elements. The present invention is particularly useful for micro LEDs and laser diodes such as edge-emitting lasers and vertical cavity surface-emitting lasers (VCSELs). The present invention is particularly useful for semiconductor lasers having cleaved facets.

[0155] Processing the LED element In the case of processing the LED element 114, the same process may be used up to step 6. This discussion briefly describes a method of fabricating two types of LEDs. Type 1 LEDs have two electrodes (a p-electrode and an n-electrode) on one side of the chip, while type 2 LEDs have electrodes on opposite sides of the chip.

[0156] First, in the case of type 1 LEDs, the p-electrode and the n-electrode are formed on the upper surface of the element 114 in step 6. Then, the bar 501 of the element 114 is removed as described in step 8, and the removed element 114 is mounted on the heat sink plate 1006.

[0157] Second, in the case of the type 2 LED, substantially the same process is used up to step 6, and the ITO electrode is formed on the p-GaN contact layer of the element 114. Also, it is preferable that the layer bending region 108 is eliminated.

[0158] Process flowchart FIG. 17 is a flowchart illustrating the device processing process described above, and the final block of the flowchart represents the product resulting from the device processing process, i.e., one or more group III nitride semiconductor devices processed according to the present method and the substrate that has been removed from the device and is available for recycling and reuse.

[0159] Block 1701 represents the step of etching the substrate to form one or more grooves on the surface of the substrate.

[0160] Block 1702 is the step of depositing a growth-limiting mask on or above the substrate, at least partially covering the grooves or within them, the growth-limiting mask having one or more open areas where the surface of the substrate is exposed. The etching of the substrate to form grooves on the surface of the substrate may result in one or more residual surface regions of the substrate, and the growth-limiting mask may be deposited on at least a portion of the residual surface region of the substrate, a portion of the residual surface region having an edge of the residual surface region. The growth-limiting mask deposited on a portion of the residual surface region determines the location where cleavage should be initiated to remove the device from the substrate.

[0161] Block 1703 represents a step of growing one or more group-III nitride ELO layers on the surface of the substrate in the open area of the growth-limiting mask, where the group-III nitride ELO layer has a separate region with a depression formed by a groove in the substrate. The growth-limiting mask deposited in the groove may have one or more of the open areas in the groove, and the group-III nitride ELO layer may be grown in the open area in the groove. The group-III nitride ELO layer is grown from the open area of the growth-limiting mask without fusion, leaving a non-growth region between separate islands of the group-III nitride ELO layer. The groove may result in a symmetric shape with respect to separate islands of the group-III nitride ELO layer, and the symmetric shape with respect to separate islands of the group-III nitride ELO layer results in an element suitable for flip-chip bonding. The surface of the separate region with the depression may be higher than the bottom of the group-III nitride ELO layer, and one or more cleavage points are located higher than the bottom of the group-III nitride ELO layer such that a force is applied to the cleavage point for removal of the element from the substrate.

[0162] Block 1704 represents a step of growing one or more group-III nitride semiconductor element layers on the group-III nitride ELO layer and generating one or more island-shaped group-III nitride semiconductor layers on which one or more optoelectronic elements are processed.

[0163] Block 1705 represents the result from the process, which may include an intermediate structure processed according to steps 1701 - 1704. For example, the intermediate structure may include a substrate that is etched to form one or more grooves on the surface of the substrate, and a growth-limiting mask that is deposited on or above the substrate, at least partially covering the grooves or within them. The growth-limiting mask has an open area where the surface of the substrate is exposed. One or more group-III nitride ELO layers are grown on the surface of the substrate in the open area of the growth-limiting mask. The group-III nitride ELO layers have distinct regions with depressions formed by the grooves in the substrate. One or more group-III nitride semiconductor element layers are grown on the group-III nitride ELO layers to form an island-shaped group-III nitride semiconductor layer on which one or more optoelectronic devices are processed.

[0164] Block 1706 represents the step of removing the optoelectronic device from the substrate using the grooves.

[0165] Block 1707 represents the result from the process, which may include the final device processed according to steps 1701 - 1706. For example, the final device may include one or more group-III nitride ELO layers grown on the surface of the substrate in one or more open areas of the growth-limiting mask. The substrate includes one or more grooves on its surface. The group-III nitride ELO layers have distinct regions with depressions formed by the grooves in the substrate. One or more group-III nitride semiconductor element layers are grown on the group-III nitride ELO layers to form an island-shaped group-III nitride semiconductor layer on which one or more optoelectronic devices are processed.

[0166] Advantages and Benefits The present invention provides several advantages and benefits. · The expensive group-III nitride-based substrate 101 can be reused after the substrate 101 is removed from the element 114 layer. · High-quality layers 105, 106, 110 can be obtained using a substrate 101 of the same or similar material with a very low defect density. · Using the same or similar material for both the substrate 101 and the layers 105, 106, 110 can reduce the strain within the layers 105, 106, 110. · Using a material with the same or similar thermal expansion for both the substrate 101 and the layers 105, 106, 110 can reduce the bending of the substrate 101 during epitaxial growth. · The layer 105 grown by ELO is of high quality. · The group-III nitride ELO layer 105 does not fuse with each other, and the internal strain is released, which helps to avoid any occurrence of cracks. For the element layer 106 which is an AlGaN layer, this is particularly useful especially in the case of a high-Al-containing layer. · The island-shaped group-III nitride semiconductor layers 110 are formed independently, and thus tensile or compressive stress is not directed towards other island-shaped group-III nitride semiconductor layers 110. · Also, the growth-limiting mask 102 and the group-III nitride ELO layer 105 are not chemically bonded, and thus the stress within the group-III nitride ELO layer 105 and the additional element layer 106 can be relaxed by the sliding caused at the interface between the growth-limiting mask 102 and the group-III nitride ELO layer 105. · The presence of the non-growth regions 104 between each of the island-shaped group-III nitride semiconductor layers 110 provides flexibility, and the substrate 101 can be easily deformed and bent when an external force is applied. Thus, even if a slight warp, curvature, or deformation occurs within the substrate 101, this can be easily corrected by a small external force, and the occurrence of cracks can be avoided. As a result, the handling of the substrate 101 by a vacuum chuck is possible, which enables the semiconductor device manufacturing process to be carried out more easily. · The non-growth regions 104 facilitate the division of a large area of the growth-limiting mask 102. · High-quality semiconductor crystal layers 105, 106, 110 can be grown by suppressing the curvature of the substrate 101. Further, even when the layers 105, 106, 110 are very thick, the occurrence of cracks and the like can be suppressed, whereby a large-area semiconductor device can be easily realized. · The processing method can also be easily adopted for wafers of large sizes (>2 inches).

[0167] Modifications and alternatives Some modifications and alternatives can be made without departing from the scope of the present invention.

[0168] For example, the present invention may be used in combination with group III nitride substrates 101 of other orientations. Specifically, the substrate 101 may be a semi-polar plane group having at least two non-zero h, i, or k Miller indices and a non-zero l Miller index such as the basal non-polar m-plane {10-10} group and the {20-2-1} plane. The semi-polar substrate 101 of (20-2-1) is particularly useful due to the large area of planarized ELO growth.

[0169] In another embodiment, the present invention is described as being used for processing different optoelectronic device structures such as light-emitting diodes (LEDs), laser diodes (LDs), Schottky barrier diodes (SBDs), or metal-oxide-semiconductor field-effect transistors (MOSFETs). The present invention may also be used for processing other optoelectronic devices such as micro-LEDs, vertical-cavity surface-emitting lasers (VCSELs), edge-emitting laser diodes (EELDs), and solar cells.

[0170] Conclusion Here, the description of the preferred embodiments of the present invention is concluded. The foregoing description of one or more embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be defined not by the embodiments for carrying out the invention, but rather, by the claims appended hereto.

Claims

1. A method comprising: preparing an ELO layer forming substrate, wherein the ELO layer forming substrate comprises: a substrate having one or more grooves on its surface; and one or more island-shaped group III nitride epitaxial lateral overgrowth (ELO) layers grown on the surface of the substrate in an open area of a growth-limiting mask deposited on or in the grooves at least partially on the grooves, wherein the group III nitride ELO layer has a separate region with depressions formed by the grooves in the substrate and the growth-limiting mask on or in the grooves; one or more island-shaped group III nitride ELO layers and; growing one or more group III nitride semiconductor element layers on the group III nitride ELO layer, and generating one or more island-shaped group III nitride semiconductor layers on which one or more optoelectronic elements are processed thereon; removing the optoelectronic element from the substrate using the groove; and including.

2. The method according to claim 1, wherein the substrate is a GaN template or a hetero-substrate on which other group III nitride-based semiconductor layers are deposited.

3. The method according to claim 1, wherein the surface of the separate region with depressions is higher than the bottom of the group III nitride ELO layer.

4. The method according to claim 3, wherein one or more cleavage points are located higher than the bottom of the group III nitride ELO layer such that a force is applied to the cleavage points for removal of the optoelectronic element from the substrate.

5. A structure comprising: a substrate having one or more grooves on its surface; One or more island-shaped group-III nitride epitaxial lateral overgrowth (ELO) layers grown on the surface of the substrate in the open area of a growth-limiting mask deposited at least partially over or within the groove, wherein the group-III nitride ELO layer has distinct regions with depressions formed by the groove in the substrate and the growth-limiting mask over or within the groove One or more group-III nitride semiconductor device layers grown on the group-III nitride ELO layer to produce an island-shaped group-III nitride semiconductor layer on which one or more optoelectronic devices are fabricated A structure comprising Claim 6 The structure according to claim 5, wherein the substrate is a GaN template or a hetero-substrate on which other group-III nitride-based semiconductor layers are deposited Claim 7 The structure according to claim 5, wherein the groove provides a symmetric shape with respect to distinct islands of the group-III nitride ELO layer Claim 8 The structure according to claim 5, wherein the surface of the distinct region with the depression is higher than the bottom of the group-III nitride ELO layer Claim 9 The structure according to claim 8, wherein one or more cleavage points are located higher than the bottom of the group-III nitride ELO layer such that a force is applied to the cleavage point for removal of the optoelectronic device from the substrate Claim 10 A device, comprising One or more island-shaped group-III nitride epitaxial lateral overgrowth (ELO) layers on the surface of a substrate, wherein the substrate includes one or more grooves on the surface of the substrate, and the group-III nitride ELO layer is grown at least partially in an open area of a growth-limiting mask deposited on the substrate over or within the groove, and the group-III nitride ELO layer has a separate region with depressions formed by the groove in the substrate and the growth-limiting mask over or within the groove, one or more island-shaped group-III nitride epitaxial lateral overgrowth (ELO) layers One or more group-III nitride semiconductor element layers grown on the group-III nitride ELO layer to form an island-shaped group-III nitride semiconductor layer on which one or more optoelectronic elements are processed An element comprising: Claim 11 The element according to claim 10, wherein the substrate is a GaN template or a hetero-substrate on which another group-III nitride-based semiconductor layer is deposited. Claim 12 The element according to claim 10, wherein the groove provides a symmetric shape with respect to separate islands of the group-III nitride ELO layer. Claim 13 The element according to claim 10, wherein the surface of the separate region with depressions is higher than the bottom of the group-III nitride ELO layer. Claim 14 The element according to claim 13, wherein one or more cleavage points are located higher than the bottom of the group-III nitride ELO layer such that a force is applied to the cleavage point for removal of the optoelectronic element from the substrate.

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