Drive device for semiconductor switching element

Abstract

The driving unit (301) is configured to be able to adjust the driving ability of the semiconductor switching element (Q), and drives the semiconductor switching element (Q) according to a driving signal (Vin) for controlling the switching operation of the semiconductor switching element (Q). The adjusting unit (302) adjusts the driving ability of the semiconductor switching element (Q) by the driving unit (301) so that the switching speed of the semiconductor switching element (Q) changes. The adjusting unit (302) generates a driving ability signal (Vcap) for adjusting the driving ability of the semiconductor switching element (Q) by the driving unit (301) based on an adjustment signal (Vin) different from the driving signal (Vin), and outputs the generated driving ability signal (Vcap) to the driving unit (301). The driving unit (301) adjusts the driving signal (Vin) according to the driving ability signal (Vcap), and outputs the adjusted driving signal (Sg) to the control electrode (G).

Description

Technical Field

[0001] The present disclosure relates to a driving device for a semiconductor switching element.

Background Art

[0002] In recent years, semiconductor switching elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have become widely popular. These semiconductor switching elements are used, for example, as power semiconductor elements in power conversion devices.

[0003] Japanese Patent Application Laid-Open No. 2019-22253 (Patent Document 1) discloses a semiconductor driving device. As shown in FIGS. 10 and 11 of Patent Document 1, the short-circuit protection board of the semiconductor driving device includes an overcurrent detection circuit and a short-circuit detection circuit. When an overcurrent flowing through the IGBT is detected by the overcurrent detection circuit, the short-circuit detection circuit determines that the IGBT has short-circuited. Then, the short-circuit detection circuit reduces the gate voltage of the IGBT to cut off the IGBT (see

[0055] to

[0058] ).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0005] The semiconductor drive device described in Patent Document 1 only shuts off the IGBT when a short circuit occurs in the IGBT. This merely controls the driving ability of the IGBT under the condition that the operation of the IGBT has to be stopped in order to prevent the destruction of the IGBT.

[0006] Depending on the conditions under which a semiconductor switching element (or a power conversion device incorporating such an element) is used, the required operation of the semiconductor element can be different. It is desirable to cause the semiconductor switching element to perform an operation suitable for the conditions under which it is used.

[0007] The present disclosure has been made in consideration of the above problems, and one of the objects of the present disclosure is to provide a drive device for a semiconductor switching element capable of causing the semiconductor switching element to perform an operation suitable for the conditions under which it is used.

Means for Solving the Problems

[0008] A drive device for a semiconductor switching element having a control electrode according to an aspect includes a drive unit and an adjustment unit. The drive unit is configured to be able to adjust the driving ability of the semiconductor switching element, and drives the semiconductor switching element according to a drive signal for controlling the switching operation of the semiconductor switching element. The adjustment unit adjusts the driving ability of the semiconductor switching element by the drive unit so that the switching speed of the semiconductor switching element changes. The adjustment unit generates a driving ability signal for adjusting the driving ability of the semiconductor switching element by the drive unit based on an adjustment signal different from the drive signal, and outputs the generated driving ability signal to the drive unit. The drive unit adjusts the drive signal according to the driving ability signal, and outputs the adjusted drive signal to the control electrode.

Effects of the Invention

[0009] The switching waveform (the waveform of voltage and / or current during switching) of the semiconductor switching element changes according to the switching speed of the semiconductor switching element. As will be described in detail later, there is a trade-off relationship between the loss (switching loss) and noise (switching noise) generated during the switching operation of the switching element, regarding whether the change in the switching waveform is steep or gentle. According to the present disclosure, since the switching speed is adjusted according to the adjustment signal, it is possible to reduce the switching loss or reduce the switching noise according to the conditions under which the semiconductor switching element is used. Therefore, it is possible to cause the semiconductor switching element to perform an operation suitable for the conditions under which the semiconductor switching element is used.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference characters, and the description thereof will not be repeated.

[0012] In the following embodiment, a configuration in which a driving device for a switching element according to the present disclosure is applied to a power conversion device will be described as an example. However, the application of the driving device for a switching element according to the present disclosure is not limited to power conversion.

[0013] Embodiment 1 <System configuration> 1 is a block diagram showing an example of a configuration of a power conversion system according to Embodiment 1. The power conversion system 100 includes a power conversion device 1, a power source 8, and a load 9.

[0014] The power supply 8 supplies power to the power conversion device 1. The power supply 8 is, for example, an AC power supply (AC system), typically a commercial power supply. The power supply 8 may be a DC power supply (DC system) such as a storage battery or a solar cell. The power supply 8 may include an AC / DC converter connected to the AC power supply. The power supply 8 may include a DC / DC converter that boosts or lowers the DC power output from the DC power supply.

[0015] The load 9 is a device driven by power supplied from the power conversion device 1. The load 9 is, for example, an AC load. Specifically, the load 9 may be a three-phase motor for a hybrid car, an electric car, a railroad car, an elevator, or an air conditioner. The load 9 may be, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system. The load 9 may be, for example, a DC load (for example, a storage battery).

[0016] The power conversion device 1 is electrically connected between a power source 8 and a load 9. The power conversion device 1 converts power supplied from the power source 8 into power suitable for use by the load 9, and supplies the converted power to the load 9. The power conversion device 1 includes a main conversion device 2, a main drive device 3, and a control device 4.

[0017] The main conversion device 2 includes a semiconductor module 201 for performing the above-described power conversion operation. The semiconductor module 201 includes, for example, switching elements Q1 to Q6 (see FIG. 2). Each of the switching elements Q1 to Q6 is a MOSFET, IGBT, MESFET (Metal-Semiconductor Field-Effect Transistor), bipolar transistor, or the like. The material of the switching elements Q1 to Q6 is typically Si, but other materials (SiC, GaN, G a 2O3, diamond, etc.) may also be used.

[0018] The main drive device 3 drives the semiconductor module 201 within the main conversion device 2. The control device 4 controls the main drive device 3.

[0019] FIG. 2 is a diagram showing an example of the configuration of the power conversion device 1. In this example, the power source 8 is a three-phase AC power source 81, which supplies AC power to the main conversion device 2 via three AC input terminals Ta, Tb, and Tc. The load 9 is a three-phase motor 91, which receives the supply of AC power from the main conversion device 2 via three AC output terminals Tu, Tv, and Tw. The main conversion device 2 includes a rectifier circuit 21 and an inverter circuit 22.

[0020] The rectifier circuit 21 is, for example, a full-wave rectifier circuit and includes six diodes 211 to 216. Diode 211 has a cathode connected to the high-potential DC power line PL and an anode connected to the AC input terminal Ta. Diode 212 has a cathode connected to the AC input terminal Ta and an anode connected to the low-potential DC power line NL. Diode 213 has a cathode connected to the high-potential DC power line PL and an anode connected to the AC input terminal Tb. Diode 214 has a cathode connected to the AC input terminal Tb and an anode connected to the low-potential DC power line NL. Diode 215 has a cathode connected to the high-potential DC power line PL and an anode connected to the AC input terminal Tc. Diode 216 has a cathode connected to the AC input terminal Tc and an anode connected to the low-potential DC power line NL.

[0021] The inverter circuit 22 is, for example, a two-level three-phase full-bridge circuit, and includes six switching elements Q1 to Q6 and six freewheel diodes D1 to D6. The freewheel diodes D1 to D6 are connected in anti-parallel to the switching elements Q1 to Q6 respectively. The switching elements Q1 and Q2 are connected in series with each other to form the U-phase arm 22U of the full-bridge circuit. The switching elements Q3 and Q4 are connected in series with each other to form the V-phase arm 22V of the full-bridge circuit. The switching elements Q5 and Q6 are connected in series with each other to form the W-phase arm 22W of the full-bridge circuit. Each phase arm is connected between the high-potential DC power line PL and the low-potential DC power line NL. The U-phase arm, the V-phase arm, and the W-phase arm are connected to the AC output terminals Tu, Tv, and Tw respectively.

[0022] The main drive device 3 includes six drive devices 31 to 36. The drive devices 31 to 36 drive the switching elements Q1 to Q6 respectively. The configuration of each of the drive devices 31 to 36 will be described after FIG. 4.

[0023] The control device 4 outputs drive signals Vinj (j = 1 to 6) to each of the six drive devices 31 to 36.

[0024] FIG. 3 is a diagram showing an example of the hardware configuration of the control device 4. The control device 4 includes, for example, a processor 41, a memory 42, a receiver 43, and a display 44.

[0025] The processor 41 is an arithmetic processing device such as a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). The memory 42 includes a volatile storage device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), and a non-volatile storage device such as an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a flash memory. The memory 42 stores a system program including an OS (Operating System), a control program including computer-readable code, and various parameters for controlling the power conversion operation. The processor 41 realizes various arithmetic processes by reading out the system program, the control program, and the parameters, expanding them in the memory 42, and executing them.

[0026] The control device 4 may be realized by a processing circuit (not shown) such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). In that case, the control device 4 may include the processing circuit instead of or in addition to the processor 41 and the memory 42.

[0027] The receiving device 43 is a touch panel, an operation button, etc., and receives an operation by the user. The display 44 is a monitor, etc., and displays the progress and results of the arithmetic processing by the processor 41 to the user. The control device 4 may include a communication module (not shown) for transmitting the progress and results of the arithmetic processing by the processor 41 to the outside instead of or in addition to the display 44.

[0028] The components of the control device 4 are typically connected by wire. However, some of the components may be wirelessly connected. Also, a part of the electric circuit arranged in the processor 41 transmits signals to another part by wire, but some signals (for example, the adjustment signal Vref described later) may be transmitted wirelessly to the drive devices 31 to 36.

[0029] <Device Configuration> ≪Basic Configuration≫ FIG. 4 is a diagram showing the basic configuration of the main drive device 3 and the control device 4. Each of the drive devices 31 to 36 shown in FIG. 3 executes the same processing for the corresponding switching element among the switching elements Q1 to Q6. Therefore, in order to avoid complicating the drawing, in each of the following figures, only one of the six switching elements Q1 to Q6, which is the switching element Q, and the drive device 30 that drives the switching element Q (the drive device corresponding to the switching element Q among the drive devices 31 to 36) are typically shown.

[0030] The switching element Q is a power semiconductor element. The switching element Q is a power MOSFET in this example and includes a drain D, a source S, and a gate G (control electrode). The switching element Q may be an IGBT, a MESFET, or a bipolar power transistor as described above.

[0031] The control device 4 generates a drive signal Vin for controlling the switching operation of the switching element Q. The control device 4 generates the drive signal Vin by, for example, PWM (Pulse Width Modulation) control based on the comparison between a triangular wave carrier signal and a voltage command value. The control device 4 may generate the drive signal Vin using another method such as the space vector method instead of the triangular wave carrier signal. The control device 4 outputs the generated drive signal Vin to the drive device 30.

[0032] The drive device 30 is connected to the power supply voltage Vcc and the reference potential (ground GND in FIG. 4). However, the power supply voltage Vcc and the reference potential are different between the drive devices 31, 33, 35 that drive the upper arm and the drive devices 32, 34, 36 that drive the lower arm. The drive device 30 includes a drive unit 301, an adjustment unit 302, and terminals T1 to T3. The terminal T1 is electrically connected to the control device 4. Since the reference potential may be different between the drive devices 31, 33, 35 that drive the upper arm and the control device 4, an interface (such as a level shift circuit or an isolator) (not shown) is provided between each terminal T1 of the drive devices 31, 33, 35 and the control device 4. The terminal T2 is connected to the control device 4 (or an external device not shown). The terminal T3 is electrically connected to the switching element Q.

[0033] The adjustment unit 302 adjusts the driving ability of the switching element Q by the drive unit 301. The driving ability of the switching element Q by the drive unit 301 determines the switching speed of the switching element Q. The higher the driving ability of the switching element Q by the drive unit 301, the faster the switching speed of the switching element Q.

[0034] More specifically, the adjustment unit 302 receives an adjustment signal Vref from the control device 4 (or an external device) via the terminal T2. The adjustment unit 302 determines a target driving ability, which is a target regarding the adjustment of the driving ability of the drive unit 301, based on the adjustment signal Vref. Then, the adjustment unit 302 generates a driving ability signal Vcap for adjusting the driving ability of the switching element Q by the drive unit 301 based on the target driving ability, and outputs the generated driving ability signal Vcap to the drive unit 301.

[0035] The driving unit 301 receives a driving signal Vin from the control device 4 via the terminal T1 and also receives a driving ability signal Vcap from the adjustment unit 302. The driving unit 301 generates a gate signal Sg based on the driving signal Vin and the driving ability signal Vcap. More specifically, the driving unit 301 is configured such that the driving ability of the switching element Q is adjusted according to the driving ability signal Vcap, and the gate signal Sg is generated from the driving signal Vin according to the adjusted driving ability. The driving unit 301 outputs the generated gate signal Sg to the gate G of the switching element Q via the terminal T3. Thereby, the waveform (gate waveform) of the gate signal Sg applied to the gate G of the switching element Q can be changed according to the driving ability signal Vcap. Note that the gate signal Sg corresponds to the "adjusted driving signal" according to the present disclosure.

[0036] <<Configuration of driving unit>> Three typical configuration examples of the driving unit 301 will be described. However, the configuration of the driving unit 301 is not limited to these as long as the driving ability (switching speed) of the switching element Q can be adjusted.

[0037] FIG. 5 is a diagram showing a first example of the configuration of the driving unit. The driving unit 301A has a variable gate resistance included in the driving unit 301. The driving unit 301A includes a control circuit 51 and a resistance adjustment circuit 52.

[0038] The control circuit 51 generates the gate signal Sg by driving the resistance adjustment circuit 52 based on the driving signal Vin and the driving ability signal Vcap. The resistance adjustment circuit 52 includes, for example, a plurality of series circuits. Each of the plurality of series circuits includes a resistance element 521 and a switch 522 connected in series with each other. Each switch 522 is controlled to be turned on and off in response to a control signal from the control circuit 51. The control circuit 51 selects a resistance element to be controlled (which resistance element to connect and which to cut off) among the plurality of resistance elements 521 included in the resistance adjustment circuit 52 based on the driving ability signal Vcap, and switches the on / off of the switch corresponding to the selected resistance element. Thereby, the gate resistance of the switching element Q can be adjusted to a desired value.

[0039] FIG. 6 is a diagram showing a configuration example of the resistance adjustment circuit 52 shown in FIG. 5. The resistance adjustment circuit 52 includes a plurality (eight in this example) of P-channel MOSFETs 610 to 617 connected in parallel to each other, and a plurality (eight in this example) of N-channel MOSFETs 620 to 627 connected in parallel to each other.

[0040] The eight P-channel MOSFETs 610 to 617 have different gate widths (more specifically, gate widths that increase by a factor of two between Wp and 128Wp). The same applies to the eight N-channel MOSFETs 620 to 627. Each of the P-channel MOSFETs 610 to 617 and the N-channel MOSFETs 620 to 627 is turned on and off in response to signals (Hp[0] to Hp[7], Hn[0] to Hn[7]) from the control circuit 51. The common drain of the P-channel MOSFETs 610 to 617 and the common drain of the N-channel MOSFETs 620 to 627 are connected to the gate of the switching element Q. By adopting such a circuit configuration, the gate resistance of the switching element Q can be adjusted stepwise (256 steps in this example).

[0041] FIG. 7 is a diagram showing a second example of the configuration of the drive unit. The drive unit 301B is configured to be variable in the gate current of the switching element Q. The drive unit 301B includes a control circuit 53 and a current adjustment circuit 54.

[0042] The current adjustment circuit 54 includes, for example, a switch 541 connected to the gate of the switching element Q and an operational amplifier 542. The operational amplifier 542 changes the current (gate current) flowing through the switch 541 so as to follow the drive ability signal Vcap given from the adjustment unit 302. The control circuit 53 turns on and off the current flowing through the switch 541 by switching the switch 541 in response to the drive signal Vin.

[0043] FIG. 8 is a diagram showing a configuration example of the current adjustment circuit 54 shown in FIG. 7. The current adjustment circuit 54 includes a current mirror circuit 63, an error amplification circuit 64, and a switch 65.

[0044] The current mirror circuit 63 includes a pair of transistors (in this example, P-channel MOSFETs) 631 and 632 with a transistor size ratio of 1:x (for example, x = 100). The gates of the transistors 631 and 632 are connected to each other. The sources of the transistors 631 and 632 are connected in parallel to the power supply voltage Vcc. The drain of the transistor 631 is connected to the common gate of the transistors 631 and 632. The current mirror circuit 63 causes a current Ib proportional to the current Ia flowing through the input-side transistor 631 to flow through the output-side transistor 632.

[0045] The error amplification circuit 64 includes a transistor (in this example, an N-channel MOSFET) 641 for changing the magnitude of the current Ia flowing through the input-side transistor 631, a resistor 642 for generating a voltage Va corresponding to the current Ia, and an operational amplifier 643. The transistor 641 (drain and source) and the resistor 642 are connected in series between the drain of the transistor 631 of the current mirror circuit 63 and the ground GND. The non-inverting input terminal of the operational amplifier 643 is connected to a node that receives the drive ability signal Vcap from the adjustment unit 302. The inverting input terminal of the operational amplifier 643 is connected to the source of the transistor 641. The error amplification circuit 64 detects the current Ia flowing into the input side of the current mirror circuit 63 and generates a voltage Va corresponding to the current Ia. The error amplification circuit 64 changes the current Ia so that the voltage Va follows the drive ability signal Vcap.

[0046] The switch 65 is a transistor (an N-channel MOSFET in this example) for on / off controlling the gate current of the switching element Q. The gate of the switch 65 is connected to the node that receives the drive signal Vin from the control device 4. The drain of the switch 65 is connected to the drain of the transistor 632 on the output side of the current mirror circuit 63. The source of the switch 65 is connected to the gate of the switching element Q. By adopting such a circuit configuration, the gate current of the switching element Q (the current Ib on the output side of the current mirror circuit 63) can be adjusted according to the drive ability signal Vcap.

[0047] Figure 9 is a diagram showing a third example of the configuration of the drive unit. The drive unit 301C is configured to be variable in the gate voltage of the switching element Q. The drive unit 301C includes a voltage adjustment circuit 55 and a drive circuit 56. The drive circuit 56 includes, for example, an NPN bipolar transistor 561 and a PNP bipolar transistor 562 connected in series between the power supply voltage Vcc and the ground GND. The voltage adjustment circuit 55 includes a voltage amplifier 551 (for example, an operational amplifier circuit). The amplification factor of the voltage amplifier 551 is adjusted by the drive ability signal Vcap. The common gate of the bipolar transistors 561 and 562 receives the drive signal Vin amplified by the voltage amplifier 551. The common output node of the bipolar transistors 561 and 562 is connected to the gate of the switching element Q. Thereby, the gate voltage of the switching element Q can be adjusted according to the drive ability signal Vcap.

[0048] <Drive ability signal> Figure 10 is a diagram showing an example of the relationship between the adjustment signal Vref and the drive ability signal Vcap. Figure 11 is a diagram showing another example of the relationship between the adjustment signal Vref and the drive ability signal Vcap. The horizontal axis represents the adjustment signal Vref (voltage value). The vertical axis represents the drive ability signal Vcap (voltage value).

[0049] The higher the adjustment signal Vref is, the higher the driving ability signal Vcap is. The driving ability signal Vcap may increase linearly as shown in FIG. 10 or may increase stepwise as shown in FIG. 11 as the adjustment signal Vref increases. Although not shown, the driving ability signal Vcap may increase non-linearly (curvilinearly) as the adjustment signal Vref increases.

[0050] <Operation of the driving device> FIG. 12 is a time chart for explaining the operation of the driving device 30. The horizontal axis represents the elapsed time. The vertical axis represents, in order from the top, the adjustment signal Vref, the driving ability signal Vcap, the driving signal Vin, and the gate signal Sg. The same applies to other examples (see FIGS. 20 and 21) described later.

[0051] The adjustment signal Vref at the initial time t10 is 0V. The adjustment signal Vref rises at time t11 and further rises at time t14. The driving signal Vin repeats periodic (cyclic) changes (rise and fall) between a high level (H) and a low level (L).

[0052] In the example shown in FIG. 12, the rising edge of the driving signal Vin is the generation (update) timing of the driving ability signal Vcap. Therefore, the driving ability signal Vcap is generated (updated) based on the adjustment signal Vref at the times t12, t15, and t17 when the driving signal Vin rises.

[0053] When the switching element Q is turned on, the voltage applied between the drain D (positive electrode) and the source S (negative electrode) of the switching element Q decreases, and the current flowing between the drain D and the source S increases. When the switching element Q is turned off, the voltage applied between the drain D and the source S increases, and the current flowing between the drain D and the source S decreases. A waveform indicating at least one of these changes in voltage (the voltage between the drain D and the source S) and current (the current flowing between the drain D and the source S) during switching is called a "switching waveform".

[0054] Generally, switching loss and conduction loss occur with the switching operation of a switching element. The switching loss depends on the area of the region where the voltage waveform and the current waveform overlap. Therefore, the switching loss decreases when the switching waveform shows a steep change, while it increases when the switching waveform shows a gentle change. Also, high-frequency switching noise is generated with the switching operation of the switching element and is superimposed on the switching waveform. The switching noise increases when the switching waveform shows a steep change, while it is reduced when the switching waveform shows a gentle change. Thus, regarding whether the change in the switching waveform is steep or gentle, there is a trade-off relationship between the switching loss and the switching noise.

[0055] When the driving ability signal Vcap is set so that the driving ability of the switching element Q by the driving unit 301 increases, the switching speed of the switching element Q increases and the switching waveform shows a steep change. Therefore, while the switching noise increases, the switching loss decreases (loss reduction mode). Thereby, the energy-saving performance of the power conversion device 1 can be improved and the energy consumption can be reduced.

[0056] Conversely, when the driving ability signal Vcap is set so that the driving ability of the switching element Q by the driving unit 301 decreases, the switching speed of the switching element Q decreases and the switching waveform shows a gentle change. Therefore, while the switching loss increases, the switching noise decreases (noise reduction mode). Thereby, it becomes easier to make the power conversion device 1 conform to the EMC (Electromagnetic Compatibility) standard. Also, since EMC countermeasure components may become unnecessary, there is a possibility of reducing the component cost.

[0057] <Processing Flow> FIG. 13 is a flowchart showing an example of a processing procedure for generating a driving ability signal Vcap in Embodiment 1. The processing shown in this flowchart is executed, for example, at each predetermined control cycle. Each step may be realized by hardware (an electric circuit) arranged in the driving device 30 (and the control device 4), or may be realized by software processing by the driving device 30 (and the control device 4). The same applies to the processing shown in other flowcharts described later. Hereinafter, steps are abbreviated as S.

[0058] In S101, the driving device 30 determines whether a condition (hereinafter also referred to as a "trigger condition") that triggers the generation (or update) of the driving ability signal Vcap is satisfied. Various trigger conditions will be described in Embodiment 2.

[0059] If the trigger condition is not satisfied (NO in S101), the driving device 30 ends the process without executing the subsequent processes. If the trigger condition is satisfied (YES in S101), the driving device 30 determines whether it has received the adjustment signal Vref (S102).

[0060] If it has not received the adjustment signal Vref (NO in S102), the driving device 30 ends the process without executing the subsequent processes. If it has received the adjustment signal Vref (YES in S102), the driving device 30 determines which voltage range of the input voltage range VR the voltage value of the adjustment signal Vref belongs to (S103). The input voltage range VR is a voltage range determined based on the input / output characteristics of the driving device 30, and is typically the operating voltage range described in the specification. In this example, the input voltage range VR is divided into three: a low voltage range, a medium voltage range, and a high voltage range.

[0061] When the adjustment signal Vref belongs to the low voltage range, the driving device 30 sets the driving ability signal Vcap to the first voltage value V1 (S104). Thereby, a "noise reduction mode" in which noise reduction is prioritized over loss reduction is realized.

[0062] When the adjustment signal Vref belongs to the medium voltage range, the driving device 30 sets the driving ability signal Vcap to a second voltage value V2 higher than the first voltage value V1 (S105). V2 is, for example, an intermediate voltage value between V1 and V3 (V2 = (V1 + V3) / 2). Thereby, a "balance mode" in which noise reduction and loss reduction are weighted equally is realized.

[0063] When the adjustment signal Vref belongs to the high voltage range, the driving device 30 sets the driving ability signal Vcap to a third voltage value V3 even higher than the second voltage value V2 (S106). Thereby, a "loss reduction mode" in which loss reduction is prioritized over noise reduction is realized.

[0064] According to the processing procedure shown in FIG. 13, it becomes possible to operate the driving device 30 according to an appropriate mode selected according to the conditions under which the power conversion device 1 is used. For example, when the power conversion device 1 is driven with a small current, since the noise itself is small, the loss reduction mode can be selected to improve the energy saving performance. Conversely, when the power conversion device 1 is driven with a large current, since large noise can be generated, the noise reduction mode can be selected to reduce the switching noise.

[0065] Alternatively, when the power conversion device 1 is installed in a quiet place, or when the power conversion device 1 is driven during a quiet time period, etc., the noise reduction mode can be selected. Conversely, when the power conversion device 1 is installed in a noisy place, or when the power conversion device 1 is driven during a noisy time period, etc., the loss reduction mode can be selected. The balance mode may be selected in a moderate noise environment.

[0066] The user of the power conversion device 1 may manually set which mode is selected. Alternatively, the mode may be set by a wireless command from a remote location (for example, a command from a server that manages the power conversion device 1). The mode may be set according to the usage conditions of the power conversion device 1 detected by various sensors (for example, a noise sensor). The mode may be preset at the time of shipment or installation of the power conversion device 1 according to the usage conditions (installation environment) of the power conversion device 1.

[0067] As described above, regarding whether the change in the switching waveform of the switching element Q is steep or gentle, there is a trade-off relationship between switching loss and switching noise. In Embodiment 1, the switching speed of the switching element Q by the driving device 30 is adjusted according to the adjustment signal Vref. Thereby, it is possible to switch whether to prioritize reduction of switching loss, reduction of switching noise, or reduction of both switching loss and switching noise to a certain extent according to the usage conditions of the switching element Q. Therefore, according to Embodiment 1, it is possible to cause the switching element Q to perform an operation suitable for the conditions under which the switching element Q is used.

[0068] In this example, for ease of understanding, it was described that the driving ability signal Vcap is set in three levels. However, the driving ability signal Vcap may be set in two levels or may be set in multiple levels of four or more levels. By sufficiently increasing the number of levels (for example, setting to 256 levels as described in FIG. 6), the driving ability signal Vcap can be set substantially steplessly. Thereby, a "custom mode" is realized in which it is possible to freely set which of noise reduction and loss reduction is prioritized and to what extent.

[0069] Embodiment 2. In FIG. 4 of Embodiment 1, the basic configuration of the driving device 30 was described. In Embodiment 2, various configuration examples (modification examples) that can be adopted as the driving device will be described.

[0070] <Configuration of the driving device> FIG. 14 is a diagram showing a first example of the configuration of the driving device in Embodiment 2. The driving device 30A is different from the driving device 30 (see FIG. 4) having the basic configuration in that it further includes a timer unit 303.

[0071] The timer unit 303 outputs a timer signal TMR to the adjustment unit 302. The timer signal TMR may be a signal that is activated when a preset time arrives, or may be a signal that is activated each time a specified time elapses since the previous activation. The adjustment unit 302 generates (updates) a driving ability signal Vcap based on the adjustment signal Vref in response to the timer signal TMR. As a result, the driving ability signal Vcap is generated in synchronization with the timer signal TMR. As a result, it becomes possible to generate the driving ability signal Vcap intermittently or to generate the driving ability signal Vcap periodically (cyclically).

[0072] In the configuration example shown in FIG. 12, the adjustment signal Vref is supplied from the control device 4. However, the supply source of the adjustment signal Vref is not particularly limited, and it may be an external device (not shown) other than the control device 4. The same applies to other examples described later.

[0073] FIG. 15 is a diagram showing a second example of the configuration of the driving device in Embodiment 2. The driving device 30B is different from the driving device 30 (see FIG. 4) having the basic configuration in that the adjustment unit 302 receives the driving signal Vin from the control device 4.

[0074] The adjustment unit 302 generates (updates) a driving ability signal Vcap based on the adjustment signal Vref in response to the driving signal Vin. As a result, the driving ability signal Vcap is generated in synchronization with the driving signal Vin.

[0075] FIG. 16 is a diagram showing a third example of the configuration of the driving device in Embodiment 2. The power conversion device 1 shown in FIG. 16 further includes a clock circuit 7. The driving device 30C is different from the driving device 30 (see FIG. 4) having the basic configuration in that the adjustment unit 302 receives the clock signal CLK from the clock circuit 7.

[0076] The adjustment unit 302 generates (updates) a driving ability signal Vcap based on an adjustment signal Vref in response to a clock signal CLK. Thereby, the driving ability signal Vcap is generated in synchronization with the clock signal CLK.

[0077] Note that the clock signal CLK is an example of the "periodic signal" according to the present disclosure. The clock signal CLK may be supplied to the adjustment unit 302 via the control device 4. The "periodic signal" according to the present disclosure is not particularly limited as long as it is a signal that is supplied from outside the driving device 30C to the driving device 30C and changes periodically, and may be, for example, a signal generated by an oscillation circuit.

[0078] FIG. 17 is a diagram showing a fourth example of the configuration of the driving device in the second embodiment. The control device 4 shown in FIG. 17 outputs an enable signal EN for switching between enabling and disabling the driving device 30D to the driving device 30D. The driving device 30D is different from the driving device 30 (see FIG. 4) having the basic configuration in that the adjustment unit 302 receives the enable signal EN from the control device 4. The enable signal EN may be supplied to the adjustment unit 302 from an external device (not shown) other than the control device 4.

[0079] The adjustment unit 302 generates (updates) a driving ability signal Vcap based on an adjustment signal Vref in response to the enable signal EN, particularly at the timing of switching from disable to enable. Thereby, the driving ability signal Vcap is generated in synchronization with the enable signal EN.

[0080] FIG. 18 is a diagram showing a fifth example of the configuration of the driving device in Embodiment 2. The driving device 30E is different from the driving device 30 (see FIG. 4) having the basic configuration in that it further includes a voltage detection unit 304. The voltage detection unit 304 is, for example, a power-on reset IC (Integrated Circuit), and detects the power supply voltage Vcc (that is, power-on to the driving device 30E). When the driving device 30E is powered on, the voltage detection unit 304 outputs a power-on reset signal POR to the adjustment unit 302.

[0081] In response to the power-on reset signal POR, the adjustment unit 302 generates (updates) a driving ability signal Vcap based on the adjustment signal Vref. As a result, the driving ability signal Vcap is generated in synchronization with the power-on reset signal POR.

[0082] FIG. 19 is a diagram showing a sixth example of the configuration of the driving device in Embodiment 2. The driving device 30F is different from the driving device 30 (see FIG. 4) having the basic configuration in that the adjustment unit 302 receives a driving signal Vin from the control device 4 and the adjustment unit 302 includes a delay filter 305.

[0083] In response to the driving signal Vin, the adjustment unit 302 generates a driving ability signal Vcap based on the adjustment signal Vref. At this time, a delay is given to the driving signal Vin by the delay filter 305. The delay time td (see FIG. 21) is determined by the time constant of the delay filter 305 and is preferably a time length in the range from the order of 1 digit nanosecond to the order of 2 digit nanoseconds. As a result, the driving ability signal Vcap is generated (updated) in synchronization with the driving signal Vin.

[0084] The order of 1 digit nanosecond means a time range of 1 nanosecond or more and less than 10 nanoseconds. The order of 2 digit nanoseconds means a time range of 10 nanoseconds or more and less than 100 nanoseconds. From the order of 1 digit nanosecond to the order of 2 digit nanoseconds typically means a time length from several nanoseconds to several tens of nanoseconds. The delay filter 305 corresponds to the "delay circuit" according to the present disclosure.

[0085] <Generation Timing of Driving Ability Signal> In FIG. 12 of Embodiment 1, a first example in which the rising edge of the drive signal Vin is the generation (update) timing of the driving ability signal Vcap was described. In FIGS. 20 to 22, other examples of the generation timing of the driving ability signal Vcap will be described.

[0086] FIG. 20 is a time chart for explaining a second example of the generation timing of the driving ability signal Vcap. Similar to FIG. 12, it is assumed that the adjustment signal Vref, which was 0V at the initial time t10, rises at time t21 and further rises at time t24.

[0087] In FIG. 20, the falling edge of the drive signal Vin is the generation timing of the driving ability signal Vcap. Therefore, at times t23, t26, and 28 when the drive signal Vin falls, the driving ability signal Vcap is generated (updated) from the adjustment signal Vref.

[0088] FIG. 21 is a time chart for explaining a third example of the generation timing of the driving ability signal Vcap. As shown in FIG. 21, the time when a delay time td has elapsed from the rising edge of the drive signal Vin may be the generation (update) timing of the driving ability signal Vcap. Although not shown, the time when a delay time td has elapsed from the falling edge of the drive signal Vin may be the generation timing of the driving ability signal Vcap. As described with reference to FIG. 19, the delay time td is set based on, for example, the time constant of the delay filter 305.

[0089] FIG. 22 is a time chart for explaining a fourth example of the generation timing of the driving ability signal Vcap. The horizontal axis represents the elapsed time. The vertical axis represents, in order from the top, the adjustment signal Vref, the driving ability signal Vcap, the enable signal EN, the drive signal Vin, and the gate signal Sg.

[0090] In FIGS. 12, 20, and 21, an example where the generation timing of the driving ability signal Vcap is associated with the driving signal Vin was described. However, as shown in FIG. 22, the generation timing of the driving ability signal Vcap may be associated with the enable signal EN. In this example, the rising edges of the enable signal EN (see times t402 and t409) are the generation timing of the driving ability signal Vcap. Although not shown, the falling edge of the enable signal EN may be the generation timing of the driving ability signal Vcap. Also, the time when a delay time td has elapsed from the rising or falling edge of the enable signal EN may be the generation timing of the driving ability signal Vcap.

[0091] The signal associated with the generation timing of the driving ability signal Vcap is not limited to the driving signal Vin or the enable signal EN. Any signal can be used as the associated signal. The associated signal may be a timer signal TMR (see FIG. 14), a clock signal CLK (see FIG. 16), or a power-on reset signal POR (see FIG. 18). The generation timing of the driving ability signal Vcap may be associated with either the rising / falling edge of these signals, or a delay time td may be provided with respect to the rising / falling edge of these signals.

[0092] As described above, in Embodiment 2, similar to Embodiment 1, the switching element Q can be made to execute an operation suitable for the conditions under which the switching element Q is used. In addition, according to Embodiment 2, the driving ability signal Vcap is generated in synchronization with "trigger signals" such as the driving signal Vin, the clock signal CLK (periodic signal), the enable signal EN, and the power-on reset signal POR (power-on). Alternatively, the generation timing of the driving ability signal Vcap is set to the rising edge of the "trigger signal", the falling edge of the "trigger signal", or the change timing of the delayed "trigger signal". Thereby, it becomes possible to switch the switching speed of the switching element Q at a desired timing.

[0093] Embodiment 3 There may be a case where the adjustment signal Vref is not supplied to the adjustment unit 302, or the adjustment signal Vref supplied to the adjustment unit 302 is outside the range of the predetermined input voltage range VR. In Embodiment 3, it will be described what kind of drive ability signal Vcap the drive device 30 can generate (update) in such a case.

[0094] <Generation process of drive ability signal> FIG. 23 is a flowchart showing a second example of the processing procedure of the generation process of the drive ability signal Vcap in Embodiment 3. The processing of S201 regarding the trigger condition is the same as the processing of S101 in Embodiment 1 (see FIG. 13).

[0095] In S202, the drive device 30 determines whether it has received the adjustment signal Vref. If the drive device 30 has received the adjustment signal Vref (YES in S202), the drive device 30 determines whether the voltage value of the adjustment signal Vref is within the input voltage range VR (S203). If the voltage value of the adjustment signal Vref is within the input voltage range VR (YES in S203), the drive device 30 sets the drive ability signal Vcap to a voltage value corresponding to the voltage value of the adjustment signal Vref (S204). Since this processing is the same as the processing of S103 to S106 in Embodiment 1, the description will not be repeated.

[0096] If the adjustment signal Vref has not been received in S202 (NO in S202) or the voltage value of the adjustment signal Vref is outside the input voltage range VR in S203 (NO in S203), the drive device 30 proceeds to S205 and sets the drive ability signal Vcap to V1, which is the lowest among V1 to V3. Thereby, the noise reduction mode is realized.

[0097] Thus, in the second example, when the adjustment signal Vref is not received or the voltage value of the adjustment signal Vref is outside the input voltage range VR, the driving ability signal Vcap is set to V1, which is the lowest among V1 to V3. In other words, the default value of the driving ability signal Vcap is set to V1. Thereby, even in a situation where the driving device 30 cannot receive an appropriate adjustment signal Vref, the switching noise of the switching element Q can be surely reduced.

[0098] FIG. 24 is a flowchart showing a third example of the processing procedure of the generation process of the driving ability signal Vcap in Embodiment 3. Since the processes of S301 to S304 are the same as the processes of S201 to S204 in the second example, the description will not be repeated.

[0099] When the adjustment signal Vref is not received at S302 (NO at S302) or the voltage value of the adjustment signal Vref is outside the input voltage range VR at S303 (NO at S303), the driving device 30 advances the process to S305 and sets the driving ability signal Vcap to V2. Thereby, the balance mode is realized.

[0100] Thus, in the third example, when the adjustment signal Vref is not received or the voltage value of the adjustment signal Vref is outside the input voltage range VR, the driving ability signal Vcap is set to V2, which is the intermediate value (typical value) among V1 to V3. In other words, the default value of the driving ability signal Vcap is set to V2. Thereby, even in a situation where the driving device 30 cannot receive an appropriate adjustment signal Vref, it is possible to achieve both a reduction in a certain degree of switching loss of the switching element Q and a reduction in a certain degree of switching noise.

[0101] FIG. 25 is a flowchart showing a fourth example of the processing procedure of the generation process of the driving ability signal Vcap in Embodiment 3. Since the processes of S401 to S404 are the same as the processes of S201 to S204 in the second example, the description will not be repeated.

[0102] When the adjustment signal Vref is not received in S402 (NO in S402) or when the voltage value of the adjustment signal Vref is outside the input voltage range VR in S403 (NO in S403), the drive device 30 proceeds with the process to S405 and sets the drive capability signal Vcap to V3. Thereby, the loss reduction mode is realized.

[0103] As described above, in the third example, when the adjustment signal Vref is not received or when the voltage value of the adjustment signal Vref is outside the input voltage range VR, the drive capability signal Vcap is set to V3, which is the highest among V1 to V3. In other words, the default value of the drive capability signal Vcap is set to V3. Thereby, even in a situation where the drive device 30 cannot receive an appropriate adjustment signal Vref, the switching loss of the switching element Q can be surely reduced.

[0104] FIG. 26 is a flowchart showing a fourth example of the processing procedure for generating the drive capability signal Vcap in the third embodiment. The processes of S501 to S504 are the same as the processes of S201 to S204 in the second example, and thus the description will not be repeated.

[0105] After setting the drive capability signal Vcap to a voltage value corresponding to the adjustment signal Vref in S504, the drive device 30 proceeds with the process to S505. In S505, the drive device 30 stores the voltage value of the drive capability signal Vcap set in S504 as the previous value.

[0106] When the adjustment signal Vref is not received in S502 (NO in S502) or when the voltage value of the adjustment signal Vref is outside the input voltage range VR in S503 (NO in S503), the drive device 30 proceeds with the process to S506 and sets the drive capability signal Vcap to the stored previous value.

[0107] Thus, in the fourth example, when the adjustment signal Vref is not received or when the voltage value of the adjustment signal Vref is outside the input voltage range VR, the drive ability signal Vcap is set to the previous value. The previous value of the drive ability signal Vcap is likely to be set to a voltage value suitable for the usage conditions of the switching element Q (or the power conversion device 1 incorporating the switching element Q). Therefore, even in a situation where the drive device 30 cannot receive an appropriate adjustment signal Vref, the switching element Q can be made to perform an operation suitable for the usage conditions of the switching element Q.

[0108] As described above, in Embodiment 3, similar to Embodiment 1, the switching element Q can be made to perform an operation suitable for the conditions under which it is used. In addition, in Embodiment 3, even when the drive device 30 does not receive the adjustment signal Vref or when the voltage value of the adjustment signal Vref is outside the input voltage range VR, the drive device 30 generates the drive ability signal Vcap according to a predetermined rule. Thereby, even if for some reason the control device 4 cannot appropriately adjust the adjustment signal Vref, it becomes possible to prioritize noise reduction or loss reduction according to the preset. Also, even in a situation where the drive device 30 cannot receive an appropriate adjustment signal Vref, the switching element Q can be made to perform an operation that is likely to be suitable for the conditions under which it is used.

[0109] It should be considered that all the disclosed embodiments are illustrative and not restrictive in any way. The scope of this application is indicated by the claims rather than the description of the above embodiments, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Description of Reference Numerals

[0110] 1 Power conversion device, 2 Main conversion device, 201 Semiconductor module, 21 Rectifier circuit, 211 - 216 Diodes, 22 Inverter circuit, 22U, 22V, 22W Arms, 3 Main drive device, 30, 30A - 30F, 31 - 36 Drive devices, 301, 301A - 301C Drive parts, 302 Adjustment part, 303 Timer part, 304 Voltage detection part, 305 Delay filter, 4 Control device, 41 Processor, 42 Memory, 43 Receiver, 44 Display, 51, 53 Control circuits, 52 Resistance adjustment circuit, 521 Resistance element, 522 Switch, 54 Current adjustment circuit, 541 Switch, 542 Operational amplifier, 55 Voltage adjustment circuit, 551 Voltage amplifier, 56 Drive circuit, 561, 562 Bipolar transistors, 610 - 617, 620 - 627 MOSFETs, 63 Current mirror circuit, 631, 632 Transistors, 64 Error amplification circuit, 641 Transistor, 642 Resistance, 643 Operational amplifier, 65 Switch, 7 Clock circuit, 8 Power supply, 81 AC power supply, 9 Load, 91 Motor, 100 Power conversion system, D1 - D6 Freewheel diodes, EN Enable signal, NL, PL DC power lines, Q, Q1 - Q6 Switching elements, T1, T2, T3 Terminals, Ta, Tb, Tc AC input terminals, Tu, Tv, Tw AC output terminals.

Claims

1. A driving device for a semiconductor switching element having a control electrode, comprising a driving unit configured to adjust the driving ability of the semiconductor switching element and drive the semiconductor switching element according to a driving signal for controlling the switching operation of the semiconductor switching element; and an adjusting unit configured to adjust the driving ability of the semiconductor switching element by the driving unit so that the switching speed of the semiconductor switching element changes. When the trigger signal changes, the adjusting unit generates a driving ability signal for adjusting the driving ability of the semiconductor switching element by the driving unit based on an adjustment signal different from the driving signal, and outputs the generated driving ability signal to the driving unit. The driving unit adjusts the driving signal according to the driving ability signal and outputs the adjusted driving signal to the control electrode. A driving device for a semiconductor switching element.

2. The driving device for a semiconductor switching element according to claim 1, wherein the adjusting unit outputs the driving ability signal to the driving unit at at least one of the rising and falling edges of the trigger signal.

3. A driving device for a semiconductor switching element having a control electrode, comprising a driving unit configured to adjust the driving ability of the semiconductor switching element and drive the semiconductor switching element according to a driving signal for controlling the switching operation of the semiconductor switching element; and an adjusting unit configured to adjust the driving ability of the semiconductor switching element by the driving unit so that the switching speed of the semiconductor switching element changes. When a delay time has elapsed after the trigger signal changes, the adjusting unit generates a driving ability signal for adjusting the driving ability of the semiconductor switching element by the driving unit based on an adjustment signal different from the driving signal, and outputs the generated driving ability signal to the driving unit. The driving unit is a driving device for a semiconductor switching element that adjusts the driving signal according to the driving ability signal and outputs the adjusted driving signal to the control electrode.

4. The driving device for a semiconductor switching element according to claim 3, further comprising a delay circuit that delays the trigger signal by the delay time.

5. The driving device for a semiconductor switching element according to claim 3, wherein the delay time is set by the adjustment unit.

6. The driving device for a semiconductor switching element according to claim 3, wherein the delay time is a time length from the order of one-digit nanoseconds to the order of two-digit nanoseconds.

7. The driving device further comprises a timer that outputs a timer signal, The driving device for a semiconductor switching element according to claim 2, wherein the trigger signal is the timer signal.

8. The driving device for a semiconductor switching element according to any one of claims 1 to 6, wherein the trigger signal is the driving signal.

9. The driving device further comprises an external terminal that receives a periodic signal from outside the driving device, The driving device for a semiconductor switching element according to any one of claims 1 to 6, wherein the trigger signal is the periodic signal.

10. The driving device further comprises an enable terminal that receives an enable signal for switching between enabling and disabling the driving device, The driving device for a semiconductor switching element according to any one of claims 1 to 6, wherein the trigger signal is the enable signal.

11. The driving device for a semiconductor switching element according to any one of claims 1 to 6, wherein the trigger signal is the power supply voltage of the driving device.

12. The adjustment signal is a voltage signal represented by a voltage value, The driving device for a semiconductor switching element according to any one of claims 1 to 6, wherein the adjusting unit generates the driving ability signal indicating a predetermined value when the adjusting signal is not received or when the adjusting signal is outside the input voltage range.

13. The input voltage range includes a first voltage range, a second voltage range higher than the first voltage range, and a third voltage range even higher than the second voltage range. The driving device for a semiconductor switching element according to claim 12, wherein the adjusting unit sets the predetermined value within the first voltage range when the adjusting signal is not received or when the adjusting signal is outside the input voltage range.

14. The input voltage range includes a first voltage range, a second voltage range higher than the first voltage range, and a third voltage range even higher than the second voltage range. The driving device for a semiconductor switching element according to claim 12, wherein the adjusting unit sets the predetermined value within the second voltage range when the adjusting signal is not received or when the adjusting signal is outside the input voltage range.

15. The input voltage range includes a first voltage range, a second voltage range higher than the first voltage range, and a third voltage range even higher than the second voltage range. The driving device for a semiconductor switching element according to claim 12, wherein the adjusting unit sets the predetermined value within the third voltage range when the adjusting signal is not received or when the adjusting signal is outside the input voltage range.

16. The driving device for a semiconductor switching element according to claim 12, wherein the adjusting unit sets the predetermined value to a lower voltage value when the adjusting signal is not received or when the adjusting signal is outside the input voltage range, compared to when the adjusting signal is within the input voltage range.

17. When the adjustment unit does not receive the adjustment signal or the adjustment signal is outside the input voltage range, the adjustment unit sets the predetermined value to a higher voltage value than when the adjustment signal is within the input voltage range. The driving device for a semiconductor switching element according to claim 12.

18. When the adjustment signal is within the input voltage range, the adjustment unit stores the voltage value of the adjustment signal as the previous value. When the adjustment unit does not receive the adjustment signal or the adjustment signal is outside the input voltage range, the adjustment unit sets the predetermined value to the previous value. The driving device for a semiconductor switching element according to claim 12.

Images