Imaging device, distance measuring device, and electronic device

Abstract

[Problem] To provide an image-capturing element, a ranging device, and an electronic appliance that make it possible to improve the resolution of a distance image, while suppressing the occurrence of electromagnetic noise. [Solution] An image-capturing element according to the present disclosure is provided with: a signal generator configured to generate a clock signal; a plurality of cascaded flip-flops; a circuit block configured to supply a first signal to individual clock terminals of the plurality of flip-flops in accordance with the clock signal and to supply a second signal to an input terminal of the flip-flop at the first stage among the plurality of flip-flops; and a pixel array including pixels configured to be driven with pulse signals supplied from different stages of the plurality of flip-flops.

Description

Technical Field

[0001] The present disclosure relates to an imaging device, a distance measuring device, and an electronic device.

Background Art

[0002] Distance measurement techniques using an indirect ToF (Time of Flight) method are known. In such a distance measurement system, a sensor that detects reflected light obtained by reflecting light irradiated from a light source at a predetermined phase and distributes the charge of the optical signal to different regions is used. When using a sensor of the indirect ToF method, it is possible to perform distance measurement based on signals distributed to each charge accumulation region according to the phase of the incident light. In distance measurement by the indirect ToF method, generally, a sensor in which a plurality of pixels are two-dimensionally arranged is used. In recent years, the number of pixels mounted on the sensor has been increasing in order to obtain a distance image with higher resolution.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a sensor of the indirect ToF method, in order to detect the charge corresponding to the incident light, a drive signal is supplied to each pixel. When increasing the number of pixels to which the drive signal is supplied, a drive signal with a larger current is required. When the total current of the drive signal increases, the electromagnetic noise generated at the time of detecting the incident light becomes large, and there is a risk that the requirements related to EMC (Electro-Magnetic Compatibility) cannot be satisfied.

[0005] Therefore, the present disclosure provides an imaging device, a distance measuring device, and an electronic device capable of improving the resolution of a distance image while suppressing the generation of electromagnetic noise.

Means for Solving the Problem

[0006] An image sensor according to an aspect of the present disclosure may include a signal generator configured to generate a clock signal, a plurality of flip-flops connected in series, and a circuit block configured to supply a first signal to each clock terminal of the plurality of flip-flops and a second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops in response to the clock signal, and a pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops.

[0007] The pixels in the pixel array may include a signal extraction unit configured to detect charges generated by photoelectric conversion when the pulse signal is supplied.

[0008] The pixels in the pixel array may include a plurality of the signal extraction units, and each of the signal extraction units may be configured to detect the charges generated at different timings.

[0009] The image sensor may further include a plurality of clock distribution circuits connected to any of the stages of the plurality of flip-flops on the input side and connected to the pixels in the pixel array via driving lines on the output side.

[0010] At least any one of the clock distribution circuits may be a clock tree type.

[0011] A pixel column or a pixel row in the pixel array may be configured to be driven by the pulse signal supplied from a common stage of the plurality of flip-flops.

[0012] The pulse signal may be supplied from different stages of the plurality of flip-flops depending on the region in the pixel array where the pixels are arranged.

[0013] It may further include a multiplexer configured to select the pulse signal supplied to the pixels in the pixel array.

[0014] The circuit block may be configured to output the first signal of a first frequency and output the second signal of a second frequency different from the first frequency.

[0015] The circuit block may be configured to output the first signal and the second signal synchronized with each other.

[0016] The circuit block may further include a frequency division circuit configured to generate the first signal based on the clock signal.

[0017] The circuit block may be configured to output the first signal of a first frequency equal to the clock frequency of the clock signal.

[0018] It may further include a control unit configured to output a control signal to the circuit block, and the circuit block may be configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the supplied control signal.

[0019] A distance measuring device according to an aspect of the present disclosure may include a signal generator configured to generate a clock signal, a plurality of flip-flops connected in series, a circuit block configured to supply a first signal to each clock terminal of the plurality of flip-flops in response to the clock signal and supply a second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops, a pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops, and a signal processing unit configured to generate a distance image based on charges generated by photoelectric conversion in the pixels of the pixel array.

[0020] An electronic device according to one aspect of the present disclosure may include a signal generator configured to generate a clock signal, a plurality of flip-flops connected in series, a circuit block configured to supply a first signal to each clock terminal of the plurality of flip-flops in response to the clock signal and supply a second signal to an input terminal of the first-stage flip-flop of the plurality of flip-flops, and a pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Embodiments for Carrying Out the Invention

[0022] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

[0023] The present disclosure suppresses the generation of electromagnetic noise in an image sensor (light receiving element) mounted in a distance measurement system (distance measurement device) that performs distance measurement by an indirect ToF method. The image sensor may be mounted in various electronic devices.

[0024] As an example of a distance measurement system, there is an in-vehicle system mounted on a vehicle and measuring the distance to an object outside the vehicle. Further, the distance measurement system may be applied to a gesture recognition system that measures the distance to an object such as a user's hand and recognizes the user's gesture based on the measurement result. For example, the operation of a car navigation system can be performed using the result of gesture recognition. However, the result of gesture recognition may be used for other purposes.

[0025] The block diagram of FIG. 1 shows an example of an image sensor (light receiving element) according to the present disclosure.

[0026] The imaging device 11 in FIG. 1 is, for example, a back-illuminated sensor and is mounted on an imaging device having a distance measurement function. However, the imaging device 11 may be a front-illuminated sensor.

[0027] The imaging device 11 has, for example, a pixel array unit 21 formed on a semiconductor substrate (not shown) and a peripheral circuit unit integrated on the same semiconductor substrate as the pixel array unit 21. The peripheral circuit unit includes, for example, a pixel driving unit 22, a column processing unit 23, a lead driving unit 24, and a system control unit 25.

[0028] The imaging device 11 may further include a signal processing unit 26 and a data storage unit 27. The signal processing unit 26 and the data storage unit 27 may be mounted on the same substrate as the imaging device 11 or on a substrate different from the imaging device 11.

[0029] In the pixel array unit 21, for example, unit pixels are arranged in an array. A unit pixel (hereinafter also referred to as a pixel) generates an electric charge corresponding to the amount of received light and outputs a signal corresponding to the electric charge. The pixels are arranged, for example, in two directions, the row direction and the column direction, within the pixel array. However, the pixels can take an arbitrary two-dimensional array within the pixel array unit 21. That is, the pixel array unit 21 has a plurality of pixels that photoelectrically convert incident light and output a signal corresponding to the electric charge obtained thereby.

[0030] Here, the row direction refers to the arrangement direction of the pixels in a pixel row (i.e., the horizontal direction). Also, the column direction refers to the arrangement direction of the pixels in a pixel column (i.e., the vertical direction). The row direction corresponds to the horizontal direction in the figure, and the column direction corresponds to the vertical direction in the figure.

[0031] In the pixel array unit 21, for the matrix-shaped pixel array, pixel driving lines 28 are wired along the row direction for each pixel row. Also, two vertical signal lines 29 are wired along the column direction for each pixel column. For example, the pixel driving line 28 transmits a driving signal for driving when reading a signal from the pixel. In FIG. 1, the pixel driving line 28 is shown as one signal line, but the number of signal lines is not limited to one. One end of the pixel driving line 28 is connected to the output end corresponding to each row of the pixel driving unit 22.

[0032] The pixel driving unit 22 is a circuit that drives some of the pixels in the pixel array unit 21 in a predetermined order. The combination of pixels driven by the pixel driving unit 22 each time and the order in which each combination of pixels is driven are called the driving pattern of the pixels. The pixel driving unit 22 according to the present disclosure suppresses the generated electromagnetic noise by reducing the number of pixels driven simultaneously in the pixel array unit 21. The pixel driving unit 22 includes, for example, a shift register or an address decoder. The pixel driving unit 22, together with the system control unit 25 that controls the pixel driving unit 22, forms a driving unit that controls the operation of each pixel in the pixel array unit 21. Details of the pixel driving unit according to the present disclosure will be described later.

[0033] In the image sensor used for distance measurement by the indirect ToF method, the accuracy of the driving timing depends on the number of elements connected to the same control line. In the pixel array of the image sensor used for distance measurement by the indirect ToF method, since the control line in the horizontal direction is long, there is a possibility that a delay occurs in the driving timing. For this reason, not only the control line in the horizontal direction but also other signal lines such as the vertical signal line 29 may be used to drive the pixels. In this case, a driving signal may be output to the vertical signal line 29 from a separately provided driving unit (for example, a read driving unit) different from the pixel driving unit 22.

[0034] The signal output from each pixel of the pixel row according to the drive control by the pixel drive unit 22 is input to the column processing unit 23 via the vertical signal line 29. The column processing unit 23 executes predetermined signal processing on the signal output from each pixel via the vertical signal line 29 and temporarily holds the pixel signal after the signal processing. The column processing unit 23 may execute at least one of noise removal processing or AD (Analog to Digital) conversion processing as the signal processing. As an example of the noise removal processing, correlated double sampling (CDS) can be mentioned, but other types of processing may be executed.

[0035] The read drive unit 24 is composed of, for example, a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 23. By the selection scan by the read drive unit 24, the pixel signals signal-processed for each unit circuit in the column processing unit 23 are output sequentially.

[0036] The system control unit 25 includes, for example, a timing generator that generates various timing signals. The system control unit 25 performs drive control of the pixel drive unit 22, the column processing unit 23, the read drive unit 24, etc. based on the various timing signals generated by the timing generator.

[0037] The signal processing unit 26 has at least an arithmetic processing function and performs various signal processes such as arithmetic processing based on the pixel signal output from the column processing unit 23. The data storage unit 27 temporarily stores the data necessary for the processing when performing signal processing in the signal processing unit 26.

[0038] The block diagram of FIG. 2 shows an example of an image sensor according to Modification 1. As in the example of FIG. 2, the pixel driving unit 22 may be connected to the pixel array in the pixel array unit 21 via pixel driving lines 28A wired along the vertical direction. In this case, as in FIG. 1, two vertical signal lines 29 may be wired along the column direction for each pixel column. Further, as will be described later, the pixel driving unit 22 may output a driving signal to a first pixel driving line wired along the vertical direction and a second pixel driving line wired along the horizontal direction to drive the pixels in the pixels in the pixel array unit 21. Thus, the direction and combination of the signal lines (pixel driving lines) for driving the pixels in the pixel array unit 21 are not limited.

[0039] <Example Configuration of Pixel> Next, an example configuration of the pixels provided in the pixel array unit 21 will be described. FIG. 3 shows an example of a pixel provided in the pixel array unit 21.

[0040] FIG. 3 shows a cross section of one pixel 51 provided in the pixel array unit 21. This pixel 51 receives light incident from the outside, performs photoelectric conversion, and outputs a signal corresponding to the charge obtained as a result. The pixel 51 can receive, for example, infrared light. However, the wavelength of the electromagnetic wave received by the pixel 51 is not limited.

[0041] The pixel 51 has, for example, a substrate 61 (semiconductor layer) and an on-chip lens 62 formed on the substrate 61. As the substrate 61, for example, a silicon substrate including a P-type semiconductor region can be used.

[0042] For example, the thickness of the substrate 61 in the z-axis direction (the thickness in the direction perpendicular to the surface of the substrate 61) is set to 20 μm or less. However, the thickness of the substrate 61 may be 20 μm or more. The thickness of the substrate 61 can be determined according to the design and use of the image sensor 11.

[0043] As the substrate 61, for example, a high-resistance P-Epi substrate with a substrate concentration of 1E+13 order or less can be used. In this case, the resistance (resistivity) of the substrate 61 is, for example, 500 [Ωcm] or more.

[0044] The value of the resistance of the substrate 61 depends on the substrate concentration. For example, when the substrate concentration is 6.48E+12 [cm3], the resistance is 2000 [Ωcm]. Also, when the substrate concentration is 1.30E+13 [cm3], the resistance is 1000 [Ωcm]. When the substrate concentration is 2.59E+13 [cm3], the resistance is 500 [Ωcm]. Furthermore, when the substrate concentration is 1.30E+14 [cm3], the resistance is 100 [Ωcm].

[0045] On the surface of the substrate 61 on the positive z-axis side, that is, the surface on the side where light from the outside enters the substrate 61 (hereinafter also referred to as the incident surface), an on-chip lens 62 for condensing the light incident from the outside and making it enter the substrate 61 is formed.

[0046] Furthermore, in the pixel 51, pixel-interval light-shielding portions 63-1 and 63-2 for preventing color mixing between adjacent pixels are formed at the end portions of the pixel 51 on the incident surface of the substrate 61.

[0047] In this example, light from the outside enters the substrate 61 through the on-chip lens 62. It is preferable that the light incident from the outside passes through a part of the on-chip lens 62 and the substrate 61 and does not enter the regions of other pixels provided adjacent to the pixel 51 in the substrate 61. In the example of FIG. 3, the light incident from the outside on the on-chip lens 62 and heading into other pixels adjacent to the pixel 51 is shielded by the pixel-interval light-shielding portion 63-1 and the pixel-interval light-shielding portion 63-2, preventing it from entering other adjacent pixels. Hereinafter, when there is no need to particularly distinguish between the pixel-interval light-shielding portion 63-1 and the pixel-interval light-shielding portion 63-2, it is simply referred to as the pixel-interval light-shielding portion 63.

[0048] Since the imaging element 11 is a back-illuminated sensor, the incident surface of the substrate 61 is the so-called back surface of the substrate 61. A wiring layer including wirings and the like is not formed on the back surface side of the substrate 61. Also, on the surface portion of the substrate 61 opposite to the incident surface, a wiring layer is formed in which wirings for driving transistors and the like formed in the pixel 51 in the stacked structure and wirings for reading out signals from the pixel 51 are formed.

[0049] On the surface side opposite to the incident surface within the substrate 61, that is, the inner portion of the surface on the negative z-axis direction side, an oxide film 64 and signal extraction portions 65-1 and 65-2 called Taps are formed.

[0050] In this example, an oxide film 64 is formed in the central portion of the pixel 51 near the surface opposite to the incident surface of the substrate 61, and signal extraction portions 65-1 and 65-2 are formed at both ends of the oxide film 64, respectively.

[0051] Here, the signal extraction portion 65-1 includes an N+ semiconductor region 71-1, an N+ semiconductor region 71-1, an N- semiconductor region 72-1, a P+ semiconductor region 73-1, and a P- semiconductor region 74-1. The N+ semiconductor region 71-1 is an N-type semiconductor region. The N- semiconductor region 72-1 is an N-type semiconductor region having a lower donor impurity concentration than the N+ semiconductor region 71-1. The P+ semiconductor region 73-1 is a P-type semiconductor region. The P- semiconductor region 74-1 is a P-type semiconductor region having a lower acceptor impurity concentration than the P+ semiconductor region 73-1. For example, when a silicon (Si) substrate is used, as the donor impurity, an element belonging to Group 5 in the periodic table such as phosphorus (P) or arsenic (As) can be used. In this case, as the acceptor impurity, for example, an element belonging to Group 3 in the periodic table such as boron (B) can be used. The element serving as the donor impurity is also called a donor element, and the element serving as the acceptor impurity is also called an acceptor element.

[0052] An N+ semiconductor region 71-1 is formed at a position on the positive x-axis side of the oxide film 64 in a portion near the surface on the side opposite to the incident surface of the substrate 61. Further, an N- semiconductor region 72-1 is formed on the positive z-axis side of the N+ semiconductor region 71-1 so as to cover (surround) the N+ semiconductor region 71-1.

[0053] Furthermore, a P+ semiconductor region 73-1 is formed at a position adjacent to the positive x-axis side of the N+ semiconductor region 71-1 in a portion near the surface on the side opposite to the incident surface of the substrate 61. Also, a P- semiconductor region 74-1 is formed on the positive z-axis side of the P+ semiconductor region 73-1 so as to cover (surround) the P+ semiconductor region 73-1.

[0054] Note that when the substrate 61 is viewed from a direction perpendicular to the surface of the substrate 61, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 may be formed so as to surround the periphery of the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 with the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 as the center.

[0055] Similarly, the signal extraction section 65-2 includes an N+ semiconductor region 71-2, an N- semiconductor region 72-2, a P+ semiconductor region 73-2, and a P- semiconductor region 74-2. The N+ semiconductor region 71-2 is an N-type semiconductor region. The N- semiconductor region 72-2 is an N-type semiconductor region having a lower donor impurity concentration than the N+ semiconductor region 71-2. The P+ semiconductor region 73-2 is a P-type semiconductor region. The P- semiconductor region 74-2 is a P-type semiconductor region having a lower acceptor impurity concentration than the P+ semiconductor region 73-2.

[0056] An N+ semiconductor region 71-2 is formed at a position adjacent to the negative x-axis side of the oxide film 64 in a portion near the surface on the side opposite to the incident surface of the substrate 61. Further, an N- semiconductor region 72-2 is formed on the positive z-axis side of the N+ semiconductor region 71-2 so as to cover (surround) the N+ semiconductor region 71-2.

[0057] Furthermore, a P+ semiconductor region 73-2 is formed at a position adjacent to the axially negative direction side of the N+ semiconductor region 71-2 in a portion near the surface on the side opposite to the incident surface of the substrate 61. Also, a P- semiconductor region 74-2 is formed on the positive z-axis side of the P+ semiconductor region 73-2 so as to cover (surround) the P+ semiconductor region 73-2.

[0058] Note that when the substrate 61 is viewed from a direction perpendicular to the surface of the substrate 61, an N+ semiconductor region 71-2 and an N- semiconductor region 72-2 may be formed so as to surround the peripheries of the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 centered on the P+ semiconductor region 73-2 and the P- semiconductor region 74-2.

[0059] Hereinafter, when there is no need to particularly distinguish between the signal extraction unit 65-1 and the signal extraction unit 65-2, these may be simply referred to as the signal extraction unit 65.

[0060] Also, hereinafter, when there is no need to particularly distinguish between the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, these may be simply referred to as the N+ semiconductor region 71. Also, when there is no need to particularly distinguish between the N- semiconductor region 72-1 and the N- semiconductor region 72-2, these may be simply referred to as the N- semiconductor region 72.

[0061] Furthermore, hereinafter, when there is no need to particularly distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, these may be simply referred to as the P+ semiconductor region 73. Also, when there is no need to particularly distinguish between the P- semiconductor region 74-1 and the P- semiconductor region 74-2, these may be simply referred to as the P- semiconductor region 74.

[0062] Also, between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 in the substrate 61, a separation portion 75-1 for separating these regions is formed by an oxide film or the like. Similarly, between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2, a separation portion 75-2 for separating these regions is also formed by an oxide film or the like. Hereinafter, when there is no need to particularly distinguish between the separation portion 75-1 and the separation portion 75-2, these will be simply referred to as the separation portion 75.

[0063] The N+ semiconductor region 71 provided on the substrate 61 functions as a charge detection portion for detecting the amount of light (the amount of signal carriers generated by photoelectric conversion by the substrate 61) of the light incident on the pixel 51 from the outside. Note that not only the N+ semiconductor region 71 but also the N- semiconductor region 72 with a low donor impurity concentration can be used as a charge detection portion. Further, the P+ semiconductor region 73 functions as a voltage application portion for directly applying a voltage to the substrate 61 to generate an electric field in the substrate 61. At this time, a majority carrier current can be injected into the substrate 61. Note that in addition to the P+ semiconductor region 73, the P- semiconductor region 74 with a low acceptor impurity concentration can also be used as a voltage application portion.

[0064] In the pixel 51, an FD (Floating Diffusion) portion (hereinafter also particularly referred to as the FD portion A), which is a floating diffusion region not shown in the figure, is directly connected to the N+ semiconductor region 71-1. Further, the FD portion A is connected to the vertical signal line 29 via an amplification transistor or the like not shown in the figure.

[0065] Similarly, another FD portion different from the FD portion A (hereinafter particularly referred to as the FD portion B) is directly connected to the N+ semiconductor region 71-2. Further, the FD portion B is connected to the vertical signal line 29 via an amplification transistor or the like not shown in the figure. Here, the FD portion A and the FD portion B are connected to different vertical signal lines 29.

[0066] For example, when attempting to measure the distance to an object by means of the indirect ToF method, infrared light is irradiated from the imaging device provided with the imaging element 11 toward the object. Then, when the infrared light is reflected by the object and returns to the imaging device as reflected light, the substrate 61 of the imaging element 11 receives the incident reflected light (infrared light) and performs photoelectric conversion.

[0067] At this time, the pixel driving unit 22 drives the pixel 51. As a result, a signal corresponding to the charge obtained by photoelectric conversion can be distributed to the FD unit A and the FD unit B. Note that, as described above, the driving of the pixel 51 may be performed not by the pixel driving unit 22 but by a separately provided driving unit, a lead driving unit 24, etc. via the vertical signal line 29 or other control lines wired in the vertical direction.

[0068] For example, at a certain timing, the pixel driving unit 22 applies a voltage to the two P+ semiconductor regions 73 via contacts or the like. For example, the pixel driving unit 22 applies a HIGH (e.g., 1.5V) voltage to the P+ semiconductor region 73-1 and a LOW (e.g., 0V) voltage to the P+ semiconductor region 73-2.

[0069] As a result, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and a current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, holes in the substrate 61 move in the direction of the P+ semiconductor region 73-2, and electrons move in the direction of the P+ semiconductor region 73-1.

[0070] Infrared light (reflected light) from the outside enters the substrate 61 through the on-chip lens 62, and the infrared light is photoelectrically converted in the substrate 61 and converted into a pair of electrons and holes. The electrons obtained in the above state are guided in the direction of the P+ semiconductor region 73-1 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-1.

[0071] In this case, the electrons generated by photoelectric conversion are used as a signal carrier (charge) for detecting a signal corresponding to the amount of infrared light (infrared light reception amount) incident on the pixel 51.

[0072] As a result, charges are accumulated in the N+ semiconductor region 71-1 in response to the electrons that have moved into the N+ semiconductor region 71-1. The accumulated charges are detected by the column processing unit 23 via the FD unit A, the amplification transistor, or the vertical signal line 29 or the like.

[0073] The accumulated charges in the N+ semiconductor region 71-1 are transferred to the FD unit A directly connected to the N+ semiconductor region 71-1. Then, a signal corresponding to the charges transferred to the FD unit A is read out by the column processing unit 23 via the amplification transistor and the vertical signal line 29. Then, for the read signal, processing such as AD conversion processing is performed in the column processing unit 23, and the generated pixel signal is supplied to the signal processing unit 26.

[0074] This pixel signal is a signal indicating the amount of charge (the amount of charge accumulated in the FD unit A) corresponding to the electrons detected by the N+ semiconductor region 71-1. That is, it can also be said that the pixel signal is a signal indicating the amount of infrared light received by the pixel 51.

[0075] Note that, similar to the case of the N+ semiconductor region 71-1, a pixel signal corresponding to the electrons detected by the N+ semiconductor region 71-2 may be used for distance measurement.

[0076] Also, at the next timing, a voltage is applied to the two P+ semiconductor regions 73 via contacts or the like by the pixel driving unit 22 so that an electric field in the direction opposite to the electric field that has been generated in the substrate 61 so far is generated. Specifically, for example, a HIGH (for example, 1.5 V) voltage is applied to the P+ semiconductor region 73-2, and a LOW (for example, 0 V) voltage is applied to the P+ semiconductor region 73-1.

[0077] As a result, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and a current flows from the P+ semiconductor region 73-2 to the P+ semiconductor region 73-1.

[0078] Infrared light (reflected light) from the outside enters the substrate 61 through the on-chip lens 62, and the infrared light is photoelectrically converted in the substrate 61 to generate a pair of electrons and holes. In the above state, the generated electrons are guided in the direction of the P+ semiconductor region 73-2 by the electric field between the P+ semiconductor regions 73 and move into the N+ semiconductor region 71-2.

[0079] As a result, charges corresponding to the electrons that have moved into the N+ semiconductor region 71-2 are accumulated in the N+ semiconductor region 71-2. The accumulated charges are detected by the column processing unit 23 via the FD unit B, the amplification transistor, the vertical signal line 29, etc.

[0080] The accumulated charges in the N+ semiconductor region 71-2 are transferred to the FD unit B directly connected to the N+ semiconductor region 71-2. Then, a signal corresponding to the charges transferred to the FD unit B is read out by the column processing unit 23 via the amplification transistor and the vertical signal line 29. Then, for the read signal, processing such as AD conversion processing is performed in the column processing unit 23, and the generated pixel signal is supplied to the signal processing unit 26.

[0081] Note that, similar to the case of the N+ semiconductor region 71-2, distance measurement may be performed using the pixel signal corresponding to the electrons detected in the N+ semiconductor region 71-1.

[0082] In this way, when pixel signals obtained by photoelectric conversion in different periods are obtained for the same pixel 51, the signal processing unit 26 calculates distance information indicating the distance to the object based on those pixel signals and outputs the distance information to the subsequent circuit. The distance information may be, for example, a distance image including distance values for each pixel.

[0083] As described above, the technique of distributing signal carriers to different N+ semiconductor regions 71 and calculating distance information based on the signals corresponding to those signal carriers is called the indirect ToF method.

[0084] Here, an example has been described in which the voltage applied to the P+ semiconductor region 73 is controlled by the pixel driving unit 22. However, as described above, a driving unit (block) that functions as a voltage application control unit for controlling the voltage applied to the P+ semiconductor region 73 may be provided in the imaging device 11 separately from the pixel driving unit 22.

[0085] When the portion of the signal extraction unit 65 in the pixel 51 is viewed from the positive z-axis direction (the direction perpendicular to the surface of the substrate 61) in FIG. 2, for example, a structure in which the periphery of the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71 as shown in FIG. 3 may be adopted. In FIG. 3, the same reference numerals are given to the portions corresponding to the components in FIG. 2, and the description will be omitted as appropriate.

[0086] In the example of FIG. 3, an oxide film 64 (not shown) is formed in the central portion of the pixel 51. Also, the signal extraction unit 65 is formed at a portion shifted from the center of the pixel 51. Two signal extraction units 65 are formed in the pixel 51 of FIG. 3.

[0087] And in each signal extraction unit 65, a P+ semiconductor region 73 is formed in a rectangular shape at its center position. Also, with the P+ semiconductor region 73 as the center, the periphery of the P+ semiconductor region 73 is surrounded by a rectangular frame-shaped N+ semiconductor region 71. That is, the N+ semiconductor region 71 is formed so as to surround the periphery of the P+ semiconductor region 73.

[0088] Also, in the pixel 51, an on-chip lens 62 is formed in the central portion of the pixel 51, that is, the portion indicated by the arrow A11, so that the infrared light incident from the outside is condensed. In other words, the infrared light incident on the on-chip lens 62 from the outside is condensed by the on-chip lens 62 at the position indicated by the arrow A11, that is, the position on the positive z-axis side of the oxide film 64 in FIG. 2.

[0089] Therefore, the infrared light will be focused at a position between the signal extraction unit 65-1 and the signal extraction unit 65-2. This can suppress the infrared light from entering the pixels adjacent to the pixel 51 and causing color mixing, and also suppress the infrared light from directly entering the signal extraction unit 65.

[0090] For example, if the infrared light directly enters the signal extraction unit 65, the charge separation efficiency, Cmod (Contrast between active and inactive tap), and Modulation contrast will decrease.

[0091] The signal extraction unit 65 (tap) from which the signal corresponding to the charge (electron) obtained by photoelectric conversion is read out is called an active tap.

[0092] The signal extraction unit 65 (tap) from which the signal corresponding to the charge obtained by photoelectric conversion is not read out, that is, the signal extraction unit 65 that is not an active tap, is referred to as an inactive tap.

[0093] In the above example, the signal extraction unit 65 to which a HIGH (for example, 1.5V) voltage is applied to the P+ semiconductor region 73 is the active tap. Also, the signal extraction unit 65 to which a LOW (for example, 0V) voltage is applied to the P+ semiconductor region 73 is the inactive tap.

[0094] Cmod is an index indicating what percentage of the charges generated by the photoelectric conversion of the incident infrared light can be detected in the N+ semiconductor region 71 of the signal extraction unit 65, which is an active tap, that is, whether a signal corresponding to the charge can be extracted, and it indicates the charge separation efficiency.

[0095] Therefore, for example, when infrared light incident from the outside enters the area of the inactive tap and photoelectric conversion is performed within the inactive tap, electrons, which are signal carriers generated by the photoelectric conversion, are likely to move to the N+ semiconductor region 71 within the inactive tap. Then, the charges of some of the electrons obtained by the photoelectric conversion will not be detected in the N+ semiconductor region 71 within the active tap, and Cmod (charge separation efficiency) will decrease.

[0096] Therefore, in pixel 51, by condensing infrared light near the central portion of pixel 51 at a position approximately equidistant from the two signal extraction portions 65, the probability that the infrared light incident from the outside is photoelectrically converted in the area of the inactive tap can be reduced, and the charge separation efficiency can be improved. Also, in pixel 51, the modulation contrast can be improved. That is, the electrons obtained by the photoelectric conversion are more likely to be induced in the N+ semiconductor region 71 within the active tap.

[0097] 〈Example of equivalent circuit configuration of pixel〉 Next, an example of the circuit configuration in a pixel will be described. FIG. 5 shows the equivalent circuit of pixel 51.

[0098] Pixel 51 includes a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplification transistor 724A, and a selection transistor 725A corresponding to the signal extraction portion 65-1 including the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1.

[0099] Also, pixel 51 includes a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplification transistor 724B, and a selection transistor 725B corresponding to the signal extraction portion 65-2 including the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2.

[0100] The pixel driving unit 22 applies a predetermined voltage MIX0 (first voltage) to the P+ semiconductor region 73-1 and a predetermined voltage MIX1 (second voltage) to the P+ semiconductor region 73-2. In the above example, one of the voltages MIX0 and MIX1 is HIGH (e.g., 1.5V) and the other is LOW (e.g., 0V). The P+ semiconductor regions 73-1 and 73-2 correspond to voltage application portions to which the first voltage or the second voltage is applied.

[0101] The N+ semiconductor regions 71-1 and 71-2 correspond to charge detection portions that detect and accumulate charges generated by photoelectric conversion of light incident on the substrate 61.

[0102] When the drive signal TRG supplied to the gate electrode of the transfer transistor 721A becomes active, the transfer transistor 721A becomes conductive accordingly. Thereby, the charges accumulated in the N+ semiconductor region 71-1 are transferred to FD722A. When the drive signal TRG supplied to the gate electrode of the transfer transistor 721B becomes active, the transfer transistor 721B becomes conductive accordingly. Thereby, the charges accumulated in the N+ semiconductor region 71-2 are transferred to FD722B.

[0103] FD722A temporarily holds the charges supplied from the N+ semiconductor region 71-1. On the other hand, FD722B temporarily holds the charges supplied from the N+ semiconductor region 71-2. FD722A corresponds to the FD portion A described in the description of FIG. 2. On the other hand, FD722B corresponds to the FD portion B.

[0104] When the drive signal RST supplied to the gate electrode of the reset transistor 723A becomes active, the reset transistor 723A becomes conductive accordingly. As a result, the potential of FD722A is reset to a predetermined level (reset voltage VDD). When the drive signal RST supplied to the gate electrode of the reset transistor 723B becomes active, the reset transistor 723B becomes conductive accordingly. As a result, the potential of FD722B is reset to a predetermined level (reset voltage VDD). When the reset transistors 723A and 723B are in the active state, the transfer transistors 721A and 721B can be made active.

[0105] The source electrode of the amplification transistor 724A is connected to the vertical signal line 29A via the selection transistor 725A. As a result, a load MOS of the constant current source circuit section 726A connected to one end of the vertical signal line 29A and a source follower circuit are formed. The source electrode of the amplification transistor 724B is connected to the vertical signal line 29B via the selection transistor 725B. As a result, a load MOS of the constant current source circuit section 726B connected to one end of the vertical signal line 29B and a source follower circuit are formed.

[0106] The selection transistor 725A is connected between the source electrode of the amplification transistor 724A and the vertical signal line 29A. When the selection signal SEL supplied to the gate electrode of the selection transistor 725A becomes active, the selection transistor 725A becomes conductive accordingly. As a result, the pixel signal output from the amplification transistor 724A is output to the vertical signal line 29A.

[0107] The selection transistor 725B is connected between the source electrode of the amplification transistor 724B and the vertical signal line 29B. When the selection signal SEL supplied to the gate electrode of the selection transistor 725B becomes active, the selection transistor 725B becomes conductive accordingly. As a result, the pixel signal output from the amplification transistor 724B is output to the vertical signal line 29B.

[0108] The transfer transistors 721A and 721B, reset transistors 723A and 723B, amplification transistors 724A and 724B, and selection transistors 725A and 725B of the pixel 51 are controlled by, for example, the pixel driving unit 22.

[0109] FIG. 6 shows other equivalent circuits of the pixel 51.

[0110] In FIG. 6, the parts corresponding to those in FIG. 5 are denoted by the same reference numerals, and the description of the components denoted by the same reference numerals is omitted.

[0111] In the equivalent circuit of FIG. 6, an additional capacitor 727 and a switching transistor 728 for controlling its connection are added to each of the signal extraction units 65-1 and 65-2 with respect to the equivalent circuit of FIG. 5.

[0112] Specifically, an additional capacitor 727A is connected between the transfer transistor 721A and the FD 722A via a switching transistor 728A. Also, an additional capacitor 727B is connected between the transfer transistor 721B and the FD 722B via a switching transistor 728B.

[0113] The switching transistor 728A becomes conductive in response to the driving signal FDG supplied to the gate electrode becoming active. Thereby, the additional capacitor 727A is connected to the FD 722A. The switching transistor 728B becomes conductive in response to the driving signal FDG supplied to the gate electrode becoming active. Thereby, the additional capacitor 727B is connected to the FD 722B.

[0114] The pixel driving unit 22 activates the switching transistors 728A and 728B and connects the FD 722A and the additional capacitor 727A, for example, when the amount of incident light is large at high illuminance. Also, the pixel driving unit 22 connects the FD 722B and the additional capacitor 727B. Thereby, it becomes possible to accumulate more charges at high illuminance.

[0115] On the other hand, when the amount of incident light is small, i.e., in low illuminance conditions, the pixel driving unit 22 deactivates the switching transistors 728A and 728B. As a result, the additional capacitors 727A and 727B are disconnected from the FDs 722A and 722B, respectively.

[0116] As shown in the example of FIG. 6, by implementing the additional capacitor 727 and making proper use according to the amount of incident light, a high dynamic range can be ensured. However, a configuration in which the additional capacitor 727 is omitted, as in the equivalent circuit of FIG. 5, may also be used.

[0117] (Configuration example of the distance measurement module) FIG. 7 is a block diagram showing a configuration example of a distance measurement module that outputs distance measurement information using the imaging device 11 of FIG. 1.

[0118] The distance measurement module 1000 includes a light emitting unit 1011, a light emission control unit 1012, and a light receiving unit 1013.

[0119] The light emitting unit 1011 has a light source that emits light of a predetermined wavelength and emits irradiation light with periodically varying brightness to irradiate an object. For example, the light emitting unit 1011 has a light emitting diode that emits infrared light with a wavelength in the range of 780 nm to 1000 nm as the light source. The light emitting unit 1011 generates irradiation light, for example, in synchronization with the rectangular wave light emission control signal CLKp supplied from the light emission control unit 1012.

[0120] Note that, as the light emission control signal CLKp, for example, a periodic signal can be used. The periodic signal is not limited to a rectangular wave. For example, the light emission control signal CLKp may be a sine wave.

[0121] The light emission control unit 1012 supplies the light emission control signal CLKp to the light emitting unit 1011 and the light receiving unit 1013 and controls the irradiation timing of the irradiation light. The frequency of this light emission control signal CLKp is, for example, 20 megahertz (MHz). Note that the frequency of the light emission control signal CLKp is not limited to 20 megahertz (MHz) and may be set to other values such as 5 megahertz (MHz).

[0122] The light receiving unit 1013 receives the reflected light reflected from the object, calculates distance information for each pixel according to the light receiving result, generates a distance image representing the distance to the object for each pixel with a gradation value, and outputs the distance image.

[0123] As the light receiving unit 1013, for example, the above-described imaging element 11 can be used. When the imaging element 11 is used as the light receiving unit 1013, based on the emission control signal CLKp, distance information can be calculated for each pixel based on the signal intensities detected by the charge detection units (N+ semiconductor regions 71) of the signal extraction units 65-1 and 65-2 of each pixel 51 in the pixel array unit 21.

[0124] As described above, the imaging element 11 in FIG. 1 can be incorporated as the light receiving unit 1013 of the distance measurement module 1000 that obtains and outputs distance information to the subject by the indirect ToF method. By adopting the above-described imaging element 11 as the light receiving unit 1013 of the distance measurement module 1000, the generated electromagnetic noise can be suppressed.

[0125] Also, in the above, an example using electrons as the signal carrier has been described, but holes generated by photoelectric conversion may be used as the signal carrier. In this case, the charge detection unit for detecting the signal carrier is formed by a P+ semiconductor region. Also, the voltage application unit for generating an electric field in the substrate is formed by an N+ semiconductor region. Further, in the charge detection unit provided in the signal extraction unit, holes as the signal carrier may be detected.

[0126] (Configuration example of imaging element) FIG. 8 shows an example when all the pixels in the imaging element are driven simultaneously. FIG. 8 shows in more detail a part including the pixel driving unit 22A, the pixel array unit 21, and the column processing unit 23 in FIG. 2. The pixel driving unit 22A in FIG. 8 includes a PLL (Phase Locked Loop) 31, a pulse generator 30, and a clock distribution circuit 37. Also, the column processing unit 23 includes an analog-to-digital converter 240.

[0127] PLL 31 is an example of a signal generator that generates a clock signal. Hereinafter, the case where a PLL is used as the signal generator will be described as an example. However, it does not prevent the use of other types of circuits as the signal generator. A pulse generator 30 is connected to the subsequent stage of the PLL 31. Further, a clock distribution circuit 37 is connected to the subsequent stage of the pulse generator 30. The clock distribution circuit 37 in FIG. 8 realizes signal distribution by a clock tree method. However, a mesh method (batch drive method) clock distribution circuit may be used, and the method of the clock distribution circuit is not limited. The clock distribution circuit 37 includes a plurality of output terminals. Each output terminal of the clock distribution circuit 37 is connected to each pixel column in the pixel array unit 21 via the pixel drive line 28A. Further, each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via the vertical signal line 29.

[0128] The clock signal with frequency f0 output from the PLL 31 is supplied to the pulse generator 30. The pulse generator 30 generates pulses at a predetermined period based on the clock signal with frequency f0. The pulses generated by the pulse generator 30 are supplied to each pixel column in the pixel array unit 21 at substantially the same timing via the clock distribution circuit 37.

[0129] For this reason, in the image sensor of FIG. 8, all the pixels in the pixel array unit 21 are driven at one phase (PHASE = 0 degrees). In the image sensor of FIG. 8, as the number of pixels in the pixel array unit 21 increases, the total value of the drive current output from the pulse generator 30 in the pixel drive unit 22A increases. Since the change in the current value becomes large, there is a possibility that the electromagnetic noise generated at the time of detecting incident light becomes large. Therefore, as will be described later, a pulse generator capable of generating pulses of a plurality of phases can be implemented in the pixel drive unit 22 or the pixel drive unit 22A.

[0130] FIG. 9 shows an example of a pulse generator according to the present disclosure. The pulse generator 30A in FIG. 9 includes a plurality of output terminals (output terminals C1 to C4). The output terminals C1 to C4 are connected to the pixel driving line 28 or the pixel driving line 28A via, for example, a signal distribution circuit described later. As will be described later, the pulse generator 30A can output pulses with different phases from each signal line. The pulse generator 30A includes a circuit block 33 and flip-flops 340 to 343. The flip-flops 340 to 343 are, for example, D flip-flops having D terminals, Q terminals, and CLK terminals. However, the type of flip-flop used is not limited.

[0131] There are two types of D flip-flops: (1) a type that latches the signal input to the D terminal at the timing of the rising edge of the signal input to the CLK terminal, and (2) a type that latches the signal input to the D terminal at the timing of the falling edge of the signal input to the CLK terminal. As the flip-flops 340 to 343, either the type (1) or the type (2) may be used. Also, the flip-flops 340 to 343 may contain a mixture of the type (1) flip-flops and the type (2) flip-flops. By mixing different types of flip-flops, the timing at which pulses are output from each of the output terminals C1 to C4 can be shifted.

[0132] The circuit block 33 is connected to the PLL 31 via the signal line L0. Also, the circuit block 33 is connected to the system control unit 25 via the signal line L3. The circuit block 33 is connected to the D terminal of the flip-flop 340 via the signal line L2. Also, the circuit block 33 is connected to the CLK terminals of the flip-flops 340 to 343 via the signal line L1.

[0133] The circuit block 33 includes, for example, a frequency division circuit. In this case, the frequency division circuit of the circuit block 33 generates a signal with a frequency different from that of the input clock signal based on the input clock signal. The setting of the frequency division circuit of the circuit block 33 may be changeable by, for example, a register or the voltage level of a signal line. In this case, the system control unit 25 can adjust the frequency of the signal output from the circuit block 33. However, the configuration and function of the circuit block 33 may be different from this. For example, it is not necessary to adopt a configuration in which the setting of the circuit block 33 is always changed by the system control unit 25.

[0134] In FIG. 9, a plurality of flip-flops are connected in series. For example, the Q terminal of the flip-flop 340 is connected to the D terminal of the flip-flop 341. On the other hand, the Q terminal of the flip-flop 341 is connected to the D terminal of the flip-flop 342. The Q terminal of the flip-flop 342 is connected to the D terminal of the flip-flop 343.

[0135] Also, the Q terminal of each flip-flop is connected to a corresponding output terminal. For example, the output terminal C1 is connected to the Q terminal of the flip-flop 340. Also, the output terminal C2 is connected to the Q terminal of the flip-flop 341. The output terminal C3 is connected to the Q terminal of the flip-flop 342. The output terminal C4 is connected to the Q terminal of the flip-flop 343. However, it is not necessary that the Q terminals of all the flip-flops connected in series are connected to any output terminal. For example, the Q terminals of some of the flip-flops connected in series may be connected to any output terminal.

[0136] Next, the operation of the pulse generator 30A will be described.

[0137] The PLL 31 supplies a clock signal with a frequency f0 to the circuit block 33 via the signal line L0. The circuit block 33 supplies a first signal with a frequency f1 from the signal line L1 to the CLK terminals of the flip-flops 340 to 343. Further, the circuit block 33 supplies a second signal with a frequency f2 to the D terminal of the flip-flop 340 via the signal line L2. The second signal is also called a modulation signal or a guide pulse.

[0138] Assume that the frequency f1 (first frequency) of the first signal and the frequency f2 (second frequency) of the second signal are different. Hereinafter, the case where the first frequency f1 is higher than the second frequency f2 will be described. However, the second frequency f2 may be set higher than the first frequency f1. The circuit block 33 can output the first signal and the second signal synchronized with each other. However, the first signal and the second signal do not necessarily have to be synchronized with each other.

[0139] Here, the description will be made assuming that the frequency f0 (clock frequency) of the clock signal is equal to the first frequency f1. However, the clock frequency f0 generated by the signal generator and the first frequency f1 may be different. For example, the circuit block 33 may convert the frequency of the clock signal by a frequency divider or the like.

[0140] As a result, pulses that have passed through the delays caused by different numbers of flip-flops are output from the output terminals C1 to C4 of the pulse generator 30A. In the case of the example in FIG. 9, the pulses are output in the order of the output terminal C1, the output terminal C2, the output terminal C3, and the output terminal C4. That is, pulses are output from the output terminals C1 to C4 of the pulse generator 30A at different timings. Hereinafter, the difference in the timing at which pulses are output from any of the signal lines even without a pulse generator will be described by the phase (PHASE in the figure).

[0141] In the pulse generator according to the present disclosure, it is possible to adjust the timing deviation of the pulses output from a plurality of output terminals based on the first frequency f1 and the second frequency f2. The phase delay Δθ caused by the second signal passing through a single-stage flip-flop is Δθ = 360 × f2 / f1. For example, when f1 = 2.0 GHz and f2 = 500 MHz, Δθ = 90 degrees. In this case, as shown in FIG. 9, pulse signals are output from the output terminals C1, C2, C3, and C4 with phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. The values of the first frequency f1 and the second frequency f2 described here are only examples. Therefore, the first frequency f1 and the second frequency f2 may be set to different values.

[0142] Hereinafter, let the phase of the pulse signal output from the output terminal C1 be P1, the phase of the pulse signal output from the output terminal C2 be P2, the phase of the pulse signal output from the output terminal C3 be P3, and the phase of the pulse signal output from the output terminal C4 be P4. For example, when f1 = 2.0 GHz and f2 = 500 MHz as described above, P1 = 0 degrees, P2 = 90 degrees, P3 = 180 degrees, and P4 = 270 degrees.

[0143] Note that the first frequency f1 of the first signal and the second frequency f2 of the second signal do not have to be fixed. For example, the circuit block 33 may change at least one of the first frequency f1 of the first signal or the second frequency f2 of the second signal based on a control signal transmitted from the system control unit 25 via the signal line L3. Thereby, the pulse generator can change the frequency of the pulse signal. Also, the pulse generator can output pulse signals related to various phase combinations.

[0144] The pulse generator according to the present disclosure can change, for example, the frequency of the pulse signal or the combination of phases used in the pulse signal according to the object to be detected or the operation mode. For example, when an object at a relatively short distance is to be detected, the pulse frequency can be set high. Also, when an object at a relatively long distance is to be detected, the pulse frequency can be set low. Since the pulse generator according to the present disclosure does not use an inverter chain to generate a pulse signal of a plurality of phases, it is possible to suppress individual variations in the delay amount. Also, in the pulse generator according to the present disclosure, the generated distortion can be suppressed. For this reason, the pulse generator according to the present disclosure can also be combined with a signal generator (for example, PLL31) that outputs a relatively low clock frequency.

[0145] In this way, the circuit block may be configured to output a first signal of a first frequency and a second signal of a second frequency different from the first frequency. The circuit block may be configured to output a first signal and a second signal synchronized with each other. Also, the circuit block may be configured to output a first signal of a first frequency equal to the clock frequency of the clock signal.

[0146] Also, the image sensor according to the present disclosure may include a control unit configured to output a control signal to the circuit block. The above-described system control unit 25 is an example of the control unit. In this case, the circuit block may be configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the supplied control signal.

[0147] The pixel driving unit 22B in FIG. 10 includes a PLL 31 (signal generation unit), a pulse generator 30A, and a circuit block 370. The imaging device in FIG. 10 corresponds to the imaging device in FIG. 8 with the pulse generator 30 replaced by the pulse generator 30A in FIG. 9 and the clock distribution circuit 37 in FIG. 8 replaced by the circuit block 370. The circuit block 370 includes clock distribution circuits 371 to 374. The clock distribution circuits 371 to 374 in FIG. 10 are in a clock tree format. However, at least one of the clock distribution circuits 371 to 374 may be of another format such as a mesh format (batch driving format).

[0148] The clock distribution circuits 371 to 374 are each connected to one of the output terminals C1 to C4 of the pulse generator 30A. Therefore, the clock distribution circuits 371 to 374 each distribute one of the signals with phases P1 to P4. Hereinafter, it will be described assuming that the output terminal C1 is connected to the clock distribution circuit 371, the output terminal C2 is connected to the clock distribution circuit 372, the output terminal C3 is connected to the clock distribution circuit 373, and the output terminal C4 is connected to the clock distribution circuit 374. However, the connection relationship between the output terminals and the clock distribution circuits may be different from this.

[0149] Each pixel column in the pixel array unit 21 is connected to one of the clock distribution circuits 371 to 374 via a pixel driving line 28A. The timing (phase of the pulse signal) at which the pixel column in the pixel array unit 21 is driven by a pulse depends on the clock distribution circuit to which the corresponding pixel driving line 28A is connected. In the example of FIG. 10, the pixel column connected to the clock distribution circuit 371 is driven at phase P1, the pixel column connected to the clock distribution circuit 372 is driven at phase P2, the pixel column connected to the clock distribution circuit 373 is driven at phase P3, and the pixel column connected to the clock distribution circuit 374 is driven at phase P4. Therefore, in the example of FIG. 10, the pixels in the imaging device are driven in column units.

[0150] In the pixel array unit 21 of FIG. 10, pixel columns driven by phase P1, pixel columns driven by phase P2, pixel columns driven by phase P3, and pixel columns driven by phase P4 are arranged in a pattern (order) from left to right. However, this pattern is only an example. Therefore, the pixel columns of the pixel array unit 21 may be driven in a pattern different from this. In FIG. 10, the number of pixels included in the pixel array unit 21 is 8×8 = 64. However, the number of pixels included in the pixel array unit 21 is not limited. Therefore, a different number of pixels (for example, more pixels) may be implemented in the pixel array unit 21.

[0151] Each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via the vertical signal line 29. The column processing unit 23 may be connected to a read drive unit 24 (not shown). When the read drive unit 24 is implemented, the read drive unit 24 can select a unit circuit corresponding to the pixel column of the column processing unit 23. The read drive unit 24 may perform selective scanning for the pixel columns driven in each phase (for example, P1 to P4). In this case, the column processing unit 23 can use the analog-to-digital converter 240 to convert the pixel signal from an analog signal to a digital signal and output the pixel signal to the subsequent signal processing unit 26.

[0152] Pixel signals related to the pixel columns driven and read in a plurality of phases (for example, P1 to P4) are input to the signal processing unit 26. In the image sensor of FIG. 10, a shift in the driving timing and a shift in the read timing of the pixel signal occur due to the pixel columns. Therefore, the data of the pixel signal may be stored in the buffer memory in the signal processing unit 26 to generate a distance image corresponding to the entire pixel array unit 21.

[0153] The image sensor according to the present disclosure may include a signal generator, a plurality of flip-flops connected in series, a circuit block, and a pixel array. The signal generator is configured to generate a clock signal. The circuit block is configured to supply a first signal to each clock terminal of the plurality of flip-flops in response to the clock signal, and to supply a second signal to the input terminal of the first-stage flip-flop of the plurality of flip-flops. The pixel array includes pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops. The above-described pixel array unit is an example of a pixel array. As the signal generator, for example, a PLL can be used. As the flip-flop, for example, a D flip-flop can be used. The first-stage flip-flop is, for example, the above-described flip-flop 340.

[0154] Pixels in the pixel array may include a signal extraction unit configured to detect charges generated by photoelectric conversion when a pulse signal is supplied. Also, pixels in the pixel array may include a plurality of signal extraction units, and each signal extraction unit may be configured to detect charges generated at different timings.

[0155] Further, the image sensor according to the present disclosure may further include a plurality of clock distribution circuits connected to any stage of the plurality of flip-flops on the input side and connected to pixels in the pixel array via drive lines on the output side. At least any one of the clock distribution circuits may be a clock tree system.

[0156] FIG. 10 illustrates an example of an image sensor capable of setting drive timing (phase of a pulse signal) in units of pixel columns. However, the pixels in the pixel array unit 21 may be controlled in different units and patterns. For example, as in the example of FIG. 11, an image sensor in which drive timing (phase of a pulse signal) is set in units of pixel rows may be used.

[0157] The imaging device in Fig. 11 corresponds to the one obtained by replacing the pixel driving unit 22 in Fig. 1 with the pixel driving unit 22C. The pixel driving unit 22C includes a PLL 31 (signal generator), a pulse generator 30A, and a circuit block 380. Further, the circuit block 380 includes clock distribution circuits 381 to 384. The clock distribution circuits 381 to 384 in Fig. 11 adopt a clock tree method. However, at least any one of the clock distribution circuits 381 to 384 may be based on another method such as a mesh method (batch driving method).

[0158] The clock distribution circuits 381 to 384 are respectively connected to any one of the output terminals C1 to C4 of the pulse generator 30A. Therefore, the clock distribution circuits 381 to 384 respectively distribute any one of the signals with phases P1 to P4. Hereinafter, it will be described assuming that the output terminal C1 is connected to the clock distribution circuit 381, the output terminal C2 is connected to the clock distribution circuit 382, the output terminal C3 is connected to the clock distribution circuit 383, and the output terminal C4 is connected to the clock distribution circuit 384. However, the connection relationship between the output terminal and the clock distribution circuit may be different from this.

[0159] Each pixel row in the pixel array unit 21 is connected to any one of the clock distribution circuits 381 to 384 via a pixel driving line 28. The timing (phase of the pulse signal) at which the pixel row in the pixel array unit 21 is driven by a pulse depends on the clock distribution circuit to which the corresponding pixel driving line 28 is connected. In the example of Fig. 11, the pixel row connected to the clock distribution circuit 381 is driven at the phase P1, the pixel row connected to the clock distribution circuit 382 is driven at the phase P2, the pixel row connected to the clock distribution circuit 383 is driven at the phase P3, and the pixel row connected to the clock distribution circuit 384 is driven at the phase P4. Therefore, in the example of Fig. 11, the pixels in the imaging device are driven in units of rows.

[0160] In the pixel array unit 21 of FIG. 11, pixel rows driven by phase P1, pixel rows driven by phase P2, pixel rows driven by phase P3, and pixel rows driven by phase P4 are arranged in a pattern (order) from the upper side to the lower side. This pattern is only an example. Therefore, the pixel rows of the pixel array unit 21 may be driven in a pattern different from this. In FIG. 11, the number of pixels included in the pixel array unit 21 is 8×8 = 64. However, the number of pixels included in the pixel array unit 21 is not limited. Therefore, a different number of pixels (for example, more pixels) may be implemented in the pixel array unit 21.

[0161] Each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via the vertical signal line 29. The column processing unit 23 may be connected to a read drive unit 24 (not shown). When the read drive unit 24 is implemented, the read drive unit 24 can select a unit circuit corresponding to the pixel column of the column processing unit 23. The read drive unit 24 may perform selective scanning on the pixel column. In this case, the column processing unit 23 can use the analog-to-digital converter 240 to convert the pixel signal from an analog signal to a digital signal and output the pixel signal to the subsequent signal processing unit 26.

[0162] The pixel signals related to the read pixel columns are input to the signal processing unit 26. In the image sensor of FIG. 10, a deviation in driving timing occurs due to pixel rows, and a deviation in the read timing of pixel signals occurs due to pixel columns. Therefore, the data of the pixel signals may be stored in the buffer memory in the signal processing unit 26 to generate a distance image corresponding to the entire pixel array unit 21.

[0163] As described above, in the image sensor according to the present disclosure, the pixel columns or pixel rows in the pixel array may be configured to be driven by a pulse signal supplied from a common stage of a plurality of flip-flops.

[0164] FIG. 11 described an example of an image sensor in which drive timing (phase of a pulse signal) is set for each pixel row. However, the pixels in the pixel array unit 21 may be controlled in units and patterns different from this. For example, as in the example of FIG. 12, an image sensor in which drive timing (phase of a pulse signal) is set for each region in the pixel array unit 21 may be used.

[0165] The image sensor of FIG. 12 includes a pixel drive unit 22B, a pixel array unit 21A, a column processing unit 23, and a timing control unit 32. The configuration of the pixel drive unit 22B in FIG. 12 is the same as that of the pixel drive unit 22B in FIG. 10. The timing control unit 32 outputs a timing signal to the pixel drive line 28 based on the pulse signals output by the clock distribution circuits 371 to 374 to the pixel drive line 28A.

[0166] For example, it is assumed that each pixel in the pixel array unit 21A includes a logic circuit (not shown) that performs an operation based on a pulse signal and a timing signal. Each pixel in the pixel array unit 21A is driven when the level of the output voltage of the logic circuit satisfies a predetermined condition. The driving conditions may be different for different pixels. For example, in the pixel array unit 21A, there may be a mixture of pixels that are driven when the level of the output voltage of the logic circuit is HIGH and pixels that are driven when the level of the output voltage of the logic circuit is LOW. Except for the fact that each pixel includes a logic circuit, the configuration of the pixel array unit 21A is the same as that of the above-described pixel array unit 21.

[0167] As a result, as shown in the example of FIG. 12, for each region of the pixels in the image sensor, the drive timing (phase of the pulse signal) can be set. In the example of FIG. 12, one of the phases P1 to P4 is periodically assigned to each square region. However, the assignment pattern in FIG. 12 is only an example. For example, the drive timing (phase of the pulse signal) may be set for each region having other shapes such as a polygon or a ring shape. Also, the order of assigning phases to each region is not particularly limited. The phase assignment order may be based on a predetermined rule or may be random.

[0168] As shown in FIG. 12, the timing control unit 32 may be connected to the system control unit 25. In this case, the timing control unit 32 may change the timing signal output to the pixel drive line 28 based on the control signal supplied from the system control unit 25. Thereby, it becomes possible to dynamically change the drive timing (phase of the pulse signal) in each region in the pixel array unit 21A.

[0169] In the image sensor of FIG. 12, the configuration of the column processing unit 23 and the circuits subsequent thereto is the same as that of the image sensors of FIGS. 10 and 11. Note that FIG. 12 is only an example of an image sensor in which the drive timing (phase of the pulse signal) can be set for each region. Therefore, the drive timing (phase of the pulse signal) of the pixels may be set for each region by a circuit having a configuration different from this.

[0170] As described above, the image sensor according to the present disclosure may be configured such that a pulse signal is supplied from different stages of a plurality of flip - flops depending on the region in the pixel array where the pixels are arranged.

[0171] FIG. 9 shows a pulse generator 30A capable of generating pulses with four phases (phases P1 to P4). However, the pulse generator 30A in FIG. 9 is only an example of an image sensor that can be used in the image sensor according to the present disclosure. For example, instead of the pulse generator 30A in FIG. 9, the pulse generator 30B in FIG. 13 may be used.

[0172] The pulse generator 30B in FIG. 13 corresponds to increasing the number of stages of the cascaded flip-flops in the pulse generator 30A in FIG. 9 from 4 to 8. Here, the pulse generator 30B will be described centering on the differences from the pulse generator 30A. Similar to FIG. 9, the Q terminal of the flip-flop 340 is connected to the circuit block 33 via the signal line L2. Also, the Q terminal and the D terminal of the flip-flops connected in a dependent manner are connected. Further, the circuit block 33 is connected to the CLK terminals of the flip-flops 340 to 347 via the signal line L1. The Q terminal of each flip-flop in the pulse generator 30B is connected to the corresponding output terminal (output terminals C1 to C8). The output terminals C1 to C8 are connected to the pixel drive line 28 or the pixel drive line 28A via different clock distribution circuits respectively.

[0173] In the examples of FIGS. 9 and 13, the Q terminals of all the cascaded flip-flops in the pulse generator are connected to any of the output terminals. However, it is not always necessary to connect the Q terminals of all the cascaded flip-flops to any of the output terminals. For example, when only a part of the phases of the generated pulse signal is required, the Q terminals of some of the cascaded flip-flops may be connected to the output terminals.

[0174] The operation of the pulse generator 30B is the same as that of the above-described pulse generator 30A except that the number of phases of the generated pulse signal increases. That is, based on the first frequency f1 of the first signal output by the circuit block 33 to the signal line L1 and the first frequency f2 of the second signal output by the circuit block 33 to the signal line L2, it is possible to adjust the timing deviation of the pulses output from the plurality of output terminals. Similar to FIG. 9, the phase delay Δθ caused by the second signal passing through one stage of the flip-flop is Δθ = 360 × f2 / f1. Similar to the above, let the phases of the pulse signals output from the output terminals C1 to C8 be P1 to P8 respectively.

[0175] For example, when f1 = 2.0 GHz and f2 = 250 MHz, Δθ = 45 degrees. In this case, as shown in FIG. 13, pulses are output from output terminals C1, C2, C3, C4, C5, C6, C7, and C8 at phases of 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees, and 315 degrees, respectively. That is, in the pulse generator 30B, the phases of the pulse signals are P1 = 0 degrees, P2 = 45 degrees, P3 = 90 degrees, P4 = 135 degrees, P5 = 180 degrees, P6 = 225 degrees, P7 = 270 degrees, and P8 = 315 degrees. The values of the first frequency f1 and the second frequency f2 described here are merely examples. Therefore, the first frequency f1 and the second frequency f2 may be set to different values.

[0176] Note that the other components of FIG. 13 (pulse generator 30B) are the same as those of FIG. 9. The image sensor according to the present disclosure only needs to include a pulse generator capable of generating pulses at a plurality (two or more) of phases (timings). Therefore, the number of stages of flip - flops in the pulse generator can be set to any number of two or more.

[0177] The pulse generators of FIGS. 9 and 13 are configured to include a plurality of output terminals, and pulse signals with different phases are output from each output terminal. However, the pulse generator according to the present disclosure may be configured to output any one of the pulse signals with a plurality of phases.

[0178] FIG. 14 shows a pulse generator 30C in which the number of stages of flip - flops is three and a multiplexer 36 is further implemented. Hereinafter, the pulse generator 30C of FIG. 14 will be described centering on the differences from FIGS. 9 and 13.

[0179] The multiplexer 36 has input terminals in1 to in3. In the pulse generator 30C, the Q terminals of the respective flip - flops are connected to the input terminals of the multiplexer 36. That is, the Q terminal of the flip - flop 340 is connected to the input terminal in1 of the multiplexer 36 via the signal line c1. The Q terminal of the flip - flop 341 is connected to the input terminal in2 of the multiplexer 36 via the signal line c2. Note that, among a plurality of cascaded flip - flops, only the Q terminals of some of the flip - flops may be connected to the input terminals of the multiplexer 36.

[0180] The Q terminal of the flip - flop 342 is connected to the input terminal in3 of the multiplexer 36 via the signal line c3. The control terminal of the multiplexer 36 is connected to the system control unit 25 via the signal line cnt. Also, the output terminal mout of the multiplexer 36 is connected to the output terminal of the pulse generator 30C.

[0181] The multiplexer 36 selects a signal supplied from the Q terminal of any one of the flip - flops based on a control signal supplied from the system control unit 25. Then, the multiplexer 36 outputs the selected signal to the circuit at the subsequent stage from the output terminal mout. That is, the pulse generator 30C can output a pulse signal of any one of the phases P1 to P3 according to the setting by the system control unit 25. Also in FIG. 14, the equation regarding the above - mentioned phase delay Δθ holds.

[0182] The circuit block 33A of the pulse generator 30C includes a frequency - dividing circuit 35. The frequency - dividing circuit 35 is, for example, a 1 - time frequency - dividing circuit. However, the frequency - division ratio of the frequency - dividing circuit may be different from this. The frequency - division ratio of the frequency - dividing circuit can be determined according to the clock frequency f0 and the first frequency f1 of the first signal to be generated. The input side of the frequency - dividing circuit 35 is connected to the PLL 31 via the signal line L0. Also, the output side of the frequency - dividing circuit 35 is connected to the CLK terminals of the flip - flops 340 to 342 via the signal line L1.

[0183] Therefore, a first signal with a first frequency f1 that is 1 / 2 of the clock frequency f0 is supplied to the CLK terminals of the flip-flops 340 to 342 via the signal line L1. For example, when the clock frequency f0 generated by the PLL 31 is 1.6 GHz, the first frequency f1 of the first signal is 800 MHz. When the second frequency f2 of the second signal output from the circuit block 33A via the signal line L2 is 100 MHz, the phase delay Δθ caused by the second signal passing through one stage of flip-flop is Δθ = 45 degrees. Therefore, assuming the phase P1 is 0 degrees, the phase P2 is 45 degrees and the phase P3 is 90 degrees. Note that the circuit block 33A may generate a second signal synchronized with the first signal.

[0184] The clock frequency f0, the first frequency f1, and the second frequency f2 described here are merely examples. Therefore, in the pulse generator according to the present disclosure, signals with different frequencies may be used. Also, as described above, the first frequency f1 of the first signal and the second frequency f2 of the second signal generated by the circuit block may be adjustable (variable) frequencies instead of fixed frequencies.

[0185] As described above, the image sensor according to the present disclosure may further include a multiplexer configured to select a pulse signal supplied to the pixels in the pixel array. Also, the circuit block may further include a frequency division circuit that generates a first signal based on a clock signal.

[0186] In the example of FIG. 14, the number of stages of the flip-flop is 3, but the number of stages of the flip-flop may be different from this. For example, it is possible to cascade-connect any number of two or more flip-flops to generate pulse signals related to a plurality of phases. When the number of stages of the flip-flop increases compared to the example of FIG. 14, a multiplexer with three or more input terminals may be used, or a plurality of multiplexers may be implemented in the pulse generator.

[0187] FIG. 15 shows an example of an imaging device provided with a plurality of pulse generators 30C of FIG. 14. FIG. 15 includes a system control unit 25, a pixel driving unit 22C, a pixel array unit 21, and a column processing unit 23. The pixel driving unit 22C includes a PLL 31 (signal generator), a pulse generator 30C-1, a pulse generator 30C-2, a pulse generator 30C-3, and a circuit block 370A. The pulse generators 30C-1, 30C-2, and 30C-3 correspond to the pulse generator 30C of FIG. 14. Further, the circuit block 370A includes clock distribution circuits 371 to 373. The clock distribution circuits 371 to 373 are, for example, clock tree type circuits, but the type of the clock distribution circuit is not limited.

[0188] The PLL 31 is connected to the signal lines L0 of the pulse generators 30C-1, 30C-2, and 30C-3. The output terminals of the pulse generators 30C-1, 30C-2, and 30C-3 are connected to any one of the clock distribution circuits in the circuit block 370A. Also, each pixel column in the pixel array unit 21 is connected to any one of the clock distribution circuits 371 to 373 via the pixel driving line 28A. And each pixel column in the pixel array unit 21 is connected to the column processing unit 23 via the vertical signal line 29.

[0189] In the example of FIG. 15, it is assumed that the pulse generator 30C-1 outputs a pulse signal with a phase P1 = 0 degrees, the pulse generator 30C-2 outputs a pulse signal with a phase P2 = 45 degrees, and the pulse generator 30C-3 outputs a pulse signal with a phase P3 = 90 degrees. Therefore, the pixel columns in the pixel array unit 21 connected to the pulse generator 30C-1 via any one of the clock distribution circuits are driven by the pulse signal with the phase P1. On the other hand, the pixel columns in the pixel array unit 21 connected to the pulse generator 30C-2 via any one of the clock distribution circuits are driven by the pulse signal with the phase P2. Also, the pixel columns in the pixel array unit 21 connected to the pulse generator 30C-3 via any one of the clock distribution circuits are driven by the pulse signal with the phase P3.

[0190] By using the imaging device of FIG. 15, it becomes possible to dynamically change the timing at which each pixel column in the pixel array unit 21 is driven. That is, in the imaging device of FIG. 15, among the phases that each pulse generator can generate, at least one of the pulse signals can be used to drive the pixel columns in the pixel array unit 21. For this reason, it is also possible to drive all the pixels in the pixel array unit 21 at almost the same timing as in the example of FIG. 8 according to the usage. Also, during the operation of the imaging device, the number of phases used for driving the pixels in the pixel array unit 21 can be changed.

[0191] In the imaging device of FIG. 15, the driving timing (phase of the pulse signal) can be set for each pixel column in the pixel array unit 21. However, the setting unit of the driving timing (phase of the pulse signal) is not limited to the pixel column. For example, the driving timing (phase of the pulse signal) may be set for each pixel row as in the example of FIG. 11. Also, the driving timing (phase of the pulse signal) may be set for each region in the pixel array unit 21 as in the example of FIG. 12.

[0192] As described above, when using the imaging device according to the present disclosure, it is possible to drive the pixels in the pixel array at a plurality of timings without driving all the pixels in the pixel array at the same timing all at once. Thereby, the total current of the drive signal at each drive timing can be suppressed. For this reason, it becomes possible to improve the resolution of the distance image while suppressing the generation of electromagnetic noise.

[0193] (Configuration example of an electronic device) Figures 16 and 17 show examples of electronic devices according to the present disclosure. FIG. 16 shows the configuration of the electronic device 1 when viewed from the positive z-axis direction side. On the other hand, FIG. 17 shows the configuration of the electronic device 1 when viewed from the negative z-axis direction side. The electronic device 1 is, for example, substantially flat and has a display unit 1a on at least one surface (here, the surface on the positive z-axis direction side). The display unit 1a can display an image, for example, by liquid crystal, micro LED, or organic electroluminescence method. However, the display method in the display unit 1a is not limited. Also, the display unit 1a may include a touch panel and a fingerprint sensor.

[0194] On the surface of the electronic device 1 on the negative z-axis direction side, a first imaging unit 110, a second imaging unit 111, a first light emitting unit 112, and a second light emitting unit 113 are mounted. The first imaging unit 110 is, for example, a camera module capable of taking a color image. The camera module includes, for example, a lens system and an imaging element that performs photoelectric conversion of the light collected by the lens system. The first light emitting unit 112 is, for example, a light source used as a flash for the first imaging unit 110. As the first light emitting unit 112, for example, a white LED can be used. However, the type of the light source used as the first light emitting unit 112 is not limited.

[0195] The second imaging unit 111 is, for example, an imaging element capable of distance measurement by an indirect ToF method. As the second imaging unit 111, for example, the imaging element according to the present disclosure can be mounted. The second imaging unit 111 corresponds to, for example, the light receiving unit 1013 in FIG. 7. The second light emitting unit 113 is a light source that can be used for distance measurement by an indirect ToF method. The second light emitting unit 113 corresponds to, for example, the light emitting unit 1011 in FIG. 7. That is, the distance measurement module 1000 in FIG. 7 may be mounted on the electronic device 1. The electronic device 1 can execute various processes based on the distance image output from the distance measurement module 1000.

[0196] Here, the case where the electronic device according to the present disclosure is a smartphone or a tablet has been described. However, the electronic device according to the present disclosure may be other types of devices such as, for example, a game machine, an in-vehicle device, a PC, a surveillance camera, and the like.

[0197] The distance measuring device according to the present disclosure may include a signal generator, a plurality of flip-flops connected in series, a circuit block, a pixel array, and a signal processing unit. The signal generator is configured to generate a clock signal. The circuit block is configured to supply a first signal to each clock terminal of the plurality of flip-flops and a second signal to the input terminal of the first-stage flip-flop of the plurality of flip-flops in response to the clock signal. The pixel array includes pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops. The signal processing unit is configured to generate a distance image based on charges generated by photoelectric conversion in the pixels of the pixel array.

[0198] The electronic device according to the present disclosure may include a signal generator, a plurality of flip-flops connected in series, a circuit block, and a pixel array. The signal generator is configured to generate a clock signal. The circuit block is configured to supply a first signal to each clock terminal of the plurality of flip-flops and a second signal to the input terminal of the first-stage flip-flop of the plurality of flip-flops in response to the clock signal. The pixel array includes pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops.

[0199] (Application Example to a Moving Body) The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, and the like.

[0200] FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a movement control system to which the technology according to the present disclosure can be applied.

[0201] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 18, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0202] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for a driving force generation device for generating a driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0203] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp. In this case, radio waves transmitted from a portable device substituting for a key or signals of various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these inputs of radio waves or signals and controls a door lock device, a power window device, lamps, etc. of the vehicle.

[0204] The vehicle external information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle external information detection unit 12030. The vehicle external information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The vehicle external information detection unit 12030 may perform object detection processing or distance detection processing on a person, a vehicle, an obstacle, a sign, or characters on the road surface, etc., based on the received image.

[0205] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared light.

[0206] The vehicle interior information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 may calculate the degree of driver fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0207] The microcomputer 12051 calculates control target values for the driving force generation device, the steering mechanism, or the braking device based on the vehicle interior and exterior information acquired by the vehicle external information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for realizing functions of an ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, collision warning of the vehicle, or lane departure warning of the vehicle.

[0208] Further, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving or the like in which it autonomously travels without relying on the driver's operation by controlling a driving force generator, a steering mechanism, a braking device, or the like based on information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040.

[0209] Also, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for the purpose of anti-glare, such as controlling the headlamp according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030 and switching the high beam to the low beam.

[0210] The audio-visual output unit 12052 transmits at least one of an audio output signal and a video output signal to an output device capable of notifying information visually or auditorily to the vehicle occupants or the outside of the vehicle. In the example of FIG. 18, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are illustrated as the output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0211] FIG. 19 is a diagram showing an example of the installation position of the imaging unit 12031.

[0212] In FIG. 19, the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0213] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose of the vehicle 12100, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or the back door mainly acquires images behind the vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used for detecting a preceding vehicle or detecting pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0214] Note that FIG. 19 shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the back door. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 seen from above can be obtained.

[0215] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0216] For example, based on the distance information obtained from imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each solid object within the imaging ranges 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100). Thus, it can extract, as the leading vehicle, the closest solid object on the traveling path of the vehicle 12100 that is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more). Further, the microcomputer 12051 can set the inter-vehicle distance that should be secured in advance in front of the leading vehicle and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, etc., without relying on the driver's operation.

[0217] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 classifies and extracts solid object data regarding solid objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other solid objects, and can use it for automatic avoidance of obstacles. For example, the microcomputer 12051 discriminates obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and there is a possibility of collision, it can output an alarm to the driver via the audio speaker 12061 or the display unit 12062, or perform forced deceleration or avoidance steering via the drive system control unit 12010 to provide driving assistance for collision avoidance.

[0218] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian exists in the captured image of the imaging units 12101 to 12104. Such recognition of a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as an infrared camera and a procedure of performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured image of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio-visual image output unit 12052 controls the display unit 12062 to superimpose and display a rectangular outline for emphasizing the recognized pedestrian. Further, the audio-visual image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0219] As described above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, an image sensor according to the present disclosure can be mounted on the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to improve the resolution of the distance image while suppressing the generation of electromagnetic noise, and to enhance the functionality and safety of the vehicle 12100.

[0220] Note that the present technology can be configured as follows. (1) A signal generator configured to generate a clock signal, A plurality of flip-flops connected in series, A circuit block configured to supply a first signal to each clock terminal of the plurality of flip-flops in response to the clock signal and supply a second signal to an input terminal of the first-stage flip-flop of the plurality of flip-flops. A pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops, An image sensor comprising the same. (2) The pixel in the pixel array includes a signal extraction unit configured to detect charges generated by photoelectric conversion when the pulse signal is supplied. The image sensor according to (1). (3) The pixel in the pixel array includes a plurality of the signal extraction units, and each of the signal extraction units is configured to detect the charges generated at different timings. The image sensor according to (2). (4) The image sensor further includes a plurality of clock distribution circuits connected to any of the stages of the plurality of flip-flops on the input side and connected to the pixels in the pixel array via drive lines on the output side. The image sensor according to any one of (1) to (3). (5) At least any one of the clock distribution circuits is of a clock tree type. The image sensor according to (4). (6) A pixel column or a pixel row in the pixel array is configured to be driven by the pulse signal supplied from the common stage of the plurality of flip-flops. The image sensor according to any one of (1) to (5). (7) The pulse signal is configured to be supplied from different stages of the plurality of flip-flops by an area in the pixel array where the pixels are arranged. The image sensor according to any one of (1) to (6). (8) The image sensor further includes a multiplexer configured to select the pulse signal supplied to the pixels in the pixel array. The image sensor according to any one of (1) to (7). (9) The circuit block is configured to output the first signal of a first frequency and output the second signal of a second frequency different from the first frequency. The imaging device according to any one of (1) to (8). (10) The circuit block is configured to output the first signal and the second signal synchronized with each other. The imaging device according to any one of (1) to (9). (11) The circuit block further includes a frequency division circuit that generates the first signal based on the clock signal. The imaging device according to any one of (1) to (10). (12) The circuit block is configured to output the first signal of a first frequency equal to the clock frequency of the clock signal. The imaging device according to any one of (1) to (10). (13) The circuit block further includes a control unit configured to output a control signal to the circuit block. The circuit block is configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the supplied control signal. The imaging device according to any one of (1) to (12). (14) A signal generator configured to generate a clock signal, A plurality of flip-flops connected in series, A circuit block configured to supply the first signal to each clock terminal of the plurality of flip-flops in response to the clock signal and supply the second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops, A pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops, A signal processing unit configured to generate a distance image based on charges generated by photoelectric conversion in the pixels of the pixel array; A distance measuring device comprising the same. (15) A signal generator configured to generate a clock signal; A plurality of flip-flops connected in series; A circuit block configured to supply a first signal to clock terminals of each of the plurality of flip-flops in response to the clock signal and supply a second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops; A pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops; An electronic device comprising the same.

[0221] Aspects of the present disclosure are not limited to the individual embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described content. That is, various additions, changes, and partial deletions are possible without departing from the conceptual ideas and spirits of the present disclosure derived from the content defined in the claims and their equivalents.

Description of Reference Numerals

[0222] 1 Electronic device 11, 11A Image sensor 21 Pixel array unit 22, 22A, 22B Pixel driving unit 23 Column processing unit 24 Read driving unit 25 System control unit 26 Signal processing unit 27 Data storage unit 30, 30A, 30B, 30C, 30C-1, 30C-2, 30C-3 Pulse generator 31 PLL 32 Timing control unit 33, 33A, 370, 370A, 380 Circuit block 35 Frequency division circuit 36 Multiplexer 37, 371, 372, 373, 374, 381, 382, 383, 384 Clock Distribution Circuit 240 Analog-to-Digital Converter 340, 341, 342, 343, 344, 345, 346, 347 Flip-Flop 1000 Distance Measurement Module 1011 Light Emitting Unit 1012 Light Emission Control Unit 1013 Light Receiving Unit

Claims

1. A signal generator configured to generate a clock signal; A plurality of flip-flops connected in series; A circuit block configured to supply a first signal to clock terminals of each of the plurality of flip-flops and supply a second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops in response to the clock signal; A pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops; A timing control unit configured to output a timing signal to the pixels in the pixel array based on the pulse signal; A system control unit configured to supply a control signal to the timing control unit; comprising: The pixels in the pixel array are: Each provided with a logic circuit that performs an operation based on the pulse signal and the timing signal; The pixels are configured to be driven when the output voltage level of the logic circuit satisfies a predetermined condition for each pixel; The timing control unit is configured to change the timing signal output to the pixels based on the control signal. An image sensor.

2. The pixels in the pixel array include a signal extraction unit configured to detect charges generated by photoelectric conversion when the pulse signal is supplied. The image sensor according to claim 1.

3. The pixels in the pixel array include a plurality of the signal extraction units, and each of the signal extraction units is configured to detect the charges generated at different timings. The image sensor according to claim 2.

4. Further comprising a plurality of clock distribution circuits connected to any one of the plurality of flip-flops on the input side and connected to the pixels in the pixel array via a driving line on the output side. The imaging device according to claim 1.

5. At least any one of the clock distribution circuits is a clock tree type. The imaging device according to claim 4.

6. The pixel columns or pixel rows in the pixel array are configured to be driven by the pulse signal supplied from the common stage of the plurality of flip-flops. The imaging device according to claim 1.

7. The pulse signal is configured to be supplied from different stages of the plurality of flip-flops according to the region in the pixel array where the pixels are arranged. The imaging device according to claim 1.

8. Further comprising a multiplexer configured to select the pulse signal supplied to the pixels in the pixel array. The imaging device according to claim 1.

9. The circuit block is configured to output the first signal of the first frequency and the second signal of the second frequency different from the first frequency. The imaging device according to claim 1.

10. The circuit block is configured to output the first signal and the second signal synchronized with each other. The imaging device according to claim 1.

11. The circuit block further includes a frequency division circuit that generates the first signal based on the clock signal. The imaging device according to claim 1.

12. The circuit block is configured to output the first signal having a first frequency equal to the clock frequency of the clock signal. The imaging device according to claim 1.

13. The apparatus further includes a control unit configured to output a control signal to the circuit block. The circuit block is configured to adjust the first frequency of the first signal or the second frequency of the second signal based on the supplied control signal. The imaging device according to claim 1.

14. A signal generator configured to generate a clock signal, A plurality of flip-flops connected in series, A circuit block configured to supply a first signal to respective clock terminals of the plurality of flip-flops in response to the clock signal and supply a second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops, A pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops, A signal processing unit configured to generate a distance image based on charges generated by photoelectric conversion in the pixels of the pixel array, A timing control unit configured to output a timing signal to the pixels in the pixel array based on the pulse signal, A system control unit configured to supply a control signal to the timing control unit, and includes The pixels in the pixel array each include a logic circuit that performs an operation based on the pulse signal and the timing signal, The pixels are configured to be driven when an output voltage level of the logic circuit satisfies a predetermined condition for each pixel, The timing control unit is configured to change the timing signal output to the pixels based on the control signal. Distance measuring device.

15. A signal generator configured to generate a clock signal; A plurality of flip-flops connected in series; A circuit block configured to supply a first signal to each clock terminal of the plurality of flip-flops and a second signal to an input terminal of a first-stage flip-flop of the plurality of flip-flops in response to the clock signal; A pixel array including pixels configured to be driven by pulse signals supplied from different stages of the plurality of flip-flops; A timing control unit configured to output a timing signal to the pixels in the pixel array based on the pulse signals; A system control unit configured to supply a control signal to the timing control unit; comprising The pixels in the pixel array each include a logic circuit that performs an operation based on the pulse signal and the timing signal; The pixels are configured to be driven when the output voltage level of the logic circuit satisfies a predetermined condition for each pixel; The timing control unit is configured to change the timing signal output to the pixels based on the control signal. Electronic device.

Images