Audio circuit, electronic device using the same, and in-vehicle audio system

Abstract

This class-D amplification circuit 200 receives an analog audio signal VIN that uses a first reference voltage VFIL as a center level, and outputs an output pulse signal SOUT that has a duty cycle corresponding to the analog audio signal VIN. A bias circuit 310 generates a second reference voltage VFILP that has a voltage level obtained by dividing the first reference voltage VFIL and a power supply voltage VCC. A cyclic voltage generation circuit 260 of the class-D amplification circuit 200 generates a cyclic voltage VOSC of a sawtooth wave or a triangular wave having an amplitude corresponding to the second reference voltage VFILP.

Description

[Technical field]

[0001] The present disclosure relates to an audio amplifier circuit that drives a speaker or a headphone. [Background technology]

[0002] A highly efficient class D amplifier is used as a power amplifier for driving an electroacoustic conversion element such as a speaker or a headphone. Fig. 1 is a block diagram of an audio system 100R using a class D amplifier. The audio system 100R mainly includes a speaker 102, a low-pass filter 104, and an audio circuit 900R.

[0003] The audio circuit 900R includes a class-D amplifier circuit 200R. The class-D amplifier circuit 200R receives an analog audio signal V IN An output pulse signal S having a duty cycle according to OUT The low-pass filter 104 generates the output pulse signal S of the class-D amplifier circuit 200R. OUT The high frequency components are removed and the signal is supplied to the speaker 102.

[0004] The class D amplifier circuit 200R is a class D amplifier with feedback, and includes an integrator 210, a periodic voltage generating circuit 220, a PWM (Pulse Width Modulation) comparator 230, and a bridge circuit 240.

[0005] The integrator 210 includes resistors R11 and R12, a capacitor C11, and an error amplifier 212. An analog audio signal V is input to an inverting input terminal (−) of the error amplifier 212 via a first resistor R11. IN is input, and the output pulse signal S OUT Feedback signal V according to FB The capacitor C11 is provided between the output and the inverting input terminal of the error amplifier 212, and the reference voltage V COM The gain g of this class D amplifier circuit 200R is Dis given by R12 / R11.

[0006] The periodic voltage generation circuit 220 generates a periodic voltage V of a triangular wave or a sawtooth wave. OSC The periodic voltage V OSC is a carrier wave for pulse width modulation. The frequency of the periodic voltage V OSC is the PWM frequency, which is higher than the audible frequency band (20 Hz to 20 kHz) and is determined in the range of several hundred kHz to several MHz. The PWM comparator 230 compares the output signal V INT of the integrator 210 with the periodic voltage V OSC and generates a PWM signal S PWM that takes high or low according to the comparison result.

[0007] The driver 250 switches the high-side transistor MH and the low-side transistor ML of the bridge circuit 240 complementarily according to the PWM signal S PWM The driver 250 inserts a dead time so that the high-side transistor MH and the low-side transistor ML do not turn on simultaneously.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] In the audio circuit 900R of FIG. 1, the amplitude of the periodic voltage V OSC generated by the periodic voltage generation circuit 220 was fixed regardless of the power supply voltage V CC .

[0010] The voltage range of the output voltage V INT of the integrator 210 needs to be included between the peak and the bottom of the periodic voltage V OSC . Therefore, the analog audio signal V INThe maximum amplitude ΔV MAX was restricted by the amplitude ΔV OSC of the periodic voltage V OSC . Specifically, the amplitude ΔV OSC of the periodic voltage V OSC was fixed at about 2Vpp, for example, and the center level V IN of the analog audio signal V BIAS was 2.5V, and its maximum amplitude ΔV MAX was determined to be 5Vpp.

[0011] Even when the audio circuit 900R in FIG. 1 is used in a system where the power supply voltage V CC is large, in other words, the amplitude of the output pulse signal S OUT is large, the amplitude (signal level) of the input voltage V IN is restricted by the periodic voltage V OSC and cannot be increased.

[0012] Also, in the audio system 100R, in order to obtain a full-scale output, the gain g of the class-D amplifier circuit 200R needs to be designed as (V CC / ΔV MAX ) times. When V CC = 15V and ΔV MAX = 5V, the gain g of the integrator 210 needs to be 3 times. A large gain g is a factor in the deterioration of the noise characteristics.

[0013] The present disclosure has been made in view of such problems, and an exemplary object of one of its aspects is to provide an audio circuit capable of flexible signal level design according to the power supply voltage.

Means for Solving the Problems

[0014] The audio circuit according to the present disclosure includes a class-D amplifier circuit that receives an analog audio signal having a first reference voltage as a center level and outputs an output pulse signal having a duty cycle corresponding to the analog audio signal, and a bias circuit that generates a second reference voltage having a voltage level obtained by dividing the first reference voltage and a power supply voltage. The class-D amplifier circuit includes an integrator that receives a feedback signal corresponding to the analog audio signal and the output pulse signal, a periodic voltage generation circuit that generates a periodic voltage of a triangular wave or a sawtooth wave, a PWM (Pulse Width Modulation) comparator that compares the output of the integrator with the periodic voltage, a bridge circuit supplied with a power supply voltage, and a driver that drives the bridge circuit according to the output of the PWM comparator. The integrator includes a first operational amplifier that receives the second reference voltage at a non-inverting input terminal, a first resistor having an analog audio signal input to one end and the other end connected to the inverting input terminal of the first operational amplifier, and a second resistor having a feedback signal input to one end and the other end connected to the inverting input terminal of the first operational amplifier. The periodic voltage generation circuit generates a periodic voltage having an amplitude corresponding to the second reference voltage.

[0015] In addition, any combination of the above components, and those obtained by converting the expression of the present invention between methods, devices, etc., are also effective as aspects of the present invention. Furthermore, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore, sub-combinations of these described features can also be the present invention.

Effects of the Invention

[0016] According to an aspect of the present disclosure, flexible signal level design is possible according to the power supply voltage.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

DETAILED DESCRIPTION OF THE INVENTION

[0018] (Overview of the Embodiment) The overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description to follow, and is intended to provide a basic understanding of the embodiments by simplifying and explaining some concepts of one or more embodiments. It is not intended to limit the scope of the invention or the disclosure. Also, this overview is not an all-inclusive overview of all possible embodiments and does not limit essential components of the embodiments. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed in this specification.

[0019] An audio circuit according to an embodiment receives an analog audio signal having a first reference voltage as a center level, and outputs an output pulse signal having a duty cycle corresponding to the analog audio signal. The D-class amplifier circuit includes a bias circuit that generates a second reference voltage having a voltage level obtained by dividing the first reference voltage and the power supply voltage. The D-class amplifier circuit includes an integrator that receives a feedback signal corresponding to the analog audio signal and the output pulse signal, a periodic voltage generation circuit that generates a triangular wave or a sawtooth periodic voltage, a PWM (Pulse Width Modulation) comparator that compares the output of the integrator with the periodic voltage, a bridge circuit to which the power supply voltage is supplied, and a driver that drives the bridge circuit according to the output of the PWM comparator. The integrator includes a first operational amplifier that receives the second reference voltage at a non-inverting input terminal, a first resistor having an analog audio signal input to one end and the other end connected to the inverting input terminal of the first operational amplifier, and a second resistor having a feedback signal input to one end and the other end connected to the inverting input terminal of the first operational amplifier. The periodic voltage generation circuit generates a periodic voltage having an amplitude corresponding to the second reference voltage.

[0020] According to this configuration, the second reference voltage supplied to the integrator changes following the power supply voltage, and the amplitude of the periodic voltage serving as the carrier wave of pulse width modulation also changes according to the second reference voltage. As a result, the degree of freedom in designing the signal level of the analog audio signal is increased.

[0021] In one embodiment, it is also possible to set the signal level (center level and maximum amplitude) of the analog audio signal so as to be proportional to the power supply voltage. In that case, it is also possible to keep the gain of the D-class amplifier circuit constant regardless of the power supply voltage.

[0022] Also, in one embodiment, when the power supply voltage is high, it is possible to set the gain of the D-class amplifier circuit low by increasing the signal level (center level and maximum amplitude) of the analog audio signal, thereby suppressing the deterioration of noise characteristics.

[0023] In one embodiment, the periodic voltage generation circuit may include a clock generation circuit that generates a first clock signal having an amplitude equal to twice the second reference voltage, and a triangular wave generation circuit that generates a periodic voltage based on the first clock signal. Thereby, a triangular wave having the second reference voltage as the center level can be generated.

[0024] In one embodiment, the clock generation circuit receives a second clock signal having a frequency twice that of the periodic voltage, and includes a level shift circuit that level-shifts the high-level voltage of the second clock signal to a voltage level twice that of the second reference voltage, and a frequency divider that divides the third clock signal after level-shifting by the level shift circuit by 1 / 2 to generate the first clock signal. Thereby, the duty cycle of the first clock signal can be maintained at 50%, and the quality of the triangular wave waveform can be improved.

[0025] In one embodiment, the frequency divider may include a flip-flop.

[0026] In one embodiment, the triangular wave generation circuit includes a second operational amplifier, a third resistor having one end receiving the first clock signal and the other end connected to the inverting input terminal of the second operational amplifier, a first capacitor provided between the output terminal and the inverting input terminal of the second operational amplifier, a third operational amplifier having its non-inverting input terminal receiving the second reference voltage and its output terminal connected to the non-inverting input terminal of the second operational amplifier, a fourth resistor having one end connected to the output terminal of the second operational amplifier and the other end connected to the inverting input terminal of the third operational amplifier, and a second capacitor provided between the output terminal and the inverting input terminal of the third operational amplifier. The output voltage of the second operational amplifier may be the periodic voltage. According to this configuration, the voltage supplied to the non-inverting input terminal of the second operational amplifier is adjusted so that the center level of the periodic voltage approaches the second reference voltage. As a result, variations in the output impedance of the clock generation circuit and deterioration of characteristics due to power supply voltage fluctuations can be suppressed.

[0027] In one embodiment, the bias circuit may include a first voltage dividing circuit that generates a midpoint voltage which is half of the power supply voltage, and a second voltage dividing circuit that divides the first reference voltage and the midpoint voltage.

[0028] In one embodiment, the voltage division ratio of the second voltage dividing circuit may be equal to the gain of the class-D amplifier circuit. Thereby, the class-D amplifier circuit can be operated at an optimal operating point according to the power supply voltage.

[0029] In one embodiment, the audio circuit may be integrally integrated on one substrate. "Integrally integrated" includes cases where all of the circuit components are formed on the substrate, or cases where the main components of the circuit are integrally integrated. Some resistors, capacitors, etc. may be provided outside the substrate for adjusting circuit constants. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0030] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and repeated descriptions will be omitted as appropriate. Also, the embodiments are illustrative rather than limiting the disclosure and the invention, and not all of the features described in the embodiments and their combinations are necessarily essential to the disclosure and the invention.

[0031] In this specification, the state where "member A is connected to member B" includes cases where member A and member B are physically directly connected, and cases where member A and member B are indirectly connected via other members that do not affect the electrical connection state or inhibit the function.

[0032] Similarly, the state where "member C is provided between member A and member B" includes cases where member A and member C, or member B and member C are directly connected, as well as cases where they are indirectly connected via other members that do not affect the electrical connection state or inhibit the function.

[0033] FIG. 2 is a block diagram of an audio system 100 including an audio circuit 300 according to an embodiment. The audio system 100 includes a speaker 102, a low-pass filter 104, and an audio circuit 300.

[0034] The audio circuit 300 includes a class-D amplifier circuit 200 and a bias circuit 310, and is configured as a functional IC (Integrated Circuit) integrated on one semiconductor chip. A power supply voltage V is supplied to the power supply pin VCC of the audio circuit 300 from the outside. CC is supplied.

[0035] An analog audio signal V having a first reference voltage V as a center level is input to the class-D amplifier circuit 200. The class-D amplifier circuit 200 generates an output pulse signal S having a duty cycle corresponding to the analog audio signal V. The low-pass filter 104 removes high-frequency components of the output pulse signal S of the class-D amplifier circuit 200 and supplies it to the speaker 102. FIL as a center level is input to the class-D amplifier circuit 200. The class-D amplifier circuit 200 generates an output pulse signal S having a duty cycle corresponding to the analog audio signal V. The low-pass filter 104 removes high-frequency components of the output pulse signal S of the class-D amplifier circuit 200 and supplies it to the speaker 102. IN is input. The class-D amplifier circuit 200 generates an output pulse signal S having a duty cycle corresponding to the analog audio signal V. The low-pass filter 104 removes high-frequency components of the output pulse signal S of the class-D amplifier circuit 200 and supplies it to the speaker 102. IN to the speaker 102. OUT having a duty cycle corresponding to the analog audio signal V. The low-pass filter 104 removes high-frequency components of the output pulse signal S of the class-D amplifier circuit 200 and supplies it to the speaker 102. OUT having a duty cycle corresponding to the analog audio signal V. The low-pass filter 104 removes high-frequency components of the output pulse signal S of the class-D amplifier circuit 200 and supplies it to the speaker 102.

[0036] A first reference voltage V (or a voltage proportional thereto) and a power supply voltage V (or a voltage proportional thereto) are supplied to the bias circuit 310. The bias circuit 310 generates a second reference voltage V obtained by dividing the first reference voltage V and the power supply voltage V. FIL (or a voltage proportional thereto) and a power supply voltage V (or a voltage proportional thereto) are supplied to the bias circuit 310. The bias circuit 310 generates a second reference voltage V obtained by dividing the first reference voltage V and the power supply voltage V. CC (or a voltage proportional thereto) are supplied to the bias circuit 310. The bias circuit 310 generates a second reference voltage V obtained by dividing the first reference voltage V and the power supply voltage V. FIL and the power supply voltage V are supplied to the bias circuit 310. The bias circuit 310 generates a second reference voltage V obtained by dividing the first reference voltage V and the power supply voltage V. CC are supplied to the bias circuit 310. The bias circuit 310 generates a second reference voltage V obtained by dividing the first reference voltage V and the power supply voltage V. FILP obtained by dividing the first reference voltage V and the power supply voltage V.

[0037] The class-D amplifier circuit 200 is a class-D amplifier with feedback, and includes an integrator 210, a periodic voltage generation circuit 260, a PWM (Pulse Width Modulation) comparator 230, and a bridge circuit 240.

[0038] The integrator 210 includes resistors R11 and R12, a capacitor C11, and an error amplifier 212. An analog audio signal V IN is input to the inverting input terminal (-) of the error amplifier 212 via the first resistor R11, and a feedback signal V OUT corresponding to the output pulse signal S FB is input via the second resistor R12. The capacitor C11 is provided between the output of the error amplifier 212 and the inverting input terminal, and a second reference voltage V FILP is input to the non-inverting input terminal of the error amplifier 212. The gain g D of this class-D amplifier circuit 200 is given by R12 / R11.

[0039] The class-D amplifier circuit 200 may be configured such that its gain is variable and freely changeable by the designer of the audio system 100.

[0040] Preferably, the second reference voltage V FILP is generated to satisfy the following equation. V FILP =(V CC / 2×R12 + V FIL ×R11) / (R11 + R12)

[0041] The periodic voltage generation circuit 260 generates a periodic voltage V OSC that is a triangular wave or a sawtooth wave. The periodic voltage V OSC is a carrier wave for pulse width modulation. The frequency of the periodic voltage V OSC is the PWM frequency, which is higher than the audible frequency band (20 Hz to 20 kHz) and is determined in the range of several hundred kHz to several MHz.

[0042] The PWM comparator 230 compares the output signal V INT of the integrator 210 with the periodic voltage V OSC and generates a PWM signal S PWM that takes high and low levels according to the comparison result.

[0043] The bridge circuit 240 is a push-pull type inverter, and the power supply voltage V CCis being supplied. The bridge circuit 240 includes a high-side transistor MH and a low-side transistor ML. The high-side transistor MH may be a PMOS transistor or an NMOS transistor.

[0044] Driver 250 is a PWM signal S PWM In response, the high-side transistor MH and the low-side transistor ML of the bridge circuit 240 are switched complementarily. The driver 250 inserts a dead time so that the high-side transistor MH and the low-side transistor ML do not turn on simultaneously.

[0045] A second reference voltage V FILP is being supplied to the periodic voltage generation circuit 260. The periodic voltage generation circuit 260 generates a periodic voltage V FILP having a peak-to-peak amplitude ΔV OSC in response to the second reference voltage V OSC For example, the amplitude ΔV OSC can be set to V CC / N (N is a constant), and for example, N = 4 may be used.

[0046] The above is the configuration of the audio circuit 300. Next, its operation will be described. FIGS. 3(a) to 3(e) are diagrams for explaining the operation of the audio circuit 300 of FIG. 2. FIGS. 3(a) to 3(e) show different combinations of the power supply voltage V CC , the gain of the class-D amplifier circuit 200, and the signal levels of the analog audio signal V IN .

[0047] For ease of understanding, in FIGS. 3(a) and 3(c), V CC = 10V, and in FIGS. 3(b), 3(d), and 3(e), V CC = 15V. Also, in FIGS. 3(a) and 3(b), V FIL = 2.5V, in FIGS. 3(c) and 3(d), V FIL = 5V, and in FIG. 3(e), V FIL = 7.5V. The gains in FIGS. 3(a) to 3(e) are set to 2 times, 3 times, 1 time, 1.5 times, and 1 time, respectively.

[0048] In each of FIGS. 3(a) to 3(e), the second reference voltage V OSC at the center level of the periodic voltage V FILP is 4.17V, 6.25V, 5V, 6.5V, and 7.5V, respectively. Also, the peak-to-peak amplitude ΔV OSC of the periodic voltage V OSC in each of FIGS. 3(a) to 3(e) is 1 / 4 times the power supply voltage V DD , which is 2.5V, 3.75V, 2.5V, 3.75V, and 3.5V. In any case, the analog audio signal V IN can be amplified to full scale to drive the speaker 102.

[0049] Thus, according to the audio circuit 300 according to this embodiment, a flexible signal level design becomes possible according to the power supply voltage V CC .

[0050] For example, as shown in FIGS. 3(c) and 3(e), it is possible to set the signal level (center level and maximum amplitude) of the analog audio signal V CC to be proportional to the power supply voltage V IN . In that case, it is possible to keep the gain of the class D amplifier circuit 200 constant regardless of the power supply voltage V CC .

[0051] Also, as shown in FIGS. 3(c), 3(e), or 3(d), when the power supply voltage V CC is high, by increasing the signal level (center level and maximum amplitude) of the analog audio signal V IN , it is possible to set the gain of the class D amplifier circuit 200 low. Thereby, the noise characteristics can be improved compared to the case where the gain of the class D amplifier circuit 200 is high (for example, 3 times).

[0052] Alternatively, the signal level of the analog audio signal V IN may be determined according to the set value of the volume. Thereby, full-scale output becomes possible at various volumes.

[0053] The present disclosure is understood as the circuit diagram of FIG. 2, or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. Hereinafter, in order to facilitate and clarify the understanding of the essence of the invention and the circuit operation rather than narrowing the scope of the present invention, more specific configuration examples will be described.

[0054] FIG. 4 is a circuit diagram showing a configuration example of the bias circuit 310. The bias circuit 310 includes resistors R23 to R26 and buffers 313 and 314.

[0055] The fifth resistor R25, the sixth resistor R26, and the buffer 313 constitute a first voltage dividing circuit 316 that divides the power supply voltage V CC When R25 = R26, in the voltage dividing circuit 316, the midpoint voltage V CC / 2 of the power supply voltage V CC is generated and output via the buffer 313.

[0056] The third resistor R23 and the fourth resistor R24 are provided between the output of the voltage dividing circuit 316 and the node (line) FIL where the first reference voltage V FIL is generated, and constitute a second voltage dividing circuit 317.

[0057] The ratio of the resistance values of the third resistor R23 and the fourth resistor R24 may be determined according to the gain g D of the class D amplifier circuit 200, that is, according to the resistance values of the first resistor R11 and the second resistor R12 in FIG. 2. R24:R23 = R11:R12

[0058] At the connection node Nx of the third resistor R23, the fourth resistor R24, and, a voltage Vx is generated which internally divides the voltage V CC / 2 and the voltage V FIL . Vx = (V FIL ×R23 + V CC / 2×R24) / (R23 + R24)

[0059] Buffer 314 has a high input impedance and a low output impedance, and outputs a second reference voltage V at the same voltage level as voltage Vx. FILP Outputs it.

[0060] Figure 5 is a circuit diagram showing a configuration example of the periodic voltage generation circuit 260. The periodic voltage generation circuit 260 includes a clock generation circuit 262 and a triangular wave generation circuit 264.

[0061] The clock generation circuit 262 generates a first clock signal CLK1 with an amplitude of a voltage level 2×V that is twice the second reference voltage V. FILP Based on the first clock signal CLK1, the triangular wave generation circuit 264 generates a periodic voltage V. FILP OSC OSC Generates.

[0062] The voltage source 266 generates a voltage level 2×V that is twice the second reference voltage V. FILP A second clock signal CLK2 having a frequency twice that of the periodic voltage V is input to the level shift circuit 268. The level shift circuit 268 shifts the high level voltage (for example, the power supply voltage V) of the second clock signal CLK2 to a voltage level 2×V that is twice the second reference voltage V. FILP OSC OSC DD DD ) to a voltage level 2×V that is twice the second reference voltage V. FILP FILP FILP Level shift.

[0063] The frequency divider 270 divides the third clock signal CLK3 after level shifting by the level shift circuit 268 by 1 / 2 to generate the first clock signal CLK1. For example, the frequency divider 270 can be composed of flip-flops. By passing through the level shift circuit 268 or due to fluctuations in the power supply voltage, the duty cycle of the clock output by the level shift circuit 268 may deviate from 50%. According to the clock generation circuit 262 in FIG. 5, by inputting the second clock signal CLK2 having a frequency twice that of the final frequency into the level shift circuit 268 and dividing it by 1 / 2 after level shifting, the duty cycle of the first clock signal CLK1 can be maintained at 50%. Thereby, the quality of the triangular wave waveform can be improved, and the modulation accuracy can be enhanced.

[0064] Subsequently, a configuration example of the triangular wave generation circuit 264 will be described. The triangular wave generation circuit 264 includes operational amplifiers OA31 and OA32, resistors R31 and R32, and capacitors C31 and C32. One end of the resistor R31 receives the first clock signal CLK1, and the other end is connected to the inverting input terminal (-) of the operational amplifier OA31. The capacitor C31 is provided between the output terminal of the operational amplifier OA31 and the inverting input terminal (-) of the operational amplifier OA31.

[0065] The second reference voltage V FILP is input to the non-inverting input terminal of the operational amplifier OA32. The output terminal of the operational amplifier OA32 is connected to the non-inverting input terminal (+) of the operational amplifier OA31. One end of the resistor R32 is connected to the output terminal of the operational amplifier OA31, and the other end is connected to the inverting input terminal of the operational amplifier OA32. The capacitor C32 is provided between the output terminal of the operational amplifier OA32 and the inverting input terminal of the operational amplifier OA32. The output voltage of the operational amplifier OA31 becomes the periodic voltage V OSC .

[0066] According to this configuration, the center level of the periodic voltage V OSC is the second reference voltage V FILPThe voltage supplied to the non-inverting input terminal of the operational amplifier OA31 is adjusted so as to approach [the target value]. As a result, it is possible to suppress variations in the output impedance of the clock generation circuit 262 and deterioration of characteristics due to power supply voltage fluctuations.

[0067] Next, the input interface of the audio circuit 300 will be described.

[0068] FIG. 6 is a diagram showing a configuration example (300A) of the audio circuit 300. The audio circuit 300A includes a digital audio interface circuit 330 and a D / A converter 320 in addition to the bias circuit 310 and the class-D amplifier circuit 200.

[0069] The digital audio interface circuit 330 receives a digital audio signal S DIG from an external sound source. The format of the digital audio signal S DIG is not particularly limited, and examples include I 2 S (I 2 S (Inter IC Sound)).

[0070] The D / A converter 320 converts the digital audio signal S DIG received by the digital audio interface circuit 330 into an analog audio signal V IN .

[0071] In this configuration, the center level V IN of the analog audio signal V FIL is defined according to the reference voltage V REF of the D / A converter 320. Therefore, the bias circuit 310 may be supplied with a first reference voltage V REF having a voltage level based on the reference voltage V FIL .

[0072] FIG. 7 is a diagram showing another configuration example (300B) of the audio circuit 300. The audio circuit 300B includes an analog input interface circuit 340 in addition to the bias circuit 310 and the class-D amplifier circuit 200. The analog input interface circuit 340 includes, for example, a resistor R41 provided between the analog input pin IN and the generation node of the first reference voltage V FIL . The analog audio signal S ANLG is input to the analog input pin IN via a coupling capacitor. In this case, the bias circuit 310 may be supplied with the first reference voltage V FIL .

[0073] (Application) The application of the audio circuit 300 will be described. FIG. 8 is a block diagram of an in-vehicle audio system using the audio circuit according to the embodiment.

[0074] The in-vehicle audio system 500 includes four speakers 502 FL , 502 FR , 502 RL , 502 RR , four filters 504 FL , 504 FR , 504 RL , 504 RR , a sound source 506, and the audio circuit 300.

[0075] The sound source 106 outputs a digital audio signal of two channels of left and right (LR) or multi-channels. The audio circuit 300 includes an interface circuit 301 between the four-channel class-D amplifier circuit 200 and the sound source 106. The interface circuit 301 can be associated with the digital audio interface circuit 330 and the D / A converter 320 in FIG. 3.

[0076] The filter 504, the sound source 506, and the audio circuit 300 are built in an audio head unit or a car navigation device. Alternatively, the audio circuit 300 may be a product independent of the sound source 106.

[0077] Figs. 9(a) and 9(b) are diagrams showing an electronic device using the audio circuit according to the embodiment. The electronic device in Fig. 9(a) is a display device 600 such as a television. The display device 600 includes speakers 602L, 602R, filters 604L, 604R, a sound source 606, an audio circuit 300, and a display panel 610.

[0078] The electronic device in Fig. 9(b) is an audio component device 800. The audio component device 800 includes an audio signal processing circuit 806 corresponding to a sound source, an audio circuit 300, and a filter (not shown). The audio circuit 300 drives 802L, 802R connected via speaker cables.

[0079] It should be understood by those skilled in the art that the above-described embodiments are examples, and various modifications are possible for the combination of each component and each processing process. Hereinafter, such modifications will be described.

[0080] In the embodiment, a half-bridge type class-D amplifier has been described, but the present invention is also applicable to a full-bridge type (BTL: Bridge-Tied Load) class-D amplifier. In this case, the DC block capacitor of the low-pass filter 104 becomes unnecessary. Further, in the full-bridge type class-D amplifier, a filterless modulation method in which the low-pass filter 104 is omitted may be adopted.

Industrial Applicability

[0081] The present disclosure can be used in an audio device.

Explanation of Reference Numerals

[0082] 100 Audio system 102 Speaker 104 Low-pass filter 106 Sound source 300 Audio circuit VCC Power supply pin 200 Class-D amplifier circuit 210 Integrator 212 Error Amplifier 230 PWM Comparator 240 Bridge Circuit 250 Driver 260 Periodic Voltage Generation Circuit 262 Clock Generation Circuit 264 Triangular Wave Generation Circuit 266 Voltage Source 268 Level Shift Circuit 270 Divider 310 Bias Circuit 320 D / A Converter 330 Digital Audio Interface Circuit

Claims

1. A class-D amplifier circuit that receives an analog audio signal having a first reference voltage as a center level and outputs an output pulse signal having a duty cycle corresponding to the analog audio signal; A bias circuit that generates a second reference voltage having a voltage level obtained by dividing the first reference voltage and the power supply voltage; Comprising: The class-D amplifier circuit includes: An integrator that receives the analog audio signal and a feedback signal corresponding to the output pulse signal; A periodic voltage generation circuit that generates a periodic voltage of a triangular wave or a sawtooth wave; A PWM (Pulse Width Modulation) comparator that compares the output of the integrator and the periodic voltage; A bridge circuit supplied with the power supply voltage; A driver that drives the bridge circuit in response to the output of the PWM comparator; Comprising: The integrator includes: A first operational amplifier that receives the second reference voltage at a non-inverting input terminal; A first resistor having one end receiving the analog audio signal and the other end connected to the inverting input terminal of the first operational amplifier; A second resistor having one end receiving the feedback signal and the other end connected to the inverting input terminal of the first operational amplifier; Including: The periodic voltage generation circuit generates a periodic voltage having an amplitude corresponding to the second reference voltage, The periodic voltage generation circuit includes: A clock generation circuit that generates a first clock signal having an amplitude of a voltage level twice that of the second reference voltage; A triangular wave generation circuit that generates the periodic voltage based on the first clock signal; An audio circuit.

2. The clock generation circuit includes: A level shift circuit that receives a second clock signal having a frequency twice that of the periodic voltage and level-shifts the high-level voltage of the second clock signal to a voltage level twice that of the second reference voltage; A frequency divider that divides the third clock signal after level shifting by the level shift circuit by 1 / 2 to generate the first clock signal; The audio circuit according to claim 1, including:

3. The frequency divider includes a flip-flop, and the audio circuit according to claim 2.

4. The triangular wave generation circuit includes: A second operational amplifier; A third resistor having one end receiving the first clock signal and the other end connected to the inverting input terminal of the second operational amplifier; A first capacitor provided between the output terminal of the second operational amplifier and the inverting input terminal of the second operational amplifier; A third operational amplifier that receives the second reference voltage at a non-inverting input terminal thereof and has an output terminal connected to the non-inverting input terminal of the second operational amplifier; A fourth resistor having one end connected to the output terminal of the second operational amplifier and the other end connected to the inverting input terminal of the third operational amplifier; A second capacitor provided between the output terminal of the third operational amplifier and the inverting input terminal of the third operational amplifier; The audio circuit according to any one of claims 1 to 3, including the above, wherein the output voltage of the second operational amplifier is the periodic voltage.

5. The bias circuit includes: A first voltage dividing circuit that generates a midpoint voltage that is half of the power supply voltage; A second voltage dividing circuit that divides the first reference voltage and the midpoint voltage; The audio circuit according to any one of claims 1 to 4, including the above.

6. The audio circuit according to claim 5, wherein the voltage division ratio of the second voltage dividing circuit is equal to the gain of the class D amplifier circuit.

7. The audio circuit according to any one of claims 1 to 6, which is integrally integrated on one substrate.

8. A speaker; The audio circuit according to any one of claims 1 to 7 for driving the speaker; An in-vehicle audio system comprising the above.

9. An electronic device comprising the audio circuit according to any one of claims 1 to 7.

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