Semiconductor device and display device

Abstract

One of the problems is to suppress the potential drop of the gate of the pull-up transistor. . 【Solution】For the first transistor included in the drive circuit, the first terminal is electrically connected to the second wiring, the second terminal is electrically connected to the first wiring, and the gate is electrically connected to the first terminals of the second circuit and the third transistors. For the second transistor, the first terminal is electrically connected to the first wiring, the second terminal is electrically connected to the sixth wiring, and the gate is electrically connected to the first circuit and the gates of the third transistors. For the third transistor , the second terminal is electrically connected to the sixth wiring. The first circuit is electrically connected to the third wiring, the fourth wiring , the fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.

Description

[Technical field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device and a display device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a liquid crystal display device, a driving method thereof, or the semiconductor device and the display device. or an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on a substrate is expected to contribute greatly to reducing costs and improving reliability. Development is underway actively to contribute significantly to the

[0003] A transistor formed of a non-single crystal semiconductor has an increased threshold voltage or a decreased mobility. If the deterioration of this transistor progresses, the driver circuit may not function properly. There was a problem that the image could not be displayed because the image became too blurred. The patent discloses a shift register that can suppress the deterioration of transistors. In Figure 7 of Reference 1, two transistors are used to suppress the degradation of the transistor characteristics. One transistor is connected to the output terminal of the flip-flop and VSS (hereafter referred to as the negative power supply). The other transistor is connected between the output of the flip-flop and the line that supplies the The flip-flop is connected between the input terminal and the gate of the pull-up transistor. During the period when the output signal of the When one transistor turns on, VSS is supplied to the output terminal of the flip-flop through the one transistor. When the other transistor turns on, VSS supplied to the gate of the pull-up transistor is supplied to the output terminal of the flip-flop through the other transistor. In this way, deterioration of the transistor can be suppressed. Further, since VSS is always supplied to the output terminal of the flip-flop, it becomes easier to maintain the output signal of the flip-flop at the L level.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the configuration shown in Patent Document 1, during the period when the output signal of the flip-flop becomes the H level, since the other transistor turns on for a short time, the gate of the pull-up transistor and the output terminal of the flip-flop become conductive for a short time. At this time, the potential of the gate of the pull-up transistor is at a high potential, and the potential of the output terminal of the flip-flop is at a low potential. One aspect of the present invention is to increase the potential of the gate of the pull-up transistor.

[0006] Or, when the potential of the gate of the pull-up transistor decreases, the pull-up transistor may turn off. One aspect of the present invention is to prevent malfunction of the shift register.

[0007] Or, even if the pull-up transistor is turned on and the shift register can operate normally the potential of the gate of the pull-up transistor will inevitably decrease. One aspect of the present invention aims to increase the potential difference (Vgs) between the gate and the source of the pull-up transistor.

[0008] Or, when the Vgs of the pull-up transistor becomes small, the on-resistance of the pull-up transistor will increase. One aspect of the present invention aims to reduce the size of the display device. Or, one aspect of the present invention aims to increase the definition of the display device.

[0009] Or, when the Vgs of the pull-up transistor becomes small, the rising time or the falling time of the output signal of the flip-flop will become long. One aspect of the present invention aims to prevent the writing of an incorrect signal to the pixel (for example, a video signal to a pixel belonging to another row) and to improve the display quality.

[0010] Or, when the Vgs of the pull-up transistor becomes small, it is necessary to increase the channel width of the pull-up transistor. And when the channel width of the pull-up transistor becomes large, it is also necessary to increase the channel width of other transistors. One aspect of the present invention aims to reduce the layout area. Or, one aspect of the present invention aims to narrow the frame of the display device.

[0011] Or, when the channel width of the transistor becomes large, the gate of the transistor and the source or the drain are likely to short-circuit. One aspect of the present invention aims to improve the yield. ​​​​An object is to achieve this. Or, an aspect of the present invention is to reduce costs.

[0012] Or, when the channel width of the transistor increases, the parasitic capacitance of the shift register increases and this causes problems. An aspect of the present invention is to reduce distortion or delay in the signal input to the shift register. Or, an aspect of the present invention is to reduce power consumption. An object is to achieve this. Or, an aspect of the present invention is to reduce power consumption. To improve this, it is necessary to use a circuit having a large current capacity as a circuit for supplying a signal or voltage to the shift register. An aspect of the present invention is to reduce the size of the external circuit. Or, an aspect of the present invention is to reduce the size of the external circuit. Or, an aspect of the present invention is to reduce the size of the display device. An object is to achieve this. Or, an aspect of the present invention is to reduce the size of the display device. An object is to achieve this.

[0013] Note that the description of the above problems does not prevent the existence of other problems.

Means for Solving the Problems

[0014] An aspect of the present invention includes a driving circuit having a first transistor, a second transistor, a third transistor, a first circuit, and a second circuit, and a pixel having a liquid crystal element. The first transistor has a first terminal electrically connected to a second wiring having a function as a signal line or a clock signal line, a second terminal electrically connected to a first wiring having a function as a signal line, a gate line, a scanning line, or an output signal line, and a gate electrically connected to a first terminal of the second circuit and the third transistor. The second transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a sixth wiring having a function as a power supply line or a ground line, and a gate electrically connected to the gates of the first circuit and the third transistor. The second transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a sixth wiring having a function as a power supply line or a ground line, and a gate electrically connected to the gates of the first circuit and the third transistor. The second transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a sixth wiring having a function as a power supply line or a ground line, and a gate electrically connected to the gates of the first circuit and the third transistor. The second transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a sixth wiring having a function as a power supply line or a ground line, and a gate electrically connected to the gates of the first circuit and the third transistor. The second transistor has a first terminal electrically connected to the first wiring, a second terminal electrically connected to a sixth wiring having a function as a power supply line or a ground line, and a gate electrically connected to the gates of the first circuit and the third transistor. is electrically connected to the gate, and the third transistor has its second terminal electrically connected to the sixth wiring The second circuit is connected to a signal line, or a third wiring functioning as a clock signal line, a fourth wiring functioning as a signal line, a fifth wiring functioning as a signal line, and the sixth wiring. The first circuit is a liquid crystal display device electrically connected to the first wiring, the second wiring, and the sixth wiring. The second circuit is connected to a signal line, or a third wiring functioning as a clock signal line, a fourth wiring functioning as a signal line, a fifth wiring functioning as a signal line, and the sixth wiring. The first circuit is a liquid crystal display device electrically connected to the first wiring, the second wiring, and the sixth wiring. The second circuit is connected to a signal line, or a third wiring functioning as a clock signal line, a fourth wiring functioning as a signal line, a fifth wiring functioning as a signal line, and the sixth wiring. The first circuit is a liquid crystal display device electrically connected to the first wiring, the second wiring, and the sixth wiring. The second circuit is connected to a signal line, or a third wiring functioning as a clock signal line, a fourth wiring functioning as a signal line, a fifth wiring functioning as a signal line, and the sixth wiring. The first circuit is a liquid crystal display device electrically connected to the first wiring, the second wiring, and the sixth wiring.

[0015] In one aspect of the present invention, the first transistor may function as a bootstrap transistor that controls the timing of supplying the signal of the second wiring to the first wiring according to the potential of the gate of the first transistor. In one aspect of the present invention, the first transistor may function as a bootstrap transistor that controls the timing of supplying the signal of the second wiring to the first wiring according to the potential of the gate of the first transistor. In one aspect of the present invention, the first transistor may function as a bootstrap transistor that controls the timing of supplying the signal of the second wiring to the first wiring according to the potential of the gate of the first transistor.

[0016] In one aspect of the present invention, the second transistor may function as a switch that controls the conduction state between the sixth wiring and the first wiring according to the output signal of the first circuit or the potential of the gate of the second transistor. In one aspect of the present invention, the second transistor may function as a switch that controls the conduction state between the sixth wiring and the first wiring according to the output signal of the first circuit or the potential of the gate of the second transistor. In one aspect of the present invention, the second transistor may function as a switch that controls the conduction state between the sixth wiring and the first wiring according to the output signal of the first circuit or the potential of the gate of the second transistor.

[0017] In one aspect of the present invention, the third transistor may function as a switch that controls the conduction state between the sixth wiring and the gate of the first transistor according to the output signal of the first circuit. In one aspect of the present invention, the third transistor may function as a switch that controls the conduction state between the sixth wiring and the gate of the first transistor according to the output signal of the first circuit. In one aspect of the present invention, the third transistor may function as a switch that controls the conduction state between the sixth wiring and the gate of the first transistor according to the output signal of the first circuit.

[0018] In one aspect of the present invention, the first circuit controls the timing of supplying the voltage of the sixth wiring to the gate of the second transistor according to the signal of the first wiring or the signal of the second wiring, so as to increase, decrease or maintain the potential of the gate of the second transistor, or function as a control circuit that makes the gate of the second transistor in a floating state. In one aspect of the present invention, the first circuit controls the timing of supplying the voltage of the sixth wiring to the gate of the second transistor according to the signal of the first wiring or the signal of the second wiring, so as to increase, decrease or maintain the potential of the gate of the second transistor, or function as a control circuit that makes the gate of the second transistor in a floating state. In one aspect of the present invention, the first circuit controls the timing of supplying the voltage of the sixth wiring to the gate of the second transistor according to the signal of the first wiring or the signal of the second wiring, so as to increase, decrease or maintain the potential of the gate of the second transistor, or function as a control circuit that makes the gate of the second transistor in a floating state. In one aspect of the present invention, the first circuit controls the timing of supplying the voltage of the sixth wiring to the gate of the second transistor according to the signal of the first wiring or the signal of the second wiring, so as to increase, decrease or maintain the potential of the gate of the second transistor, or function as a control circuit that makes the gate of the second transistor in a floating state.

[0019] In one aspect of the present invention, the second circuit controls the timing of supplying the signal supplied to the third wiring, the signal supplied to the fourth wiring, or the signal supplied to the fifth wiring to the gate of the first transistor, and supplies the signal supplied to the fourth wiring or the voltage of the sixth wiring. It may function as a control circuit that raises, decreases, or maintains the potential of the gate of the first transistor, or that floats the potential of the gate of the first transistor. According to the signal supplied to the signal supplied to the fourth wiring or the fifth wiring, the timing of supplying the signal supplied to the fourth wiring or the voltage of the sixth wiring to the gate of the first transistor is controlled, The function of raising, decreasing, or maintaining the potential of the gate of the first transistor, or the gate of the first transistor It may function as a control circuit that floats the potential.

[0020] In one aspect of the present invention, the first circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The fourth transistor has a first terminal electrically connected to the second wiring, a second terminal electrically connected to the gate of the second transistor, the fifth transistor has a first terminal electrically connected to the sixth wiring, and a second The terminal is electrically connected to the gate of the second transistor, and the gate is electrically connected to the first wiring. The sixth transistor has a first terminal electrically connected to the second wiring, and a second The terminal is electrically connected to the gate of the fourth transistor, and the gate is electrically connected to the second wiring. The seventh transistor has a first terminal electrically connected to the sixth wiring, and a second The terminal is electrically connected to the gate of the fourth transistor, and the gate is electrically connected to the first wiring.

[0021] In one aspect of the present invention, the second circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The eighth transistor has a first terminal electrically connected to the fourth wiring, and a second terminal electrically connected to the first transistor ​​​​​​is electrically connected to the gate of the transistor, and the gate is electrically connected to the third wiring, the ninth The transistor has a first terminal electrically connected to the gate of the first transistor, and a second terminal electrically connected to the fourth wiring, and the gate is electrically connected to the fourth wiring, the tenth transistor has a first terminal electrically connected to the gate of the first transistor, and a second terminal electrically connected to the sixth wiring, and the gate is electrically connected to the fifth wiring, the first 1 transistor has a first terminal electrically connected to the first wiring, and a second terminal electrically connected to the sixth wiring, and the gate is electrically connected to the fifth wiring, and the twelfth transistor has a first terminal electrically connected to the first wiring, and a second terminal electrically connected to the sixth wiring and the gate may be electrically connected to the third wiring.

[0022] In one aspect of the present invention, the drive circuit may be formed on the same substrate as the pixel .

[0023] In one aspect of the present invention, the channel width of the first transistor may be larger than the channel widths of the second transistor and the third transistor.

[0024] Note that switches can be of various forms. Examples include electrical switches and mechanical switches. That is, any device that can control the flow of current is acceptable and is not limited to a specific one. For example, as a switch, a transistor (e.g., a bipolar transistor, a MOS transistor, etc.), a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semicon ductor) diodes, transistor connected in diode configuration, etc.) are often used. Alternatively, a logic circuit combining these can be used as a switch.

[0025] Examples of mechanical switches include those using MEMS (Micro-Electro-Mechanical System) technology, such as Digital Micro-Mirror Device (DMD). There are switches using MEMS (Micro-Electro-Mechanical System) technology.

[0026] In addition, a CMOS type switch using both N-channel transistors and P-channel transistors can also be used as a switch.

[0027] When it is explicitly stated that A and B are connected, it includes the case where A and B are electrically continuous, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, but also includes those other than the connection relationship shown in the figure or the text.

[0028] For example, when A and B are electrically connected, one or more elements (for example, switches, transistors, capacitor elements, inductors, resistor elements, diodes, etc.) enabling the electrical connection between A and B may be connected between A and B. Alternatively, when A and B are functionally connected, a circuit (for example ​​​​​​​​​​then, a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit , buck circuit, etc.), level shifter circuit for changing the potential level of a signal, etc.), voltage source, current source , switching circuit, amplifier circuit (circuit capable of increasing the signal amplitude or current amount, etc., operational amplifier , differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) may be connected by one or more between A and B. For example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, A and B are considered to be functionally connected.

[0029] In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered the same as when it is only explicitly described that they are connected.

[0030] In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, display device, light-emitting element or light-emitting device, EL (electrolumine Sensor element (EL element including organic and inorganic materials, organic EL element, inorganic EL element), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (transistor that emits light according to current) , electron-emitting element, liquid crystal element, electronic ink, electrophoretic element, gr ating light valve (GLV), plasma display (PDP), digital micro mirror device (DMD), piezoelectric ceramic display, carbon nanotube , etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action .

[0031] Note that a liquid crystal element is an element that controls light transmission or non-transmission by the optical modulation action of liquid crystal and is composed of a pair of electrodes and liquid crystal. Note that the optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Note that as liquid crystal elements , nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal , discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular liquid crystal , polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal , side chain polymer liquid crystal, plasma addressed liquid crystal (PALC), banana type liquid crystal, etc. can be mentioned . Also, as the driving method of liquid crystal, TN (Twisted Nematic) mode , STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching) mode, FFS (Fringe Field Swi tching) mode, MVA (Multi-domain Vertical Ali gnment) mode, PVA (Patterned Vertical Alignm ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetric aligned Micro-cell) mode , OCB (Optically Compensated Birefringence ) mode, ECB (Electrically Controlled Birefri ngence) mode, FLC (Ferroelectric Liquid Crys tal) mode, AFLC (AntiFerroelectric Liquid Cr ystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, guest-host mode, blue phase (Blue Phase) mode and the like can be used. However, it is not limited thereto, and various ones can be used as the liquid crystal element and its driving method and the like.

[0032] In addition, as the light source, electroluminescence, cold cathode tubes, hot cathode tubes, LEDs, laser light sources, mercury lamps, etc. can be used. However, it is not limited thereto, and various ones can be used as the light source and the like.

[0033] In addition, the configuration of the transistor can take various forms and is not limited to a specific configuration . For example, a multi-gate structure with two or more gate electrodes can be applied. In the multi gate structure, since the channel regions are connected in series, a configuration in which a plurality of transistors are connected in series is formed.

[0034] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied .

[0035] A structure in which a gate electrode is disposed over a channel region, a gate electrode disposed under the channel region A structure, a positive stagger structure, an inverse stagger structure, a structure in which the channel region is divided into a plurality of regions A structure in which the channel regions are connected in parallel, or a configuration in which the channel regions are connected in series is also applicable. Further, a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof) is also applicable. Alternatively, a structure provided with an LDD region can be applied. When it is explicitly described that B is formed on A, or B is formed over A, it is not limited to the case where B is formed in direct contact with A. It shall include the case where they are not in direct contact, that is, the case where another object is interposed between A and B.

[0036] Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). When it is explicitly described that layer B is formed on layer A (or over layer A), it includes the case where layer B is formed in direct contact with layer A, and the case where another layer (for example, layer C or layer D) is formed in direct contact with layer A and layer B is formed in direct contact therewith. Note that the other layer (for example, layer C or layer D) may be a single layer or a multilayer. In addition, the same applies to the case where it is explicitly described that B is formed above A. It is not limited to the case where B is in direct contact with A, and it shall include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, When it is explicitly described that B is formed over A, it is not limited to the case where B is in direct contact with A, and it shall include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed in direct contact with layer A, and the case where another layer (for example, layer C or layer D) is formed in direct contact with layer A and layer B is formed in direct contact therewith. Note that the other layer (for example, layer C or layer D) may be a single layer or a multilayer.

[0037] Therefore, for example, when it is explicitly described that layer B is formed on (or over) layer A, it includes the case where layer B is formed in direct contact with layer A and the case where another layer (for example, layer C or layer D) is formed in direct contact with layer A and layer B is formed in direct contact therewith. When it is explicitly described that layer B is formed on layer A (or over layer A), it includes the case where layer B is formed in direct contact with layer A and the case where another layer (for example, layer C or layer D) is formed in direct contact with layer A and layer B is formed in direct contact therewith. When it is explicitly described that layer B is formed on layer A (or over layer A), it includes the case where layer B is formed in direct contact with layer A and the case where another layer (for example, layer C or layer D) is formed in direct contact with layer A and layer B is formed in direct contact therewith. is formed thereon. Note that the other layer (for example, layer C or layer D) may be a single layer or a multilayer. is formed thereon. Note that the other layer (for example, layer C or layer D) may be a single layer or a multilayer.

[0038] Furthermore, the same applies to the case where it is explicitly described that B is formed above A. It is not limited to the case where B is in direct contact with A, and it shall include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it is not limited to the case where B is in direct contact with A, and it shall include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, In the case where layer B is formed directly on layer A, and in the case where another layer (such as layer C or layer D) is formed directly on layer A and layer B is formed directly on top of that layer. It shall include both cases. Note that another layer (such as layer C or layer D) may be a single layer or a multi-layer.

[0039] In addition, when it is explicitly described that B is formed on A, B is formed above A, or B is formed over A, it shall include the case where B is formed obliquely above.

[0040] The same applies to the case where B is below A or B is beneath A.

[0041] For those explicitly described as singular, it is desirable to be singular. However, it is not limited thereto, and it is also possible to be plural. Similarly, for those explicitly described as plural, it is desirable to be plural. However, it is not limited thereto, and it is also possible to be singular.

[0042] In the figure, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0043] The figure schematically shows an ideal example and is not limited to the shape or value shown in the figure. For example, it may include variations in shape due to manufacturing technology, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0044] Note that technical terms are often used for the purpose of describing specific embodiments, examples, etc., but are not limited thereto.

[0045] Note that words that are not defined (including scientific and technical terms such as technical terms or academic terms) can be used with a meaning equivalent to the general meaning understood by those of ordinary skill in the art. Words defined by a dictionary or the like are preferably interpreted in a meaning that is not inconsistent with the background of the related art.

[0046] Note that terms such as first, second, and third are used to distinguish various elements, members, regions, layers, and areas from others. Therefore, terms such as first, second, and third do not limit the number of elements, members, regions, layers, areas, etc. Further, for example, "first" can be replaced with "second" or "third", etc.

Advantages of the Invention

[0047] One aspect of the present invention can increase the potential of the gate of a transistor. Or, one aspect of the present invention can prevent malfunction. Or, one aspect of the present invention can increase the Vgs of a transistor. Or, one aspect of the present invention can reduce the on-resistance of a transistor. Or, one aspect of the present invention can reduce the channel width of a transistor. Or, one aspect of the present invention can suppress or mitigate the degradation of a transistor. Or, one aspect of the present invention can reduce the layout area. Or, one aspect of the present invention can shorten the fall time or rise time of the output signal of a drive circuit such as a flip-flop, a shift register, or a scan line drive circuit. It is possible. Or, one aspect of the present invention can increase the size of the display device. Or, one aspect of the present invention can improve the definition of the display device. Or, one aspect of the present invention can narrow the frame of the display device. Or, one aspect of the present invention can write an accurate signal to the pixel. Or, one aspect of the present invention can enhance the display quality. Or, one aspect of the present invention can increase the yield. Or, one aspect of the present invention can reduce the cost. Or, one aspect of the present invention can reduce the smear or delay of the signal input to the shift register. Or, one aspect of the present invention can reduce the power consumption. Or, one aspect of the present invention can reduce the current capacity of the external circuit. Or, one aspect of the present invention can reduce the size of the external circuit or the size of the display device having the external circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0048]

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[0049] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention may be embodied in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the form and details of the present invention. It should not be construed as being limited to the description of the embodiment. In the drawings, the same reference numerals are used to indicate the same objects, and the same parts or the same components are shown in different drawings. Detailed description of the parts having various functions will be omitted.

[0050] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment, and / or one or more other embodiments The application, combination, or replacement of the contents (or part of the contents) described in the form It is possible to do the following:

[0051] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0052] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part of it) described in another embodiment of the present invention , and many more diagrams can be constructed.

[0053] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. The semiconductor device of this embodiment is For example, it can be used in a shift register, a gate driver, a source driver, or a display device, etc. Note that the semiconductor device can be referred to as a flip-flop or a drive circuit.

[0054] First, an example of the semiconductor device of this embodiment will be described with reference to FIG. 1(A). FIG. 1 (A) shows a circuit 100. Note that the circuit 100 can be referred to as a semiconductor device, a drive circuit, or a flip flop.

[0055] The circuit 100 includes a transistor 101 (also referred to as a first transistor), a transistor 10 2 (also referred to as a second transistor), a transistor 103 (also referred to as a third transistor ), a circuit 104 (also referred to as a first circuit), and a circuit 105 (also referred to as a second circuit). The circuit 104 has a plurality of terminals such as a terminal 104a, a terminal 104b, a terminal 104c, and a terminal 104d. The circuit 105 has a plurality of terminals such as a terminal 105a, a terminal 105b, a terminal 105c, a terminal 105d, a terminal 105e, and a terminal 105f. However, it is not limited to this, and any of these transistors, or any of these circuits, can be omitted, or replaced with various elements such as a capacitor element, a resistor element, or a diode, or a circuit combined with any of these elements. Alternatively, various elements such as a transistor, a capacitor element, a resistor element, or a diode, or a circuit combined with any of these elements can be newly added. Or, a circuit formed by combining any of these elements can be newly added. Or, a circuit formed by combining any of these elements can be newly added. Or, a circuit ​​Depending on the configurations of circuit 104 and circuit 105, it is possible to add or omit terminals. It is possible.

[0056] As an example, assume that transistors 101 to 103 are of the N-channel type. An N-channel transistor is assumed to turn on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth). However, it is not limited to this, and transistors 101 to 103 can be of the P-channel type. A P-channel transistor is assumed to turn on when the potential difference (Vgs) between the gate and the source is less than the threshold voltage (Vth). A P-channel transistor turns on when the potential difference (Vgs) between the gate and the source is less than the threshold voltage (Vth). However, it is not limited to this. 101 to 103 can be of the P-channel type. A P-channel transistor turns on when the potential difference (Vgs) between the gate and the source is less than the threshold voltage (Vth). It is assumed to turn on.

[0057] As an example, as shown in Fig. 28(A), assume that circuit 104 is a logic circuit combining a 2-input AND and a NOT. This combined logic circuit takes the logical product of one input signal (for example, the signal on wiring 113) and the inverted signal of the other input signal (for example, the signal on wiring 111). However, it is not limited to this, and as circuit 104, as shown in Fig. 28(B), it is possible to use a 2-input NOR. In addition, various circuits can be used as circuit 104. This combined logic circuit takes the logical product of one input signal (for example, the signal on wiring 113) and the inverted signal of the other input signal (for example, the signal on wiring 111). For example, the signal on wiring 113 and the inverted signal of the other input signal (for example, the signal on wiring 111). However, it is not limited to this. 8(B), it is possible to use a 2-input NOR. In addition, various circuits can be used as circuit 104.

[0058] As an example, assume that circuit 104 and circuit 105 have one or more transistors. And the polarities of these transistors are assumed to be the same as those of transistors 101 to 103. By making the polarities of the transistors the same, it is possible to reduce the manufacturing process, improve the yield, improve the reliability, or reduce the cost. However, it is not limited to this, and circuit 104 and circuit 105 can be N-channel transistors and P Assume that circuit 104 and circuit 105 have one or more transistors. And the polarities of these transistors are assumed to be the same as those of transistors 101 to 103. By making the polarities of the transistors the same, it is possible to reduce the manufacturing process, improve the yield, improve the reliability, or reduce the cost. However, it is not limited to this, and circuit 104 and circuit 105 can be N-channel transistors and P It is possible to have a channel-type transistor. That is, circuits 104 and 105 can be CMOS circuits.

[0059] As an example, terminals 104a to 104c function as input terminals, and terminal 104d functions as an output terminal. And as an example, terminals 105a to 105d function as input terminals, and terminals 105e and 105f function as output terminals as well. However, it is not limited to this.

[0060] Note that circuit 104 and / or circuit 105 can further have more terminals or circuit 104 and / or circuit 105 can omit some of the terminals as well.

[0061] Next, an example of the connection relationship of circuit 100 will be described. The first terminal of transistor 101 is connected to wiring 112, and the second terminal of transistor 101 is connected to wiring 111 The first terminal of transistor 102 is connected to wiring 116, and the second terminal of transistor 102 is connected to wiring 111. The first terminal of transistor 103 is wiring 11 6, and the second terminal of transistor 103 is connected to the gate of transistor 101 and the gate of transistor 103 is connected to the gate of transistor 102. Circuit Terminal 104a of 104 is connected to wiring 112, terminal 104b of circuit 104 is wiring 1 11, terminal 104c of circuit 104 is connected to wiring 116, and the end of circuit 104 Terminal 104d is connected to the gate of transistor 102. Terminal 105a of circuit 105 is connected to wiring 113, terminal 105b of circuit 105 is connected to wiring 114, circuit 1 Terminal 105c of 05 is connected to wiring 115, and terminal 105d of circuit 105 is connected to wiring 11 6, terminal 105e of circuit 105 is connected to the gate of transistor 101, and terminal 105f of circuit 105 is connected to wiring 111. However, it is not limited to this, and other connection configurations are also possible.

[0062] Note that the connection point of the gate of transistor 101, the second terminal of transistor 103, or terminal 105e of circuit 10 5 is indicated as node A. And the connection point of the gate of transistor 102, terminal 104d of circuit 104, or the gate of transistor 103 is indicated as node B. Note that node A and node B can be indicated as wiring or terminals.

[0063] Note that wiring 111, wiring 112, wiring 113, wiring 114, wiring 115, and wiring 116 can be indicated as terminals.

[0064] Note that as already described, new terminals can be added to circuit 104 and / or circuit 105. In such a case, the terminal can be connected to various wirings or various elements.

[0065] Note that any of wirings 111 to 116 can be omitted and / or new wiring can be added.

[0066] Next, an example of the signal or voltage input to or output from wirings 111 to 116 will be described. As an example, assume that signal OUT is output from wiring 111. Signal OUT is often a digital signal having H level and L level, and is often the output signal of circuit 100, selection ​​Function as a selection signal, transfer signal, start signal, reset signal, gate signal, or scan signal is possible. As an example, signal IN1 is input to wiring 112. Signal IN1 is often a digital signal and can function as a clock signal. As an example, signal IN2 is input to wiring 113. Signal I N2 is often the inverted signal of signal IN1 or a signal with a 180° phase shift from signal IN1, and can function as an inverted clock signal. As an example, signal IN3 is input to wiring 114. Signal IN3 is often a digital signal and can function as a start signal or a vertical synchronization signal. Or, when circuit 1 00 is used in a shift register or a display device, signal IN3 can function as a transfer signal from another stage (e.g., the previous stage) or a signal for selecting another row (e.g., the previous row). As an example, signal IN4 is input to wiring 115. Signal IN 4 is often a digital signal and can function as a reset signal. Or, when circuit 100 is used in a shift register or a display device, signal IN4 can function as a signal for selecting another row (e.g., the next row). As an example, voltage V1 is input to wiring 116. Voltage V1 is often approximately equal to the signal OUT at the L level, signal IN1, signal IN2, signal IN3, or signal IN4, and can function as a ground voltage, a power supply voltage, or a negative power supply voltage. However, it is not limited to this, and various other signals, various currents, or various voltages can be input to wirings 111 to 116. For example, wirings 112, 113, 114 ​ and / or, a voltage such as voltage V1 or voltage V2 can be supplied to wiring 115 Or, signals such as signal OUT, signal IN1, signal IN2, signal IN3, or signal IN4 can be input to wiring 116. Or, without inputting signals or voltages such as to wiring 111, wiring 112, wiring 113, wiring 114, wiring 115, and / or wiring 116, these wirings can be made floating states

[0067] Note that "substantially" includes various errors such as errors due to noise, errors due to process variations, errors due to variations in the manufacturing process of elements, and / or measurement errors etc

[0068] Note that wiring 111 (also referred to as the first wiring) can function as a signal line, a gate line, a scanning line, or an output signal line. Wiring 112 (also referred to as the second wiring) can function as a signal line or as a clock signal line. Wiring 113 (also referred to as the third wiring) can function as a signal line or a clock signal line. Wiring 114 (also referred to as the fourth wiring) can function as a signal line. Wiring 115 (also referred to as the fifth wiring too) can function as a signal line. Wiring 116 (also referred to as the sixth wiring ) can function as a power line or a ground line. However, it is not limited to this, and wirings 111 to 116 can also function as various other wirings. For example when a voltage is supplied to wiring 112, wiring 113, wiring 114, and / or wiring 115, these wirings can function as power lines. Or when a signal is input to wiring 116, wiring 116 can function as a signal line. Also when a voltage is supplied to wiring 112, wiring 113, wiring 114, and / or wiring 115, these wirings can function as power lines. Or when a signal is input to wiring 116, wiring 116 can function as a signal line. Also when a voltage is supplied to wiring 112, wiring 113, wiring 114, and / or wiring 115, these wirings can function as power lines. Or when a signal is input to wiring 116, wiring 116 can function as a signal line. Also when a signal is input to wiring 116, wiring 116 can function as a signal line Alternatively, like the wiring 111, the wiring 114 and / or the wiring 115 can function as a signal line, a gate line , a scanning line, or an output signal line.

[0069] Note that the circuit 100 can receive a multi-phase clock signal. For example, when referring to an n-phase clock signal (where n is a natural number), the n-phase clock signal refers to n clock signals whose periods are shifted by 1 / n period each. Alternatively, any two of the multi-phase clock signals can be input to the wiring 112 and the wiring 113, respectively. n is a natural number), the n-phase clock signal refers to n clock signals whose periods are shifted by 1 / n period each. Or, any two of the multi-phase clock signals can be input to the wiring 112 and the wiring 113, respectively.

[0070] Note that as the signal IN1 or the signal IN2, a balanced clock signal can be used, or an unbalanced clock signal can be used. By "balanced", it means that the period of the H level and the period of the L level in one cycle are equal. By "unbalanced", it means that the period of the H level and the period of the L level in one cycle are different. Alternatively, as the signal IN1 or the signal IN2, a balanced clock signal can be used, or an unbalanced (also referred to as non-balanced) clock signal can be used. By "balanced", it means that the period of the H level and the period of the L level in one cycle are equal. By "unbalanced", it means that the period of the H level and the period of the L level in one cycle are different. That is, it means that the period of the H level and the period of the L level in one cycle are equal. By "unbalanced", it means that the period of the H level and the period of the L level in one cycle are different. That is, it means that the period of the H level and the period of the L level in one cycle are different.

[0071] Note that as an example, assume that the potential of the L-level signal is V1 and the potential of the H-level signal is V2. And assume that V2 > V1. And when referring to the voltage V2, the voltage V2 is approximately equal to the H level of the signal. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. Let's assume that the potential of the L-level signal is V1 and the potential of the H-level signal is V2. And assume that V2 > V1. And when referring to the voltage V2, the voltage V2 is approximately equal to the H level of the signal. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. That is, the voltage V2 is approximately equal to the H level of the signal. However, it is not limited to this, and the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. That is, the potential of the L-level signal can be lower than V1 or higher than V1. Or, the potential of the H-level signal can be lower than V2 or higher than V2. Or, the potential of the H-level signal can be lower than V2 or higher than V2.

[0072] Next, an example of the functions of the transistors 101 to 103 and the circuits 104 and 105 will be described. ​​​​

[0073] Transistor 101 controls the timing of supplying the H-level signal IN1 to wiring 111 according to the potential of node A, thereby controlling the timing at which signal OUT becomes H-level. It has the function of acting as a pull-up transistor or a bootstrap transistor and can function as such. Transistor 102 controls the conduction state between wiring 116 and wiring 111 according to the output signal of circuit 104 or the potential of node B, thereby controlling the timing of supplying voltage V1 to wiring 111. It has the function of acting as a switch and can function as such. Transistor 103 controls the conduction state between wiring 116 and node A according to the output signal of circuit 104 or the potential of node B, thereby controlling the timing of supplying voltage V1 to node A. It has the function of acting as a switch and can function as such.

[0074] Circuit 104 controls the timing of supplying signal IN3 or voltage V1 to node B according to signal OUT or signal IN1, thereby having the function of increasing, decreasing or maintaining the potential of node B, or floating node B. It can function as a control circuit. And circuit 104 can have the function of controlling the conduction states of transistor 102 and transistor 103 by controlling the potential of node B. For example, when signal IN2 becomes L-level, circuit 104 has the function of decreasing the potential of node B by supplying voltage V1 or the L-level signal IN2 to node B. Another example is that when signal OUT becomes H-level, circuit 104 has the function of decreasing the potential of node B by supplying voltage V1 or the L-level signal IN2 to node B. ​​​​​​​​​​​​​​​It has a function of reducing the potential of Node B by supplying a signal to Node B. Another example is that when the signal OUT is at the L level and the signal IN2 becomes at the H level, the voltage V2 or the signal IN2 at the H level is supplied to Node B, thereby having a function of increasing the potential of Node B.

[0075] Circuit 105 controls the timing of supplying signal IN3 or voltage V1 to Node A according to signal IN2, signal IN3, or signal IN4, thereby having a function of increasing, decreasing, or maintaining the potential of Node A, or a function of floating Node A, and can function as a control circuit. Or, circuit 105 controls the timing of supplying voltage V1 to wiring 111 according to signal IN2, signal IN3, or signal IN4, thereby having a function of decreasing or maintaining the potential of wiring 111, or a function of floating wiring 111. For example, when signal IN2 or signal IN3 becomes at the H level, circuit 105 has a function of increasing the potential of Node A by supplying signal IN3 at the H level or voltage V2 to Node A. As another example, when signal IN2 or signal IN4 becomes at the H level, circuit 105 has a function of decreasing the potential of Node A or the potential of wiring 111 by supplying voltage V1 or a signal at the L level to Node A or wiring 111. However, it is not limited thereto, and transistors 101 to 103 and circuits 104 to 105 can have various other functions. Or, these elements or circuits may not have the functions described above.

[0076]

[0077] ​​​​​​​​​​​Next, regarding the operation of the semiconductor device in Fig. 1(A), it will be described with reference to Fig. 1(B), Fig. 2(A), Fig. 2(B ), Fig. 2(C), Fig. 3(A), and Fig. 3(B). Fig. 1(B) is an example of a timing chart for explaining the operation of the semiconductor device. Fig. 1(B) shows an example of the signals IN1, IN2, IN3, IN4, the potential Va of node A , the potential Vb of node B, and the signal OUT during one operation period. And one operation period of the timing chart in Fig. 1(B) has periods T1, T2, T3, T4, and T5. Fig. 2(A) is an example of a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T1 . Fig. 2(B) is an example of a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T2 . Fig. 2(C) is an example of a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T3 . Fig. 3(A) is an example of a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T4 . Fig. 3(B) is an example of a schematic diagram of the operation of the semiconductor device in Fig. 1(A) during period T5 . . .

[0078] As an example, when the signal IN3 becomes high level, the semiconductor device in Fig. 1(A) is assumed to perform the operations during period T 1, the operation during period T2, and the operation during period T3 in sequence. And then, until the signal IN3 becomes high level again, the semiconductor device in Fig. 1(A is assumed to repeat the operation during period T4 and the operation during period T5 in sequence. However, it is not limited to this, and the semiconductor device in Fig. 1(A) can perform the operations during periods T1 to T5 in various orders. .

[0079] First, during period T1, the signal IN1 becomes low level, the signal IN2 becomes high level, Signal IN3 becomes high level and signal IN4 becomes low level. Since signal IN3 becomes high level , circuit 105 starts to increase the potential of node A. At this time, since signal IN1 becomes low level, circuit 104 starts to decrease the potential of node B to V1. Thus, transistors 102 and 103 turn off, so wiring 116 and wiring 111 are in a non-conductive state, and wiring 116 and node A are in a non-conductive state. After that, when the potential of node A reaches the sum of the potential of wiring 112 (V1) and the threshold voltage (Vth101) of transistor 101 (V1 + Vth101), transistor 101 turns on. Then, since wiring 112 and wiring 111 are in a conductive state, the low-level signal IN1 is supplied from wiring 112 through transistor 101 to wiring 111. Therefore, the potential of wiring 111 becomes V1, so signal OUT becomes low level. After that, circuit 105 continues to increase the potential of node A. And when circuit 105 raises the potential of node A to a certain value (at least V1 + Vth101 or more), the supply of the signal or voltage to node A is stopped. Therefore, node A becomes a floating state while maintaining the potential at this time (for example, V1 + Vth101 or more).

[0080] Note that in period T1, circuit 105 often supplies voltage V1 or a low-level signal to wiring 111. However, it is not limited to this. Circuit 105 can make wiring 111 and circuit 105 in a non-conductive state by not supplying voltage or signal etc. to wiring 111.

[0081] Next, in period T2, signal IN1 becomes high level, signal IN2 becomes low level, The signal IN3 becomes the L level, and the signal IN4 remains at the L level. Since the circuit 105 often does not supply a voltage or a signal to the node A, the node A remains in a floating state while maintaining the potential (V1 + Vth101 or higher) during the period T1. Therefore, the transistor 101 remains on, and the wiring 112 and the wiring 111 remain in a conductive state. At this time, since the signal IN1 rises from the L level to the H level, the voltage of the wiring 111 starts to rise from V1. Then, since the node A is in a floating state, the potential of the node A rises due to the parasitic capacitance between the gate of the transistor 101 and the second terminal. This is a so-called bootstrap operation. Thus, the potential of the node A rises to V2 + Vth10 1 + α (α is a positive number). Then, since the potential of the wiring 111 rises to the potential of the H-level signal IN2, that is, V2, the signal OUT becomes the H level. At this time, since the signal OUT becomes the H level, the circuit 104 supplies a voltage V1 or an L-level signal to the node B to maintain the potential of the node B at V1. Therefore, the transistors 10 2 and 103 remain off, so the wiring 116 and the wiring 111 remain in a non-conductive state, and the wiring 116 and the node A remain in a non-conductive state. Note that during the period T2, the circuit 104 can make the circuit 104 and the node B non-conductive by not supplying a signal or a voltage to the node B. And the circuit 104 can make the node B in a floating state. Even in this case, since the node B is in a floating state, the potential of the node B often remains at V1.

[0082]

[0083] ​​​​​​​During period T2, circuit 105 does not supply a signal or voltage etc. to wiring 111, and thereby, it is possible to make circuit 105 and wiring 111 in a non-conductive state. However, not limited to this, circuit 105 can supply a voltage V2 or a signal of H level etc. to wiring 111.

[0084] Next, during period T3, signal IN1 becomes L level, signal IN2 becomes H level, signal IN3 remains at L level, and signal IN4 becomes H level. Since signal IN4 becomes H level, circuit 105 decreases the potential of node A to be V1. Thus, transistor 101 turns off, and wiring 112 and wiring 111 become non-conductive. Here, since the potential of node A is controlled by the voltage or signal supplied via circuit 105, the timing when transistor 101 turns off is often later than the timing when signal IN1 becomes L level. That is, when transistor 101 is on, signal IN1 may become L level. In this case, the L-level signal IN1 is supplied from wiring 11 2 to wiring 111 via transistor 101. Thus, the potential of wiring 111 becomes V1, and signal OUT becomes L level. At this time, since signal IN1 is L level, circuit 104 supplies an L-level signal IN2 or voltage V1 to node B to maintain the potential of node B at V1. Thus, transistor 102 and transistor 103 remain off, so wiring 116 and wiring 111 remain non-conductive, and wiring 116 and node A remain non-conductive. Note that during period T3, circuit 104 does not supply a signal or voltage etc. to node B.

[0085] ​​​​ It is possible to make the circuit 104 and the node B non-conductive by [reference]. And the circuit 104 can make the node B in a floating state. Even in this case, since the node B is in a floating state, the potential of the node B is often maintained at V1.

[0086] Note that during the period T2, the circuit 105 can supply a signal of voltage V1 or L level to the wiring 111. Or, the circuit 105 can make the circuit 105 and the wiring 111 non-conductive by not supplying a voltage or a signal etc. to the wiring 111. Or, the circuit 105 can make the circuit 105 and the wiring 111 non-conductive by not supplying a voltage or a signal etc. to the wiring 111. to the wiring 111.

[0087] Next, during the period T4, the signal IN1 becomes H level, the signal IN2 becomes L level, the signal IN3 remains at L level, and the signal IN4 becomes L level. Since the signal OUT remains at L level and the signal IN1 becomes H level, the circuit 104 raises the potential of the node B to V2 by supplying the H-level signal IN1 or the voltage V2 to the node B. Then, since the transistor 102 and the transistor 103 are turned on, the wiring 11 6 and the wiring 111 become conductive, and the wiring 116 and the node A become conductive. Thus, the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 102, so the potential of the wiring 111 is maintained at V1. And since the voltage V1 is supplied from the wiring 116 to the node A through the transistor 103, the potential of the node A is maintained at V1. In this way, the signal OUT remains at L level. 103, the potential of the node A is maintained at V1. In this way, the signal OUT remains at L level.

[0088] Note that the circuit 105 can supply a voltage V1 or a signal of L level etc. to the wiring 111 or the node A. ​It is possible. Or, the circuit 105 can be made non-conductive between the circuit 105 and the node A by not supplying a voltage or a signal or the like to the wiring 111 or the node A, and the circuit 105 and the wiring 111 can be made non-conductive.

[0089] Next, in the period T5, the signal IN1 becomes the L level, the signal IN2 becomes the H level, the signal IN3 remains at the L level, and the signal IN4 remains at the L level. Since the signal IN1 becomes the L level, the circuit 104 supplies the L-level signal IN1 or the voltage V1 to the node B to decrease the potential of the node B to V1. Therefore, the transistors 102 and 103 are turned off, so that the wiring 116 and the wiring 111 become non-conductive, and the wiring 116 and the node A become non-conductive. Here, if the circuit 105 supplies the voltage V1 or an L-level signal or the like to the wiring 111 or the node A, the potential of the wiring 111 or the node A is maintained at V1. However, even when the circuit 105 does not supply a voltage or a signal or the like to the wiring 111 or the node A, the potential of the wiring 111 or the node A is maintained at V 1. This is because the wiring 111 and the node A are in a floating state and thus maintain the potential (V1) in the period T 4. Thus, the signal OUT remains at the L level.

[0090] The operation of the semiconductor device in FIG. 1(A) has been described above. In the semiconductor device of FIG. 1(A), in the period T2, a decrease in the potential of the node A can be prevented. In the conventional technology, in the period T2, until the potential of the wiring 111 rises to a certain value, the node A and the wiring 1 ​​​​11 was in a conductive state. Therefore, the potential of node A was decreasing. However, in the semiconductor device of FIG. 1( A), during period T2, node A and wiring 111 do not become conductive . Therefore, a decrease in the potential of node A can be prevented. As a result, a decrease in Vgs of transistor 101 can be prevented. Or, Vgs of transistor 101 can be increased. Or, malfunction due to the potential of node A decreasing too much can be prevented. Or, a decrease in Vgs of transistor 101 can be prevented so that the channel width (W) of transistor 101 can be reduced. Therefore, the layout area can be reduced. Or, since Vgs of transistor 101 can be increased , the on-resistance of transistor 101 can be reduced. Thus , a decrease in the fall time or rise time of signal OUT, or a decrease in the delay of signal OUT can be achieved.

[0091] Or, in the semiconductor device of FIG. 1(A), the polarity of all transistors can be N-channel type or P -channel type. Therefore, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. In particular, when all transistors are N-channel type, as the semiconductor layer of the transistor, a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor , or an oxide semiconductor can be used. Therefore, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. However, it is not limited to this , and the semiconductor device of FIG. 1(A) can have a CMOS circuit composed of P-channel type transistors and N-channel type transistors . Or, the transistor As the semiconductor layer of the transistor, a single crystal semiconductor or a polycrystalline semiconductor can be used.

[0092] Or, in the semiconductor device of Fig. 1(A), in at least one of period T4 and period T5, transistors 101 to 103 turn off. Therefore, since the transistors do not remain on throughout one operation period, it is possible to suppress characteristic degradation of the transistors such as an increase in threshold voltage or a decrease in mobility. In particular, when a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor is used as the semiconductor layer of the transistor, characteristic degradation of the transistors often appears significantly. However, in the semiconductor device of Fig. 1(A), since characteristic degradation of the transistors can be suppressed, it becomes easy to use a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor as the semiconductor layer of the transistor. However, it is not limited thereto, and as the semiconductor layer, a polycrystalline semiconductor or a single crystal semiconductor can be used.

[0093] Note that period T2 can be indicated as the selection period, and the other periods (period T1, period T3, period T4, and period T5) can be indicated as non-selection periods. Or, period T1, period T2, period T3, period T4, and period T5 can be indicated as a set period, an output period, a reset period, a first non-selection period, and a second non-selection period, respectively.

[0094] Note that in an example of the timing chart of Fig. 1(B), the case where signal IN1 and signal IN2 are in balance is shown, but it is not limited thereto. As already described, signal IN1 and signal IN2 can be non-balanced. Or, the timing chart of Fig. 1(B) In the case where the time that signal IN1 (or signal IN2) becomes the H level and the time that signal IN1 (or signal IN2) becomes the L level are approximately equal, that is, when the duty ratio of signal IN1 and signal IN 2 is approximately 50%, it has been shown, but it is not limited to this. The duty ratio of signal IN1 and signal IN2 can be 50% or more, and can also be 50% or less. In FIG. 4(A), the case where signal IN1 and signal IN2 are unbalanced and the duty ratio of signal IN1 and signal IN2 is not 50% is shown in the timing chart. In the timing chart of FIG. 4(A), in period T2, when signal I N1 becomes the H level, the potential of node A rises by the bootstrap operation, and signal OUT becomes the H level. Thereafter, signal IN1 becomes the L level. In the timing chart of FIG. 1(B), at the same time as this, or slightly delayed, the potential of node A decreases to V1. That is, when signal IN1 becomes the L level, at the same time as or slightly delayed, transistor 101 turns off. However, in the timing chart of FIG. 4(A), until signal IN4 becomes the H level, or until signal IN2 becomes the H level, the potential of node A remains high. That is, even after signal IN1 becomes the L level, transistor 101 remains on. Therefore, since wiring 112 and wiring 111 remain in the conductive state, the L-level signal IN1 is supplied from wiring 112 to wiring 111 via transistor 101. Then, since the channel width (W) of transistor 101 is often large, the potential of wiring 111 quickly decreases to V1. Therefore, the fall time of signal OUT can be shortened.

[0095] In FIG. 4(A), one period of signal IN1 is denoted as period Tck. And, among one period, the period during which signal IN1 is at the H level is denoted as period Tck(H), and among one period, the period during which signal IN1 is at the L level is denoted as period Tck(L). Similarly, one period of signal IN2 is denoted as period Tckb. And, among one period, the period during which signal IN2 is at the H level is denoted as period Tckb (H), and among one period, the period during which signal IN2 is at the L level is denoted as period Tckb(L). The relationship between period Tck and period Tckb, the relationship between period Tck(H) and period Tckb(H), and the relationship between period Tck(L) and period Tckb(L) are often Tck≈Tckb, Tck(H)≈Tckb(H), and Tck(L)≈Tckb(L), respectively. However, it is not limited to this.

[0096] In FIG. 4(A), the relationship between period Tck(H) and period Tck(L) is preferably Tck( H)<Tck(L). Similarly, the relationship between period Tckb(H) and period Tckb (L) is preferably Tckb(H)<Tckb(L). By doing so, as described above, the fall time of signal OUT can be shortened. However, it is not limited to this, and it is possible that Tck(H)>Tck(L), and it is also possible that Tc kb(H)>Tckb(L).

[0097] As shown in the timing chart of FIG. 4(A), it is possible to set signal OUT to the L level in the middle of period T2. To achieve this, in the middle of period T2, set signal IN 4 to the H level. Then, the circuit 100 in FIG. 1(A) forcibly operates in period T3, or ​​Starts an operation according to this. First, since signal IN4 becomes the H level, circuit 105 supplies a voltage V1 or a signal of the L level to node A and wiring 111, thereby decreasing the potentials of node A and wiring 111 to V1. Thus, signal OUT becomes the L level. And since signal OUT becomes the L level and signal IN1 remains at the H level , circuit 104 supplies the H-level signal IN1 to node B in the same manner as during period T4, thereby setting the potential of node B to V2. Then, since transistors 102 and transistor 103 turn on, wiring 116 and wiring 111 become conductive, and wiring 116 and node A become conductive. Thus, since voltage V1 is supplied from wiring 116 to wiring 111 via transistor 102, the potential of wiring 111 is maintained at V1. On the other hand, since voltage V1 is supplied from wiring 116 to node A via transistor 103, the potential of node A is maintained at V1. At this time, since the potential of node A is V1, transistor 101 turns off. Thus, wiring 112 and wiring 111 become non-conductive. In this way, the period during which signal OUT becomes the H level can be made shorter than the time during which signal IN1 becomes the H level. As a result, the driving frequency becomes slower compared to the case where the time during which signal IN1 becomes the H level and the time during which signal OUT becomes the H level are approximately equal. Thus, power consumption can be reduced. Note that, as an example, among transistors 101 to 103, or among the transistors included in the semiconductor device of FIG. 1(A),

[0098] it is preferable that the channel width of transistor 101 is the largest. By doing so, the on-resistance of transistor 101 is reduced. ​ Therefore, the rising time or the falling time of the signal OUT can be shortened. However and not limited thereto, the channel width of the transistor 101 can be smaller than any of the transistors of the semiconductor device shown in Fig. 1(A).

[0099] When referring to the channel width of a transistor, this can be rephrased as the W / L (W: channel width, L: channel length) ratio of the transistor.

[0100] As an example, the channel width of the transistor 102 is preferably larger than the channel width of the transistor 103. This is because the wiring 111 is often connected to a gate line or a pixel, etc., so the load of the wiring 111 is often larger than the load of the node A. And the transistor 102 has the function of supplying the voltage V1 to the wiring 111, and the transistor 103 has the function of supplying the voltage V1 to the node A. However, and not limited thereto, the channel width of the transistor 102 can be smaller than the channel width of the transistor 103.

[0101] As an example, in the transistor 101, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because in the period T2, the potential of the node A is likely to increase due to the bootstrap operation. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto.

[0102] ​Note that the wiring can be divided into a plurality of wirings. And, the same signal or voltage can be input to the plurality of wirings, or different signals or voltages can be input. Alternatively, the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in FIG. 5(A) shows a configuration in the case where wiring 112 is divided into a plurality of wirings 112A to 112B and wiring 116 is divided into a plurality of wirings 116A to 116D. The first terminal of transistor 101 is connected to wiring 112A, and terminal 104a of circuit 104 is connected to wiring 112B. The first terminal of transistor 102 is connected to wiring 116A, the first terminal of transistor 103 is connected to wiring 116B, terminal 104c of circuit 104 is connected to wiring 116C, and terminal 105d of circuit 105 is connected to wiring 116D. However, it is not limited thereto, and wiring 111, wiring 113, wiring 114, and / or wiring 115 can be divided into a plurality of wirings. Or only one of wiring 112 and wiring 116 can be divided into a plurality of wirings.

[0103] Note that in FIG. 5(A), wirings 112A to 112B correspond to wiring 112 in FIG. 1(A). Therefore, signal IN1 can be input to wirings 112A to 112B, and wirings 112A to 112B can function as signal lines or clock signal lines. However, it is not limited thereto, and any voltage such as voltage V1 or voltage V2 can be supplied to wirings 112A to 112B, and wirings 112A to 112B can function as power supply lines. It is possible. Or, various signals, or various voltages can be input to wirings 112A to 112B. Or, various other signals, various voltages, or various currents can be input to wirings 112A to 112B. In addition, in FIG. 5(A), wirings 116A to 116D correspond to the wiring 116 in FIG. 1(A). Therefore, it is possible to supply the voltage V1 to wirings 116A to 116D, and wirings 116A to 116D can function as power supply lines. However, it is not limited to this, and signals such as signal OUT, or signals IN1 to IN4 can be input to wirings 116A to 116D, and wirings 116A to 116D can function as signal lines. Or, various signals, or various voltages can be input to wirings 116A to 116D. Or, various other signals, various voltages, or various currents can be input to wirings 116A to 116D.

[0104]

[0105] In addition, in FIG. 5(A), it is possible to input a signal that becomes an L level to wirings 116A and 116B during period T4. For example, it is possible to input signal IN2 to wirings 116A and 116B. In this case, as shown in FIG. 5(B), the first terminals of transistor 102 and transistor 103 can be connected to wiring 113. Thus, a reverse bias can be applied to transistor 102 and transistor 103, so that the characteristic degradation of transistor 102 and transistor 103 can be alleviated. However, it is not limited to this, and wiring 116A and ​​​​​​​​​​​​​​​Input signal IN2 to one of line 116B, and only one of wiring 116A and wiring 116B can be connected to wiring 113. Alternatively, it is possible to input signal OUT, signal IN3, signal IN4, or other signals to wiring 116A and / or wiring 1 16B. In this case, the first terminal of transistor 103 and / or the first terminal of transistor 10 2 can be connected to wiring 111, wiring 114, or wiring 115. Or, it is possible to input signal OUT, signal IN2, signal IN3, signal IN4, or other signals to wiring 116C and / or wiring 116D. In this case, terminal 104c of circuit 104 and / or terminal 105d of circuit 105 can be connected to wiring 111, wiring 1 13, wiring 114, or wiring 115. As shown in FIG. 6(A), it is possible to newly connect a capacitive element 121 between the gate and the second terminal of transistor 101. By doing so, during the bootstrap operation in period T2, the potential of node A can be increased. Therefore, the Vgs of transistor 101 becomes larger, so the fall time or rise time of signal OUT can be shortened. However, it is not limited to this, and as the capacitive element 121,

[0106] it is possible to use a transistor as a MOS capacitor. In this case, in order to increase the capacitance value of the transistor used as the MOS capacitor, the gate of the transistor is connected to node A and it is preferable that the first terminal or the second terminal of the transistor is connected to wiring 111. Thus, during the bootstrap operation in period T2, the potential of node A can be increased. Therefore, the Vgs of transistor 101 becomes larger, so the fall time or rise time of signal OUT can be shortened. However, it is not limited to this, and as the capacitive element 121, it is possible to use a transistor as a MOS capacitor. In this case, in order to increase the capacitance value of the transistor used as the MOS capacitor, the gate of the transistor is connected to node A and it is preferable that the first terminal or the second terminal of the transistor is connected to wiring 111. it is possible to use a transistor as a MOS capacitor. In this case, in order to increase the capacitance value of the transistor used as the MOS capacitor, the gate of the transistor is connected to node A and it is preferable that the first terminal or the second terminal of the transistor is connected to wiring 111. and the first terminal or the second terminal of the transistor is connected to wiring 111. This is preferable.

[0107] Note that, similar to FIG. 6(A), in FIGS. 5(A) to (B) as well, a capacitor element 121 can be newly connected between the gate of the transistor 101 and the second terminal. Or, a transistor can be newly added in which the first terminal and the second terminal are connected to the wiring 111 and the gate is connected to the node A.

[0108] Note that, as shown in FIG. 6(B), a transistor 122 can be newly added in which the first terminal is connected to the wiring 111, the second terminal is connected to the node A, and the gate is connected to the wiring 112. The polarity of the transistor 122 is preferably the same as that of the transistors 101 to 103, and is often an N-channel type. However, it is not limited thereto, and the polarity of the transistor 122 can be a P-channel type. The transistor 12 2 has a function of controlling the timing at which the node A and the wiring 111 become conductive in response to the signal IN2, and can function as a switch. The transistor 122 turns on during the period T4 and makes the node A and the wiring 111 conductive.

[0109] Note that, similar to FIG. 6(B), in FIGS. 5(A) to (B) and FIG. 6(A) as well, a transistor 122 can be newly added in which the first terminal is connected to the wiring 111, the second terminal is connected to the node A, and the gate is connected to the wiring 112.

[0110] Note that, as shown in FIG. 6(C), the transistor 103 can be omitted. In this case, during the period T4, the node A often becomes a floating state. However, it is not limited thereto, and the transistor 102 can be omitted. In this case, during the period T4, ​​​​​​​​The wiring 111 often becomes a floating state. Thus, by omitting one of the transistor 102 and the transistor 103, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield, etc.

[0111] Similar to FIG. 6(C), in FIGS. 5(A) to (B) and FIGS. 6(A) to (B) as well, it is possible to omit the transistor 102 or the transistor 103. In particular, in FIG. 6 (B), it is preferable to omit one of the transistor 102 and the transistor 103. This is because in FIG. 6(B), during the period T4, the node A and the wiring 111 are in a conductive state, so the node A or the wiring 111 does not become a floating state.

[0112] As shown in FIG. 7(A), the transistor 102 can be replaced with a diode 102a in which one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the node B. Or, the transistor 103 can be replaced with a diode 103a in which one terminal (hereinafter also referred to as the positive electrode) is connected to the node A and the other terminal (hereinafter also referred to as the negative electrode) is connected to the node B. In this case, the circuit 104 can decrease the potential of the node B to V1 during the period T4 and increase the potential of the node B to V2 during the periods T1, T2, and T5. However, it is not limited to this, and only one of the transistor 102 and the transistor 103 can be replaced with a diode. Or, the diode 102a and / or the diode 103a can be newly added. One terminal (hereinafter also referred to as the positive electrode) is connected to the node A, and the other terminal (hereinafter also referred to as the negative electrode) is connected to the node B. It is possible to replace it with a diode 103a. In this case, the circuit 104 can decrease the potential of the node B to V1 during the period T4 and increase the potential of the node B to V2 during the periods T1, T2, and T5. However, it is not limited to this, and only one of the transistor 102 and the transistor 103 can be replaced with a diode. Or, the diode 102a and / or the diode 103a can be newly added. However, it is not limited to this, and only one of the transistor 102 and the transistor 103 can be replaced with a diode. Or, the diode 102a and / or the diode 103a can be newly added. One terminal (hereinafter also referred to as the positive electrode) is connected to the node A, and the other terminal (hereinafter also referred to as the negative electrode) is connected to the node B. It is possible to replace it with a diode 103a. In this

[0113] Note that, similar to FIG. 7(A), in FIGS. 5(A) to (B) and FIGS. 6(A) to (C) as well, the transistor 102 can be replaced with a diode 102a having one terminal connected to the wiring 111 and the other terminal connected to the node B. Or, the transistor 10 3 can be replaced with a diode 103a having one terminal connected to the node A and the other terminal connected to the node B. Or, the diode 102a and / or the diode 103a can be newly added. 103a can be newly added. In addition, although not shown, in FIGS. 1(A), 5(A) to (B), 6(A) to (C), and FIG.

[0114] 7(A), the transistor 102 or the transistor 103 can be diode-connected. In this case, the first terminal of the transistor 102 is connected to the node B, the second terminal of the transistor 102 is connected to the wiring 111, and the gate of the transistor 102 is connected to the node B or the wiring 111. The first terminal of the transistor 103 is connected to the node B, the second terminal of the transistor 103 is connected to the node A, and the gate of the transistor 103 is connected to the node A or the node B. However, it is not limited thereto, and only one of the transistor 102 and the transistor 103 can be diode-connected. is possible. is possible.

[0115] Note that, as shown in FIG. 7(B), the terminal 104b of the circuit 104 can be connected to the node A. By doing so, during the period T2, a signal of L level can be prevented from being input to the terminal 104b of the circuit 104, so that the potential of the node B can be maintained at V1. It becomes easier. Therefore, the potential of node B instantaneously rises, and it is possible to prevent transistors 102 and transistor 103 from turning on.

[0116] Similar to FIG. 7(B), in FIGS. 5(A) to (B), FIGS. 6(A) to (C), and FIG. 7(A), the terminal 104b of circuit 104 can be connected to node A.

[0117] Note that, as shown in FIG. 7(C), circuit 105 can be omitted.

[0118] Similar to FIG. 7(C), in FIGS. 5(A) to (B), FIGS. 6(A) to (C), and FIG. 7(A) to (B), circuit 105 can be omitted.

[0119] Note that, as shown in FIG. 28(B), the terminal 104a of circuit 104 can be connected to wiring 113. However, it is not limited thereto, and the terminal 104a of circuit 104 can also be connected to various other wirings, terminals, or nodes. Similar to FIG. 28(B), in FIGS. 5(A) to (B), FIGS. 6(A) to (C), and FIGS. 7(A) to (B), the terminal 104a of circuit 104 can be connected to wiring 113.

[0120] Note that, as shown in FIG. 8(A), P-channel type transistors can be used as transistors 101 to 103. Transistors 101p, 102p, and transistor 103p respectively correspond to transistors 101, 102, and transistor 103 and are of P-channel type. And, as shown in FIG. 8(B), when the polarity of the transistor is of P-channel type, voltage V2 is supplied to wiring 116, and signal OUT, signal ​​​​Signal IN1, signal IN2, signal IN3, signal IN4, the potential of node A, and the potential of node B It should be noted that it is inverted compared to the timing chart of Fig. 1(B).

[0121] In addition, in Fig. 8(A), the polarities of the transistors included in circuit 104 and circuit 105 are preferably P-channel type. However, it is not limited thereto, and the polarities of the transistors included in circuit 104 and circuit 105 can be N-channel type.

[0122] In addition, similar to Fig. 8(A) and Fig. 8(B), in Fig. 5(A) to (B), Fig. 6(A) to (C) , and Fig. 7(A) to (C), P-channel type transistors can also be used as transistors 101 to 103.

[0123] (Embodiment 2) In this embodiment, a specific example of circuit 104 described in Embodiment 1 will be described. Note that circuit 104 can be shown as a semiconductor device, a drive circuit, or a gate driver. Note that , the content described in Embodiment 1 will be omitted. Note that the content described in Embodiment 1 can be freely combined with the content described in this embodiment.

[0124] First, an example of circuit 104 will be described with reference to Fig. 9(A). In an example of Fig. 9(A) , circuit 104 includes transistor 201 (also referred to as the fourth transistor), transistor 202 (also referred to as the fifth transistor), transistor 203 (also referred to as the sixth transistor) , and transistor 204 (also referred to as the seventh transistor). However, it is not limited thereto, and any of these transistors can be omitted. Or , any of these transistors can be replaced with various elements such as a capacitive element, a resistive element, or a diode, or a circuit combining any of these elements. Or, it is possible to newly add various elements such as a transistor, a capacitive element, a resistive element, or a diode, or a circuit combining any of these elements.

[0125] As an example, assume that transistors 201 to 204 are N-channel type. In particular, when the transistors 101 to 103 described in Embodiment 1 are N-channel type, it is preferable that transistors 201 to 204 are N-channel type. In this way, all the transistors can be made N-channel type. However, it is not limited to this, and transistors 201 to 204 can be P-channel type.

[0126] Next, an example of the connection relationship of circuit 104 will be described. The first terminal of transistor 201 is connected to wiring 112, and the second terminal of transistor 201 is connected to node B. The first terminal of transistor 202 is connected to wiring 116, the second terminal of transistor 202 is connected to node B, and the gate of transistor 202 is connected to wiring 111. The first terminal of transistor 203 is connected to wiring 112, the second terminal of transistor 203 is connected to the gate of transistor 201, and the gate of transistor 203 is connected to wiring 112. The first terminal of transistor 204 is connected to wiring 116, the second terminal of transistor 204 is connected to the gate of transistor 201, and the gate of transistor 204 is connected to wiring 111. However, it is not limited to this, and there are other​​ It is possible to adopt various connection configurations.

[0127] Note that the connection point of the gate of transistor 201, the second terminal of transistor 203, or the second terminal of transistor 204 is denoted as node C. Note that node C can be represented by a wiring or a terminal. Note that node C can be represented by a wiring or a terminal. It is possible to represent it.

[0128] Note that various signals, various voltages, or various currents can be input to wiring 111, wiring 112, or wiring 116 as described in Embodiment 1. Here, as an example, it is assumed that the signal OUT described in Embodiment 1 is input to wiring 111. As an example, it is assumed that the signal IN1 described in Embodiment 1 is input to wiring 112. As an example, it is assumed that the voltage V1 described in Embodiment 1 is supplied to wiring 116. However, it is not limited thereto. Note that various signals, various voltages, or various currents can be input to wiring 111, wiring 112, or wiring 116 as described in Embodiment 1. Here, as an example, it is assumed that the signal OUT described in Embodiment 1 is input to wiring 111. As an example, it is assumed that the signal IN1 described in Embodiment 1 is input to wiring 112. As an example, it is assumed that the voltage V1 described in Embodiment 1 is supplied to wiring 116. However, it is not limited thereto. Note that various signals, various voltages, or various currents can be input to wiring 111, wiring 112, or wiring 116 as described in Embodiment 1. Here, as an example, it is assumed that the signal OUT described in Embodiment 1 is input to wiring 111. As an example, it is assumed that the signal IN1 described in Embodiment 1 is input to wiring 112. As an example, it is assumed that the voltage V1 described in Embodiment 1 is supplied to wiring 116. However, it is not limited thereto. Note that various signals, various voltages, or various currents can be input to wiring 111, wiring 112, or wiring 116 as described in Embodiment 1. Here, as an example, it is assumed that the signal OUT described in Embodiment 1 is input to wiring 111. As an example, it is assumed that the signal IN1 described in Embodiment 1 is input to wiring 112. As an example, it is assumed that the voltage V1 described in Embodiment 1 is supplied to wiring 116. However, it is not limited thereto. Note that various signals, various voltages, or various currents can be input to wiring 111, wiring 112, or wiring 116 as described in Embodiment 1. Here, as an example, it is assumed that the signal OUT described in Embodiment 1 is input to wiring 111. As an example, it is assumed that the signal IN1 described in Embodiment 1 is input to wiring 112. As an example, it is assumed that the voltage V1 described in Embodiment 1 is supplied to wiring 116. However, it is not limited thereto. However, it is not limited thereto.

[0129] Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... Next, an example of the functions of transistors 201 to 204 will be described. Transistor 201 has a function of controlling the timing of supplying signal IN2 to node B according to the potential of node C, and can function as a bootstrap transistor or a switch. Transistor 202 has a function of controlling the timing of supplying voltage V1 to node B by controlling the conduction state between wiring 116 and node B according to the potential (signal OUT) of wiring 111, and can function as a switch. Transistor 203 has a function of floating node C after raising the potential of node C, and can function as a diode. Transistor 204 has a function of... According to the signal OUT), by controlling the conduction state between the wiring 116 and the node C, the timing of supplying the voltage V1 to the node C is controlled, and it can function as a switch. However, it is not limited to this, and the transistors 201 to 204 can have various other functions. Or, these elements or circuits may not have the functions described above. It has a function of controlling the timing of supplying the voltage V1 to the node C and can function as a switch. However, it is not limited to this, and the transistors 201 to 204 can have various other functions. Or, these elements or circuits may not have the functions described above.

[0130] Next, the operation of the circuit 104 will be described with reference to FIGS. 1(B), 9(B), 9(C), 9(D), 9(E), and 9(F). FIG. 9(B) is an example of a schematic diagram of the operation of the circuit 104 in the period T1. FIG. 9(C) is an example of a schematic diagram of the operation of the circuit 104 in the period T2. FIG. 9(D) is an example of a schematic diagram of the operation of the circuit 104 in the period T3. FIG. 9(E) is an example of a schematic diagram of the operation of the circuit 104 in the period T4. FIG. 9(F) is an example of a schematic diagram of the operation of the circuit 104 in the period T5.

[0131] First, for the sake of convenience, the operations in the period T2 will be described first in order. In the period T2, the signal IN2 becomes the H level, and the signal OUT becomes the H level. Since the signal OUT becomes the H level, the transistors 202 and 204 are turned on. Then, the wiring 116 and the node B are in a conductive state, and the wiring 116 and the node C are in a conductive state. Therefore, the voltage V1 is supplied from the wiring 116 to the node B through the transistor 202, so the potential of the node B decreases to V1. And since the voltage V1 is supplied from the wiring 116 to the node C through the transistor 204, the potential of the node C decreases. The potential of the node C at this time is It is determined by the operating point with the transistor 203 and the transistor 204. Here, as an example, the potential of node C is assumed to be lower than the sum of the voltage V1 and the threshold voltage (Vth201) of the transistor 201 (V1 + Vth201). Therefore, the transistor 201 is turned off, and the wiring 112 and the node B are in a non-conductive state. The potential of node C is lower than the sum of the voltage V1 and the threshold voltage (Vth201) of the transistor 201 (V1 + Vth201). Therefore, the transistor 201 is turned off, and the wiring 112 and the node B are in a non-conductive state. Therefore, the wiring 112 and the node B are in a non-conductive state.

[0132] Next, in the period T3, the signal IN1 becomes the L level and the signal OUT becomes the L level. Since the signal OUT becomes the L level, the transistor 202 and the transistor 203 are turned off. Therefore, the wiring 116 and the node B are in a non-conductive state, and the wiring 116 and the node C are in a non-conductive state. And since the signal IN1 becomes the L level, the transistor 203 is turned off. Then, the node C becomes a floating state and maintains the potential in the period T2. Therefore, the transistor 201 remains off. Since the signal OUT becomes the L level, the transistor 202 and the transistor 203 are turned off. Therefore, the wiring 116 and the node B are in a non-conductive state, and the wiring 116 and the node C are in a non-conductive state. And since the signal IN1 becomes the L level, the transistor 203 is turned off. Then, the node C becomes a floating state and maintains the potential in the period T2. Therefore, the transistor 201 remains off.

[0133] Next, in the period T4, the signal IN1 becomes the H level and the signal OUT remains the L level. Since the signal OUT remains the L level, the transistor 202 and the transistor 203 remain off. Therefore, the wiring 116 and the node B remain in a non-conductive state, and the wiring 116 and the node C remain in a non-conductive state. At this time, the signal IN1 becomes the H level. Then, the transistor 203 is turned on, and the wiring 112 and the node C are in a conductive state. Therefore, the H-level signal IN1 is supplied from the wiring 112 to the node C through the transistor 203, and the potential of the node C starts to rise. After that, when the potential of the node C becomes V1 + Vth201, the transistor 201 is turned on. Then, the wiring 112 and the node Since the signal OUT remains the L level, the transistor 202 and the transistor 203 remain off. Therefore, the wiring 116 and the node B remain in a non-conductive state, and the wiring 116 and the node C remain in a non-conductive state. At this time, the signal IN1 becomes the H level. Then, the transistor 203 is turned on, and the wiring 112 and the node C are in a conductive state. Therefore, the H-level signal IN1 is supplied from the wiring 112 to the node C through the transistor 203. Therefore, the potential of the node C starts to rise. After that, when the potential of the node C becomes V1 + V th201, the transistor 201 is turned on. Then, the wiring 112 and the node Node B becomes conductive. Thus, the H-level signal IN1 is supplied from wiring 112 to node B via transistor 201, and the potential of node B begins to rise. After that, when the potential of node C reaches the value (V2 - Vth203) obtained by subtracting the threshold voltage (Vth203) of transistor 203 from the potential (V2) of the H-level signal IN1, transistor 203 turns off. Thus, wiring 112 and node C become non-conductive. Then, since node C is in a floating state, the potential of node C continues to rise further due to the capacitive coupling of the parasitic capacitance between the gate of transistor 201 and the second terminal, that is, the bootstrap operation. And if the potential of this node C becomes higher than V2 + Vth201, the potential of node B rises to V2.

[0134] Next, in period T5 or period T1, signal IN1 becomes L-level and signal OUT remains at L-level. Since signal OUT remains at L-level, transistors 202 and transistor 203 remain off. Thus, wiring 116 and node B remain non-conductive, and wiring 116 and node C remain non-conductive. And when signal IN1 becomes L-level, transistor 203 turns off, so wiring 112 and node C remain non-conductive. Thus, node C is in a floating state and maintains a potential higher than V2 + Vth201. As a result, transistor 201 remains on, so wiring 112 and node B remain conductive. Thus, the L-level signal IN1 is supplied from wiring 1 12 to node B via transistor 201, and the potential of node B decreases to V1. At this time, since node C is in a floating state, between the gate of transistor 201 and the second terminal of transistor 201...​​​​​​​​​​​​ Due to capacitive coupling of the parasitic capacitance between the terminal of 2, the potential often decreases. And the potential of node C often decreases by the amount that has been raised by the bootstrap operation during period T4.

[0135] Above, the circuit 104 in Fig. 9(A) has been described. The circuit 104 in Fig. 9(A) can raise the potential of node B to V2 by using the bootstrap operation. Therefore, the Vgs of the transistor 102 and the transistor 103 described in Embodiment 1 can be increased. As a result, the channel widths of the transistor 102 and the transistor 103 can be reduced, so that the layout area can be reduced. Or, even if the threshold voltages of the transistor 102 and the transistor 103 increase, the transistors can be easily turned on. Or, since the on-resistances of the transistor 102 and the transistor 103 become small, it is easy to maintain the potential of node A and the potential of the wiring 111 at V1. Or, in the circuit 104 of Fig. 9(A), the polarities of all the transistors can be N-channel type or P-channel type. Therefore, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost

[0136] can be reduced. In particular, when all the transistors are N-channel type, as the semiconductor layer of the transistors, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, etc. Therefore, the number of processes can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. However, not limited to this, the circuit 104 in Fig. 9(A) is a P-channel type transistor and an N-channel type transistor. tor can be used.​​​ It is possible to have a CMOS circuit composed of a stack. Or, it is possible to use a single-crystalline semiconductor or a polycrystalline semiconductor as the semiconductor layer of the transistor. Or, in the circuit 104 of FIG. 9(A), in at least one of the period T4 and the period T5, the transistors 202 to 204 are turned off. Therefore, since the transistor does not remain on throughout one operation period, it is possible to suppress characteristic degradation of the transistor such as an increase in the threshold voltage or a decrease in the mobility. Or, in the period T4 and the period T5, the node C repeats an increase and a decrease in potential. Thus, since a pulse is applied to the transistor 201, it is possible to suppress characteristic degradation of the transistor such as an increase in the threshold voltage or a decrease in the mobility. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer.

[0137] Also, as an example, it is preferable that the channel width of the transistor 203 is smaller than the channel width of the transistor 204. This is because, in the period T2, when the transistor 203 and the transistor 204 are turned on, the potential of the node C is lowered. For the same reason. during which the transistor does not stay on all the time, so that characteristic degradation of the transistor such as an increase in the threshold voltage or a decrease in mobility can be suppressed. Or, in periods T4 and T5, node C repeats an increase and a decrease in potential. Thus, since a pulse is applied to transistor 201, characteristic degradation of the transistor such as an increase in the threshold voltage or a decrease in mobility can be suppressed. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. C repeats an increase and a decrease in potential. Thus, since a pulse is applied to transistor 201, characteristic degradation of the transistor such as an increase in the threshold voltage or a decrease in mobility can be suppressed. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. C repeats an increase and a decrease in potential. Thus, since a pulse is applied to transistor 201, characteristic degradation of the transistor such as an increase in the threshold voltage or a decrease in mobility can be suppressed. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. In particular, when a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. is used as the semiconductor layer of the transistor, characteristic degradation of the transistor often appears significantly. However, in the semiconductor device of FIG. 9(A), since characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single-crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer. However, it is not limited to this, and a polycrystalline semiconductor or a single-crystalline semiconductor can be used as the semiconductor layer.

[0138] As an example, the channel width of transistor 203 is preferably smaller than the channel width of transistor 204. This is because, in period T2, when transistors 203 and 204 are turned on, the potential of node C is lowered. 204 are turned on, the potential of node C is lowered. By way of example, the channel length of transistor 203 is preferably shorter than the channel length of transistor 204. However, it is not limited thereto, and the channel width of transistor 203 can be larger than the channel width of transistor 204. Or, the channel length of transistor 203 can be smaller than the channel length of transistor 204. However, it is not limited thereto. The channel width of transistor 203 can be larger than the channel width of transistor 204. Or, the channel length of transistor 203 can be smaller than the channel length of transistor 204. That is possible.

[0139] Incidentally, by way of example, the channel width of transistor 204 is preferably smaller than the channel width of transistor 202. This is because the load at node B is often larger than the load at node C. For the same reason, the channel width of transistor 203 is preferably smaller than the channel width of transistor 201. However, it is not limited thereto, and the channel width of transistor 204 can be larger than the channel width of transistor 202. Or, the channel width of transistor 203 can be larger than the channel width of transistor 201. This is because the load at node B is often larger than the load at node C. For the same reason, the channel width of transistor 203 is preferably smaller than the channel width of transistor 201. However, it is not limited thereto. The channel width of transistor 204 can be larger than the channel width of transistor 202. Or, the channel width of transistor 203 can be larger than the channel width of transistor 201. That is possible.

[0140] Incidentally, by way of example, the channel width of transistor 201 and the channel width of transistor 202 are preferably approximately equal. This is because both transistor 201 and transistor 202 control the potential at node C and are transistors of the same polarity. However, it is not limited thereto, and the channel width of transistor 201 can be larger than the channel width of transistor 202, or can be smaller than the channel width of transistor 202. This is because both transistor 201 and transistor 202 control the potential at node C and are transistors of the same polarity. However, it is not limited thereto, and the channel width of transistor 201 can be larger than the channel width of transistor 202, or can be smaller than the channel width of transistor 202. However, it is not limited thereto. The channel width of transistor 201 can be larger than the channel width of transistor 202, or can be smaller than the channel width of transistor 202.

[0141] Incidentally, by way of example, transistors 201, 202, 203, or The channel width of the transistor 204 is preferably smaller than the channel width of the transistor 101, the transistor 102, or the transistor 103 described in Embodiment 1. However, it is not limited thereto, and the channel width of any one of the transistors 201 to 204 can be larger than the channel width of the transistor 101, the transistor 102, or the transistor 103 in FIG. 1(A). Preferably, the channel width of the transistor 204 is smaller than the channel width of the transistor 101, the transistor 102, or the transistor 103 described in Embodiment 1. However, it is not limited thereto, and the channel width of any one of the transistors 201 to 204 can be larger than the channel width of the transistor 101, the transistor 102, or the transistor 103 in FIG. 1(A). However, it is not limited thereto, and the channel width of any one of the transistors 201 to 204 can be larger than the channel width of the transistor 101, the transistor 102, or the transistor 103 in FIG. 1(A). In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto.

[0142] In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto. In the transistor 201, similar to the transistor 101 described in Embodiment 1, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal. This is because the potential of the node C tends to increase due to the body strap operation during the period T4. Therefore, the area where the conductive layer functioning as the gate and the conductive layer functioning as the source or drain overlap is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto.

[0143] A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with an L-level potential lower than V1 can be input to the terminal 104b. Thus, a reverse bias can be applied to the transistor 202 and the transistor 204, so that the characteristic degradation of the transistor 202 and the transistor 204 can be alleviated. Or, a signal with an H-level potential lower than V2 can be input to the terminal 104b. Thus, the Vgs when the transistor 202 and the transistor 204 are on can be reduced, so that the characteristic degradation of the transistor 202 and the transistor 204 can be suppressed. In such a case, an L-level A signal with a potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. However, it is not limited to this. Terminal 104b is connected to a wiring different from wiring 111, and a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the said wiring. is possible. Moreover, as in the first embodiment, it is possible to divide a wiring into a plurality of wirings. And the same signal or voltage can be input to the plurality of wirings, or different signals or voltages can be input. Or the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in Fig. 10(A) shows a configuration where wiring 111 is divided into a plurality of wirings such as wiring 111A to 111B, wiring 112 is divided into a plurality of wirings such as wiring 112C to 112D, and wiring 116 is divided into a plurality of wirings such as wiring 116E to 116F. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is possible.

[0144] voltages. Or the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in Fig. 10(A) shows a configuration where wiring 111 is divided into a plurality of wirings such as wiring 111A to 111B, wiring 112 is divided into a plurality of wirings such as wiring 112C to 112D, and wiring 116 is divided into a plurality of wirings such as wiring 116E to 116F. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings voltages. Or the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in Fig. 10(A) shows a configuration where wiring 111 is divided into a plurality of wirings such as wiring 111A to 111B, wiring 112 is divided into a plurality of wirings such as wiring 112C to 112D, and wiring 116 is divided into a plurality of wirings such as wiring 116E to 116F. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings voltages. Or the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in Fig. 10(A) shows a configuration where wiring 111 is divided into a plurality of wirings such as wiring 111A to 111B, wiring 112 is divided into a plurality of wirings such as wiring 112C to 112D, and wiring 116 is divided into a plurality of wirings such as wiring 116E to 116F. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings voltages. Or the plurality of wirings can be connected to the same wiring or the same element, or the plurality of wirings can be connected to different wirings or different elements. An example in Fig. 10(A) shows a configuration where wiring 111 is divided into a plurality of wirings such as wiring 111A to 111B, wiring 112 is divided into a plurality of wirings such as wiring 112C to 112D, and wiring 116 is divided into a plurality of wirings such as wiring 116E to 116F. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is shown. And the gate of transistor 204 is connected to wiring 111A, and the gate of transistor 202 is connected to wiring 111B. The first terminal of transistor 201 is connected to wiring 112C, and the first terminal and the gate of transistor 203 are connected to wiring 112D. The first terminal of transistor 202 is connected to wiring 116E, and the first terminal of transistor 204 is connected to wiring 116F. However, it is not limited to this, and only one or two of wiring 111, wiring 112, and wiring 116 may be divided into a plurality of wirings is possible.​ It is possible. Alternatively, different signals or different voltages can be input to the gate and the first terminal of the transistor 203. In this case, the gate of the transistor 203 and the first terminal can be connected to different wirings.

[0145] Note that in FIG. 10(A), the wirings 111A to 111B correspond to the wiring 111 in FIG. 9(A). Therefore, similar to the wiring 111, the signal OUT can be input to the wirings 111A to 111B, and the wirings 111A to 111B can function as signal lines. However, it is not limited to this, and voltages such as voltage V1 or voltage V2 can be supplied to the wirings 111A to 111B, and the wirings 111A to 111B can function as power supply lines. Alternatively, different signals or different voltages can be input to the wirings 111A to 111B. Or, various other signals, various voltages, or various currents can be input to the wirings 111A to 111B.

[0146] Note that in FIG. 10(A), the wirings 112C to 112D correspond to the wiring 112 in FIG. 9(A). Therefore, similar to the wiring 112, the signal IN1 can be input to the wirings 112C to 112D, and the wirings 112C to 112D can function as signal lines. However, it is not limited to this, and voltages such as voltage V1 or voltage V2 can be supplied to the wirings 112C to 112D, and the wirings 112C to 112D can function as power supply lines. Alternatively, different signals or different voltages can be input to the wirings 112C to 112D. Or, various other signals, various voltages, or various currents can be input to the wirings 112C to 112D. ​​​​​​​​​​​​​It is possible to input a signal, a different voltage, or a different current.

[0147] In FIG. 10A, the wirings 116E to 116F correspond to the wiring 116 in FIG. Therefore, like the wiring 116, the voltage V1 is supplied to the wirings 116E to 116F. The wirings 116E to 116F can function as power supply lines. However, the present invention is not limited to this. The wirings 116E to 116F may be connected to a signal OUT or a signal I By inputting signals such as N1 to IN4, the wirings 116E to 116F function as signal lines. Alternatively, the wirings 116E to 116F may be connected to separate voltages or Alternatively, the wirings 116E to 116F may be connected to other It is possible to input various signals, various voltages, or various currents.

[0148] Note that in FIG. 10A, the wirings 116E and 116F are For example, a signal that becomes an L level can be input to the wiring 116E and the wiring 1 A signal IN2 can be input to the wiring 116E and the wiring 116F. The line 116F can be connected to the wiring 113 described in the first embodiment. As a result, a reverse bias is applied to the transistors 202 and 204. Therefore, the deterioration of the characteristics of the transistors 202 and 204 can be reduced. However, the present invention is not limited to this. A signal may be provided to only one of the wiring 116E and the wiring 116F. In this case, only one of the wiring 116E and the wiring 116F can be used to input the signal IN2. can be connected to the wiring 113. Alternatively, the wiring 116E and / or the wiring It is possible to input the signal IN3 or the signal IN4 to the input terminal 116F. 116E and / or 116F may be replaced with the wiring 114 or wiring 11 described in the first embodiment. It is possible to connect to 5.

[0149] In FIG. 10A, the signal IN2 can be input to the wiring 112D. In this case, the gate and the first terminal of the transistor 203 are connected to the wiring 113. By doing so, the potential of the node C is at the H level during the period T3. The threshold voltage (Vth203) of the transistor 203 is subtracted from the potential (V2) of the signal IN2 of the After that, during a period T4, the signal IN1 becomes H level. Therefore, the voltage at node C becomes V2-Vth203 by the bootstrap operation. Therefore, the potential of the node C increases, and the V As a result, the output signal of the circuit 104 (potential of the node B) The fall time and rise time can be shortened. However, the present invention is not limited to this. It is possible to provide a voltage V2.

[0150] As shown in FIG. 10B, between the gate and the second terminal of the transistor 201, It is possible to newly connect a capacitor 221. By doing so, the capacitor 221 shown in FIG. Similarly, the potential of the node C can be increased. However, this is not limited to this, and the potential of the node C can be increased as shown in FIG. As in A), the first terminal and the second terminal of the capacitance element 221 are connected to the node B. A transistor whose gate is connected to node C can be used as a MOS capacitor. It is.

[0151] In addition, similar to FIG. 10(B), in FIG. 10(A) as well, a capacitor element 221 can be newly connected between the gate of the transistor 201 and the second terminal. Or, a transistor can be newly connected in which the first terminal and the second terminal are connected to node B and the gate is connected to node C. It is possible.

[0152] In addition, as shown in FIG. 10(C), the transistor 204 can be omitted. Also as shown in FIG. 10(D), the transistor 202 can be omitted. By doing so, the number of transistors can be reduced. Therefore, reduction of the layout area or improvement of the yield can be achieved. However, it is not limited thereto, and both the transistor 202 and the transistor 204 can be omitted.

[0153] In addition, similar to FIG. 10(C) or FIG. 10(D), in FIGS. 10(A) to (B) as well, the transistor 202 and / or the transistor 204 can be omitted.

[0154] In addition, as shown in FIG. 10(E), the transistor 202 can be replaced with a diode 202a in which one terminal (hereinafter also referred to as the positive electrode) is connected to node B and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 111. Or, the transistor 203 can be replaced with a diode 203a in which one terminal (hereinafter also referred to as the positive electrode) is connected to node C and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 111. In this case, at the terminal 104b of the circuit 104, an inverted signal of the signal OUT or the potential of node A is. It is possible to input an inverted signal. To achieve this, wiring 111, or node A can be connected to terminal 104b of circuit 104 via a circuit having a function of inverting and outputting an input signal such as an inverter circuit, a NAND circuit, or a NOR circuit. However, it is not limited to this, and it is possible to replace one of transistor 202 and transistor 204 with a diode. Or, it is possible to newly add diode 202a and / or diode 203a. Note that, similar to FIG. 10(E), also in FIGS. 10(A) to (D), it is possible to replace transistor 202 with diode 202a having one terminal connected to node B and the other terminal connected to wiring 111. Or, it is possible to replace transistor 203 with diode 203a having one terminal connected to node C and the other terminal connected to wiring 111. Or, it is possible to newly add diode 202a and / or diode 203a. Note that although not shown, in FIGS. 10(A) to (E), by connecting the first terminal of transistor 202 to wiring 111, the second terminal of transistor 202 to node B, and the gate of transistor 202 to wiring 111 or node B, it is possible to diode-connect transistor 202. Or, by connecting the first terminal of transistor 204 to wiring 111, the second terminal of transistor 204 to node C, and the gate of transistor 204 to wiring 111 or node C, it is possible to diode-connect transistor 204.

[0155]

[0156] ​​​​​​​​​​​​, the transistor 204 can be diode-connected. However, it is not limited to this, and only one of the transistors 202 and 204 can be diode-connected. It is possible.

[0157] As shown in FIG. 10(F), P-channel transistors can be used as the transistors 201 to 204. In particular, when P-channel transistors are used as the transistors 101 to 103 in FIG. 1(A), it is preferable to use P-channel transistors as the transistors 201 to 204. The transistors 201p, 202p, 203p, and 204p respectively correspond to the transistors 201, 202, 203, and 204 and are P-channel type.

[0158] Similar to FIG. 10(F), in FIGS. 10(A) to (E) as well, P-channel transistors can be used as the transistors 201 to 204.

[0159] As already described, it is possible to use the configuration of the circuit 104 described in this embodiment for the circuit 104 included in the circuit 100 described in Embodiment 1. FIG. 11 shows, as an example, the configuration when an example of the circuit 104 in FIG. 9(A) is used for the circuit 104 included in the circuit 100 in FIG. 7(C). However, it is not limited to this, and the circuit 104 in FIG. 9(A), FIG. 10(A), FIG. 10(B), FIG. 10(C), FIG. 10(D), FIG. 10(E), FIG. 10(F), or a combination thereof can be used for the circuits in FIG. 1(A), FIG. 5(A), FIG. 5(B), FIG. 6(A), FIG. 6. ​​​​​​​​​​​​​(B), FIG. 6(C), FIG. 7(A), FIG. 7(B), FIG. 8(A), or a combination thereof In this case, the circuit 100 may include a circuit 104.

[0160] (Embodiment 3) In this embodiment, a specific example of the circuit 105 will be described. In addition, the first embodiment and the second embodiment can be referred to as a gate driver. The contents described in the second embodiment will not be described. The contents described in the second embodiment can be freely combined with the contents described in this embodiment.

[0161] First, an example of the circuit 105 will be described with reference to FIG. In the circuit 105, a transistor 301 (also referred to as an eighth transistor) A transistor 302 (also called a ninth transistor), a transistor 303 (also called a tenth transistor), a transistor 304 (also referred to as an eleventh transistor), and a transistor 305 (also referred to as a twelfth transistor). However, the present invention is not limited to this. It is possible to omit any of the transistors. Any of the above may be used as a capacitance element, a resistance element, a diode, or other various elements. It is possible to replace the transistor with a circuit that combines any of the elements. Various elements such as a transistor, a capacitance element, a resistance element, or a diode, or It is possible to add a new circuit that combines any of these elements.

[0162] As an example, the transistors 301 to 305 are N-channel transistors. to the transistors 101 to 103 described in Embodiment 1 and the transistors 201 to 204 described in Embodiment 2, when they are N-channel type, the transistors 301 to 305 are , preferably N-channel type. In this way, all the transistors can have the same polarity. However, it is not limited to this, and the transistors 301 to 305 can be P-channel type.

[0163] Next, an example of the connection relationship of the circuit 105 in FIG. 12(A) will be described. The first terminal of the transistor 30 1 is connected to the wiring 114, the second terminal of the transistor 301 is connected to the node A, and the gate of the transistor 301 is connected to the wiring 114. The first terminal of the transistor 302 is connected to the wiring 114, the second terminal of the transistor 302 is connected to the node A, and the gate of the transistor 302 is connected to the wiring 113. The first terminal of the transistor 303 is connected to the wiring 116, the second terminal of the transistor 303 is , connected to the node A, and the gate of the transistor 303 is connected to the wiring 115. The first terminal of the transistor 304 is connected to the wiring 116, the second terminal of the transistor 304 is , connected to the wiring 111, and the gate of the transistor 304 is connected to the wiring 115. . The first terminal of the transistor 305 is connected to the wiring 116, the second terminal of the transistor 305 is connected to the wiring 111, and the gate of the transistor 305 is connected to the wiring 113. However, it is not limited to this, and various other connection configurations are possible.

[0164] Note that the wiring 113, the wiring 114, the wiring 115, or the wiring 116 may be the same as those described in Embodiment 1. It is possible to input various signals, various voltages, or various currents. Here as an example, the signal IN2 described in Embodiment 1 is input to the wiring 113. As an example, the signal IN3 described in Embodiment 1 is input to the wiring 114. As an example, the signal IN4 shown in FIG. 1(B) or FIG. 3(A) is input to the wiring 115. As an example, the voltage V1 is supplied to the wiring 116. However, it is not limited thereto.

[0165] Next, an example of the functions of the transistors 301 to 305 will be described. The transistor 301 can control the timing of supplying the H-level signal IN2 to the node A according to the signal IN3 and function as a diode. Or, the transistor 301 has a function of controlling the timing of supplying the signal IN3 to the node A by controlling the conduction state between the wiring 114 and the node A according to the potential of the node A. The transistor 3 02 has a function of controlling the timing of supplying the signal IN3 to the node A by controlling the conduction state between the wiring 114 and the node A according to the signal IN2 and can function as a switch. The transistor 303 has a function of supplying the voltage V1 to the node A by controlling the conduction state between the wiring 116 and the node A according to the signal IN4 and can function as a switch. The transistor 304 has a function of supplying the voltage V1 to the wiring 111 by controlling the conduction state between the wiring 116 and the wiring 111 according to the signal IN4 and can function as a switch. The transistor 3 05 controls the conduction state between the wiring 116 and the wiring 111 according to the signal IN2. Thereby, it has a function of supplying the voltage V1 to the wiring 111 and can function as a switch. Thereby, it has a function of supplying the voltage V1 to the node A and can function as a switch. The transistor 304 has a function of supplying the voltage V1 to the wiring 111 by controlling the conduction state between the wiring 116 and the wiring 111 according to the signal IN4 and can function as a switch. The transistor 3 05 controls the conduction state between the wiring 116 and the wiring 111 according to the signal IN2. Thereby, it has a function of supplying the voltage V1 to the wiring 111 and can function as a switch. Thereby, it controls the conduction state between the wiring 116 and the wiring 111 according to the signal IN2. and has a function of supplying the voltage V1 to the wiring 111 and can function as a switch However, it is not limited to this, and the transistors 301 to 305 can have various other functions as well. Alternatively, these elements or circuits may not have the functions described above either.

[0166] Next, the operation of the circuit 105 will be described with reference to FIGS. 1(B), 12(B), 12(C), 13( A), 13(B), and 13(C). FIG. 12(B) is an example of a schematic diagram of the operation of the circuit 105 in the period T1. FIG. 12(C) is an example of a schematic diagram of the operation of the circuit 105 in the period T2. FIG. 13(A) is an example of a schematic diagram of the operation of the circuit 105 in the period T3. FIG. 13(B) is an example of a schematic diagram of the operation of the circuit 105 in the period T4. FIG. 13(C) is an example of a schematic diagram of the operation of the circuit 105 in the period T5.

[0167] First, in the period T1, the signal IN2 becomes the H level, the signal IN3 becomes the H level, and the signal IN4 becomes the L level. Since the signal IN3 becomes the H level, the transistor 301 is turned on . At the same time, since the signal IN2 becomes the H level, the transistors 302 and 305 are turned on. Then, since the wiring 114 and the node A are in a conductive state, the signal IN 3 is supplied from the wiring 114 to the node A through the transistors 301 and 302 . Therefore, the potential of the node A starts to rise. Similarly, since the wiring 116 and the wiring 111 are in a conductive state, the voltage V1 is supplied from the wiring 116 to the wiring 11 1 through the transistor 305. Therefore, the potential of the wiring 111 becomes V1. At this time, the signal IN4 is at the L level Since the transistor 303 and the transistor 304 are turned off, the wiring The wiring 116 and the node A are brought out of conduction, and the wiring 116 and the wiring 111 are brought out of conduction. After that, the potential of the node A changes from the potential of the wiring 114 (V2) to the threshold voltage of the transistor 301. When the voltage (Vth301) is subtracted from the value (V2-Vth301), the transistor Similarly, the potential of the node A changes from the potential of the wiring 113 (V2) to the potential of the transistor 301. The point where the threshold voltage of the first transistor (Vth302) is subtracted from the threshold voltage of the second transistor (Vth302) is (V2-Vth302). Therefore, the transistor 302 is turned off. Therefore, there is no electrical continuity between the wiring 114 and the node A. Here, as an example, when the potential of node A becomes V2-Vth301, Therefore, the transistors 301 and 302 are turned off. A becomes floating while maintaining the potential at V2-Vth301.

[0168] Next, in the period T2, the signal IN3 goes to the L level, the signal IN4 goes to the L level, and the signal Since the signal IN3 becomes L level, the transistor 301 At the same time, the signal IN2 goes low, so the transistor 302 The transistor 303 remains off, and the wiring 114 and the node A are The non-conductive state remains, and the wiring 116 and the wiring 111 are non-conductive. Since the signal IN4 remains at the L level, the transistors 303 and 304 are off. Therefore, the wiring 116 and the node A remain in a non-conductive state, and the wiring 116 and the wiring 111 remain in a non-conductive state.

[0169] Next, in period T3, signal IN2 becomes high level, signal IN3 remains low level , and signal IN4 becomes high level. Since signal IN3 remains low level, transistor 30 1 remains off. And since signal IN2 becomes high level, transistors 302 , and transistor 304 turn on. Then, since wiring 114 and node A become conductive , low-level signal IN3 is supplied from wiring 114 to node A via transistor 302 . Similarly, since wiring 116 and wiring 111 become conductive, voltage V1 is supplied from wiring 116 to wiring 111 via transistor 305. At this time, since signal IN 4 becomes high level, transistors 303 and transistor 304 turn on. Then, since wiring 116 and node A become conductive, voltage V1 is supplied from wiring 116 to node A via tra nsistor 303. Similarly, since wiring 116 and wiring 111 become conductive , voltage V1 is supplied from wiring 116 to wiring 111 via transistor 304 . Therefore, the potential of node A decreases to V1, and the potential of wiring 111 decreases to V1.

[0170] Next, in period T4, signal IN2 becomes low level, signal IN3 remains low level , and signal IN4 becomes low level. Since signal IN3 remains low level, transistor 30 1 remains off. And since signal IN2 becomes low level, transistors 302 , and transistor 305 turn off. Thus, wiring 114 and node A become non-conductive , and wiring 116 and wiring 111 become non-conductive. At the same time, since signal IN4 becomes low level , transistors 303 and transistor 304 turn off. Thus, the wiring 116 and node A are in a non-conductive state, and wiring 116 and wiring 111 are in a non-conductive state. . Thus, in period T4, in many cases, the circuit 105 does not supply a signal, voltage, etc. to node A or wiring 111.

[0171] Next, in period T5, signal IN2 becomes high level, signal IN3 remains low level, and signal IN4 remains low level. Since signal IN4 remains low level, transistors 303 and transistor 304 turn off. Therefore, wiring 116 and node A are in a non- conductive state, and wiring 116 and wiring 111 are in a non-conductive state. Similarly, since signal IN3 remains low level, transistor 301 remains off. At this time, since signal IN2 becomes high level, transistors 302 and transistor 305 turn on. Then, since wiring 114 and node A become conductive, the low-level signal IN3 is supplied from wiring 114 to node A via transistor 302. Therefore, the potential of node A is maintained at V1. Similarly, since wiring 116 and wiring 111 become conductive, voltage V1 is supplied from wiring 116 to wiring 111 via transistor 305. Therefore, the potential of wiring 111 is maintained at V1.

[0172] Above, the circuit 105 in FIG. 12(A) has been described. In the circuit 105 of FIG. 12(A), all transistors can be of N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. In particular, when all transistors are of N-channel type, as the semiconductor layer of the Thus, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. Therefore, it is possible to reduce the number of steps, improve the yield, improve the reliability, or reduce the cost. However, it is not limited thereto. The circuit 105 in FIG. 12(A) can be composed of a P-channel type transistor and an N-channel type transistor to form a CMOS circuit. Or, as the semiconductor layer of the transistor, it is possible to use a single crystal semiconductor or a polycrystalline semiconductor. Moreover, in the circuit 105 of FIG. 12(A), at least one of the period T4 and the period T5, the transistors 301 to 305 are turned off. Therefore, since the transistors do not remain in the on state throughout one operation period, it is possible to suppress the characteristic degradation of the transistors such as an increase in the threshold voltage or a decrease in the mobility. In particular, when a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as the semiconductor layer of the transistor, the characteristic degradation of the transistor often appears significantly. However, in the circuit 105 of FIG. 12(A), since the characteristic degradation of the transistor can be suppressed, it becomes easy to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like as the semiconductor layer of the transistor. However, it is not limited thereto, and as the semiconductor layer, it is possible to use a polycrystalline semiconductor or a single crystal semiconductor. In addition, as an example, the channel width of the transistor 305 is preferably larger than the channel width of the transistor 302. Or, as an example, the channel width of the transistor 304 is preferably larger than the channel width of the transistor 303. Because the wiring 11

[0173]

[0174] ​ The load of 1 is often greater than the load of node A, so the driving ability of the transistor that supplies a signal or voltage to wiring 111 is often greater than that of the transistor that supplies a signal or voltage to node A. This is because. And transistors 305 and 304 have the function of supplying a signal or voltage to wiring 111, and transistors 302 and 303 have the function of supplying a signal or voltage to node A. However, it is not limited to this. The channel width of transistor 305 can be smaller than the channel width of transistor 302. Or, for example, the channel width of transistor 304 can be smaller than the channel width of transistor 303. This is because noise is likely to occur at node A due to the parasitic capacitance between the first terminal and the gate of transistor 101 described in Embodiment 1. And due to this noise, transistor 101 may turn on and the potential of wiring 111 may increase.

[0175] As an example, it is preferable that the channel width of transistor 303 is larger than the channel width of transistor 302. Or, for example, it is preferable that the channel width of transistor 304 is larger than the channel width of transistor 305. By doing so, the influence of noise generated at node A and wiring 111 can be reduced. However, it is not limited to this. The channel width of transistor 303 can be smaller than the channel width of transistor 302. Or, the channel width of transistor 304 can be smaller than the channel width of transistor 305.

[0176] Note that signals with an L-level potential lower than V1 can be input to terminal 105a and terminal 105c. In this way, it becomes possible to apply a reverse bias to transistors 302 to 305, so that the characteristic degradation of transistors 302 to 305 can be alleviated. Or, signals with an H-level potential lower than V2 can be input to terminal 105a and terminal 105c. In this way, when transistors 302 to 305 are on, Vgs can be reduced, so that the characteristic degradation of transistors 302 to 305 can be suppressed. In such a case, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to wiring 113 and wiring 115. However, it is not limited to this. On one of terminal 105a and terminal 105c, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. In this case, on one of wiring 113 and wiring 115, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. Or, terminal 105a is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. Or, terminal 105 is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. However, it is not limited to this. On one of terminal 105a and terminal 105c, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. In this case, on one of wiring 113 and wiring 115, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. In this case, on one of wiring 113 and wiring 115, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. Or, terminal 105a is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. Or, terminal 105 is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. Or, terminal 105a is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. Or, terminal 105 is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. In this case, on one of wiring 113 and wiring 115, signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input. Or, terminal 105 is connected to a wiring different from wiring 113, and signals with an L-level potential lower than V1, signals with an H-level potential lower than V2, or signals with an L-level potential lower than V1 and an H-level potential lower than V2 can be input to the wiring. c is connected to a wiring other than the wiring 115, and the potential of the L level is lower than V1. A signal whose H level potential is lower than V2, or whose L level potential is lower than V1, In addition, it is possible to input a signal whose H level potential is lower than V2.

[0177] The terminal 105d is at the L level during the periods T1, T3, and T4. For example, the signal IN2 can be input to the terminal 105d. In this case, the terminal 105d can be connected to the wiring 113. By doing so, the transistor 303, the transistor 304, or the transistor Since a reverse bias can be applied to the transistor 305, the transistor 303 and the transistor This can alleviate the deterioration of the characteristics of the resistor 304 or the transistor 305.

[0178] As in the first or second embodiment, the wiring can be divided into a plurality of wirings. The same signal or voltage can be input to the multiple wirings. Alternatively, the multiple wirings may be connected to the same The wires may be connected to the same element, or the wires may be separate wires or In the example shown in FIG. 14A, the wiring 113 is a wiring The wiring 114 is divided into a plurality of wirings 114A to 114B. The wiring 115 is divided into a plurality of wirings 115A to 115B. In the case where the wiring 116 is divided into a plurality of wirings 116G to 116I, The gate of the transistor 302 is connected to the wiring 113A. The gate of transistor 305 is connected to wiring 113B. The first terminal of transistor 302 is connected to wiring 114A, and the first terminal and gate of transistor 301 are connected to wiring 114B . The gate of transistor 303 is connected to wiring 115A, and the gate of transistor 304 is connected to wiring 115B. The first terminal of transistor 303 is connected to wiring 116G , the first terminal of transistor 304 is connected to wiring 116H, and the first terminal of transistor 3 05 is connected to wiring 116I. However, it is not limited thereto, and only one, two, or three of wiring 113 , wiring 114, wiring 115, and wiring 116 can be divided into a plurality of wiring.

[0179] In addition, in FIG. 14(A), wiring 113A to 113B corresponds to wiring 113 in FIG. 12(A). Therefore, similar to wiring 113, signal IN2 can be input to wiring 113A to 113B, and wiring 113A to 113B can function as a signal line . However, it is not limited thereto, and voltage V1 or voltage V 2 or other voltages can be supplied to wiring 113A to 113B, and wiring 113A to 113B can function as a power supply line . Or, different signals or different voltages can be input to wiring 113A to 113B. Or, various other signals, various voltages, or various currents can be input to wiring 113A to 113B.

[0180] In addition, in FIG. 14(A), wiring 114A to 114B corresponds to wiring 114 in FIG. 12(A). Therefore, similar to wiring 114, signal IN3 can be input to wiring 114A to 114B, and It is possible to apply force, and wirings 114A to 114B can function as signal lines However, it is not limited to this. Voltages such as voltage V1 or voltage V 2 can be supplied to wirings 114A to 114B, and wirings 114A to 114B can function as power supply lines Or, different signals or different voltages can be input to wirings 114A to 114B. Or, various other signals, various voltages, or various currents can be input to wirings 114A to 114B.

[0181] In addition, in FIG. 14(A), wirings 115A to 115B correspond to the wiring 115 in FIG. 12(A). Therefore, similar to the wiring 115, a signal IN4 can be input to wirings 115A to 115B, and wirings 115A to 115B can function as signal lines However, it is not limited to this. Voltages such as voltage V1 or voltage V 2 can be supplied to wirings 115A to 115B, and wirings 115A to 115B can function as power supply lines However, it is not limited to this. Voltages such as voltage V1 or voltage V 2 can be supplied to wirings 115A to 115B, and wirings 115A to 115B can function as power supply lines Or, different signals or different voltages can be input to wirings 115A to 115B. Or, various other signals, various voltages, or various currents can be input to wirings 115A to 115B.

[0182] In addition, in FIG. 14(A), wirings 116G to 116I correspond to the wiring 116 in FIG. 12(A). Therefore, similar to the wiring 116, voltage V1 can be supplied to wirings 116G to 116I, and wirings 116G to 116I can function as power supply lines However, it is not limited to this. A signal OUT or a signal However, it is not limited to this. A signal OUT or a signal can be supplied to wirings 116G to 116I, and wirings 116G to 116I can function as power supply lines. However, it is not limited to this. Signals OUT, or signals By inputting signals such as IN1 to IN4, wirings 116G to 116I can function as signal lines Alternatively, different voltages, or different signals can be supplied to wirings 116G to 116I. Alternatively, various signals, various voltages, or various currents can also be input to wirings 116G to 116I.

[0183] In addition, in FIG. 14(A), it is possible to input a signal that becomes an L level to wirings 116G and 116H during period T3. For example, it is possible to input signal IN2 to wirings 116G and 116H. In this case, wirings 116G and 116H can be connected to wiring 112 described in Embodiment 1 and Embodiment 2. By doing so, reverse bias can be applied to transistors 303 and 304, so that characteristic degradation of transistors 303 and 304 can be suppressed. However, it is not limited to this, and it is possible to input signal IN2 to only one of wiring 116G and wiring 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. 16H. In this case, wirings 116G and 116H can be connected to wiring 112 described in Embodiment 1 and Embodiment 2. By doing so, reverse bias can be applied to transistors 303 and 304, so that characteristic degradation of transistors 303 and 304 can be suppressed. However, it is not limited to this, and it is possible to input signal IN2 to only one of wiring 116G and wiring 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. line 116H. In this case, wirings 116G and 116H can be connected to wiring 112 described in Embodiment 1 and Embodiment 2. By doing so, reverse bias can be applied to transistors 303 and 304, so that characteristic degradation of transistors 303 and 304 can be suppressed. However, it is not limited to this, and it is possible to input signal IN2 to only one of wiring 116G and wiring 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. can be suppressed. However, it is not limited to this, and it is possible to input signal IN2 to only one of wiring 116G and wiring 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. can be applied to transistors 303 and 304, so that characteristic degradation of transistors 303 and 304 can be suppressed. However, it is not limited to this, and it is possible to input signal IN2 to only one of wiring 116G and wiring 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. However, it is not limited to this, and it is possible to input signal IN2 to only one of wiring 116G and wiring 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. 116H. Alternatively, it is possible to input signal OUT or signal IN3 to wiring 116G and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. and / or wiring 116H. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2. In this case, wiring 116G and / or wiring 116H can be connected to wiring 111 or wiring 114 described in Embodiment 1 and Embodiment 2.

[0184] In addition, in FIG. 14(A), it is possible to input a signal that becomes an L level to wiring 116I during period T1, period T3, and period T5. For example, it is possible to input signal IN2 to wiring 116I. In this case, wiring 116I is in Embodiment 1 and Embodiment In addition, in FIG. 14(A), it is possible to input a signal that becomes an L level to wiring 116I during period T1, period T3, and period T5. For example, it is possible to input signal IN2 to wiring 116I. In this case, wiring 116I is in Embodiment 1 and Embodiment IN2 to wiring 116I. In this case, wiring 116I is in Embodiment 1 and Embodiment ​​It can be connected to the wiring 112 described in the form 2. By doing so, a reverse bias can be applied to the transistor 305, so that the characteristic deterioration of the transistor 305 can be suppressed. However, it is not limited to this. It is possible to apply a reverse bias to the transistor 305, so that the characteristic deterioration of the transistor 305 can be suppressed. However, it is not limited to this.

[0185] In addition, as shown in FIG. 14(B), it is possible to omit the transistors 303 and 304. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this, and it is possible to omit only one of the transistors 303 and 304. In addition, as in FIG. 14(B), in FIG. 14(A) as well, it is possible to omit the transistors 303 and / or the transistor 304. However, it is not limited to this, and it is possible to omit only one of the transistors 303 and 304. In addition, as shown in FIG. 14(C), it is possible to omit the transistor 305. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this.

[0186] In addition, as in FIG. 14(C), in FIGS. 14(A) to 14(B) as well, it is possible to omit the transistor 305. In addition, as shown in FIG. 15(A), it is possible to omit the transistor 302. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this.

[0187] In addition, as shown in FIG. 14(C), it is possible to omit the transistor 305. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this. In addition, as in FIG. 14(C), in FIGS. 14(A) to 14(B) as well, it is possible to omit the transistor 305. However, it is not limited to this.

[0188] In addition, as in FIG. 14(C), in FIGS. 14(A) to 14(B) as well, it is possible to omit the transistor 305. In addition, as shown in FIG. 15(A), it is possible to omit the transistor 302. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this.

[0189] In addition, as shown in FIG. 15(A), it is possible to omit the transistor 302. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this. By doing so, the number of transistors can be reduced. Therefore, it is possible to reduce the layout area or improve the yield. However, it is not limited to this.

[0190] Note that, similar to FIG. 15(A), in FIGS. 14(A) to (C) as well, the transistor 302 can be omitted.

[0191] Note that, as shown in FIG. 15(B), the transistor 301 can be omitted. By doing so, the number of transistors can be reduced. Thus, reduction of the layout area, or improvement of the yield, etc. can be achieved. However, it is not limited thereto.

[0192] Note that, similar to FIG. 15(B), in FIGS. 14(A) to (C) and FIG. 15(A) as well, the transistor 301 can be omitted.

[0193] Note that, as shown in FIG. 16(A), the transistor 303 can be replaced with a diode 303a where one terminal (hereinafter also referred to as the positive electrode) is connected to node A and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 115. Or, the transistor 304 can be replaced with a diode 304a where one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 115. However, it is not limited thereto, and either one of the transistor 303 and the transistor 304 can be replaced with a diode. Or, the diode 303a and / or the diode 304a can be newly added.

[0194] Note that, similar to FIG. 16(A), in FIGS. 14(A) to (C) and FIGS. 15(A) to (B) as well, the transistor 303 can be replaced with a diode 303a where one terminal is connected to node A and the other terminal is connected to the wiring 11 The terminal 304 can be replaced with a diode 304a in which one terminal is connected to the wiring 111 and the other terminal is connected to the wiring 115. Or, the diode 303a, and / or, a diode 304a can be newly added.

[0195] Although not shown in the drawings, in FIGS. 14(A) to (C), FIGS. 15(A) to (B), and FIGS. 16(A ), the first terminal of the transistor 303 is connected to the wiring 115, and the transistor 3 03's second terminal is connected to the node A, and the gate of the transistor 303 is connected to the node A , whereby the transistor 303 can be diode-connected. Also or, the first terminal of the transistor 304 is connected to the wiring 115, and the transistor 304's second terminal is connected to the wiring 111, and the gate of the transistor 304 is connected to the wiring 111 , whereby the transistor 304 can be diode-connected. However , it is not limited to this, and either the transistor 303 or the transistor 304 can be diode connected.

[0196] As shown in FIG. 16(B), the transistor 305 can be replaced with a diode 305a in which one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 113 . However, it is not limited to this, and a diode 305a can be newly added.

[0197] Similar to FIG. 16(B), in FIGS. 14(A) to (C), FIGS. 15(A) to (B), and FIGS. 1 6(A) as well, the transistor 305 can be replaced with a diode in which one terminal (hereinafter also referred to as the positive electrode) is connected to the wiring ​​One terminal is connected to 111, and the other terminal (hereinafter also referred to as the negative electrode) is connected to wiring 113, and it can be replaced with diode 305a. Or, it is possible to newly add diode 305a. Although not shown in the drawings, in FIGS. 14(A) to (C), FIGS. 15(A) to (B), and FIGS. 16(A ), by connecting the first terminal of transistor 305 to wiring 113, the second terminal of transistor 305 to wiring 111, and the gate of transistor 305 to wiring 111, transistor 305 can be diode-connected. However, it is not limited to this.

[0198] ), by connecting the first terminal of transistor 305 to wiring 113, the second terminal of transistor 305 to wiring 111, and the gate of transistor 305 to wiring 111, transistor 305 can be diode-connected. However, it is not limited to this. ), by connecting the first terminal of transistor 305 to wiring 113, the second terminal of transistor 305 to wiring 111, and the gate of transistor 305 to wiring 111, transistor 305 can be diode-connected. However, it is not limited to this. ), by connecting the first terminal of transistor 305 to wiring 113, the second terminal of transistor 305 to wiring 111, and the gate of transistor 305 to wiring 111, transistor 305 can be diode-connected. However, it is not limited to this. ), by connecting the first terminal of transistor 305 to wiring 113, the second terminal of transistor 305 to wiring 111, and the gate of transistor 305 to wiring 111, transistor 305 can be diode-connected. However, it is not limited to this. ), by connecting the first terminal of transistor 305 to wiring 113, the second terminal of transistor 305 to wiring 111, and the gate of transistor 305 to wiring 111, transistor 305 can be diode-connected. However, it is not limited to this.

[0199] As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117. As shown in FIG. 17(A), the gate of transistor 301 can be connected to wiring 117. For this reason, circuit 105 can newly have terminal 105g. And wiring 117 is connected to the gate of transistor 301 via terminal 105g. Voltage V2 is supplied to wiring 117, and wiring 117 can function as a power line. However, it is not limited to this. It is possible that the first terminal of transistor 301 is connected to wiring 117 and the gate of transistor 301 is connected to wiring 114. Or, it is possible to input a signal that becomes H level to wiring 117 during period T2, and wiring 117 can function as a signal line. For example, it is possible to input signal IN2 to wiring 117, and wiring 117 can be connected to wiring 113. Or, various other signals, various voltages, or various currents can be input to wiring 117.

[0200] Note that, similar to FIG. 17(A), in FIGS. 14(A) to (C), FIGS. 15(A) to (B), and FIGS. 16(A) to (B), the gate of transistor 301, or the first terminal of transistor 301 can be connected to wiring 117.

[0201] Note that, as shown in FIG. 17(B), transistors 306 and 307 can be newly added. As an example, transistors 306 and 307 are often of the same polarity as transistors 301 to 305 and are assumed to be N-channel type. The first terminal of transistor 306 is connected to wiring 116, the second terminal of transistor 306 is connected to node A, and the gate of transistor 306 is connected to wiring 118. The first terminal of transistor 307 is connected to wiring 116, the second terminal of transistor 307 is connected to wiring 111, and the gate of transistor 307 is connected to wiring 118. As an example, signal IN5 is input to wiring 118, and wiring 118 can function as a signal line. Transistor 306 has a function of controlling the conduction state between wiring 116 and node A according to signal IN5 or the potential of wiring 115, thereby controlling the timing at which voltage V1 is supplied to node A, and can function as a switch. Transistor 307 has a function of controlling the conduction state between wiring 116 and wiring 111 according to signal IN5 or the potential of wiring 115, thereby controlling the timing at which voltage V1 is supplied to wiring 111, and can function as a switch. Signal IN5 functions as a full-stage reset signal, for example. ​​​​​​​​​​​​​​​is numerous. However, it is not limited to this, and only one of the transistor 306 and the transistor 307 can be newly added.

[0202] Note that, similar to FIG. 17(B), in FIGS. 14(A) to (C), FIGS. 15(A) to (B), FIGS. 16( A) to (B), and FIG. 17(A) as well, it is possible to newly add the transistor 306 and / or the transistor 307. The first terminal of the transistor 306 is connected to the wiring 116, the second terminal of the transistor 306 is connected to the node A, and the gate of the transistor 306 is connected to the wiring 118. The first terminal of the transistor 307 is connected to the wiring 116, the second terminal of the transistor 307 is connected to the wiring 111 , and the gate of the transistor 307 is connected to the wiring 118.

[0203] Note that, as shown in FIG. 17(C), as the transistors 301 to 305, P-channel type transistors can be used. In particular, when using the transistors 101 to 103 described in Embodiment 1 and the transistors 201 to 204 described in Embodiment 2 as P-channel type transistors, it is preferable to use P-channel type transistors as the transistors 301 to 305. The transistor 301p, the transistor 302p, the transistor 303p, the transistor 304p, and the transistor 305p respectively correspond to the transistor 301, the transistor 302, the transistor 303, the transistor 304, the transistor 305.

[0204] Note that, similar to FIG. 17(C), in FIGS. 14(A) to (C), FIGS. 15(A) to (B), FIGS. 16( In FIGS. (A) to (B) and FIGS. 17(A) to (B) as well, transistors 301 to 305 can be P-channel transistors.

[0205] As already described, the configuration of circuit 105 described in this embodiment can be used for circuit 105 included in circuit 100 described in Embodiment 1. FIG. 18(A) shows, as an example, the configuration when an example of circuit 105 in FIG. 12(A) is used for circuit 105 included in circuit 100 in FIG. 1(A). And FIG. 18(B) shows, as an example, the configuration when an example of circuit 105 in FIG. 12(A) is used for circuit 105 included in circuit 100 in FIG. 1(A), and further an example of circuit 104 in FIG. 9(A) is used for circuit 104 included in circuit 100 in FIG. 1(A). However, the present invention is not limited to this. The circuit 105 in FIGS. 12(A), 14(A), 14(B), 14(C), 15(A), 15(B), 16(A), 16(B), 17(A), 17(B), 17(C), or a combination thereof can be used for circuit 105 included in circuit 100 in FIGS. 1(A), 5(A), 5(B), 6(A), 6(B), 6(C), 7(A), 7(B), 8(A), or a combination thereof. (Embodiment 4) In this embodiment, an example of a shift register will be described. The shift register of this embodiment can have the semiconductor devices of Embodiments 1 to 3. Note that the shift register can indicate a semiconductor device or a gate driver. Note that the description of the content described in Embodiments 1 to 3 is omitted.

[0206] In this embodiment, an example of a shift register will be described. The shift register of this embodiment can have the semiconductor devices of Embodiments 1 to 3. Note that the shift register can indicate a semiconductor device or a gate driver. Note that the description of the content described in Embodiments 1 to 3 is omitted. Note that the description of the content described in Embodiments 1 to 3 is omitted. The content described in Embodiment 3 can be freely combined with the content described in this embodiment. is.

[0207] First, an example of a shift register will be described with reference to FIG. 19. The shift register 40 0 has a plurality of flip-flops 401_1 to 401_N (N is a natural number). has.

[0208] Note that the flip-flops 401_1 to 401_N respectively correspond to the semiconductor devices described in Embodiments 1 to 3. In an example of FIG. 19, the case where the semiconductor device of FIG. 1(A) is used as the flip-flops 401_1 to 40 1_N is shown. However, it is not limited to this, and as the flip-flops 401_1 to 401_N, in addition to the semiconductor device of FIG. 1(A), other semiconductor devices described in Embodiments 1 to 3, or various other semiconductor devices or circuits can be used. is possible.

[0209] Next, the connection relationship of the shift register will be described. The shift register 400 is connected to the wirings 41 1_1 to 411_N, the wiring 412, the wiring 413, the wiring 414, and the wiring 415. And in the flip-flop 401_i (i is any one of 1 to N), the wiring 1 11 is connected to the wiring 411_i, the wiring 112 is connected to one of the wiring 412 and the wiring 413, the wiring 113 is connected to the other of the wiring 412 and the wiring 413, the wiring 114 is connected to the wiring 41 1_i - 1, the wiring 115 is connected to the wiring 411_i + 1, and the wiring 116 is connected to the wiring 416. Here, in many cases, the connection destinations of the wiring 112 and the wiring 113 are reversed between the odd-stage flip-flops and the even-stage flip-flops. For example, odd stages, and for even-stage flip-flops In the flip-flop of the stage, wiring 112 is connected to wiring 412, and wiring 113 is connected to wiring 413. In the flip-flop of the even stage, when wiring 112 is connected to wiring 41 3 and wiring 113 is often connected to wiring 412. On the other hand, in the flip-flop of the odd stage when wiring 112 is connected to wiring 413 and wiring 113 is connected to wiring 412 subsequently, in the flip-flop of the even stage, wiring 112 is often connected to wiring 412 and wiring 113 is connected to wiring 413. However, it is not limited to this, and other connection configurations are also possible.

[0210] Note that in flip-flop 401_1, wiring 114 is often connected to wiring 414. And in flip-flop 401_N, wiring 115 is often connected to wiring 415.

[0211] Note that wiring 411_1 to 411_N respectively correspond to wiring 111 described in Embodiment 1 to Embodiment 3. Wiring 412 corresponds to wiring 112 or wiring 113 described in Embodiment 1 to Embodiment 3. Wiring 413 corresponds to wiring 112 or wiring 113 described in Embodiment 1 to Embodiment 3. Wiring 414 corresponds to wiring 1 14 described in Embodiment 1 to Embodiment 3. Wiring 415 corresponds to wiring 115 described in Embodiment 1 to Embodiment 3. Wiring 416 corresponds to wiring 116 described in Embodiment 1 to Embodiment 3.

[0212] Next, an example of a signal or voltage input to or output from wiring 411_1 to 411_N, wiring 412, wiring 413, wiring 414, wiring 415 , and wiring 416 will be described. Wiring 411_ From 1 to 411_N, as an example, signals GOUT_1 to GOUT_N are each output respectively. Signals GOUT_1 to GOUT_N are each the output signals of flip-flops 401_1 to 401_N. And signals GOUT_1 to GOUT_N correspond to the signal OUT described in Embodiments 1 to 3, and can function as an output signal, a selection signal, a transfer signal, a start signal, a reset signal, a gate signal, or a scan signal. It is possible. As an example, it is assumed that a signal GCK is input to wiring 412. Signal GCK corresponds to the signal IN1 or signal IN2 described in Embodiments 1 to 3, and can function as a clock signal respectively. As an example, it is assumed that a signal GCKB is input to wiring 413. Signal GCKB corresponds to the signal IN1 or signal IN2 described in Embodiments 1 to 3, and can function as an inverted clock signal. As an example, it is assumed that a signal GSP is input to wiring 414. Signal GSP corresponds to the signal IN3 described in Embodiments 1 to 3, and can function as a start signal or a vertical synchronization signal respectively. As an example, it is assumed that a signal GRE is input to wiring 415. Signal GRE corresponds to the signal IN4 described in Embodiments 1 to 3, and can function as a reset signal respectively. As an example, it is assumed that a voltage V1 is input to wiring 416. However, it is not limited to this, and various other signals, various currents, or various voltages can be input to wirings 411_1 to 411_N, wiring 412, wiring 413, wiring 414, wiring 415, and / or wiring 416. For example, voltages such as voltage V1 or voltage V2 are supplied to wiring 412, wiring 41 3, wiring 414, and / or wiring 415. respectively. It is possible. However, it is not limited to this. To wirings 411_1 to 411_N, wiring 412, wiring 413, wiring 414, wiring 415, and / or wiring 416, it is also possible to input various other signals, various currents, or various voltages. For example, voltages such as voltage V1 or voltage V2 are supplied to wiring 412, wiring 41 3, wiring 414, and / or wiring 415. It is possible. Or, signals such as signal GOUT_1 to GOUT_N, signal GCK, signal GCKB, signal GSP, or signal GRE can be input to wiring 416. Or, without inputting signals or voltages, etc. to wirings 411_1 to 411_N, wiring 412, wiring 413, wiring 414, wiring 415, and / or wiring 416, these wirings can be put in a floating state.

[0213] Note that wirings 411_1 to 411_N can function as signal lines, gate lines, scan lines, or output signal lines. Wiring 412 can function as a signal line or a clock signal line. Wiring 413 can function as a signal line or a clock signal line. Wiring 414 can function as a signal line. Wiring 415 can function as a signal line. Wiring 416 can function as a power line or a ground line. However, it is not limited to this, and wirings 411_1 to 411_N, wiring 412, wiring 413, wiring 414, wiring 415, and / or wiring 416 can function as various other wirings. For example, when voltages are supplied to wiring 412, wiring 413, wiring 41 4, and / or wiring 415, these wirings can function as power lines. Or, when a signal is input to wiring 416, wiring 416 can function as a signal line.

[0214] Note that as already described, a polyphase clock signal or an unbalanced clock signal can be input to the shift register.

[0215] Note that signals or voltages, etc. are input to wiring 412, wiring 413, wiring 414, wiring 415, and wiring 416 from circuit 4 20. Circuit 420 has a function of controlling shift register 40 0 by supplying a signal or voltage, etc. thereto, and can function as a control circuit or a controller, etc. In this embodiment as an example, circuit 420 supplies signal GCK, signal GCKB, signal GSP, signal GRE, and voltage V 1 to wiring 412, wiring 413, wiring 414, wiring 415, and wiring 416, respectively. However, it is not limited thereto, and circuit 420 can supply signals or voltages to not only shift register 4 00 but also various other circuits (for example, a signal line drive circuit, a scanning line drive circuit, and / or a pixel, etc.) and control these circuits .

[0216] Note that circuit 420 has circuit 421 and circuit 422 as an example. Circuit 42 1 has a function of generating power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage, and can function as a power supply circuit or a regulator. Circuit 42 2 has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator . However, it is not limited thereto, and circuit 420 can have various other circuits or various elements in addition to circuit 42 1 and circuit 42 2. For example, circuit 42 0 can have an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, an operational amplifier, a shift register, a look-up table, a coil, a transistor . ​It is possible to have a clock, a capacitive element, a resistive element, and / or a frequency divider, etc.

[0217] Next, the operation of the shift register in FIG. 19 will be described with reference to the timing chart in FIG. 20. This will be explained. FIG. 20 is an example of a timing chart for explaining the operation of the shift register. FIG. 20 shows an example of the signals GSP, GRE, GCK, GCKB, GOU T_1, GOUT_i - 1, GOUT_i, GOUT_i + 1, and G OUT_N. Note that the parts common to the operations of the semiconductor devices in Embodiments 1 to 3 will not be described.

[0218] The operation of flip - flop 401_i will be described. First, signal GOUT_i - 1 becomes H level. Then, flip - flop 401_i starts its operation in period T1, and signal GOUT_i becomes L level. After that, signals GCK and GCKB are inverted. Then, flip - flop 401_i starts its operation in period T2, and signal GOU T_i becomes H level. Signal GOUT_i is input as a reset signal to flip - flop 401_i - 1 and as a start signal to flip - flop 401_i + 1. Thus, flip - flop 401_i - 1 starts its operation in period T3, and flip - flop 401_i + 1 starts its operation in period T1. After that, signals GCK and GCKB are inverted again. Then, flip - flop 401_i + 1 starts its operation in period T2, and signal GOUT_i + 1 becomes H level. Signal GOUT _i + 1 is input as a reset signal to flip - flop 401_i. Therefore, GCK and signal GCKB are inverted again. Then, flip - flop 401_i + 1 starts its operation in period T2, and signal GOUT_i + 1 becomes H level. Signal GOUT _i + 1 is input as a reset signal to flip - flop 401_i. Therefore, ​, since the flip-flop 401_i starts operating in the period T3, the signal GOUT_ i becomes the L level. After that, until the signal GOUT_i-1 becomes the H level again, the flip- flop 401_i repeats the operation in the period T4 and the operation in the period T5 every time the signals GCK and GCKB are inverted.

[0219] Note that in the flip-flop 401_1, instead of the output signal of the previous-stage flip-flop, the signal GSP is input from the circuit 420 via the wiring 414. Therefore, when the signal GSP becomes the H level, the flip-flop 401_1 starts operating in the period T1.

[0220] Note that in the flip-flop 401_N, instead of the output signal of the next-stage flip-flop, the signal GRE is input from the circuit 420 via the wiring 415. Therefore, when the signal GRE becomes the H level, the flip-flop 401_N starts operating in the period T3.

[0221] The operation of the shift register according to the present embodiment has been described above. The shift register according to the present embodiment can obtain the same advantages as the semiconductor device by using the semiconductor devices of Embodiments 1 to 3.

[0222] Note that, as described in Embodiments 1 to 3, it is possible to make the relationship between the signals GCK and GCKB unbalanced. For example, as shown in the timing chart of FIG. 21(A), in the signals GCK and GCKB, it is possible to make the period of becoming the H level shorter than the period of becoming the L level. By doing so, the signals GOUT_1 to GOUT ​​​​​_N can prevent these signals from becoming high level even if delay or smear occurs. Therefore, when the shift register of the present embodiment is used in a display device , it is possible to prevent a plurality of rows from being selected simultaneously. However, it is not limited to this, and in the signal GCK and / or signal GCKB, it is possible that the period of becoming high level is longer than the period of becoming low level.

[0223] As described in Embodiments 1 to 3, it is possible to use a multi-phase clock signal. For example, as shown in the timing chart of FIG. 21(B), it is possible to use an M-phase (M is a natural number ) clock signal. In this case, in signals GOUT_1 to GOUT _N, the period of becoming high level in a certain stage can overlap with the periods of becoming high level in the previous and subsequent stages. Therefore, when the present embodiment is used in a display device , a plurality of rows will be selected simultaneously. As a result, it becomes possible to use the video signals to other rows as precharge voltages.

[0224] In addition, in FIG. 21(B), it is preferable that M≤8. More preferably, it is preferable that M≤6. Even more preferably, it is preferable that M≤4. This is because when the shift register is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals will be written to the pixel . And since the period during which an incorrect video signal is input to the pixel becomes long, the display quality may deteriorate.

[0225] Similar to FIG. 21(B), also in the timing chart of FIG. 21(A), a multi-phase clock It is possible to use a lock signal.

[0226] Note that the wiring 415 can be shared with other wirings or omitted. For example, the wiring 415 can be shared with the wiring 412, the wiring 413, the wiring 414, or the wiring 416. In this case, the wiring 415 is omitted, and in the flip - flop 401_N, the wiring 115 can be connected to the wiring 412, the wiring 413, the wiring 414, or the wiring 416. As another example, the wiring 415 can be omitted. In this case, in the flip - flop 401_N, similar to FIG. 14(B), the transistors 303 and 304 included in the circuit 105 can be omitted.

[0227] Depending on the configurations of the flip - flops 401_1 to 401_N, it is possible to add new wirings. For example, as shown in FIG. 17(A) or FIG. 17(B), when a voltage V2 or a signal that can function as a full - stage reset signal is required, new wirings can be added. And signals or voltages, etc., can be supplied to the newly added wirings from the circuit 420.

[0228] Note that as shown in FIG. 22, it is possible to add transistors 431 to the flip - flops 401_1 to 401_N, respectively. The polarity of the transistor 431 is preferably the same as that of the transistor 101, and in many cases, it is an N - channel type. However, it is not limited to this, and the transistor 431 can be a P - channel type. In the flip - flop 401_i, the first terminal of the transistor 431 is connected to the wiring 112. , the second terminal of the transistor 431 is connected to the wiring 417_i, and the gate of the transistor 431 is connected to the node A. In the flip-flop 401_i, the wiring 111 is connected to the wiring 411_i, the wiring 112 is connected to one of the wirings 412 and 413, the wiring 113 is connected to the other of the wirings 412 and 413, the wiring 114 is connected to the wiring 417_i - 1, the wiring 115 is connected to the wiring 411_i + 1, and the wiring 11 6 is connected to the wiring 416. By doing so, even when a load such as a pixel or a gate line is connected to the wirings 411_1 to 411_N, there will be no distortion or delay in the transfer signal for driving the flip-flop in the next stage. Therefore, the influence of the delay of the shift register can be reduced. However, it is not limited to this, and the wiring 114 can be connected to the wiring 4 11_i - 1. Alternatively, the wiring 115 can be connected to the wiring 417_i + 1. Alternatively, it is possible to newly add a transistor for maintaining the potential of the wirings 417_1 to 417_N at V1. 1. In addition, in FIG. 22 as well, similar to FIG. 21(A), it is possible to make the signals GCK and GCKB unbalanced. Alternatively, similar to FIG. 21(B), it is possible to use a multi-phase clock signal.

[0229] Note that also in FIG. 22, similar to FIG. 21(A), it is possible to make the signals GCK and GCKB unbalanced. Alternatively, similar to FIG. 21(B), it is possible to use a multi-phase clock signal.

[0230] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0231] First, referring to FIG. 23(A), an example of the system block of a liquid crystal display device will be described. The liquid crystal display device includes circuits 5361, 5362, 5363_1, 5363_ 2. It includes a pixel section 5364, a circuit 5365, and a lighting device 5366. In the pixel section 5364 a plurality of wirings 5371 extend from the circuit 5362 and are arranged, and a plurality of wirings 5372 extend from the circuits 5363_1 and 5363_2 and are arranged. And in the intersection regions of the plurality of wirings 5371 and the plurality of wirings 5372, pixels 5367 each having display elements such as liquid crystal elements are arranged in a matrix.

[0232] The circuit 5361 has a function of supplying signals, voltages, currents, etc. to the circuits 5362, 5363_1, 5363_2, and 5365 according to the video signal 5360, and can function as a controller, a control circuit, a timing generator, a power supply circuit, a regulator, etc. In this embodiment, as an example, the circuit 5361 supplies a start signal for signal line drive circuit (SSP), a clock signal for signal line drive circuit ( SCK), an inverted clock signal for signal line drive circuit (SCKB), data for video signal (DA TA), and a latch signal (LAT) to the circuit 5362. Or, as an example, the circuit 5361 supplies a start signal for scan line drive circuit (G SP), a clock signal for scan line drive circuit (GCK), and an inverted clock signal for scan line drive circuit ( GCKB) to the circuits 5363_1 and 5363_2. Or, the circuit 5361 supplies a backlight control signal (BLC) to the circuit 5365. However, it is not limited to this, and the circuit 5361 can also supply various signals, various voltages, or various currents, etc. to the circuits 5362, 5363_1, 5363_2, and 5365.

[0233] Circuit 5362 has the function of outputting a video signal to a plurality of wirings 5371 in response to signals supplied from circuit 5361 (for example, SSP, SCK, SCKB , DATA, LAT), and can function as a signal line driving circuit. Circuit 5363_1 and circuit 536 3_2 have the function of outputting a detection signal to a plurality of wirings 5372 in response to signals (GSP, GCK, GCKB) supplied from circuit 5361, and can function as a scanning line driving circuit . Circuit 5365 has the function of controlling the amount of power supplied to lighting device 5366, or the time, etc., in response to a signal (BLC) supplied from circuit 5361, and can function as a power supply circuit by controlling the brightness (or average brightness) of lighting device 5366 . When a video signal is input to the plurality of wirings 5371, the plurality of wirings 5371 can function as signal lines, video signal lines, or source lines, etc. When a scanning signal is input to the plurality of wirings 53 72, the plurality of wirings 5372 can function as signal lines, scanning lines, or gate lines, etc. However, it is not limited to this .

[0234] When the same signal is input from circuit 5361 to circuit 5363_1 and circuit 5363_2, the scanning signal output by circuit 5363_1 to the plurality of wirings 5372 and the scanning signal output by circuit 5363 _2 to the plurality of wirings 5372 are often at approximately the same timing. Therefore, the load driven by circuit 5363_1 and circuit 5363_2 can be reduced . Thus, the display device can be enlarged. Or, the display device can be made larger

[0235] . When the same signal is input from circuit 5361 to circuit 5363_1 and circuit 5363_2, the scanning signal output by circuit 5363_1 to the plurality of wirings 5372 and the scanning signal output by circuit 5363 _2 to the plurality of wirings 5372 are often at approximately the same timing. Therefore, the load driven by circuit 5363_1 and circuit 5363_2 can be reduced . Thus, the display device can be enlarged. Or, the display device can be made larger It can be made highly precise. Or, since the channel widths of the transistors included in circuit 5363_1 and circuit 5363_2 can be reduced, a display device with a narrow border can be obtained. However, it is not limited to this. Circuit 5361 can supply separate signals to circuit 5363_1 and circuit 536 3_2.

[0236] Note that it is possible to omit one of circuit 5363_1 and circuit 5363_2.

[0237] In addition, it is possible to newly arrange wirings such as capacitance lines, power supply lines, and scanning lines in pixel section 5364. And circuit 5361 can output signals or voltages to these wirings. Or, a circuit similar to circuit 5363_1 or circuit 5363_2 can be newly added, and this newly added circuit can output signals such as scanning signals to the newly added wirings.

[0238] Note that pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in Fig. 23(B), since the display element can emit light, circuit 5 365 and lighting device 5366 can be omitted. And in order to supply power to the display element, a plurality of wirings 5373 that can function as power supply lines can be arranged in pixel section 53 64. Circuit 5361 can supply a power supply voltage called voltage (ANO) to wiring 5373. This wiring 5373 can be connected separately for each color element of the pixel, or can be commonly connected to all pixels.

[0239] In Fig. 23(B), as an example, circuit 5361 is circuit 5363_1 and circuit 536 An example of the case of supplying separate signals to 3_2 is shown. Circuit 5361 is for the scanning line driving circuit supplies signals such as a start signal (GSP1), a clock signal (GCK1) for the scanning line driving circuit, and a clock signal (GCKB1) for the inverted scanning line driving circuit to circuit 5363_1. Then, circuit 5361 supplies signals such as a start signal (GSP2) for the scanning line driving circuit, a clock signal (GCK2) for the scanning line driving circuit, and a clock signal (GCKB2) for the inverted scanning line driving circuit to circuit 5363_2. In this case, circuit 5363_1 scans only the wirings of the odd-numbered rows among the plurality of wirings 53 72, and circuit 5363_2 can scan only the wirings of the even-numbered rows among the plurality of wirings 5372. Therefore, since the driving frequencies of circuit 5363_1 and circuit 5363_2 can be reduced, power consumption can be reduced. Or, the area where one-stage flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. Or, the display device can be made large. However, it is not limited to this. Similar to FIG. 23(A), circuit 5361 can output the same signal to circuit 5363_1 and circuit 5363_2. In addition, similar to FIG. 23(B), also in FIG. 23(A), circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2. As described above, an example of the system block of the display device has been described. Next, an example of the configuration of the display device will be described with reference to FIGS. 24(A), (B), (C), (D), and ( E). However, it is not limited to this. Similar to FIG. 23(A), circuit 5361 can output the same signal to circuit 5363_1 and circuit 5363_2. However, it is not limited to this. Similar to FIG. 23(A), circuit 5361 can output the same signal to circuit 5363_1 and circuit 5363_2.

[0240] Note that, similar to FIG. 23(B), also in FIG. 23(A), circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2. Note that, similar to FIG. 23(B), also in FIG. 23(A), circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2.

[0241] As described above, an example of the system block of the display device has been described.

[0242] Next, an example of the configuration of the display device will be described with reference to FIGS. 24(A), (B), (C), (D), and ([E]). Next, an example of the configuration of the display device will be described with reference to FIGS. 24(A), (B), (C), (D), and (E).

[0243] In FIG. 24(A), circuits having a function of outputting signals to the pixel portion 5364 (for example, circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as the pixel portion 5364. And the circuit 5361 is formed on a substrate different from the pixel portion 5364 Thus, the number of external components is reduced, so that the cost can be reduced. Or, since the number of signals or voltages input to the substrate 5380 is reduced, the number of connections between the substrate 5380 and the external components can be reduced. Therefore, the reliability or the yield can be improved.

[0244] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate can be mounted on an FPC (Flexible Printed Circuit) by a TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 538 0 as the pixel portion 5364 by a COG (Chip on Glass) method.

[0245] When the circuit is formed on a substrate different from the pixel portion 5364, transistors using single-crystalline semiconductors can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in driving frequency, an improvement in driving voltage, and a reduction in variation of output signals.

[0246] In many cases, signals, voltages, currents, etc. are input from an external circuit via the input terminal 5381.

[0247] In FIG. 24(B), circuits with low driving frequencies (for example, circuit 5363_1, circuit 5363_​​​​ (2) is formed on the same substrate 5380 as the pixel portion 5364. Then, the circuit 5361, and the circuit 5362 are formed on a substrate different from the pixel portion 5364. Thus, a circuit formed on the substrate 5380 can be configured by transistors with low mobility. Therefore, as the semiconductor layer of the transistor, a polycrystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. Accordingly, enlargement of the display device, reduction of the number of processes, cost reduction, or improvement of the yield can be achieved. In addition, as shown in FIG. 24(C), a part of the circuit 5362 (circuit 5362a) is formed on the same substrate 5380 as the pixel portion 53 64, and the remaining circuit 5362 (circuit 5362b) can be formed on a substrate different from the pixel portion 5

[0248] 364. The circuit 5362a often has a circuit (for example, a shift register, a selector, a switch, etc.) that can be configured by transistors with low mobility. And the circuit 5362b often has a circuit (for example, a shift register, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.) that is preferably configured by transistors with high mobility and small characteristic variations. By doing so, as in FIG. 24(B), as the semiconductor layer of the transistor, a polycrystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, or the like can be used, and further reduction of external components can be achieved. In FIG. 24(D), a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, the circuit 5363_1, and the circuit 5363_2, etc.), and controlling these circuits a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, the circuit 5363_1, and the circuit 5363_2, etc.), and controlling these circuits . By doing so, as in FIG. 24(B), as the semiconductor layer of the transistor, a polycrystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, or the like can be used, and further reduction of external components can be achieved. a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, the circuit 5363_1, and the circuit 5363_2, etc.), and controlling these circuits

[0249] In FIG. 24(D), a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, the circuit 5363_1, and the circuit 5363_2, etc.), and controlling these circuits A circuit having a function (e.g., circuit 5361) is formed on a substrate different from the pixel portion 5364. Thus, the pixel portion and its peripheral circuits can be formed on separate substrates, enabling an improvement in yield.

[0250] Similar to FIG. 24(D), in FIGS. 24(A) to (C) as well, the circuits 5363_1 and 5363_2 can be formed on a substrate different from the pixel portion 5364.

[0251] In FIG. 24(E), a part of the circuit 5361 (circuit 5361a) is formed on the same substrate 5380 as the pixel portion 5364, and the remaining circuit 5361 (circuit 5361b) is formed on a substrate different from the pixel portion 5364. The circuit 5361a may have a circuit (e.g., a switch, selector, level shift circuit, etc.) that can be configured by transistors with low mobility. And the circuit 5361b preferably has a circuit (e.g., shift register, timing generator, oscillator, regulator, or analog buffer, etc.) that can be configured using transistors with high mobility and small variation.

[0252] In FIGS. 24(A) to (D) as well, the circuit 5361a can be formed on the same substrate as the pixel portion 5364, and the circuit 5361b can be formed on a substrate different from the pixel portion 5364.

[0253] The display device of this embodiment has been described above. The circuits 5363_1 and 5363_2 can use the semiconductor device or shift register of Embodiments 1 to 4. In this case, the circuits 5363_1 and 5363_2 and the pixel portion are formed on the same substrate. By making this so, the polarities of all the transistors formed on the substrate can be made N-channel type or P-channel type. Therefore, it is possible to reduce the number of processes, improve the yield, improve the reliability, or reduce the cost. In particular, when the polarities of all the transistors are N-channel type, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like as the semiconductor layer of the transistor. Thus, it is possible to increase the size of the display device, reduce the cost, or improve the yield.

[0254] Note that transistors using a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer often exhibit characteristic degradation such as an increase in the threshold voltage or a decrease in the mobility. However, the semiconductor devices or shift registers of Embodiments 1 to 4 can suppress the characteristic degradation of the transistors, so the life of the display device can be extended.

[0255] Note that it is possible to use the semiconductor devices or shift registers of Embodiments 1 to 4 as part of the circuit 5362. For example, the circuit 5362a can have the semiconductor devices or shift registers of Embodiments 1 to 4

[0256] (Embodiment 6) In this embodiment, an example of a signal line driving circuit will be described. Note that the signal line driving circuit can be referred to as a semiconductor device or a signal generation circuit.

[0257] An example of the signal line driving circuit will be described with reference to FIG. 25(A). The signal line driving circuit It has a plurality of circuits, namely circuits 502_1 to 502_N (N is a natural number), circuit 500, and circuit 5 01. Each of the circuits 502_1 to 502_N has a plurality of transistors, namely transistors 503_ 1 to 503_k (k is a natural number). The transistors 503 _1 to 503_k shall be of the N-channel type. However, it is not limited thereto, and the transistors 503 _1 to 503_k can be of the P-channel type, or can be a CMOS type switch.

[0258] Regarding the connection relationship of the signal line driving circuit, circuit 502_1 will be taken as an example for explanation. The first terminals of the transistors 503 _1 to 503_k are connected to wiring 505_1. The second terminals of the transistors 5 03_1 to 503_k are respectively connected to wirings S1 to Sk. The gates of the transistors 503 _1 to 503_k are respectively connected to wirings 504_1 to 504_k . For example, the first terminal of transistor 503_1 is connected to wiring 505_1, the second terminal of transistor 503_1 is connected to wiring S1, and the gate of transistor 503_1 is connected to wiring 504_1.

[0259] Circuit 500 has the function of supplying signals to circuits 502_1 to 502_ N via wirings 504_1 to 504_k, and can function as a shift register, a decoder, or the like . The signal is often a digital signal and can function as a selection signal . And wirings 504_1 to 504_k can function as signal lines .

[0260] Circuit 501 has the function of outputting signals to circuits 502_1 to 502_N, and generates a video signal It is possible to function as a circuit or the like. For example, circuit 501 supplies a signal to circuit 502_1 via wiring 505_1. At the same time, it supplies a signal to circuit 502_2 via wiring 505_2. The signal is often an analog signal and can function as a video signal. And wirings 505_1 to 505_N can function as signal lines. Circuits 502_1 to 502_N have a function of selecting which wiring to output the output signal of circuit 501 to, and can function as a selector circuit. For example, circuit 502_1 has a function of selecting which of wirings S1 to Sk to output the signal that circuit 501 outputs to wiring 505_1.

[0261] Transistors 503_1 to 503_k each have a function of controlling the conduction state between wiring 505_1 and wirings S1 to Sk according to the output signal of circuit 500, and function as switches.

[0262]

[0263] Next, the operation of the signal line driving circuit in Fig. 25(A) will be described with reference to the timing chart in Fig. 25(B). Fig. 25(B) shows an example of signal 514_1 input to wiring 504_1, signal 514_2 input to wiring 504_2, signal 514_k input to wiring 504_k, signal 515_1 input to wiring 505_1, and signal 515_2 input to wiring 505_2.

[0264] Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The one gate selection period means that the pixels belonging to a certain row are selected and a video signal is written to the pixels. ​​​​​​​​​​​It refers to the period during which it is possible.

[0265] Note that one gate selection period is divided into period T0, period T1, up to period Tk. Period T0 is a period for simultaneously applying a precharge voltage to the pixels belonging to the selected row, and thus it can function as a precharge period. Periods T1 to Tk are each a period for writing a video signal to the pixels belonging to the selected row, and thus they can function as write periods.

[0266] For the sake of convenience, the operation of the signal line driving circuit will be described by taking the operation of circuit 502_1 as an example.

[0267] First, in period T0, circuit 500 outputs H-level signals to wirings 504_1 to 504_k. Then, transistors 503_1 to 503_k turn on, so that wiring 505_1 and wirings S1 to Sk are in a conductive state. At this time, since circuit 501 supplies a precharge voltage Vp to wiring 505_1, the precharge voltage Vp is output to wirings S1 to Sk via transistors 503_1 to 503_k, respectively. And since the precharge voltage Vp is written to the pixels belonging to the selected row, the pixels belonging to the selected row are precharged.

[0268] Next, in period T1, circuit 500 outputs an H-level signal to wiring 504_1. Then, transistor 503_1 turns on, so that wiring 505_1 and wiring S1 are in a conductive state. And wiring 505_1 and wirings S2 to Sk are in a non-conductive state. At this time, assuming that circuit 501 outputs signal Data(S1) to wiring 505_1, signal D Data(S1) is output to wiring S1 via transistor 503_1. Thus, , signal Data(S1) is written to the pixels belonging to the selected row among the pixels connected to wiring S1.

[0269] Next, in period T2, circuit 500 outputs a signal of H level to wiring 504_2. Then, since transistor 503_2 turns on, wiring 505_2 and wiring S2 become conductive. And wiring 505_1 and wiring S1 become non-conductive, and wiring 505_1 and wiring S3~Sk remain non-conductive. At this time, assuming that circuit 501 outputs signal Data( S2) to wiring 505_1, signal Data(S2) is output to wiring S2 via transistor 503_2. Thus, signal Data(S2) is written to the pixels belonging to the selected row among the pixels connected to wiring S2.

[0270] Thereafter, until period Tk, circuit 500 outputs signals of H level to wirings 504_1~504_k in order. Therefore, similar to period T1 and period T2, from period T3 to period Tk, circuit 5 00 outputs signals of H level to wirings 504_3~504_k in order. Thus, transistors 503_3~503_k turn on in order, so transistors 503_1~503_ k turn on in order. Therefore, the signals output from circuit 501 are output to wirings S1~Sk in order. Thus, it becomes possible to write signals to the pixels belonging to the selected row in order.

[0271] As described above, an example of the signal line driving circuit has been explained. Since the signal line driving circuit of the present embodiment has a circuit that functions as a selector, the number of signals or the number of wirings can be reduced. ​ Alternatively, before writing a video signal to a pixel (period T0), a voltage for pre-charging is written to the pixel. Therefore, the writing time of the video signal can be shortened. Thus , it is possible to increase the size of the display device and the high definition of the display device. However, it is not limited to this , and it is possible to omit the period T0 and not pre-charge the pixel.

[0272] Note that if k is too large, the writing time to the pixel becomes short, so the writing of the video signal to the pixel may not be completed within the time. Therefore, it is preferable that k ≤ 6. More preferably, it is preferable that k ≤ 3. Even more preferably, it is preferable that k = 2.

[0273] In particular, when the color elements of the pixel are divided into n (n is a natural number) pieces, it is possible to set k = n. For example, when the color elements of the pixel are divided into three: red (R), green (G), and blue (B), , it is possible to set k = 3. In this case, one gate selection period is divided into period T0, period T1 , period T2, and period T3. And in period T1, period T2, and period T3, respectively , it is possible to write a video signal to a red (R) pixel, a green (G) pixel, and a blue (B) pixel. However, it is not limited to this, and the order of period T1, period T2, and period T3 can be arbitrarily set.

[0274] In particular, when the pixel is divided into n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or auxiliary pixels), it is possible to set k = n. For example, when the pixel is divided into two sub-pixels, it is possible to set k = 2. In this case, one gate selection period is period T . ​​0. It is divided into period T1 and period T2. During period T1, a video signal is written to one of the two sub-pixels, and during period T2, a video signal is written to the other of the two sub-pixels. This is possible.

[0275] Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuits 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 2 4(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced.

[0276] As circuit 500, the semiconductor device or shift register of Embodiments 1 to 4 can be used. In this case, the polarities of all the transistors included in circuit 500 can be N-channel type or P-channel type. Therefore, the number of manufacturing steps can be reduced, the yield can be improved, or the cost can be reduced.

[0277] Note that not only circuit 500 but also the polarities of all the transistors included in circuits 502_1 to 502_N can be N-channel type or P-channel type. Therefore, when circuits 5 00 and circuits 502_1 to 502_N are formed on the same substrate as the pixel portion, the number of manufacturing steps can be reduced, the yield can be improved, or the cost can be reduced. In particular, by making the polarities of all the transistors N-channel type, as the semiconductor layer of the transistor, non-single crystal It is possible to use a single-crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. This is because the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low.

[0278] (Embodiment 7) In this embodiment, the configuration and operation of pixels applicable to a liquid crystal display device will be described.

[0279] FIG. 26(A) shows an example of a pixel. Pixel 5420 includes a transistor 5421, a liquid crystal element 5422, and a capacitor element 5423. The first terminal of transistor 5421 is connected to wiring 5431, the second terminal of transistor 5421 is connected to one electrode of liquid crystal element 5422 and one electrode of capacitor element 5423, and the gate of transistor 5421 is connected to wiring 5432. The other electrode of liquid crystal element 5422 is connected to electrode 5434 and the other electrode of capacitor element 5423 is connected to wiring 5433.

[0280] For example, a video signal can be input to wiring 5431. For example, a scan signal, a selection signal, or a gate signal can be input to wiring 543 2. For example, a constant voltage can be supplied to wiring 5433. For example, a constant voltage can be supplied to electrode 5 434. However, this is not limited thereto. By supplying a precharge voltage to wiring 5431, it is possible to shorten the writing time of the video signal. Or, by inputting a signal to wiring 5433, it is possible to control the voltage applied to liquid crystal element 5422. Or ​​​​​When a signal is input to the electrode 5434, it is possible to realize frame inversion driving. It is possible.

[0281] Note that the wiring 5431 can function as a signal line, a video signal line, or a source line. The wiring 5432 can function as a signal line, a scanning line, or a gate line. The wiring 5433 can function as a power line or a capacitance line. The electrode 543 4 can function as a common electrode or a counter electrode. However, it is not limited to this. When a voltage is supplied to the wiring 5431 and the wiring 5432, these wirings can function as power lines. Or, when a signal is input to the wiring 5433, the wiring 5433 can function as a signal line.

[0282] The transistor 5421 has a function of controlling the timing of writing a video signal to a pixel by controlling the conduction state between the wiring 5431 and one electrode of the liquid crystal element 5422, and can function as a switch. The capacitor element 5423 has a function of holding the potential difference between one electrode of the liquid crystal element 5422 and the wiring 5433 and keeping the voltage applied to the liquid crystal element 5422 constant, and functions as a holding capacitor. However, it is not limited to this.

[0283] FIG. 26(B) shows an example of a timing chart for explaining the operation of the pixel of FIG. 26(A). FIG. 26(B) shows signals 5442_j (j is a natural number), signal 5442_j+1 , signal 5441_i (i is a natural number), signal 5441_i+1, and voltage 5442. And FIG. 26(B) shows the k-th (k is a natural number) frame and the k+1-th frame. Note that signal 5442_j, signal 5442_j + 1, signal 5441_i, signal 5441_i + 1, and voltage 5442 are, respectively, an example of a signal input to wiring 5432 in the j-th row, a signal input to wiring 5432 in the (j + 1)-th row , a signal input to wiring 5431 in the i-th column, and a signal input to wiring 5431 in the (i + 1)-th column , and a voltage supplied to wiring 5432.

[0284] The operation of pixel 5420 belonging to the j-th row and i-th column will be described. When signal 5442_j becomes H level , transistor 5421 turns on. Therefore, since one electrode of wiring 5431 in the i-th column and liquid crystal element 5422 are in a conductive state, signal 5441_j is input to one electrode of liquid crystal element 5422 through transistor 542 1. And capacitor element 5423 maintains the potential difference between the potential of one electrode of liquid crystal element 5422 at this time and the potential of wiring 5433 . Therefore, thereafter, until signal 5442_j becomes H level again, the voltage applied to liquid crystal element 542 2 becomes constant. And liquid crystal element 5422 expresses gradation according to the applied voltage .

[0285] Note that FIG. 26(B) shows an example in which a positive-polarity signal and a negative-polarity signal are alternately input to wiring 5431 every one-row selection period. The positive-polarity signal is a signal whose potential is higher than a reference value (for example the potential of electrode 5434), and the negative-polarity signal is a signal whose potential is lower than the reference value (for example, the potential of electrode 5434). However, it is not limited to this, and the signal input to wiring 5431 can have the same polarity during one frame period .

[0286] Note that FIG. 26(B) shows that the polarity of signal 5441_i and the polarity of signal 5441_i + 1 are also An example where they are different from each other is shown. However, it is not limited to this, and the polarity of signal 5441_i and the polarity of signal 5441_i + 1 can be the same.

[0287] In addition, FIG. 26(B) shows an example where the period during which signal 5442_j becomes the H level and the period during which signal 5442_j + 1 becomes the H level do not overlap. However, it is not limited to this, and as shown in FIG. 26(C), the period during which signal 5442_j becomes the H level and the period during which signal 54 42_j + 1 becomes the H level can overlap. In this case, it is preferable that signals of the same polarity are supplied to wiring 543 1 during one frame period. By doing so, using signal 5441_j written to the pixel in the j-th row, the pixel in the (j + 1)-th row can be precharged. In this way, the writing time of the video signal to the pixel can be shortened. Therefore, the display device can be made high-definition. Or, the display part of the display device can be made larger. Or, since signals of the same polarity are input to wiring 5431 during one frame period, power consumption can be reduced.

[0288] By combining the pixel configuration in FIG. 27(A) and the timing chart in FIG. 26(C), dot inversion driving can be realized. In the pixel configuration in FIG. 27(A), pixel 5420(i, j) is connected to wiring 5431_i. On the other hand, pixel 5420(i, j + 1) is connected to wiring 5431_i + 1. That is, the pixels belonging to the i-th column are alternately connected to wiring 5431_i and wiring 5431_i + 1 one row at a time. In this way, for the pixels belonging to the i-th column, signals of positive polarity and negative polarity are alternately written one row at a time, so ​​​​, dot inversion driving can be realized. However, it is not limited to this, and the pixels belonging to the i-th column can be alternately connected to the wiring 5431_i and the wiring 5431 _i + 1 in groups of a plurality of rows (for example, two or three rows).

[0289] Note that as a pixel configuration, a sub-pixel structure can be used. FIGS. 27(B), and (C) show the configuration when the pixel is divided into two sub-pixels. And in FIG. 27( B), a sub-pixel structure called 1S + 2G is shown, and in FIG. 27(C), a 2S + 1 G sub-pixel structure is shown. The sub-pixel 5420A and the sub-pixel 5420B correspond to the pixel 5420. The transistors 5421A and 5421B correspond to the transistor 5421. The liquid crystal elements 5422A and 5422B correspond to the liquid crystal element 5422. The capacitor elements 5423A and 5423B correspond to the capacitor element 5423. The wirings 5431A and 5431B correspond to the wiring 5431. The wirings 54

[0290] The pixel configuration and the pixel driving method of the present embodiment have been described above. By combining the pixel of the present embodiment with the semiconductor device, shift register, display device, or signal line driving circuit of Embodiments 1 to 6, various advantages can be obtained. For example when a sub-pixel structure is used as the pixel, the number of signals required to drive the display device increases. Therefore, the number of gate lines or source lines increases. As a result, the number of connections between the substrate on which the pixel portion is formed and the external circuit may increase significantly . However, even if the number of gate lines increases, as shown in Embodiment 5, the scanning line driving circuit can be formed on the same substrate as the pixel portion. Therefore, pixels having a sub-pixel structure can be used without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit. Alternatively, even if the number of source lines increases, the signal line driving circuit of Embodiment 6 can be formed on the same substrate as the pixel portion. Therefore, pixels having a sub-pixel structure can be used without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit. Or, when a signal is input to the capacitance line, the number of connections between the substrate on which the pixel portion is formed and the external circuit may significantly increase. Therefore, a signal can be supplied to the capacitance line using the semiconductor device or the shift register of Embodiments 1 to 4. And the semiconductor device or the shift register of Embodiments 1 to 4 can be formed on the same substrate as the pixel portion.

[0291] Therefore, a signal can be input to the capacitance line without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit. Or, when AC driving is used, the writing time of the video signal to the pixel becomes short. As a result, the writing time of the video signal to the pixel may become insufficient. Similarly, when pixels having a sub-pixel structure are used, the writing time of the video signal to the pixel becomes short. As a result, the writing time of the video signal to the pixel may become insufficient. Therefore, a video signal can be written to the pixel using the signal line driving circuit of Embodiment 6. In this case, before writing the video signal to the pixel, a voltage for pre-charging is applied to the pixel.

[0292] Or, when AC driving is used, the writing time of the video signal to the pixel becomes short. As a result, the writing time of the video signal to the pixel may become insufficient. Similarly, when pixels having a sub-pixel structure are used, the writing time of the video signal to the pixel becomes short. As a result, the writing time of the video signal to the pixel may become insufficient. Therefore, a video signal can be written to the pixel using the signal line driving circuit of Embodiment 6. In this case, before writing the video signal to the pixel, a voltage for pre-charging is applied to the pixel. Therefore, a video signal can be written to the pixel using the signal line driving circuit of Embodiment 6. In this case, before writing the video signal to the pixel, a voltage for pre-charging is applied to the pixel. ​​Since the video signal is written to the pixel in a short time, the video signal can be written to the pixel in a short time. As shown in (B), the period in which one row is selected can overlap the period in which another row is selected. By this, it is possible to use a video signal of another row as a voltage for precharging. .

[0293] (Embodiment 8) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. This will be explained with reference to C).

[0294] FIG. 29A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. , or a signal line driver circuit.

[0295] FIG. 29(B) shows an example of a cross section taken along line AB of FIG. 29(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. A conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; A conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; A liquid crystal layer 5407 is formed on the insulating layer 5408. 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0296] The conductive layer 5401 can function as a gate electrode. The insulating layer 5402 can function as a gate insulating film. The conductive layer 5404 can function as a wiring, an electrode of a transistor, or an electrode of a capacitive element. The insulating layer 5405 can function as an interlayer film or a planarization film. The conductive layer 5406 can function as a wiring, a pixel electrode, or a reflective electrode. The insulating layer 5408 can function as a sealing material. The conductive layer 5409 can function as a counter electrode or a common electrode. Here, a parasitic capacitance may occur between the driving circuit 5392 and the conductive layer 5409. As a result, a distortion or a delay may occur in the output signal of the driving circuit 5392 or the potential of each node. Or, the power consumption may increase. However, as shown in FIG. 29(B), by forming the insulating layer 5408 that can function as a sealing material on the driving circuit 5392, the parasitic capacitance generated between the driving circuit 5392 and the conductive layer 5409 can be reduced. This is because the dielectric constant of the sealing material is often lower than that of the liquid crystal layer. Therefore, the distortion or delay of the output signal of the driving circuit 5392 or the potential of each node can be reduced. Or, the power consumption of the driving circuit 5392 can be reduced.

[0297] Note that, as shown in FIG. 29(C), it is possible to form the insulating layer 5408 that can function as a sealing material on a part of the driving circuit 5392. Even in such a case,

[0298] ​​​​​​​​​​It is possible to reduce the parasitic capacitance generated between the drive circuit 5392 and the conductive layer 5409 and reduce the distortion or delay of the output signal of the drive circuit 5392 or the potential of each node However, the present invention is not limited to this, and it is possible that an insulating layer 5408 that can function as a sealing material is not formed on the drive circuit 5392

[0299] Note that the display element is not limited to a liquid crystal element, and various display elements such as an EL element or an electrophoretic element can be used

[0300] As described above, in this embodiment, an example of the cross-sectional structure of the display device has been described. Such a structure can be combined with the semiconductor device or the shift register of Embodiments 1 to 4 For example, when using a non-single crystal semiconductor, an amorphous semiconductor , a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer of the transistor, the channel width of the transistor often becomes large However, if the parasitic capacitance of the drive circuit can be reduced as in this embodiment, the channel width of the transistor can be reduced Therefore, the layout area can be reduced, and the display device can be made into a narrow bezel. Or the display device can be made high-definition

[0301] (Embodiment 9) In this embodiment, an example of the structure of the transistor will be described with reference to FIGS. 30(A), (B), and (C )

[0302] FIG. 30(A) is an example of the configuration of a top-gate type transistor. FIG. 30(B) is an example of the configuration of a bottom-gate type transistor. FIG. 30(C) uses a semiconductor substrate ​​​This is an example of the structure of a transistor manufactured in this way.

[0303] FIG. 30(A) shows a substrate 5260, an insulating layer 5261 formed on the substrate 5260, a semiconductor layer 5262 formed on the insulating layer 5261 and having regions 5262a, 5262b, 5262c, regions 5262d, and 5262e, an insulating layer 5263 formed to cover the semiconductor layer 5262, a conductive layer 5264 formed on the semiconductor layer 5262 and the insulating layer 5263, an insulating layer 5265 formed on the insulating layer 5263 and the conductive layer 5264 and having an opening, a conductive layer 5266 formed on the insulating layer 5265 and in the opening of the insulating layer 5265, a conductive layer 5268 formed on the insulating layer 5267 and in the opening of the insulating layer 5267, an insulating layer 5267 formed on the conductive layer 5266 and the insulating layer 5265 and having an opening, a conductive layer 5268 formed on the insulating layer 5267 and in the opening of the insulating layer 5267, an insulating layer 5269 formed on the insulating layer 5267 and the conductive layer 5268 and having an opening, a light-emitting layer 5270 formed on the insulating layer 5269 and in the opening of the insulating layer 5269, and a conductive layer 5271 formed on the insulating layer 5269 and the light-emitting layer 5270.

[0304] FIG. 30(B) shows a substrate 5300, a conductive layer 5301 formed on the substrate 5300, an insulating layer 5302 formed to cover the conductive layer 5301, a semiconductor layer 5303a formed on the conductive layer 5301 and the insulating layer 5302, a semiconductor layer 5303b formed on the semiconductor layer 5303a, a conductive layer 5304 formed on the semiconductor layer 5303b and the insulating layer 5302, an insulating layer 5305 formed on the insulating layer 5302 and the conductive layer 5304 and having an opening, a conductive layer 5305 formed on the insulating layer 5305 and in the opening of the insulating layer 5305, and a conductive layer 5 formed on the insulating layer 5305 and in the opening of the insulating layer 5305. 306, and a liquid crystal layer 5307 disposed on the insulating layer 5305 and the conductive layer 5306, and a conductive layer 5308 formed on the liquid crystal layer 5307 are shown.

[0305] FIG. 30(C) shows a semiconductor substrate 5352 having regions 5353 and 5355, and a semiconductor insulating layer 5356 formed on the semiconductor substrate 5352, and an insulating layer 5354 formed on the semiconductor substrate 5352 An insulating layer 5357 formed on the insulating layer 5356, and an insulating layer 535 4, an insulating layer 5356, and a conductive layer 5357, and an insulating layer 535 having an opening formed thereon 8, and a conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358 are shown. In this way, transistors are fabricated in regions 5350 and 5351, respectively.

[0306] The insulating layer 5261 can function as a base film. The insulating layer 5354 functions as an element isolation layer (e.g., a field oxide film). The insulating layers 5263, 5302, The insulating layer 5356 can function as a gate insulating film. The conductive layers 5264, 5301, The conductive layer 5357 can function as a gate electrode. The insulating layers 5265, 5267, 5305, and 5358 can function as an interlayer film or a planarization film. The conductive layers 5266, 5304, and 5 359 can function as wiring, an electrode of a transistor, or an electrode of a capacitor element, etc. The conductive layers 5268 and 5306 can function as a pixel electrode or a reflective electrode, etc. The insulating layer 5269 can function as a bank. The conductive layers 5271 and 5308 can function as a counter electrode or a common electrode, etc. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode or a common electrode, etc. The conductive layers 5271 and 5308 function as a counter electrode or a common electrode, etc. is possible.

[0307] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, a silicon substrate (or a single crystal substrate), an SOI substrate, a plastic substrate, a metal substrate, a stainless substrate, a ste substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil or a flexible substrate, etc. Examples of the glass substrate include barium borosilicate glass and aluminoborosilicate glass. Examples of the flexible substrate include polyethylene tere phthalate (PET), polyethylene naphthalate (PEN), plastics typified by polyethersulfone (PES), or synthetic resins having flexibility such as acrylic. In addition, there are laminated films (such as polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper containing fibrous materials, base films (such as polyester, polyamide, inorganic vapor deposition films, papers, etc.).

[0308] As the semiconductor substrate 5352, for example, a single crystal Si substrate having an n-type or p-type conductivity type can be used. However, it is not limited thereto, and the same as the substrate 5260 can be used. The region 5353 is, for example, a region in which impurities are added to the semiconductor substrate 5352 and functions as a well. For example, when the semiconductor substrate 5352 has a p-type conductivity type, the region 5353 has an n-type conductivity type and functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity type, the region 5353 has a p-type conductivity type and functions as a p-well. The region 5355 is, for example, a region in which impurities are added to the semiconductor substrate 5 It is an area added to 352 and functions as a source area or a drain area. Note that half It is possible to form an LDD region on the semiconductor substrate 5352.

[0309] Examples of the insulating layer 5261 include films having oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), or a stacked structure thereof. As an example of the case where the insulating layer 5261 is provided in a two-layer structure, it is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the second insulating film. As an example of the case where the insulating layer 5261 is provided in a three-layer structure, it is possible to provide a silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film as the third insulating film. It is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the second insulating film. As an example of the case where the insulating layer 5261 is provided in a three-layer structure, it is possible to provide a silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film as the third insulating film. As an example of the case where the insulating layer 5261 is provided in a two-layer structure, it is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the second insulating film. As an example of the case where the insulating layer 5261 is provided in a three-layer structure, it is possible to provide a silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film as the third insulating film. As an example of the case where the insulating layer 5261 is provided in a three-layer structure, it is possible to provide a silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film as the third insulating film. As an example of the case where the insulating layer 5261 is provided in a three-layer structure, it is possible to provide a silicon oxide film as the first insulating film, a silicon nitride film as the second insulating film, and a silicon oxide film as the third insulating film.

[0310] Examples of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b include non-crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single-crystalline semiconductors, compound semiconductors, or oxide semiconductors (ZnO, InGaZnO, SiGe, GaAs, IZO, ITO, SnO, TiO, AlZnSnO (AZTO)), organic semiconductors, or carbon nanotubes. Examples of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b include non-crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single-crystalline semiconductors, compound semiconductors, or oxide semiconductors (ZnO, InGaZnO, SiGe, GaAs, IZO, ITO, SnO, TiO, AlZnSnO (AZTO)), organic semiconductors, or carbon nanotubes. Examples of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b include non-crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single-crystalline semiconductors, compound semiconductors, or oxide semiconductors (ZnO, InGaZnO, SiGe, GaAs, IZO, ITO, SnO, TiO, AlZnSnO (AZTO)), organic semiconductors, or carbon nanotubes. Examples of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b include non-crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single-crystalline semiconductors, compound semiconductors, or oxide semiconductors (ZnO, InGaZnO, SiGe, GaAs, IZO, ITO, SnO, TiO, AlZnSnO (AZTO)), organic semiconductors, or carbon nanotubes. Examples of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b include non-crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single-crystalline semiconductors, compound semiconductors, or oxide semiconductors (ZnO, InGaZnO, SiGe, GaAs, IZO, ITO, SnO, TiO, AlZnSnO (AZTO)), organic semiconductors, or carbon nanotubes.

[0311] Note that, for example, the region 5262a is in an intrinsic state where no impurities are added to the semiconductor layer 5262 and functions as a channel region. However, it is possible to add minute impurities to the region 5262a, and the impurities added to the region 5262a are lower in concentration than the impurities added to the region 5262b, the region 5262c, the region 5262d, or the region 5262e. Note that, for example, the region 5262a is in an intrinsic state where no impurities are added to the semiconductor layer 5262 and functions as a channel region. However, it is possible to add minute impurities to the region 5262a, and the impurities added to the region 5262a are lower in concentration than the impurities added to the region 5262b, the region 5262c, the region 5262d, or the region 5262e. Note that, for example, the region 5262a is in an intrinsic state where no impurities are added to the semiconductor layer 5262 and functions as a channel region. However, it is possible to add minute impurities to the region 5262a, and the impurities added to the region 5262a are lower in concentration than the impurities added to the region 5262b, the region 5262c, the region 5262d, or the region 5262e. Note that, for example, the region 5262a is in an intrinsic state where no impurities are added to the semiconductor layer 5262 and functions as a channel region. However, it is possible to add minute impurities to the region 5262a, and the impurities added to the region 5262a are lower in concentration than the impurities added to the region 5262b, the region 5262c, the region 5262d, or the region 5262e. This is preferable. Regions 5262b and 5262d are regions where impurities are added at a low concentration and function as LDD (Lightly Doped Drain) regions. However, it is possible to omit regions 5262b and 5262d. Regions 5262c and 5262e are regions where impurities are added to semiconductor layer 5262 at a high concentration and function as source regions or drain regions.

[0312] Note that semiconductor layer 5303b is a semiconductor layer to which an impurity element such as phosphorus is added and has an n-type conductivity type.

[0313] Note that when an oxide semiconductor or a compound semiconductor is used as semiconductor layer 5303a, it is possible to omit semiconductor layer 5303b.

[0314] Examples of insulating layers 5263, 5302, and 5356 include films containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), and silicon nitride oxide (SiNxOy) (x > y), or laminated structures thereof.

[0315] Examples of conductive layers 5264, 5266, 5268, 5271, 5301, 5304, 5306, 5308, 5357, and 535 9 include single-layer conductive films or laminated structures thereof. Examples of such conductive films include aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni). ​​​​​​​​​​, platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), scandium (Sc), zinc (Zn), phosphorus (P), boron (B), arsenic (As) , gallium (Ga), indium (In), tin (Sn), oxygen (O), zirconium (Z r), cerium (Ce), a single-element film of one element selected from the group consisting of, or there is a compound containing one or more elements selected from the above group. As an example of the compound is an alloy containing one or more elements selected from the above group (indium tin oxide (I TO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITS O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminate neodymium (Al-Nd), aluminum tungsten (Al-Ta), aluminum zirconium (Al -Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo- W), molybdenum tantalum (Mo-Ta), etc. alloy materials), one or more selected from the above group compounds of elements and nitrogen (nitride films such as titanium nitride, tantalum nitride, molybdenum nitride, etc.), or compounds of one or more elements selected from the above group and silicon (tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, moly silicon, etc. silicide films), etc. There are also nanotube materials such as carbon nanotubes, organic nanotubes, inorganic nanotubes, or metal nanotubes .

[0316] Note that silicon (Si) can contain an n-type impurity (such as phosphorus) or a p-type impurity (such as boron). It is possible to include them.

[0317] Note that when copper is used as the conductive layer, it is preferable to form a laminated structure in order to improve the adhesion. It is preferable.

[0318] Note that as the conductive layer in contact with the oxide semiconductor or silicon, it is preferable to use molybdenum or titanium. It is preferable to use them.

[0319] Note that by using an alloy material of neodymium and aluminum as the conductive layer, aluminum is less likely to cause hillocks. It becomes less likely to cause hillocks.

[0320] Note that when using a semiconductor material such as silicon as the conductive layer, it is possible to form the semiconductor material such as silicon simultaneously with the semiconductor layer of the transistor. It is possible to form them simultaneously.

[0321] Note that ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanotubes, etc. have light-transmitting properties, so these materials can be used for parts that transmit light, such as pixel electrodes, counter electrodes, or common electrodes. Since they have light-transmitting properties, these materials can be used for parts that transmit light, such as pixel electrodes, counter electrodes, or common electrodes. It is possible to use them for parts that transmit light.

[0322] Note that by using a low-resistance material (such as aluminum) to form a laminated structure, the resistance of the wiring can be reduced. It is possible to reduce the resistance of the wiring.

[0323] Note that by forming a laminated structure in which a low heat-resistant material (such as aluminum) is sandwiched between high heat-resistant materials (such as molybdenum, titanium, neodymium, etc.), while taking advantage of the merits of the low heat-resistant material, the heat resistance of wiring, electrodes, etc. can be increased. By forming a laminated structure in which a low heat-resistant material (such as aluminum) is sandwiched between high heat-resistant materials (such as molybdenum, titanium, neodymium, etc.), while taking advantage of the merits of the low heat-resistant material, the heat resistance of wiring, electrodes, etc. can be increased. While taking advantage of the merits of the low heat-resistant material, the heat resistance of wiring, electrodes, etc. can be increased.

[0324] In addition, a material that reacts with other materials and changes its properties can be sandwiched or covered with a material that is less reactive to the other materials. For example, when connecting ITO and aluminum, it is possible to sandwich neodymium alloy, titanium, molybdenum, etc. between ITO and aluminum. For example, when connecting silicon and aluminum, it is possible to sandwich neodymium alloy, titanium, molybdenum between silicon and aluminum. Moreover, these materials can also be used for wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. Examples of the insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 5358 include a single-layer insulating film or a laminated structure thereof. Examples of the insulating film include a film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), a film containing carbon such as DLC (diamond-like carbon), or an organic material such as siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. Examples of the light-emitting layer 5270 include an organic EL element or an inorganic EL element. Examples of the organic EL element include a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, etc., or a single-layer structure of a layer in which a plurality of these materials are mixed, or a laminated structure thereof. For example, when connecting ITO and aluminum, it is possible to sandwich neodymium alloy, titanium, molybdenum, etc. between ITO and aluminum. For example, when connecting silicon and aluminum, it is possible to sandwich neodymium alloy, titanium, molybdenum between silicon and aluminum. Moreover, these materials can also be used for wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc.

[0325] Examples of the insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 5358 include a single-layer insulating film or a laminated structure thereof. Examples of the insulating film include a film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), a film containing carbon such as DLC (diamond-like carbon), or an organic material such as siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. Examples of the insulating film include a film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), a film containing carbon such as DLC (diamond-like carbon), or an organic material such as siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. Examples of the insulating film include a film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), a film containing carbon such as DLC (diamond-like carbon), or an organic material such as siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. Examples of the insulating film include a film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x > y), silicon nitride oxide (SiNxOy) (x > y), a film containing carbon such as DLC (diamond-like carbon), or an organic material such as siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic.

[0326] Examples of the light-emitting layer 5270 include an organic EL element or an inorganic EL element. Examples of the organic EL element include a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, etc., or a single-layer structure of a layer in which a plurality of these materials are mixed, or a laminated structure thereof. Examples of the organic EL element include a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, etc., or a single-layer structure of a layer in which a plurality of these materials are mixed, or a laminated structure thereof. Examples of the organic EL element include a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, etc., or a single-layer structure of a layer in which a plurality of these materials are mixed, or a laminated structure thereof. ​

[0327] Note that on the insulating layer 5305 and on the conductive layer 5306, an insulating layer that functions as an alignment film, an insulating layer that functions as a protrusion, etc. can be formed.

[0328] Note that on the conductive layer 5308, a color filter, a black matrix, or an insulating layer that functions as a protrusion etc. can be formed. Under the conductive layer 5308, an insulating layer that functions as an alignment film can be formed.

[0329] Note that in the cross-sectional structure of FIG. 30(A), the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 are omitted, and the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 30(B) can be formed on the insulating layer 526 7 and on the conductive layer 5268.

[0330] Note that in the cross-sectional structure of FIG. 30(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted, and the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 shown in FIG. 30(A) can be formed on the insulating layer 530 5 and on the conductive layer 5306.

[0331] Note that in the cross-sectional structure of FIG. 30(C), on the insulating layer 5358 and the conductive layer 5359, the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 shown in FIG. 30(A) can be formed. Alternatively, the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 30(B) can be formed on the insulating layer 5267 and on the conductive layer 5268. 5267 and on the conductive layer 5268.

[0332] As described above, in this embodiment, an example of the structure of the transistor has been described. The transistor of this embodiment can be applied to Embodiments 1 to 8. In particular, FIG. 3 In 0(B), when using an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor as the semiconductor layer, the transistor may deteriorate. However, in the semiconductor device, shift register, or display device according to Embodiments 1 to 8, it is advantageous because deterioration of the transistor can be suppressed.

[0333] (Embodiment 10) In this embodiment, a layout diagram (hereinafter also referred to as a top view) of the shift register will be described. In this embodiment, as an example, the layout diagram of the shift register described in Embodiment 4 will be described. Note that the content described in this embodiment can be applied not only to the shift register described in Embodiment 4 but also to the semiconductor device, shift register, or display device according to Embodiments 1 to 9. It should be noted that the layout diagram of this embodiment is

[0334] only an example and is not limited thereto.

[0334] The layout diagram of this embodiment will be described with reference to FIGS. 31 and 32. FIG. 31 shows an example of a partial layout diagram of the shift register, and FIG. 32 shows a layout diagram of the flip-flop 401_i as an example.

[0335] The transistors, wirings, etc. shown in FIGS. 31 and 32 are composed of a conductive layer 601, a semiconductor layer 60 2, a conductive layer 603, a conductive layer 604, and a contact hole 605. However, it is not limited thereto, and it is possible to newly form another conductive layer, insulating film, or another contact hole. For example, it is possible to newly add a contact hole for connecting the conductive layer 601 and the conductive layer 603.

[0336] The conductive layer 601 can include a portion that functions as a gate electrode or a wiring. Half The semiconductor layer 602 can include a portion that functions as a semiconductor layer of a transistor. The conductive layer 603 can include a portion that functions as a wiring, a source, or a drain. The conductive layer 604 can include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 605 has a function of connecting the conductive layer 601 and the conductive layer 604, or a function of connecting the conductive layer 603 and the conductive layer 604.

[0337] In an example of FIG. 31, the wiring 412 has an opening 611, and the wiring 413 has an opening 612. In this way, by having the openings in the wiring 412 and the wiring 413, the parasitic capacitance can be reduced. Or, the breakdown of the transistor caused by electrostatic breakdown can be suppressed. However, it is not limited to this, and like the wiring 416, the opening 611 or the opening 612 can be omitted. Or, an opening can be provided in the wiring 416 in the same way as the wiring 412 or the wiring 413.

[0338] In an example of FIG. 31, by providing an opening in a part of the intersection of the wiring 412 or the wiring 413 and another wiring, the crosstalk capacitance of the wiring can be reduced. Therefore, noise reduction, or reduction of signal delay or distortion can be achieved.

[0339] In an example of FIG. 31, on a part of the conductive layer 603 included in the wiring 416, the conductive layer 604 is formed. And the conductive layer 604 is connected to the conductive layer 6 through the contact hole 605. It is connected to 03. Thus, the wiring resistance can be reduced, and a decrease in voltage drop , or a reduction in signal delay or distortion can be achieved. However, it is not limited to this, and it is possible to omit the conductive layer 604 and the contact hole 605. Or , similar to the wiring 416, in the wiring 412 or the wiring 413, a part of the conductive layer 603 has the conductive layer 604 formed thereon, and the conductive layer 604 can be connected to the conductive layer 603.

[0340] Here, in an example of FIG. 31, the wiring width of the wiring 412, the wiring width of the wiring 413, and the wiring 4 16's wiring width are respectively shown as wiring width 621, wiring width 622, and width 623. And the opening 611's width, the length of the opening 611, the width of the opening 612, and the length of the opening 612 are respectively , shown as width 624, length 625, width 626, and length 627.

[0341] The signals input to the wiring 412 and the wiring 413 are often signals that are inverted with respect to each other. Therefore, it is preferable to set the wiring resistance or parasitic capacitance of the wiring 412 to be approximately equal to the wiring resistance or parasitic capacitance of the wiring 413. Thus, the wiring 412 preferably includes a portion that is approximately equal to the wiring width 622. Or, the opening 611 preferably includes a portion that is approximately equal to the width 626 or the length 627 of the opening 612. However, it is not limited to this, and the wiring width 621, the wiring width 622, the width 624 of the opening 611 624, the width 624 of the opening 611, the length 625 of the opening 611, or the length 627 of the opening 612 can be set to various values. For example, assume that the cross - capacitance between the wiring 412 and other wirings is larger than the cross - capacitance between the wiring 413 and other wirings. In this case, the wiring 41 624, the width 624 of the opening 611, the length 625 of the opening 611, or the length 627 of the opening 612 can be set to various values. For example, assume that the cross - capacitance between the wiring 412 and other wirings is larger than the cross - capacitance between the wiring 413 and other wirings. In this case, the wiring 41 2's wiring width may be adjusted accordingly.​​​ By reducing the wiring resistance of 2, the signals input to wiring 412 and wiring 413 can be set so that the delay or distortion thereof is substantially equal. For this purpose, wiring 412 can include a portion larger than wiring width 622. Or, the opening 611 can include a portion smaller than the width 626 of opening 612. Or, opening 611 can include a portion shorter than the length 627 of opening 612. On the other hand, when the capacitance between wiring 412 and other wirings is smaller than the capacitance between wiring 413 and other wirings, wiring 412 can include a portion smaller than wiring width 622. Also, opening 611 can include a portion larger than the width 626 of opening 612. Or, opening 611 can include a portion longer than the length 627 of opening 612. It is possible.

[0342] When wiring 416 does not have an opening, wiring 416 preferably includes a portion smaller than wiring width 621 or wiring width 62 2. This is because wiring 416 does not have an opening, so the wiring resistance of wiring 416 is small. However, it is not limited to this, and wiring 4 16 can include a portion larger than wiring width 621 or wiring width 622.

[0343] In an example of FIG. 32, in transistor 101, transistor 102, transistor 103, transistor 201, transistor 202, transistor 203, transistor 204, transistor 301, transistor 302, transistor 303, transistor 304, and / or transistor 305, the conductive layer 601 and the conductive layer 603 of the second terminal are ​The overlapping area is smaller than the area where the conductive layer 601 of the first terminal overlaps with the conductive layer 603. This is preferable. By doing so, noise reduction of the gate of the transistor 101 or the wiring 401_i can be achieved. Or, concentration of the electric field on the second terminal can be suppressed, so that deterioration or breakdown of the transistor can be suppressed.

[0344] As described above, an example of the layout diagram of the shift register has been described. However, as already mentioned, the layout diagram of the present embodiment is merely an example and is not limited thereto.

[0345] Note that a semiconductor layer 602 can be formed in a portion where the conductive layer 601 overlaps with the conductive layer 603. By doing so, the parasitic capacitance between the conductive layer 601 and the conductive layer 603 can be reduced, so that noise reduction can be achieved. For the same reason, a semiconductor layer 602 or a conductive layer 603 can be formed in a portion where the conductive layer 601 overlaps with the conductive layer 604.

[0346] Note that the conductive layer 604 can be formed on a part of the conductive layer 601, and the conductive layer 601 can be connected to the conductive layer 604 via a contact hole 605. By doing so, the wiring resistance can be reduced. Or, the conductive layer 603 and the conductive layer 604 can be formed on a part of the conductive layer 601, and the conductive layer 601 can be connected to the conductive layer 604 via a contact hole 605, and the conductive layer 603 can be connected to the conductive layer 604 via another contact hole 605. By doing so, the wiring resistance can be further reduced.

[0347] ​​​​​Note that a conductive layer 604 is formed on a part of the conductive layer 603, and the conductive layer 603 can be connected to the conductive layer 604 through a contact hole 605. By doing so, the wiring resistance can be reduced. Note that a conductive layer 601 or a conductive layer 603 is formed under a part of the conductive layer 604, and the conductive layer 604 can be connected to the conductive layer 601 or the conductive layer 603 through a contact hole 605. By doing so, the wiring resistance can be reduced.

[0348] Note that a conductive layer 601 or a conductive layer 603 is formed under a part of the conductive layer 604, and the conductive layer 604 can be connected to the conductive layer 601 or the conductive layer 603 through a contact hole 605. By doing so, the wiring resistance can be reduced. Note that a conductive layer 601 or a conductive layer 603 is formed under a part of the conductive layer 604, and the conductive layer 604 can be connected to the conductive layer 601 or the conductive layer 603 through a contact hole 605. By doing so, the wiring resistance can be reduced.

[0349] Note that, as described in Embodiment 1, the parasitic capacitance between the gate and the first terminal of the transistor 101 can be made larger than the parasitic capacitance between the gate and the second terminal of the transistor 101. As shown in FIG. 32, the width of the conductive layer 603 that can function as the first electrode of the transistor 101 is shown as width 631, and the width of the conductive layer 603 that can function as the second electrode of the transistor 101 is shown as width 632. And width 631 can be larger than width 632. By doing so, as described in Embodiment 1, the parasitic capacitance between the gate and the second terminal of the transistor 101 can be made larger than the parasitic capacitance between the gate and the first terminal of the transistor 101. However, it is not limited to this.

[0350] (Embodiment 11) In this embodiment, an example of an electronic device will be described.

[0351] FIGS. 33(A) to 33(H) and FIGS. 34(A) to 34(D) are diagrams showing an electronic device. ​​​​​​​​​​​Yes. These electronic devices can have a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including operation switches or power switches), connection terminals 5006, a sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 5008, etc.

[0352] Figure 33(A) is a mobile computer, and in addition to the above, it can have a switch 5009, an infrared port 5010, etc. Figure 33(B) is a portable image playback device equipped with a recording medium (for example, a DVD playback device), and in addition to the above, it can have a second display unit 5002, a recording medium reading unit 5011, etc. Figure 33(C) is a goggle type display, and in addition to the above, it can have a second display unit 5002...

Claims

1. having the first to sixth transistors, each of the first to sixth transistors is a bottom-gate type transistor, one of the source electrode or the drain electrode of the first transistor is always in conduction with the gate line, the other of the source electrode or the drain electrode of the first transistor is always in conduction with the clock signal line, one of the source electrode or the drain electrode of the second transistor is always in conduction with the gate line, one of the source electrode or the drain electrode of the third transistor is always in conduction with the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the third transistor is always in conduction with the power supply line, the gate electrode of the third transistor is always in conduction with the gate electrode of the second transistor, one of the source electrode or the drain electrode of the fourth transistor is always in conduction with the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the fourth transistor is always in conduction with the first signal line, the gate electrode of the fourth transistor is always in conduction with the first signal line, one of the source electrode or the drain electrode of the fifth transistor is always in conduction with the gate electrode of the first transistor, the other of the source electrode or the drain electrode of the fifth transistor is always in conduction with the power supply line, the gate electrode of the fifth transistor is always in conduction with the second signal line, one of the source electrode or the drain electrode of the sixth transistor is always in conduction with the third signal line, the other of the source electrode or the drain electrode of the sixth transistor is always in conduction with the gate electrode of the second transistor, when the potential of the third signal line is at the H level, the H-level potential is supplied from the third signal line to the gate electrode of the sixth transistor and one of the source electrode or the drain electrode of the sixth transistor, when the other of the source electrode or the drain electrode of the second transistor is in conduction with the gate line through at least the channel formation region of the second transistor, the potential of the other of the source electrode or the drain electrode of the second transistor is input to the gate line through at least the channel formation region of the second transistor, The first conductive layer having a function as one of the source electrode or the drain electrode of the first transistor has a function as one of the source electrode or the drain electrode of the second transistor, In a plan view, the area where the first conductive layer overlapping with the second conductive layer having a function as the gate electrode of the first transistor is larger than the area where the third conductive layer having a function as the other of the source electrode or the drain electrode of the first transistor overlaps with the second conductive layer, The fourth conductive layer having a function as one of the source electrode or the drain electrode of the third transistor has a function as one of the source electrode or the drain electrode of the fifth transistor, The fifth conductive layer having a function as the gate electrode of the second transistor has a function as the gate electrode of the third transistor, The W (channel width) / L (channel length) of the first transistor is larger than the W / L of the second transistor, The W / L of the first transistor is larger than the W / L of the third transistor, The W / L of the first transistor is larger than the W / L of the fourth transistor, The W / L of the first transistor is larger than the W / L of the fifth transistor, The W / L of the first transistor is larger than the W / L of the sixth transistor, In a plan view, the channel length direction of the first transistor is the first direction, In a plan view, the channel length direction of the fourth transistor is the first direction, In a plan view, the sixth conductive layer having a function as the gate line has a region extending in a second direction intersecting the first direction, At least one of the first to sixth transistors is a semiconductor device having a semiconductor layer including an oxide semiconductor.

2. A gate driver and pixels formed on the same substrate as the gate driver, The gate driver includes first to sixth transistors, Each of the first to sixth transistors is a bottom gate type transistor, One of the source electrode or the drain electrode of the first transistor is always in conduction with the gate line, The other of the source electrode or the drain electrode of the first transistor is always in conduction with the clock signal line, One of the source electrode or the drain electrode of the second transistor is always in conduction with the gate line, One of the source electrode or the drain electrode of the third transistor is always in conduction with the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the third transistor is always in conduction with the power supply line. The gate electrode of the third transistor is always in conduction with the gate electrode of the second transistor. One of the source electrode or the drain electrode of the fourth transistor is always in conduction with the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the fourth transistor is always in conduction with the first signal line. The gate electrode of the fourth transistor is always in conduction with the first signal line. One of the source electrode or the drain electrode of the fifth transistor is always in conduction with the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the fifth transistor is always in conduction with the power supply line. The gate electrode of the fifth transistor is always in conduction with the second signal line. One of the source electrode or the drain electrode of the sixth transistor is always in conduction with the third signal line. The other of the source electrode or the drain electrode of the sixth transistor is always in conduction with the gate electrode of the second transistor. When the potential of the third signal line is at the H level, the H-level potential is supplied from the third signal line to the gate electrode of the sixth transistor and one of the source electrode or the drain electrode of the sixth transistor. When the other of the source electrode or the drain electrode of the second transistor is in conduction with the gate line through at least the channel formation region of the second transistor, the potential of the other of the source electrode or the drain electrode of the second transistor is input to the gate line through at least the channel formation region of the second transistor. The first conductive layer having a function as one of the source electrode or the drain electrode of the first transistor has a function as one of the source electrode or the drain electrode of the second transistor. In a plan view, the area where the first conductive layer overlapping the second conductive layer having a function as the gate electrode of the first transistor is larger than the area where the third conductive layer having a function as the other of the source electrode or the drain electrode of the first transistor overlaps the second conductive layer. The fourth conductive layer having a function as one of the source electrode or the drain electrode of the third transistor has a function as one of the source electrode or the drain electrode of the fifth transistor, The fifth conductive layer having a function as the gate electrode of the second transistor has a function as the gate electrode of the third transistor, The W (channel width) / L (channel length) of the first transistor is larger than the W / L of the second transistor, The W / L of the first transistor is larger than the W / L of the third transistor, The W / L of the first transistor is larger than the W / L of the fourth transistor, The W / L of the first transistor is larger than the W / L of the fifth transistor, The W / L of the first transistor is larger than the W / L of the sixth transistor, In a plan view, the channel length direction of the first transistor is the first direction, In a plan view, the channel length direction of the fourth transistor is the first direction, In a plan view, the sixth conductive layer having a function as the gate line has a region extending in a second direction intersecting the first direction, The pixel has a seventh transistor, One of the source electrode or the drain electrode of the seventh transistor is always in conduction with the liquid crystal element, The other of the source electrode or the drain electrode of the seventh transistor is always in conduction with the fourth signal line, The gate electrode of the seventh transistor is always in conduction with the gate line, The driving mode of the liquid crystal element is the FFS mode, At least one of the first to seventh transistors has a semiconductor layer having an oxide semiconductor, a display device.

3. Having the first to sixth transistors, Each of the first to sixth transistors is a bottom gate type transistor, One of the source electrode or the drain electrode of the first transistor is always in conduction with the gate line, The other of the source electrode or the drain electrode of the first transistor is always in conduction with the clock signal line, One of the source electrode or the drain electrode of the second transistor is always in conduction with the gate line, One of the source electrode or the drain electrode of the third transistor is always in conduction with the gate electrode of the first transistor, The other of the source electrode or the drain electrode of the third transistor is always in conduction with the power supply line, The gate electrode of the third transistor is always in conduction with the gate electrode of the second transistor. One of the source electrode or the drain electrode of the fourth transistor is always in conduction with the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the fourth transistor is always in conduction with the first signal line. The gate electrode of the fourth transistor is always in conduction with the first signal line. One of the source electrode or the drain electrode of the fifth transistor is always in conduction with the gate electrode of the first transistor. The other of the source electrode or the drain electrode of the fifth transistor is always in conduction with the power supply line. The gate electrode of the fifth transistor is always in conduction with the second signal line. One of the source electrode or the drain electrode of the sixth transistor is always in conduction with the third signal line. The other of the source electrode or the drain electrode of the sixth transistor is always in conduction with the gate electrode of the second transistor. When the potential of the third signal line is at the H level, the H-level potential is supplied from the third signal line to the gate electrode of the sixth transistor and one of the source electrode or the drain electrode of the sixth transistor. When the other of the source electrode or the drain electrode of the second transistor is in conduction with the gate line through at least the channel formation region of the second transistor, the potential of the other of the source electrode or the drain electrode of the second transistor is input to the gate line through at least the channel formation region of the second transistor. The first conductive layer having a function as one of the source electrode or the drain electrode of the first transistor has a function as one of the source electrode or the drain electrode of the second transistor. In a plan view, the area where the first conductive layer overlapping with the second conductive layer having a function as the gate electrode of the first transistor is larger than the area where the third conductive layer having a function as the other of the source electrode or the drain electrode of the first transistor overlaps with the second conductive layer. The fourth conductive layer having a function as one of the source electrode or the drain electrode of the third transistor has a function as one of the source electrode or the drain electrode of the fifth transistor. The fifth conductive layer having a function as the gate electrode of the second transistor has a function as the gate electrode of the third transistor. The W (channel width) / L (channel length) of the first transistor is larger than the W / L of the second transistor, The W / L of the first transistor is larger than the W / L of the third transistor, The W / L of the first transistor is larger than the W / L of the fourth transistor, The W / L of the first transistor is larger than the W / L of the fifth transistor, The W / L of the first transistor is larger than the W / L of the sixth transistor, In plan view, the channel length direction of the first transistor is a first direction, In plan view, the channel length direction of the fourth transistor is the first direction, A semiconductor device in which a sixth conductive layer having a function as a gate line has a region extending in a second direction intersecting the first direction in plan view.

Images