Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing a decrease in signal quality.SOLUTION: A semiconductor device according to an embodiment comprises a substrate, a chip laminate laminated with a plurality of first semiconductor chips, a first wire group, a second wire, and a third wire. The substrate comprises a first surface, and first and second pads provided on the first surface. Each first semiconductor chip comprises a second surface facing the first surface, a third surface opposite to the second surface, and third and fourth pads provided on the third surface. The first wire group includes a plurality of first wires electrically connecting the first pad and the third pad of each of the first semiconductor chips. The second wire electrically connects the second pad and a fourth pad of a first semiconductor chip closest to the substrate among the plurality of first semiconductor chips. The third wire electrically connects the fourth pad of each of the plurality of first semiconductor chips.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This embodiment relates to a semiconductor device.

Background Art

[0002] A semiconductor device may have a semiconductor controller chip and a plurality of stacked semiconductor memory chips on a wiring board. A signal is transmitted by a wire that electrically connects between a signal electrode pad of the semiconductor controller chip and a signal electrode pad of the semiconductor memory chip. In a semiconductor device, for example, a signal transmitted between a semiconductor controller chip and a semiconductor memory chip is desired to have high waveform quality.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device capable of suppressing a decrease in signal quality.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment includes a substrate, a chip stack in which a plurality of first semiconductor chips are stacked, a first wire group, a second wire, and a third wire. The substrate has a first surface, a first pad and a second pad provided on the first surface. The first semiconductor chip has a second surface facing the first surface, a third surface on the opposite side of the second surface, and a third pad and a fourth pad provided on the third surface. The first wire group includes a plurality of first wires that electrically connect the first pad and each of the third pads of the first semiconductor chips. The second wire electrically connects the second pad and the fourth pad of the first semiconductor chip closest to the substrate among the plurality of first semiconductor chips. The third wire electrically connects each of the fourth pads of the plurality of first semiconductor chips.

Brief Description of Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention. In the following embodiments, the vertical direction of the wiring board indicates the relative direction when the surface on which the semiconductor chip is provided is taken as the upper side, and it may be different from the vertical direction according to the acceleration of gravity. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and the drawings, the same reference numerals are given to the same elements as those described above with respect to the previously presented drawings, and the detailed description is omitted as appropriate.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a wiring board 2, a semiconductor chip (semiconductor controller chip) 3, semiconductor chips (semiconductor memory chips) 4a to 4d, wires 18 to 24, an insulating encapsulant 25, and external connection terminals 7.

[0009] The wiring board 2 is, for example, a board such as a printed circuit board. The wiring board 2 can be connected to the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d via the wires 18 to 24. The wiring board 2 has a wiring layer (not shown).

[0010] The semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d are provided, for example, above the surface F1 of the wiring board 2 by an adhesive layer (not shown). The adhesive layer is, for example, a film-shaped resin (DAF, Die Attach Film).

[0011] The semiconductor memory chips 4a to 4d are, for example, NAND chips. The semiconductor memory chips 4a to 4d include, for example, semiconductor elements. The semiconductor elements are, for example, a memory cell array or a CMOS (Complementary Metal Oxide Semiconductor) circuit. The semiconductor memory chips 4a to 4d are adhered onto the wiring substrate 2 and other semiconductor memory chips 4a to 4d by an adhesive layer (not shown). The adhesive layer is, for example, a film-shaped resin. In the example shown in FIG. 1, the semiconductor memory chips 4a to 4d are stacked in four stages in the vertical direction via the adhesive layer. The vertical direction is substantially perpendicular to the upper surface F1 of the wiring substrate 2. Each of the plurality of stacked semiconductor memory chips 4a to 4d is, for example, a memory chip having the same configuration. Note that the number of stacked semiconductor memory chips 4a to 4d is not limited to four stages and may be arbitrarily changed. The number of stacked semiconductor memory chips 4a to 4d is set according to the required memory capacity. Also, as shown in FIG. 1, the semiconductor memory chips 4a to 4d are stacked with a shift in a stepped manner. Thereby, overlapping of other semiconductor memory chips 4a to 4d on the electrode pads 10 to 17 of the semiconductor memory chips 4a to 4d is suppressed, and the wires 19, 21 to 24 can be connected to the electrode pads 10 to 17 of the semiconductor memory chips 4a to 4d.

[0012] The semiconductor controller chip 3 includes, for example, a CMOS circuit. The semiconductor controller chip 3 is electrically connected to the semiconductor memory chips 4a to 4d to control the operation of the semiconductor memory chips 4a to 4d. The semiconductor controller chip 3 is provided adjacent to the semiconductor memory chips 4a to 4d and adhered to the wiring substrate 2 by an adhesive layer (not shown), for example, as shown in FIG. 1. The adhesive layer is, for example, a film-shaped resin. Also, the semiconductor controller chip 3 may be provided above the semiconductor memory chips 4a to 4d, for example.

[0013] The wires 18 and 20 electrically connect the wiring substrate 2 and the semiconductor controller chip 3. The material of the wires 18 and 20 is, for example, a conductive metal such as gold, silver, or copper.

[0014] Wires 19, 21 to 24 electrically connect the wiring board 2 and the semiconductor memory chips 4a to 4d. The material of the wires 19, 21 to 24 is, for example, a conductive metal such as gold, silver, or copper.

[0015] The insulating encapsulant 25 is, for example, a resin such as an epoxy resin. The insulating encapsulant 25 encapsulates the semiconductor controller chip 3, the semiconductor memory chips 4a to 4d, and the wires 18 to 24 on the upper surface of the wiring board 2. Thereby, the insulating encapsulant 25 protects the semiconductor controller chip 3, the semiconductor memory chips 4a to 4d, and the wires 18 to 24 from external impacts and outside air.

[0016] The external connection terminals 7 are, for example, metal bumps such as solder balls. In this case, the semiconductor device 1 has a BGA (Ball Grid Array) package structure. The external connection terminals 7 electrically connect the semiconductor device 1 to an external mounting board or the like (not shown). The material of the external connection terminals 7 is a conductive metal such as solder. The external connection terminals 7 are provided on the lower surface of the wiring board 2. That is, the external connection terminals 7 are provided on the surface of the wiring board 2 opposite to the surface F1 on which the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d are provided.

[0017] Next, the configuration of the wiring board 2 will be described.

[0018] The wiring board 2 has a surface F1 and electrode pads 5a, 5b, and 6. The electrode pads 5a, 5b, and 6 are provided on the surface F1.

[0019] Next, the configuration of the semiconductor controller chip 3 will be described.

[0020] The semiconductor controller chip 3 has a surface F4, a surface F5, and electrode pads 8 and 9. The surface F4 is the surface facing the surface F1 of the wiring board 2. The surface F5 is the surface opposite to the surface F4. The electrode pads 8 and 9 are provided on the surface F5.

[0021] Next, the configurations of the semiconductor memory chips 4a to 4d will be described.

[0022] The semiconductor memory chip 4a has a surface F2, a surface F3, and electrode pads 10 and 11. The semiconductor memory chip 4b has a surface F2, a surface F3, and electrode pads 12 and 13. The semiconductor memory chip 4c has a surface F2, a surface F3, and electrode pads 14 and 15. The semiconductor memory chip 4d has a surface F2, a surface F3, and electrode pads 16 and 17. The surface F2 is a surface facing the surface F1 of the wiring substrate 2. The surface F3 is a surface on the opposite side of the surface F2. The electrode pads 10 to 17 are provided on the surface F3 of the corresponding semiconductor memory chips 4a to 4d.

[0023] Next, the details of the arrangement of the electrode pads 5a, 5b, 6, 8 to 17 and the wires 18 to 24 will be described.

[0024] FIG. 2 is a plan view showing an example of the configuration of the semiconductor device 1 according to the first embodiment. The line A-A in FIG. 2 indicates a cross section corresponding to FIG. 1 which is a cross-sectional view. Note that in FIG. 1, the wires 18 to 24 are also shown as a side view.

[0025] The electrode pads 5a and 5b are, for example, electrode pads for supplying power or ground voltage. The electrode pad 5a is arranged near the semiconductor controller chip 3 on the surface F1. The electrode pad 5b is arranged near the semiconductor memory chips 4a to 4d on the surface F1.

[0026] The electrode pad 6 is, for example, an electrode pad for signal transmission. The electrode pad 6 is arranged between the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d on the surface F1.

[0027] The outer edge shape of the semiconductor controller chip 3 as viewed from the normal direction of the substrate surface of the wiring substrate 2 is substantially rectangular.

[0028] The electrode pads 8 are, for example, electrode pads for supplying a reference voltage of a power supply or ground. The electrode pads 9 are, for example, electrode pads for signal transmission. The electrode pads 8 and 9 are alternately arranged side by side on the surface F5 along one side (side 3S) of the semiconductor controller chip 3.

[0029] When viewed from the normal direction of the substrate surface of the wiring substrate 2, the outer edge shapes of the semiconductor memory chips 4a to 4d are substantially rectangular.

[0030] The semiconductor memory chips 4a to 4d are stacked so as to form a chip stack. The semiconductor memory chips 4a to 4d are stacked with a shift in the X direction. As a result, the electrode pads 10 to 17 are exposed from the semiconductor memory chips 4a to 4d stacked above, and can be connected to the wires 19, 21 to 24. The semiconductor memory chips 4a to 4d are also stacked with a shift in the Y direction. This is to facilitate direct connection of each of the semiconductor memory chips 4a to 4d to the electrode pad 6, as will be described later. That is, the semiconductor memory chips 4a to 4d are electrically connected to the electrode pad 6 of the wiring substrate 2 without passing through other semiconductor memory chips 4a to 4d.

[0031] That is, the plurality of semiconductor memory chips 4a to 4d are stacked so as to be shifted in the X direction (first direction) from the respective sides 4aS to 4dS of the semiconductor memory chips 4a to 4d toward the sides opposite to the sides 4aS to 4dS. The plurality of semiconductor memory chips 4a to 4d are stacked so as to be shifted in the Y direction perpendicular to the X direction and the Z direction (stacking direction). In the example shown in FIG. 2, the plurality of semiconductor memory chips 4a to 4d are stacked so as to be shifted in the -Y direction from the lowermost stage to the uppermost stage.

[0032] The electrode pad 10 is, for example, an electrode pad for supplying a reference voltage of a power source or a ground. The electrode pad 11 is, for example, an electrode pad for signal transmission. The electrode pads 10 and 11 are arranged alternately along one side (side 4aS) of the semiconductor memory chip 4a on the surface F3. At this time, the electrode pads may be arranged in order such as an electrode pad for power, an electrode pad for signal, an electrode pad for ground, an electrode pad for signal, and an electrode pad for power.

[0033] The electrode pad 12 is, for example, an electrode pad for supplying a reference voltage of a power source or a ground. The electrode pad 13 is, for example, an electrode pad for signal transmission. The electrode pads 12 and 13 are arranged alternately along one side of the semiconductor memory chip 4b on the surface F3. At this time, the electrode pads may be arranged in order such as an electrode pad for power, an electrode pad for signal, an electrode pad for ground, an electrode pad for signal, and an electrode pad for power.

[0034] The electrode pad 14 is, for example, an electrode pad for supplying a reference voltage of a power source or a ground. The electrode pad 15 is, for example, an electrode pad for signal transmission. The electrode pads 14 and 15 are arranged alternately along one side of the semiconductor memory chip 4c on the surface F3. At this time, the electrode pads may be arranged in order such as an electrode pad for power, an electrode pad for signal, an electrode pad for ground, an electrode pad for signal, and an electrode pad for power.

[0035] The electrode pad 16 is, for example, an electrode pad for supplying a reference voltage of a power source or a ground. The electrode pad 17 is, for example, an electrode pad for signal transmission. The electrode pads 16 and 17 are arranged alternately along one side (side 4dS) of the semiconductor memory chip 4d on the surface F3. At this time, the electrode pads may be arranged in order such as an electrode pad for power, an electrode pad for signal, an electrode pad for ground, an electrode pad for signal, and an electrode pad for power.

[0036] Wire 18 is, for example, a wire for supplying a reference voltage of a power supply or a ground. Wire 18 electrically connects the electrode pad 5a of the wiring substrate 2 and the electrode pad 8 of the semiconductor controller chip 3.

[0037] The plurality of wires 19 are, for example, wires for supplying a reference voltage of a power supply or a ground. The wire 19 electrically connects the electrode pad 5b of the wiring substrate 2 and the electrode pads 10, 12, 14, 16 of the semiconductor memory chip closest to the wiring substrate 2 among the plurality of stacked semiconductor memory chips 4a to 4d. Also, the other wires 19 electrically connect the electrode pads 10, 12, 14, 16 of the adjacent semiconductor memory chips 4a to 4d among the stacked semiconductor memory chips 4a to 4d.

[0038] The wire 19 electrically connects the electrode pad 5b of the wiring substrate 2 and the electrode pad 10 of the semiconductor memory chip 4a. Also, the wire 19 electrically connects the electrode pad 10 of the semiconductor memory chip 4a and the electrode pad 12 of the semiconductor memory chip 4b. Also, the wire 19 electrically connects the electrode pad 12 of the semiconductor memory chip 4b and the electrode pad 14 of the semiconductor memory chip 4c. Also, the wire 19 electrically connects the electrode pad 14 of the semiconductor memory chip 4c and the electrode pad 16 of the semiconductor memory chip 4d.

[0039] The wire 19 is provided one by one according to the number of the semiconductor memory chips 4a to 4d. Therefore, the wire 19 is provided so as to connect the electrode pad 5b of the wiring substrate 2 and the electrode pads 10, 12, 14, 16 of the semiconductor memory chips 4a to 4d in this order in a continuous manner. Also, the wire 19 is provided so that the height of the loop is as low as possible. Thereby, the wiring substrate 2 and the semiconductor memory chips 4a to 4d can be connected so that the wire 19 becomes shorter.

[0040] Wire 20 is, for example, a wire for signal transmission. Wire 20 electrically connects the electrode pad 6 of the wiring board 2 and the electrode pad 9 of the semiconductor controller chip 3. Incidentally, wire 20 may also be referred to as a connection conductor C.

[0041] Wire 21 is, for example, a wire for signal transmission. Wire 21 electrically connects the electrode pad 6 of the wiring board 2 and the electrode pad 11 of the semiconductor memory chip 4a.

[0042] Wire 22 is, for example, a wire for signal transmission. Wire 22 electrically connects the electrode pad 6 of the wiring board 2 and the electrode pad 13 of the semiconductor memory chip 4b.

[0043] Wire 23 is, for example, a wire for signal transmission. Wire 23 electrically connects the electrode pad 6 of the wiring board 2 and the electrode pad 15 of the semiconductor memory chip 4c.

[0044] Wire 24 is, for example, a wire for signal transmission. Wire 24 electrically connects the electrode pad 6 of the wiring board 2 and the electrode pad 17 of the semiconductor memory chip 4d.

[0045] That is, the plurality of wires 21 to 24 electrically connect the electrode pad 6 of the wiring board 2 and the electrode pads 11, 13, 15, and 17 respectively possessed by the semiconductor memory chips 4a to 4d.

[0046] Wires 21 to 24 may be collectively referred to as a wire group WG1. In the example shown in FIG. 2, the wiring board 2 has two electrode pads 6. Also, two wire groups WG1 are provided.

[0047] The signals transmitted (transmitted and received) between each of the semiconductor memory chips 4a to 4c and the semiconductor controller chip 3 pass through the electrode pad 6, the electrode pads 11, 13, 15, 17, the electrode pad 9, the wires 21 to 24, and the wire 20 (connection conductor C).

[0048] In the example shown in FIG. 2, the semiconductor memory chips 4a to 4d are stacked with a shift in the Y direction and are directly connected to the electrode pads 6. In the plan view shown in FIG. 2, the electrode pads 9, 11, 13, 15, 17 are arranged at substantially equal intervals around the electrode pad 6. In the plan view shown in FIG. 2, the wires 20 to 24 are provided with substantially the same length. Thus, as will be described with reference to FIG. 3, it is possible to suppress a deterioration in the quality of the signal.

[0049] FIG. 3 is a schematic diagram showing an example of the connection relationship between the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d according to the first embodiment. FIG. 3 shows an example in which the semiconductor memory chip 4d transmits a signal and the semiconductor controller chip 3 receives the signal. Therefore, the electrode pad 17 of the semiconductor memory chip 4d is a transmission end, and the electrode pad 9 of the semiconductor controller chip 3 is a reception end.

[0050] The signal transmitted from the electrode pad 17 is transmitted to the electrode pads 9, 11, 13, 15 via the electrode pad 6, for example. The signal is reflected, for example, at the electrode pads 9, 11, 13, 15, 17 (the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d). The signal waveform of the signal received by the electrode pad 9 which is the reception end is formed by, for example, the combination of the signal incident on the electrode pads 9, 11, 13, 15, 17 and the signal reflected from the electrode pads 9, 11, 13, 15, 17.

[0051] Here, when the transmission delays (delay times) from the central electrode pad 6 to the electrode pads 9, 11, 13, 15, 17 are substantially the same, the timings of the signal reflections substantially coincide and the influence of the reflections can be canceled out. Thereby, a deterioration in the waveform quality of the synthesized signal waveform can be suppressed. As a result, the semiconductor controller chip 3 can receive the signal more appropriately.

[0052] The transmission delay is calculated, for example, based on the electrical characteristics (signal transmission characteristics) of the wires 20 to 24 and the electrode pads 9, 11, 13, 15, 17. The signal transmission characteristics of the wires 20 to 24 are determined, for example, by the thickness and length. The signal transmission characteristics of the electrode pads 9, 11, 13, 15, 17 are determined, for example, by the capacitance.

[0053] Therefore, it is preferable that the signal transmission characteristics from the electrode pad 6 to each of the semiconductor memory chips 4a to 4d and the signal transmission characteristics from the electrode pad 6 to the semiconductor controller chip 3 are substantially the same. That is, the electrode pads 11, 13, 15, 17, the electrode pad 9, the wire group WG1 (wires 21 to 24), and the wire 20 (connection conductor C) are provided such that the signal transmission characteristics (delay time) from the electrode pad 6 to each of the semiconductor memory chips 4a to 4d and the signal transmission characteristics from the electrode pad 6 to the semiconductor controller chip 3 are substantially the same.

[0054] When the semiconductor memory chips 4a to 4d are singulated from one wafer, they are formed by the same process. Therefore, the capacitances of the respective electrode pads 11, 13, 15, 17 of the semiconductor memory chips 4a to 4d are usually substantially the same. On the other hand, the capacitance of the electrode pad 9 of the semiconductor controller chip 3 may be different from the capacitances of the electrode pads 11, 13, 15, 17 of the semiconductor memory chips 4a to 4d.

[0055] Each of the wires 20 to 24 is usually formed by the same method, and the thicknesses of the wires 20 to 24 are substantially the same. Depending on the difference between the capacitance of the electrode pad 9 of the semiconductor controller chip 3 and the capacitances of the electrode pads 11, 13, 15, 17 of the semiconductor memory chips 4a to 4d, the length of the wire 20 may be provided to be different from the lengths of the wires 21 to 24.

[0056] Next, focusing on the path from the electrode pads 6 to the semiconductor memory chips 4a to 4d, it is necessary that the signal transmission characteristics of each of the wires 21 to 24 are substantially the same. That is, the variation in the signal transmission characteristics of each of the wires 21 to 24 is below a predetermined value. More specifically, the variation in the signal transmission characteristics of each of the wires 21 to 24 is 10% or less with respect to the average value.

[0057] It is preferable that the thickness and length of each of the wires 21 to 24 are substantially the same, for example. That is, it is preferable that the variation in the thickness and length of each of the wires 21 to 24 is below a predetermined value (for example, 10% or less with respect to the average value). Each of the wires 21 to 24 is usually formed by the same method, and the thickness of each of the wires 21 to 24 is substantially the same. Therefore, it is preferable that the wires 21 to 24 are provided to have substantially the same length.

[0058] Note that in FIG. 2, the lengths of the wires 21 to 24 in a plan view are shown to be substantially the same. On the other hand, in FIG. 1, due to the difference in the height of the loops, the lengths of the wires 21 to 24 are shown to be different. For example, depending on the difference in the height of the loops, the lengths of the wires 21 to 24 in a plan view may be different so that the lengths of the wires 21 to 24 are substantially the same. For example, the maximum height of the loop may gradually decrease from the wire 24 to the wire 21.

[0059] Next, the connection method of the wires 19, 21 to 24 connected to the semiconductor memory chips 4a to 4d will be described.

[0060] FIGS. 4 to 9 are diagrams showing an example of a method for manufacturing the semiconductor device 1 according to the first embodiment. The upper parts of FIGS. 4 to 9 show cross-sectional views of the semiconductor memory chips 4a to 4d. The lower parts of FIGS. 4 to 9 show plan views of the semiconductor memory chips 4a to 4d.

[0061] First, as shown in FIG. 4, semiconductor memory chips 4a to 4d are mounted on a wiring board 2. The semiconductor memory chips 4a to 4d are stacked with misalignment in the X direction and the Y direction.

[0062] Next, as shown in FIG. 5, a plurality of wires 19 are formed. Next, as shown in FIG. 6, a wire 21 is formed. Next, as shown in FIG. 7, a wire 22 is formed. Next, as shown in FIG. 8, a wire 23 is formed. Next, as shown in FIG. 9, a wire 24 is formed.

[0063] As shown in FIGS. 5 to 9, the wires 21 to 24 are formed in order from the wire with a low loop height so that the wires 21 to 24 can be easily formed.

[0064] As described above, according to the first embodiment, the variation in the signal transmission characteristics (transmission delay) of each of the wires 21 to 24 is equal to or less than a predetermined value. Thereby, a decrease in the quality of the signal can be suppressed. As a result, the semiconductor controller chip 3 can receive the signal more appropriately.

[0065] Next, as a comparative example, a case where the wires 21 to 24 are connected in a single stroke like the plurality of wires 19 that supply a reference voltage will be described.

[0066] FIG. 10 is a schematic diagram showing an example of the connection relationship between the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d according to the comparative example. FIG. 10 shows an example in which the semiconductor memory chip 4a transmits a signal and the semiconductor controller chip 3 receives the signal. Therefore, the electrode pad 11 of the semiconductor memory chip 4a is a transmission end, and the electrode pad 9 of the semiconductor controller chip 3 is a reception end.

[0067] The signal transmitted from the electrode pad 11 is transmitted to the electrode pad 6 side and the electrode pad 13 side. The signal is reflected at the electrode pad 17 (semiconductor memory chip 4d). Due to this reflection, the waveform quality of the synthesized signal waveform deteriorates. Also, at least a part of the signal is reflected, for example, at the electrode pads 13 and 15 (semiconductor memory chips 4b and 4c). Also due to this reflection, the waveform quality of the waveform of the synthesized signal deteriorates. Also, the higher the speed of the signal, the more likely the waveform quality is to deteriorate.

[0068] In contrast, in the first embodiment, as shown in FIG. 3, each of the electrode pads 9, 11, 13, 15, and 17 of the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d is connected to the electrode pad 6. By making the transmission delay in each of the semiconductor chips substantially the same with the electrode pad 6 as the center, it is possible to suppress the deterioration of the waveform quality due to the reflection of the signal. Thereby, the waveform quality of the waveform received by the semiconductor controller chip 3 can be improved.

[0069] Note that in terms of signal transmission characteristics, the influence of the wire may be greater than that of the electrode pad in some cases. In this case, the variation in the signal transmission characteristics of each of the plurality of wires 21 to 24 and the wire 20 may be equal to or less than a predetermined value (for example, 10% with respect to the average value).

[0070] Also, the semiconductor controller chip 3 is not limited to the controller chip, and may be other semiconductor chips. The semiconductor memory chips 4a to 4d are not limited to memory chips, and may be other semiconductor chips.

[0071] Also, the number of the semiconductor memory chips 4a to 4d is not limited to four. The number of wires (wire groups) and electrode pads is not limited to the examples shown in FIGS. 1 and 2.

[0072] (Modification of the First Embodiment) FIG. 11 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to a modified example of the first embodiment. FIG. 12 is a plan view showing an example of the configuration of the semiconductor device 1 according to a modified example of the first embodiment. In the modified example of the first embodiment, the configuration of the connection conductor C is different from that of the first embodiment.

[0073] The connection conductor C includes an electrode pad C1, a wiring C2, and a wire C3. In the modified example of the first embodiment, the wire 20 is not provided.

[0074] The electrode pad C1 is, for example, an electrode pad for signal transmission. The electrode pad C1 is provided on the surface F1 of the wiring board 2.

[0075] The wiring C2 is, for example, a wiring for signal transmission. The wiring C2 is provided on the wiring board 2 and electrically connects the electrode pad 6 of the wiring board 2 and the electrode pad C1 of the wiring board 2. Note that the wiring C2 may include a columnar electrode (Via) in the wiring board 2.

[0076] The wire C3 is, for example, a wire for signal transmission. The wire C3 electrically connects the electrode pad 9 of the semiconductor controller chip 3 and the electrode pad C1 of the wiring board 2.

[0077] Regardless of the configuration of the connection conductor C, similar to the first embodiment, the signal transmission characteristics (transmission delay) are adjusted. That is, the electrode pads 11, 13, 15, 17, the electrode pad 9, the wire group WG1 (wires 21 to 24), the electrode pad C1, the wiring C2, and the wire C3 are provided such that the signal transmission characteristics from the electrode pad 6 to each of the semiconductor memory chips 4a to 4d and the signal transmission characteristics from the electrode pad 6 to the semiconductor controller chip 3 are substantially the same.

[0078] Since other configurations of the semiconductor device 1 according to the modified example of the first embodiment are the same as the corresponding configurations of the semiconductor device 1 according to the first embodiment, detailed descriptions thereof are omitted.

[0079] As in the modification of the first embodiment, the configuration of the connection conductor C may be changed. The semiconductor device 1 according to the modification of the first embodiment can obtain the same effects as the first embodiment.

[0080] (Second Embodiment) FIG. 13 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. FIG. 14 is a plan view showing an example of the configuration of the semiconductor device 1 according to the second embodiment. The line C-C in FIG. 14 indicates the cross-section corresponding to the cross-sectional view in FIG. 13.

[0081] The second embodiment is different from the first embodiment in that wires 27 to 30 are further provided.

[0082] The wiring substrate 2 has a plurality of electrode pads 6. In the example shown in FIG. 14, the wiring substrate 2 has two electrode pads 6.

[0083] The wiring substrate 2 further has an electrode pad 26 disposed between adjacent electrode pads 6. The electrode pad 26 is, for example, an electrode pad for supplying a voltage of a power source or ground.

[0084] The semiconductor memory chip 4a has a plurality of electrode pads 11. In the example shown in FIG. 14, the semiconductor memory chip 4a has two electrode pads 11. Adjacent electrode pads 11 are arranged with an electrode pad 10 interposed therebetween.

[0085] The semiconductor memory chip 4b has a plurality of electrode pads 13. In the example shown in FIG. 14, the semiconductor memory chip 4b has two electrode pads 13. Adjacent electrode pads 13 are arranged with an electrode pad 12 interposed therebetween.

[0086] The semiconductor memory chip 4c has a plurality of electrode pads 15. In the example shown in FIG. 14, the semiconductor memory chip 4c has two electrode pads 15. Adjacent electrode pads 15 are arranged with an electrode pad 14 interposed therebetween.

[0087] The semiconductor memory chip 4d has a plurality of electrode pads 17. In the example shown in FIG. 14, the semiconductor memory chip 4d has two electrode pads 17. The adjacent electrode pads 17 are arranged with the electrode pad 16 therebetween.

[0088] The semiconductor device 1 includes a plurality of wire groups WG1 corresponding to the plurality of electrode pads 6, the plurality of electrode pads 11, the plurality of electrode pads 13, the plurality of electrode pads 15, and the plurality of electrode pads 17. In the example shown in FIG. 14, the semiconductor device 1 includes two wire groups WG1.

[0089] Here, when two wire groups WG1 are arranged in proximity, the signal quality may deteriorate due to crosstalk between the wire groups WG1.

[0090] Therefore, the semiconductor device 1 further includes a wire group WG2 arranged between adjacent wire groups WG1.

[0091] The wire group WG2 includes a plurality of wires 27 to 30.

[0092] The wire 27 is, for example, a wire for supplying a reference voltage of a power supply or ground. The wire 27 electrically connects the electrode pad 26 of the wiring substrate 2 and the electrode pad 10 of the semiconductor memory chip 4a. The electrode pad 10 connected to the wire 27 is arranged between the adjacent electrode pads 11 as described above.

[0093] Also, the wire 27 connected to the semiconductor memory chip 4a is arranged between two wires 21 connected to the semiconductor memory chip 4a included in each of the adjacent wire groups WG1. The wire 27 has substantially the same loop shape as the wire 21 when viewed from the Y direction as shown in FIG. 13.

[0094] Wire 28 is, for example, a wire for supplying a reference voltage of a power supply or a ground. Wire 28 electrically connects the electrode pad 26 of the wiring substrate 2 and the electrode pad 12 of the semiconductor memory chip 4b. The electrode pad 12 connected to wire 28 is arranged between adjacent electrode pads 13 as described above.

[0095] Also, wire 28 connected to the semiconductor memory chip 4b is arranged between two wires 22 connected to the semiconductor memory chip 4b included in each of the adjacent wire groups WG1. As shown in FIG. 13, wire 28 has substantially the same loop shape as wire 22 when viewed from the Y direction.

[0096] Wire 29 is, for example, a wire for supplying a reference voltage of a power supply or a ground. Wire 29 electrically connects the electrode pad 26 of the wiring substrate 2 and the electrode pad 14 of the semiconductor memory chip 4c. The electrode pad 14 connected to wire 29 is arranged between adjacent electrode pads 15 as described above.

[0097] Also, wire 29 connected to the semiconductor memory chip 4c is arranged between two wires 23 connected to the semiconductor memory chip 4c included in each of the adjacent wire groups WG1. As shown in FIG. 13, wire 29 has substantially the same loop shape as wire 23 when viewed from the Y direction.

[0098] Wire 30 is, for example, a wire for supplying a reference voltage of a power supply or a ground. Wire 30 electrically connects the electrode pad 26 of the wiring substrate 2 and the electrode pad 16 of the semiconductor memory chip 4d. The electrode pad 16 connected to wire 30 is arranged between adjacent electrode pads 17 as described above.

[0099] Also, wire 30 connected to the semiconductor memory chip 4d is arranged between two wires 24 connected to the semiconductor memory chip 4d included in each of the adjacent wire groups WG1. As shown in FIG. 13, wire 30 has substantially the same loop shape as wire 24 when viewed from the Y direction.

[0100] The wires 27 to 30 (wire group WG2) can suppress crosstalk between adjacent wire groups WG1. As a result, a decrease in the signal quality can be suppressed.

[0101] Since other configurations of the semiconductor device 1 according to the second embodiment are the same as the corresponding configurations of the semiconductor device 1 according to the first embodiment, detailed description thereof is omitted.

[0102] As in the second embodiment, the wires 27 to 30 may be further provided. The semiconductor device 1 according to the second embodiment can obtain the same effects as the first embodiment. Further, a modification example of the first embodiment may be combined with the second embodiment.

[0103] (Third Embodiment) FIG. 15 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the third embodiment. FIG. 16 is a plan view showing an example of the configuration of the semiconductor device 1 according to the third embodiment. The line D-D in FIG. 16 indicates a cross section corresponding to the cross-sectional view in FIG. 15.

[0104] The third embodiment is different from the first embodiment in the stacked structure of the semiconductor memory chips 4a to 4d.

[0105] In the example shown in FIG. 16, the stacked structures of the semiconductor memory chips 4a to 4d are alternately shifted in the Y direction. That is, the semiconductor memory chip 4b is stacked shifted in the -Y direction with respect to the semiconductor memory chip 4a. The semiconductor memory chip 4c is stacked shifted in the +Y direction with respect to the semiconductor memory chip 4b. The semiconductor memory chip 4d is stacked shifted in the -Y direction with respect to the semiconductor memory chip 4c.

[0106] That is, the plurality of semiconductor memory chips 4a to 4d are stacked so as to be alternately shifted in the Y direction (for example, the +Y direction) perpendicular to the X direction and the Z direction and in the direction opposite to the Y direction (for example, the -Y direction) along the Z direction. Thereby, the semiconductor memory chips 4a to 4d can be stacked alternately in the Y direction so that the wires 21 to 24 do not cross in a plan view as viewed from the Z direction. Further, compared with the first embodiment described with reference to FIG. 2, the arrangement area of the semiconductor memory chips 4a to 4d in the Y direction can be suppressed.

[0107] Incidentally, the amount of shift of each of the semiconductor memory chips 4a to 4d in the Y direction may be changed within a range in which the wires 21 to 24 do not overlap in a plan view.

[0108] As shown in FIG. 15, the heights of the loops of the wires 21 to 24 are different according to the distances between the electrode pad 6 and the electrode pads 11, 13, 15, 17. For example, the wire 21 connected to the semiconductor memory chip 4a closest to the electrode pad 6 has the highest loop. The wire 24 connected to the semiconductor memory chip 4d farthest from the electrode pad 6 has the lowest loop. That is, the maximum height of the loop of the wire 24 connected to the electrode pad 17 of the semiconductor memory chip 4d farthest from the wiring board 2 is lower than the maximum height of the loop of the wire 21 connected to the electrode pad 11 of the semiconductor memory chip 4a closest to the wiring board 2.

[0109] Thus, in the second embodiment, by adjusting the height of the loop, the lengths of the wires 21 to 24 are adjusted to be substantially the same.

[0110] Since other configurations of the semiconductor device 1 according to the third embodiment are the same as the corresponding configurations of the semiconductor device 1 according to the first embodiment, detailed description thereof is omitted.

[0111] Next, a connection method of the wires 19, 21 to 24 connected to the semiconductor memory chips 4a to 4d will be described.

[0112] Figures 17 to 22 are diagrams showing an example of a method for manufacturing the semiconductor device 1 according to the third embodiment. The upper parts of Figures 17 to 22 show cross-sectional views of the semiconductor memory chips 4a to 4d. The lower parts of Figures 17 to 22 show plan views of the semiconductor memory chips 4a to 4d.

[0113] First, as shown in Figure 17, the semiconductor memory chips 4a to 4d are mounted on the wiring substrate 2. The semiconductor memory chips 4a to 4d are stacked with a shift in the X direction and the Y direction.

[0114] Next, as shown in Figure 18, a plurality of wires 19 are formed. Next, as shown in Figure 19, a wire 24 is formed. Next, as shown in Figure 20, a wire 23 is formed. Next, as shown in Figure 21, a wire 22 is formed. Next, as shown in Figure 22, a wire 21 is formed.

[0115] As shown in Figures 17 to 22, the wires 21 to 24 are formed in order from the wire with a low loop height so as to facilitate the formation of the wires 21 to 24.

[0116] Within the range where the wires 19, 21 to 24 can be connected, the stacked structure of the semiconductor memory chips 4a to 4d may be changed as in the third embodiment. The semiconductor device 1 according to the third embodiment can obtain the same effects as those of the first embodiment. Also, a modification example of the first embodiment may be combined with the third embodiment.

[0117] (Fourth Embodiment) Figure 23 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the fourth embodiment. Figure 24 is a plan view showing an example of the configuration of the semiconductor device 1 according to the fourth embodiment. The line E-E in Figure 24 shows the cross-section corresponding to the cross-sectional view in Figure 23.

[0118] The fourth embodiment is different from the third embodiment in that wires 27 to 30 are further provided. That is, the fourth embodiment is a combination of the second embodiment and the third embodiment.

[0119] As described in the second embodiment, crosstalk between adjacent wire groups WG1 can be suppressed by the wires 27 to 30 (wire group WG2). As a result, deterioration of the signal quality can be suppressed.

[0120] As in the fourth embodiment, the wires 27 to 30 may be further provided. The semiconductor device 1 according to the fourth embodiment can obtain the same effects as those of the third embodiment. Further, a modification of the first embodiment may be combined with the fourth embodiment.

[0121] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0122] 1 Semiconductor device, 2 Wiring board, 3 Semiconductor controller chip, 4a to 4d Semiconductor memory chips, 4aS to 4dS Sides, 5a Electrode pad, 5b Electrode pad, 6 Electrode pad, 8 to 17 Electrode pads, 18 to 24 Wires, 26 Electrode pad, 27 to 30 Wires, C Connection conductor, C1 Electrode pad, C2 Wiring, C3 Wire, F1 to F5 Surfaces, WG1 Wire group, WG2 Wire group

Claims

1. A substrate having a first surface, a first pad and a second pad provided on the first surface; A chip stack in which a plurality of first semiconductor chips having a second surface facing the first surface, a third surface on the opposite side of the second surface, and a third pad and a fourth pad provided on the third surface are stacked; A first wire group including a plurality of first wires that electrically connect the first pad and each of the third pads of the first semiconductor chips; A second wire that electrically connects the second pad and the fourth pad of the first semiconductor chip closest to the substrate among the plurality of first semiconductor chips; A third wire that electrically connects each of the fourth pads of the plurality of first semiconductor chips; A semiconductor device comprising:

2. The semiconductor device according to claim 1, wherein the maximum height of the loop of the first wire connected to the third pad of the first semiconductor chip farthest from the substrate is lower than the maximum height of the loop of the first wire connected to the third pad of the first semiconductor chip closest to the substrate.

3. The substrate further has a fifth pad provided on the first surface, The plurality of first semiconductor chips further have a sixth pad provided on the third surface, A fourth wire that electrically connects the fifth pad and the sixth pad of the first semiconductor chip closest to the substrate among the plurality of first semiconductor chips; Further comprising a fifth wire that electrically connects each of the sixth pads of the plurality of first semiconductor chips, The semiconductor device according to claim 1, wherein the fourth pad, the third pad, and the sixth pad are arranged in this order along one direction.

4. The semiconductor device according to claim 3, wherein when the fourth pad is a pad to which one of a power supply voltage or a ground voltage is applied, the sixth pad is a pad to which the other of the power supply voltage or the ground voltage is applied, and the third pad is a pad to which a signal is input.

5. The semiconductor device according to claim 1, wherein the variation in the thickness and length of each of the first wires is 10% or less with respect to the average value.

6. A second semiconductor chip having a fourth surface facing the first surface, a fifth surface on the opposite side of the fourth surface, and a seventh pad provided on the fifth surface; A connection conductor that electrically connects the first pad and the seventh pad; The semiconductor device according to claim 1, further comprising

7. The third pad is disposed on the third surface along a first side of the first semiconductor chip. The semiconductor device according to claim 1, wherein the plurality of first semiconductor chips are stacked so as to be displaced in a first direction from each of the first sides of the first semiconductor chip toward a second side opposite to the first side.

8. The semiconductor device according to claim 7, wherein the plurality of first semiconductor chips are stacked so as to be displaced in a second direction perpendicular to the first direction and the stacking direction.

9. The semiconductor device according to claim 7, wherein the plurality of first semiconductor chips are stacked so as to be alternately displaced in the first direction and a second direction perpendicular to the first direction and the stacking direction and in a direction opposite to the second direction along the stacking direction.

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