Static Random Access Memory Read Path with Latch

Abstract

The present invention provides a read path for reading data from a memory, the read path including a sense amplifier having a data (SAT) node and a data complement (SAC) output node, and a latch. The latch includes an input tri-state inverter including a first PMOS transistor and a second PMOS transistor connected between VDD and an intermediate node, and a first NMOS transistor and a second NMOS transistor connected between VSS and the intermediate node. The gate connections of the first PMOS transistor and the first NMOS transistor are connected to the SAT node, the gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input, and the gate connection of the second NMOS transistor is connected to the sense amplifier enable input. The latch also includes an output driver having an input connected to the intermediate node and an output connected to a data output node. Thus, the latch has two gate delays between the SAT node and the data output node.

Description

Background Art

[0001] (Related Art) Many electronic devices include integrated circuit memories that are used to store copies of data (i.e., results from computations, operands, instructions, control values, and / or other information). For example, some electronic devices include cache memories that are used to locally store copies of data to enable rapid retrieval of the data during operation by entities such as processor cores. Some of those memories include static random access memory (SRAM). SRAM is a form of integrated circuit memory in which individual cells (or "bit cells") implemented using field effect transistors are used to store individual bits of data. For example, in one common form of SRAM, each cell is implemented using six transistors configured as two back-to-back inverters for storing data and two access transistors for accessing the stored data. In some SRAM memories, the data stored in a cell is read through a read path that includes a sense amplifier and a latch. In a given read path, the sense amplifier generates a read data output based on the stored data value obtained from the cell, and the latch captures and stores the read data output from the sense amplifier and supplies the read data output to downstream circuit elements.

[0002] In some electronic devices, SRAM memory is part of a circuit in a critical timing path. For example, SRAM cache memory may be used to provide operands to a high-speed processor core and may be between the longest latency elements in the timing path associated with computational operations that depend on the operands. Additionally, in some electronic devices, SRAM memory needs to be able to operate accurately within a range of different control clock frequencies. For example, SRAM memory may be required to support different operating states, power modes, etc. that have a wide range of control clock frequencies. In some electronic devices, the control clock frequency may be set low enough that a short-circuit current occurs as the read path operates, leading to undesirable and inefficient leakage current and in some cases malfunction. Designers have expended considerable effort to optimize the SRAM memory read path to meet the dual goals of improving the operating speed of the SRAM memory read path and avoiding inefficiencies and malfunctions that may occur within the SRAM memory read path at lower control clock frequencies. For example, designers have proposed using the latch circuit shown in FIG. 1 within the SRAM memory read path. The latch circuit in FIG. 1 includes a NOR gate set-reset latch according to a logic gate that uses the complement of a sense amplifier enable signal (SAENX) to avoid short-circuit current and malfunction during lower frequency operation of the read path. As another example, designers have proposed using the latch circuit shown in FIG. 2 within the SRAM memory read path. The latch circuit in FIG. 2 includes an AND-OR inverter latch gated using the SAENX signal to avoid short-circuit current and malfunction during lower frequency operation of the read path. Using latch circuits such as those shown in FIGS. 1-2 can result in faster operation of the read path and avoid leakage current at lower frequencies, but the latch circuits include three gates that add delay to the read path, have different rise and fall times, and have other drawbacks. Therefore, a better read path for SRAM memory is desired.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0004] Throughout the drawings and the description, the same reference numerals refer to the same elements of the figures.

[0005] The following description is presented to enable any person skilled in the art to make and use the described embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications. Thus, the described embodiments are not limited to the embodiments shown, but should be accorded the widest scope consistent with the principles and features disclosed herein.

[0006] (Terminology) In the following description, various terms are used to describe embodiments. The following is a simplified summary of some of these terms. These terms may have important additional aspects not detailed herein for clarity and brevity, and thus it should be noted that the description is not intended to limit the terms.

[0007] Functional block: A functional block refers to a group, collection, and / or set of one or more interrelated circuit elements such as integrated circuit elements, discrete circuit elements, etc. The circuit elements are "interrelated" in that the circuit elements share at least one attribute. For example, the interrelated circuit elements may be included in, assembled on, or otherwise coupled to a particular integrated circuit chip or a part thereof, may be involved in the implementation of a predetermined function (such as a computing or processing function, a memory function, etc.), and may be controlled by a common control element and / or a common clock, etc. A functional block can include any number of circuit elements from a single circuit element (e.g., a single integrated circuit logic gate) to millions or billions of circuit elements (e.g., an integrated circuit memory).

[0008] Complementation: Complementation applied to a signal indicates that a given signal is the logical inversion of another signal. For example, a "bit line complementation" signal is the logical inversion of a "bit line" signal. Thus, if the bit line is logically high (e.g., approximately VDD) and then in a steady state, the bit line complementation is logically low (e.g., approximately VSS). A signal and its complement can be found on the opposite side of a particular inversion circuit element such as an inverter, a cell in an SRAM memory, etc. In this description, the complement of a signal may be indicated using an X appended to the end of the signal label. As a result, a signal labeled "SIGNALX" is the complement of the signal labeled "SIGNAL".

[0009] Signal: A signal refers to voltage, current, or other characteristics of an electrical path, route, guide, and / or other interconnection that is driven, supplied, or otherwise made available by a supply electrical circuit element and received by one or more receiving circuit elements. For example, a buffer circuit element can drive a signal having a logically high voltage value (e.g., approximately VDD) on a metal trace where the signal is received by a memory circuit element such as a latch or flip-flop circuit element. The supply circuit element can change the signal over time within an acceptable range of voltage, current, or other characteristics based on a change in the input stimulus to the supply circuit element. For example, an inverter circuit element can initially output a logically high voltage value but can transition to a logically low voltage value (e.g., approximately VSS) or an intermediate voltage value between VDD and VSS based on a corresponding change in the input to the inverter. In some cases, a signal such as a signal that is constantly driven at a logically high value (e.g., approximately VSS) or a logically low value (e.g., approximately VDD) is constant.

[0010] Gate Delay: Gate delay is an approximate and relative measurement for comparing the performance of different integrated circuits. Generally, gate delay represents the number of transistors (often within an inverter circuit element) through which a signal traverses a path through an integrated circuit. Thus, gate delay is a rough measure of the flight time of a signal through a path. Using an inverter implemented using a metal oxide silicon field effect transistor (transistor) as an example, gate delay is the approximate time between the transition of a signal connected to the gate connection of the transistors that make up the inverter at the input of the inverter and the corresponding transition at the output of the inverter.

[0011] (Overview) In the described embodiments, an integrated circuit memory storing data (e.g., operands for computational operations, results resulting from operations, instructions, configuration values, tag information, and / or other information) is included. For example, in some embodiments, the memory is a cache memory, a tag array within the cache memory, main memory, and / or another memory, or is included therein. The memory includes a static random access memory (SRAM) circuit in which bits of data are stored in cells implemented using field effect transistors (or more simply "transistors"). For example, in some embodiments, each cell is implemented using six transistors, four of which are configured as back-to-back inverters for storing bits of data, and two of which are configured as access transistors for enabling (or disabling) access to (i.e., reading and writing) the stored data. In the described embodiments, data is read from each cell in the memory via circuit elements within a corresponding "read path". Each read path includes circuit elements, i.e., sense amplifiers (sensing amplifiers) and latches, for obtaining data from one or more of the cells and supplying the data to receiving circuit elements. Generally, in the described embodiments, the circuit elements within the read path are selected and arranged such that (1) only two gate delays exist between the output of the sense amplifier and the data output of the read path, (2) short circuit currents and malfunctions (e.g., hold failures for latches) associated with lower frequency operations of the read path are avoided, (3) capacitive loads on the sense amplifier are balanced, and (4) the rise / fall times of the latches are more symmetric (i.e., than existing read path latch designs).

[0012] In the described embodiment, the latch in the read path for the memory is implemented using an array of circuit elements that includes only two gate delays in the read path between the output of the sense amplifier and the data output from the read path. In this array, the first gate (and thus the first gate delay) in the read path within each latch is a three-state inverter. On the output of the three-state inverter coupled to the intermediate node of the latch, the three-state inverter controls when it transmits the inverted version of the input signal received from the sense amplifier (SAT) output for that read path using the sense amplifier enable signal (SAEN) and its complement (SAENX) for that read path. The second gate in the read path within each latch is an output driver (e.g., an output inverter, NAND gate, three-state inverter, etc.). The output driver receives a signal from the intermediate node of the latch as an input and outputs the inverted version of the signal from the intermediate node as the data output of that read path. In addition to those two gates, each latch includes a memory element coupled to the intermediate node of that latch that maintains a value on the intermediate node of that latch (and thus is a circuit element that "stores" data in that latch). The memory element includes a back-to-back pair of an inverter and a three-state inverter, and the three-state inverter is controlled using the SAENX signal and the SAEN signal.

[0013] Due to the arrangement of circuit elements in the sense amplifier and latch, without any form of protection, especially at lower control clock frequencies, a short - circuit current may occur in the read path due to a short - circuit path formed when certain control signals overlap in time. For example, in a design where the sense amplifier pre - charge (SAPC) signal is used alone to trigger pre - charge (i.e., to pre - charge the SAT node and the sense amplifier complement (SAC) node in the pre - charge circuit within the sense amplifier), when the SAPC signal is asserted and the SAEN signal is also asserted, a short - circuit path may occur within the sense amplifier itself. As another example, when the SAPC signal is asserted and the latch is enabled (via the SAEN signal), a short - circuit path may occur through the sense amplifier and latch, which may lead to a malfunction due to corruption of the data stored in the latch. The described embodiments include a pre - charge control circuit that controls when the pre - charge circuit pre - charges the sense amplifier to avoid the short - circuit current. In the described embodiments, the pre - charge control circuit receives, as inputs, the SAPC signal and the SAENX signal, and based on the values of the SAPC signal and the SAENX signal, outputs a sense amplifier pre - charge complement (SAPCX) signal, and the SAPCX signal causes the pre - charge circuit within the sense amplifier to pre - charge the sense amplifier. By using the SAENX signal to control when the sense amplifier is pre - charged, it is necessary that pre - charging the sense amplifier and enabling the sense amplifier and latch do not overlap, which provides protection from the associated short - circuit current.

[0014] In the described embodiments, the capacitive load for the sense amplifier in each read path is balanced using a load sharing circuit. The load sharing circuit is connected to the sense amplifier complementary (SAC) node of the sense amplifier and supplies a capacitive load to the SAC node. In some embodiments, the load sharing circuit includes a three-state inverter, and the gate connections for two of the four transistors of the three-state inverter (i.e., one is an NMOS transistor and one is a PMOS transistor) are connected to the SAC node, and the gate connections for the other two transistors are connected to a disable signal that maintains the three-state inverter in an off / disabled / non-conductive state. Thus, the three-state inverter presents a capacitive load to the SAC node similar to the capacitive load presented to the SAT node by the three-state inverter described above within the latch. The load sharing circuit ensures that equal loads are presented to the sense amplifier for the SAT node and the SAC node, which improves the lifespan of the transistors within the sense amplifier and ensures more equal rise and fall times for the SAT node and the SAC node. In some embodiments, apart from supplying the capacitive load, the load sharing circuit is not involved in other operations within the read path.

[0015] In some embodiments, at least two banks of the memory within the SRAM memory share a portion of a single read path and thus selectively output data using the same single read data output. In those embodiments, the output driver, intermediate node, and storage circuit elements within the latch described above are the portions of the read path that are shared between the two banks of the memory. Thus, each bank of the memory includes its own separate sense amplifier and latch input three-state inverter, as well as its own load sharing circuit and precharge control circuit. In those embodiments, the three-state inverter within the shared portion of the read path is controlled / enabled via a combination of the individual SAEN signals and SAENX signals used within the read path for the two banks.

[0016] By using the circuit elements (i.e., latches, precharge control circuits, and load distribution circuits) described above in the read path for the SRAM memory, the described embodiments increase the speed of the read path and also ensure that short - circuit current and malfunction are avoided at lower control clock frequencies, and the overall operation of the circuit elements is improved. This then enables higher performance from the SRAM memory and the electronic device that includes the SRAM memory. Higher user satisfaction results from the SRAM memory and the electronic device.

[0017] (Electronic device) FIG. 3 is a block diagram showing an electronic device 300 according to some embodiments. The electronic device 300 includes a processor 302 and a memory 304. The processor 302 is a functional block that performs computational operations, memory access operations, and other operations within the electronic device 300. The processor 302 includes a processing subsystem 306 and a cache memory 308. The processing subsystem 306 includes one or more functional blocks such as a central processing unit (CPU) core, a graphics processing unit (GPU) core, an embedded processor, and / or an application - specific integrated circuit (ASIC) that perform general - purpose computational operations, control operations, and / or other operations.

[0018] The cache memory 308 is a functional block that performs operations for storing a copy of data (e.g., operands for computational operations, results from operations, instructions, configuration values, and / or other information) for access (e.g., read, write, etc.) by the processing subsystem 306 within the electronic device 300 and possibly by other entities. The cache memory 308 is a faster memory in which copies of data are stored to enable the data to be accessed more rapidly than accessing the data in the memory 304. In some embodiments, the cache memory 308 is located closer to the processing circuitry within the processing subsystem 306 that accesses the copies of data within the cache memory 308 and is connected to the processing circuitry via a high-speed interface, thereby enabling rapid access to the stored data. In some embodiments, the cache memory 308 includes a volatile memory circuit such as a static random access memory (SRAM) circuit used for storing data.

[0019] The memory 304 is a functional block that performs operations of the memory (e.g., main memory) within the electronic device 300. The memory 304 includes a volatile memory circuit for storing data (e.g., operands for computational operations, results from operations, instructions, configuration values, and / or other information) for use by a control circuit for manipulating access (e.g., read, write, etc.) of data within the memory circuit, together with the functional blocks within the electronic device 300. The memory circuit within the memory 304 includes a volatile memory circuit such as a fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM), a static random access memory (SRAM), and / or other types of memory circuits. In some embodiments, copies of data are retrieved from the memory 304 and stored in the cache memory 308 to enable more rapid access to the copies of data.

[0020] Electronic device 300 is shown as including a specific number and arrangement of elements (e.g., functional blocks and devices such as processor 302, memory 304, etc.). However, electronic device 300 is simplified for purposes of illustration. In some embodiments, different numbers or arrangements of elements are present in electronic device 300. For example, electronic device 300 may include a power subsystem, a human interface system, and the like. As another example, in some embodiments, electronic device 300 serves as a non-volatile storage device for data within electronic device 300, and includes a mass storage device such as a disk drive or a higher-capacity integrated circuit memory from which a copy of the data is retrieved for storage in memory 304 and / or cache memory 308. Generally, electronic device 300 includes sufficient elements to perform the operations described herein.

[0021] Electronic device 300 is shown as having only a single cache memory within processor 302, namely cache memory 308, but electronic device 300 may include more and / or differently arranged cache memories. For example, in some embodiments, electronic device 300 includes a hierarchy of cache memories having one or more cache memories within processor 302 and one or more cache memories external to processor 302, i.e., connected to processor 302 via one or more communication buses. In those embodiments, some or all of the cache memories include SRAM memory. Additionally, in some embodiments, circuits associated with performing operations within a cache memory such as a tag array and / or used to perform operations include SRAM memory.

[0022] The electronic device 300 may be, or may be included in, any electronic device that performs memory access and / or other operations. For example, the electronic device 300 may be, or may be included in, a desktop computer, a laptop computer, a wearable electronic device, a tablet computer, a smartphone, a server, an artificial intelligence device, a virtual or augmented reality device, a network appliance, a toy, an audio-visual device, a home appliance, a controller, a vehicle, etc., and / or combinations thereof.

[0023] (SRAM memory) In the described embodiments, an SRAM circuit is used to store data in a memory within the electronic device 300, such as the cache memory 308 and / or a tag array within the cache memory 308. FIG. 4 is a block diagram showing a memory 400 (or "SRAM memory") implemented using an SRAM circuit according to some embodiments. In some embodiments, some or all of the SRAM memory within the electronic device 300 is arranged similarly to that shown in FIG. 4, but this is not essential.

[0024] As can be appreciated in FIG. 4, memory 400 includes a memory array 402, which is a functional block that includes an array of SRAM cells (or “bit cells”) organized in rows and columns. A few example cells are shown in the upper left corner of memory array 402, and one of the cells is labeled as cell 404 (the rest are not shown and / or labeled in FIG. 4 for clarity). As can be appreciated in the enlarged view of cell 404 at the top of FIG. 4, cell 404 includes a set of transistors for storing bits of data and accessing the stored bits of data, as each cell within memory array 402 does. More specifically, cell 404 includes six transistors, four of which (referred to herein as “storage” transistors) are configured as a back-to-back inverter for storing bits of data in the cell, and two of which (referred to herein as “access” transistors) are configured to access the stored bits of data. One of the two access transistors within cell 404 is connected to bit line (BLT) 406, and the other access transistor is connected to bit line complement (BLC) 408, and BLT 406 and BLC 408 are signal lines used to access the data within cell 404, i.e., to read data from cell 404 and write data to cell 404. Due to the array of inversions of the back-to-back inverters within the cell and nodes to which the access transistors are connected, bit line 406 accesses the value of the data stored in cell 404, and bit line complement 408 accesses the complement / logical inversion of the value of the data stored in cell 404.

[0025] The gate connection of the access transistor within cell 404 is connected to word line 410, and a signal is driven on word line 410 to activate or deactivate the access transistor, and thus to selectively provide access to the memory transistor. In some embodiments, a group of N cells (where N is 16, 32, or another number) within a row in memory array 402 are connected to the same word line from among word lines 412 and are activated (or deactivated) as a group. Thus, the word lines from word lines 412 can be used to access data within the group of cells as a group. In addition, a group of M cells (where M is 16, 32, or another number) within a column are connected to the same bit line and bit line complement from among bit lines 414, and the word lines 412 can be used to selectively access data within a single cell within the column at one time via the corresponding bit line and bit line complement.

[0026] The multiplexer 416 is a functional block that includes several multiplexer circuit elements, which include a read multiplexer and a write multiplexer. For example, in some embodiments, the multiplexer 416 includes circuit elements that perform a multiplexing - demultiplexing function for the read multiplexer and the write multiplexer according to the direction of data flow. As a result, the circuit elements function as a multiplexer as data flows from the cell 404 for reading, and as a demultiplexer as data flows to the cell 404 for writing. The read multiplexer and the write multiplexer are used to select a column from among the columns in the memory array 402 from which data is read or to which data is written, respectively. In some embodiments, the memory array 402 includes K columns of cells (e.g., 32, 64, or another number), but only K / 2 columns or another fractional number of columns are accessed at a time. In other words, from the K columns, only a portion (half, quarter, etc.) of the columns is read or written for each read or write operation. Therefore, the multiplexers within the multiplexer 416 are used to select the columns that will be read or written.

[0027] The sense amplifier and write driver 418 is a functional block that includes sense amplifier and write driver circuit elements. The sense amplifier is a differential sense amplifier used during a read operation to detect data values (e.g., 0s or 1s) within the cells in the memory array 402 based on the bits and bit - complement values passed through the read multiplexer within the multiplexer 416. Thus, there is a separate sense amplifier for each read multiplexer within the multiplexer 416. The write driver is used during a write operation to drive data values onto the bit lines and bit - complement lines from among the bit lines 414, and thus, via the word lines selected from among the word lines 412, to the corresponding cells within the column of the memory array 402 selected through the write multiplexer within the multiplexer 416.

[0028] The input / output element 420 is a functional block including a circuit element that receives data from an entity external to the memory 400 and supplies data to an entity external to the memory 400. The input / output element 420 receives write data 442 to be written into the memory array 402 from an entity, and includes receiver circuit elements such as buffers, repeaters, latches, etc. used to pass / transfer the received data to the write driver within the sense amplifier and write driver 418. The input / output element 420 receives data read from the memory array 402 from the sense amplifier within the sense amplifier and write driver 418, and includes driver circuit elements such as buffers, repeaters, latches, etc. used to transmit the received read data 442 to an entity.

[0029] The row decoder 422 and column decoder (CDEC) 424 are functional blocks that perform operations associated with selecting data in cells within the memory array 402 to be accessed. The row decoder 422 receives a row address 428 from an external entity (e.g., an external entity accessing data), processes / decodes the row address 428 to determine a specific row of cells to be accessed from among the rows of cells within the memory array 402, and asserts a signal onto the corresponding word line from among the word lines 412 to activate the cells within the specific row. The column decoder 424 receives a column address 430 from an external entity, processes / decodes the column address 430 to determine a specific column to be accessed from among the columns of cells within the memory array 402, and asserts a signal onto the column selection from among the column selections (CSEL) 432 to allow the multiplexer within the multiplexer 416 to access the specific column. For example, when the access is a read, the column selection causes the read multiplexer to pass data (i.e., a bit and bit complement pair) from the specific column to the corresponding sense amplifier.

[0030] Control 426 is a functional block that performs operations to control when access to data in memory array 402 occurs. Control 426 receives, as inputs, various signals including read enable (RDEN) 434, write enable (WREN) 436, and clock (CLK) 438 from external entities, and generates control signals within control signal (CTRL) 440 based at least in part thereon. For example, in some embodiments, Control 426 generates signals to synchronize / trigger operations within row decoder 422, column decoder 424, and other functional blocks in memory 400 as part of control signal 440. As another example, in some embodiments, Control 426 generates signals to precharge or set sense amplifiers and / or write drivers and to enable sense amplifiers and / or write drivers as part of control signal 440.

[0031] In some embodiments, clock 438 can operate at several different frequencies that affect the timing of operations controlled by clock 438. For example, in a lower power operating mode, clock 438 can operate at a specified lower frequency (e.g., 400 megahertz, 1 gigahertz, or another frequency), and in a higher power operating mode, clock 438 can operate at a specified higher frequency (e.g., 1.6 gigahertz, 2 gigahertz, or another frequency). In the described embodiments, a specific short - circuit path through sense amplifier 504 (see FIG. 5) is avoided at lower frequencies of clock 438 by generating a precharge signal to precharge the circuitry within sense amplifier 504 using specified control signals, as will be described in more detail below.

[0032] Memory 400 is shown as including a specific number and arrangement of functional blocks and elements, but is simplified for illustration purposes. In some embodiments, memory 400 includes different and / or differently arranged functional blocks and / or elements. For example, in some embodiments, memory 400 includes a precharge functional block that precharges bit line 414 before a read operation is performed. Generally, in the described embodiments, memory 400 includes sufficient functional blocks and elements to perform the operations described herein.

[0033] FIG. 5 is a block diagram showing control signals for memory 400 according to some embodiments. With respect to FIG. 5, some of the numbered functional blocks of 400, namely memory array 402, row decoder 422, and column decoder 424, have been described above in the description of FIG. 4. However, FIG. 5 includes some functional blocks and / or circuit elements not described in the description of FIG. 4. Those functional blocks and circuit elements include read multiplexer 500, write multiplexer 502, sense amplifier (AMP) 504, write driver (DRV) 506, and latch 508. In addition, various control signals generally described above as part of word line 412, column select 432, or control signal 440 are individually illustrated in FIG. 5 and described in further detail below.

[0034] For clarity, in the example shown in FIG. 5, only two cells 404 exist in each of two rows of cells 404 and two columns of cells 404. However, in some embodiments, the memory array 402 includes more (typically, far more) rows of cells 404, where the rows include more cells 404 as shown using ellipses in FIG. 5. Additionally, in some embodiments, the memory array 402 includes more (typically, far more) columns of cells 404 as shown using ellipses in FIG. 5. In those embodiments, the other functional blocks and circuit elements within FIG. 5 increase in number accordingly. For example, the memory can be capable of reading 32, 64, or another number of bits at a time from among 32, 64, or another number of columns of cells 404 having 128, 256, or another number of rows, and thus there are 32, 64, or another number of read multiplexers 500, sense amplifiers 504, latches 508, etc. Generally, in the described embodiments, the memory 400 includes a sufficient number of functional blocks and circuit elements to perform the operations described herein.

[0035] Word lines 510 - 512 are individual word lines from among the word lines 412 connected to access transistors within rows of cells 404 in the memory array 402. When asserted (e.g., set to a high logic value), each of the word lines 510 - 512 enables access to the cells 404 within the corresponding rows of cells 404 in the memory array 402. More specifically, when enabled during a read operation, the word lines 510 - 512 connected to the gate connections of the access transistors for the cells 404 activate the access transistors, such that the data values stored in the storage transistors within the cells 404 within the corresponding rows are made available to the bit lines to which each cell 404 is connected (by values logically opposite to the bit lines and bit line complements). On the other hand, when enabled during a write operation, the word lines 510 - 512 activate the access transistors, such that values on the bit lines can be driven through the access transistors and storage transistors for storage in the corresponding cells 404.

[0036] The read multiplexer 500 is a functional block that receives signals from a pair of bit lines, shown as bit line (BLT) and bit line complement (BLC), connected to access transistors for two individual columns of cells 404 within the memory array 402 on a plurality of individual inputs, and passes a value to an output connected to the sense amplifier 504 from a selected single pair of bit lines. During a read operation, the column decoder 424 transmits a signal to the read multiplexer 500 to cause it to pass a bit line value from a desired one of the two columns of cells 404 to the sense amplifier 504 on the read column select (RD COL SEL) 514 (e.g., a logically high value or a logically low value). In some embodiments, the read multiplexer 500 includes a single transistor or transmission gate on each bit line that is activated or deactivated by the read column select 514 to pass or block the value on the corresponding bit line.

[0037] The write multiplexer 502, which is functionally and actually a demultiplexer, receives signals from a pair of signal lines connected to the write driver 506 on an input pair, and passes the received values to a pair of bit lines connected to access transistors for two columns of cells 404 in the memory array 402 via a set of outputs connected to the bit lines for the selected columns of cells 404. During a write operation, the column decoder 424 transmits a signal to the write multiplexer 502 to transfer the value and its complement received from the write driver 506 on the bit lines for a desired one of the columns of cells 404 on the write column select (WR COL SEL) 516 (e.g., a logically high value or a logically low value). For example, in some embodiments, the write multiplexer 502 includes a single transistor or transmission gate on each bit line that is activated or deactivated by the write column select 516 to pass or block the value received from the write driver 506 on the corresponding bit line.

[0038] The sense amplifier 504 receives values from the read multiplexer 500 from the bit lines and their complements, and based on the values, drives an output signal having a value corresponding to the latch 508. For the read operation, during the precharge phase, control 426 transmits a signal to precharge its output nodes (i.e., the SAT node and the SAC node of the sense amplifier 504 as described below) to the sense amplifier 504 on the line of the sense amplifier precharge (SAPC) 518. Also, during the evaluation phase, control 426 transmits a signal to the sense amplifier to evaluate the values on the output nodes (i.e., the SAT node and the SAC node) and drive the corresponding values (i.e., the values and their complements) on the output nodes on the line of the sense amplifier enable complement (SAENX) 520. The value driven on the SAT node of the sense amplifier 504 is received as an input by the latch 508. Note that a short circuit path may occur through the sense amplifier 504 if the signals on the line of the sense amplifier precharge 518 and the line of the sense amplifier enable complement 520 are logically low simultaneously (e.g., approximately VDD). In the described embodiment, the signals on the line of the sense amplifier precharge 518 and the line of the sense amplifier enable complement 520 are controlled to avoid their being logically low simultaneously.

[0039] The write driver 506 receives write data 524, i.e., the data to be written from an external entity on the input to the cells 404 in the memory array 402, and is a functional block that drives the write data 524 and its complement to the write multiplexer 502. From the write multiplexer 502, the write data 524 and its complement are passed to the selected columns of the cells 404 in the memory array 402. During the write operation, control 426 transmits a signal to the write driver 506 to drive the write data 524 to the write multiplexer 502 on the line of the write driver enable complement (WDENX) 522.

[0040] Latch 508 is a functional block that receives a value from the output node of sense amplifier 504 (i.e., the SAT node) and stores the value. Also, latch 508 supplies the value as read data 526 to an external entity. During a read operation, control 426 transmits, on the line of sense amplifier enable complement 520, a signal that causes latch 508 to capture / store the data on the output node of sense amplifier 504 and supply the data to the external entity.

[0041] Although not shown in FIG. 5, in some embodiments, bit lines (BLT and BLC) are connected to a precharge circuit element that precharges the bit lines prior to a read operation. In those embodiments, a bit line precharge (BLPC) signal line is connected to each of the bit lines.

[0042] (Sense Amplifier and Latch) In the described embodiments, a read path, which is a set of circuits used to read data from SRAM cells (e.g., cells 404 in memory array 402) within a memory array, includes a sense amplifier and a latch. FIG. 6 is a block diagram showing sense amplifier 504 and latch 508 within read path 600 according to some embodiments.

[0043] For the example in FIG. 6, the read path 600 includes several improvements over the existing SRAM cell read path. First, the latch 508 has only two gate delays between the SAT output of the sense amplifier 504 and the output of the read data 526 of the latch 508, which has fewer gate delays than the existing design. Second, the sense amplifier precharge complement (SAPCX) signal through which the sense amplifier 504 is precharged is generated based on the sense amplifier precharge (SAPC) signal and the sense amplifier enable complement (SAENX) signal. Using the SAENX signal to generate the SAPCX signal helps avoid a short circuit path involving the precharge circuit 602 within the read path 600. Third, the read path 600 includes a load distribution circuit 608 connected to the SAC output of the sense amplifier 504. In view of the capacitive load of the three-state inverter in the latch 508 connected to the SAT output of the sense amplifier 504, the load distribution circuit 608 balances the capacitive load on the sense amplifier 504 and helps ensure that the sense amplifier 504 outputs signals having approximately the same rise time and fall time.

[0044] For the example in FIG. 6, the gate connections, source connections, and drain connections of various PMOS transistors (p-channel metal-oxide-semiconductor field-effect transistors) and NMOS transistors (n-channel metal-oxide-semiconductor field-effect transistors) are connected to their respective signals, or to the source or drain connections of other PMOS and NMOS transistors. For example, the input 3-state inverter within latch 508 has four transistors, two PMOS transistors, and two NMOS transistors. The first PMOS transistor has a source connection connected to VDD, a drain connection connected to the source connection of the second PMOS transistor, and a gate connection connected to the SAT node of sense amplifier 504. The second PMOS transistor has a source connection connected to the drain connection of the first PMOS transistor, a drain connection connected to intermediate node 614 within latch 508, and a gate connection connected to the SAENX signal from control 426. In other words, the first and second PMOS transistors of the input 3-state inverter within latch 508 are coupled between VDD and intermediate node 614. The first NMOS transistor has a source connection connected to the drain connection of the second N MOS transistor, a drain connection connected to intermediate node 614, and a gate connection connected to the SAEN signal (i.e., the complement of the SAENX signal). The second NMOS transistor has a source connection connected to VSS, a drain connection connected to the source connection of the first PMOS transistor, and a gate connection connected to the SAT node of sense amplifier 504. In other words, the first and second NMOS transistors of the input 3-state inverter within latch 508 are coupled between intermediate node 614 and VSS. For the sake of brevity, the reader is referred to FIG. 6 for an illustration of the remaining gate, source, and drain connections of the NMOS and PMOS transistors within read path 600.

[0045] For the example in FIG. 6, several different signals are connected to the gate connections of one or more transistors. Among them, the signals are the sense amplifier enable (SAEN) signal and its complement, the sense amplifier enable complement (SAENX) signal. The SAENX signal is generated by control 426. The SAEN signal is generated via an inverter (or another inversion logic gate) such as the example shown in the upper right of FIG. 6. Also, among them, the signal is the sense amplifier precharge (SAPC) signal generated by control 426. In addition, among them, the signals are the disable (DSBL) and disable complement (DSBLX) signals that are generated by control 426 or fixed by connecting the gate connections of the transistors illustrated for VDD and VSS respectively, etc.

[0046] As can be understood in FIG. 6, the sense amplifier 504 includes a precharge (PRECHG) circuit 602 and an evaluation (EVAL) circuit 604. The precharge circuit 602 precharges the SAT node and the SAC node of the sense amplifier 504 to approximately VDD during the precharge phase for the sense amplifier 504. During the evaluation phase following the precharge phase, control 426 asserts a sense amplifier enable (SAEN) signal that activates a pull-down transistor connected to the footer node 610 in the evaluation circuit 604. The pull-down transistor, when activated, enables the sense amplifier 504 to be evaluated as an amplifier based on the values of the bit line (BLT) and bit line complement (BLC) signal lines provided from the read multiplexer 500 to the sense amplifier 504, and thus reduces the voltage from one of the SAT node and the SAC node.

[0047] The precharge circuit 602 is controlled by the SAPCX signal, which is generated by the precharge (PRECHG) control circuit 606 based on the SAPC signal and the SAENX signal. During operation, SAPCX has a logically high value (e.g., approximately VDD), and when either the SAPC signal or the SAENX signal has a logically low value (e.g., approximately VSS), all of the PMOS gates in the precharge circuit 602 are disabled (thereby disabling the precharge circuit 602). This occurs whenever the SAENX signal is set to a logically high value, disabling the evaluation circuit via its complement (i.e., the SAEN signal), and SAPC is set to a logically high value such that it enables the precharge circuit 602 during the precharge phase. When the SAPC signal is set to a logically high value during the precharge phase and the SAEN signal is set to a logically low value outside of the evaluation phase, the SAPCX signal is driven low, activating the PMOS gates in the precharge circuit 602, thereby activating the precharge circuit 602. As described above, when activated, the precharge circuit 602 precharges the SAT node and the SAC node to approximately VDD. By operating in this manner, the pull-down transistor connected to the footer node 610 in the evaluation circuit 604 and controlled by SAEN is disabled before the precharge begins. This can help avoid the formation of a short-circuit path through the precharge circuit 602 and the evaluation circuit 604. Additionally, by operating in this manner, a functional race is avoided that would otherwise involve the precharge circuit 602 competing with the storage element in the latch 508 during a potential overlap between SAPCX and SAEN / SAENX.

[0048] In some embodiments, the precharge control circuit 606 includes a NAND logic gate as shown in FIG. 6. However, this is not essential. Generally, in the described embodiments, any logic gate and / or circuit element that generates SAPCX based on SAPC and SAENX as described above may be used.

[0049] Latch 508 includes an input three-state inverter connected between the SAT node of sense amplifier 504 and intermediate node 614 of latch 508. The input three-state inverter is enabled and thus passes an inverted value to intermediate node 614 of latch 508 based on the value of the SAEN / SAENX signal. When the SAEN signal is set to a logically high value (thus, sense amplifier 504 is in the evaluation phase), the SAENX signal is set to a logically low value, the input three-state inverter is active, and passes an inverted value from the SAT node of sense amplifier 504 to intermediate node 614 of latch 508. In contrast, when the SAEN signal is set to a logically low value, the SAENX signal is set to a logically high value, the input three-state inverter is disabled, and does not pass a value from the SAT node of sense amplifier 504 to intermediate node 614 of latch 508. By operating as described, the input three-state inverter blocks the value propagating from the SAT node of sense amplifier 504 to intermediate node 614 of latch 508, except during the evaluation phase of sense amplifier 504. By using the SAEN signal and SAENX signal to control the input three-state inverter, the described embodiments avoid short-circuit current through the three-state inverter that occurs when the SAT node and / or SAC node discharges slowly relative to the lower operating frequency of the control clock. If circuit elements such as inverters without those controls were used instead of the input three-state inverter, those short circuits would occur and cause functional problems within the latch.

[0050] Latch 508 also includes a memory circuit element having (1) a latch inverter connected between the intermediate node 614 and the latch node 612, and (2) a latch three-state inverter connected between the latch node 612 and the intermediate node 614. In other words, the latch inverter and the latch three-state inverter of the memory circuit element form a back-to-back inverter pair used to store data values in the latch 508 (more generally, in the read path 600). During operation, SAEN is set to a logically high value and SAENX is set to a logically low value, so that the evaluation circuit 604 in the sense amplifier 504 is enabled, and when the input three-state inverter is propagating a value from the SAT node to the intermediate node 614, the latch three-state inverter is disabled. This prevents the latch three-state inverter from competing with the input three-state inverter with respect to the value on the intermediate node 614. In contrast, when SAEN is set to a logically low value and SAENX is set to a logically high value, so that the input three-state inverter is disabled and not driving the value on the intermediate node 614, the latch three-state inverter is enabled and, in combination with the latch inverter, holds the value on the intermediate node 614. Further, the latch 508 includes an output inverter connected between the intermediate node 614 and the output of the read data 526. The output inverter drives a value from the intermediate node 614 to the output of the read data 526 and thus to an external entity. Note that in some embodiments, the output inverter may be replaced by another type of output driver, such as a three-state inverter having an output enable and its complement, a NAND gate, etc., that serve as controls.

[0051] In addition, the read path 600 includes a load balancing circuit 608. The load balancing circuit 608 includes a load balancing three-state inverter having four transistors - two PMOS transistors and two NMOS transistors. The gate connections of the two transistors of the three-state inverter, shown as external PMOS and NMOS transistors, are connected to the SAC node of the sense amplifier 504 so as to provide a capacitive load to the SAC node that approximately balances the capacitive load to the SAT node of the input three-state inverter of the latch 508. In the example of FIG. 6, the gate connections of the other two transistors of the three-state inverter, shown as internal PMOS and NMOS transistors, are connected to the disable and disable complementary signals, which are constant signals that keep the internal PMOS and NMOS transistors in an off state (i.e., disabled, non-conducting, etc.). However, in some embodiments, the SAEN and SAENX can replace the disable and disable complementary signals to assist the load balancing circuit 608 in providing a similar capacitive load to the input three-state inverter within the latch 508.

[0052] (Sharing of Latches within the Read Path for a Multi-Bank Memory) In some embodiments, at least some of the circuit elements of the latch are shared within the read path for SRAM cells in two or more banks of the memory. FIG. 7 is a block diagram showing a shared latch within the read path for SRAM cells, according to some embodiments. Although specific functional blocks and circuit elements within a specific arrangement are shown in FIG. 7, it should be noted that FIG. 7 is simplified for clarity. In some embodiments, each bank includes a memory array as well as other such functional blocks and circuit elements, such as those shown in FIGS. 4 - 6. Generally, in the embodiments described, the latch may be shared among multiple read paths, or otherwise be similar to the latch 508 in arrangement and function.

[0053] In FIG. 7, separate portions of the read paths in each of banks 700 and 702 include sense amplifiers and corresponding load distribution circuits. Latches in the read paths for banks 700 and 702 are split such that each bank includes its own separate latch input 3-state inverter. The separate latch input 3-state inverters within each bank are connected to the enabling signals for that bank, i.e., SAEN0 / SAENX0 for bank 700 and SAEN1 / SAENX1 for bank 702. The memory circuit elements for the latches, i.e., the latch inverters and the latch 3-state inverters, as well as the output inverters for the latches, are shared between bank 700 and bank 702. Those portions of the latches are shown as shared latch 704 in FIG. 7. Those portions of the latches are selectively used by banks 700 and 702 and can store and output data values for one of banks 700 and 702 at a time.

[0054] The control signals for the read paths in each of banks 700 and 702, as well as the control signals for the shared portions of the latches within shared latch 704, are shown over those elements in FIG. 7. As can be understood from FIG. 7, the per-bank control signals including sense amplifier precharge (SAPCX0 / 1) and sense amplifier enable (SAEN0 / 1) are generated in the same manner as how those signals are generated in FIGS. 4-6. The control signals for the shared portions of the latches are generated based on the control signals for the banks. More specifically, the SLEN signal for the shared portions of the latches is generated as a logical (e.g., NAND) combination of the SAENX0 / 1 signals, and the SLENX signal for the shared portions of the latches is generated as a logical (e.g., NOR) combination of the SAEN0 / 1 signals. In some embodiments, the respective sense amplifier enable (SAEN0 / 1) and sense amplifier enable complement (SAENX0 / 1) signals per bank are replaced with disable (D) and disable complement (DX) signals.

[0055] (Process of Reading Data from Cells in Memory Array) In the described embodiments, data is read from SRAM cells in a memory array (e.g., memory array 402) using various circuit elements on a read path (e.g., read path 600). FIG. 8 is a flowchart showing a process for performing a read of an SRAM memory according to some embodiments. The operations shown in FIG. 8 are presented as an overall example of operations performed by some embodiments. Operations performed by other embodiments include different operations, operations performed in a different order, and / or operations performed by different entities or functional blocks.

[0056] Regarding the operations in FIG. 8, it is assumed that data has been read from a cell (e.g., cell 404) within a column of cells in the memory array. In other words, the bit lines and bit line complements connected to the cell have been precharged (e.g., to approximately VDD), and thus, the sense amplifier is no longer in the precharge phase, and the row decoder (e.g., row decoder 422) has asserted the desired word line to enable the access transistors of the cell, thereby enabling the storage transistor within the cell to drive the value of the bit of data stored in the cell, as well as its logical complement for each of the corresponding bit line and bit line complement. In addition, the column decoder (e.g., column decoder 424) enables the corresponding read multiplexer (e.g., read multiplexer 500) to pass values from the bit lines and bit line complements to the sense amplifier (e.g., sense amplifier 504).

[0057] Regarding the operations in FIG. 8, only a single cell of the memory array is read. However, in some embodiments, multiple cells (e.g., 32, 64, or another number) are read simultaneously and in parallel via separate read paths during a given read operation. The operation of reading each individual cell is similar to the operation described with respect to FIG. 8.

[0058] When a precharge circuit (e.g., precharge circuit 602) precharges the SAT node and the SAC node of the sense amplifier (step 802), the operation in FIG. 8 starts. For this operation, the precharge control circuit (e.g., precharge control circuit 606) logically drives the SAPCX signal to a low level so that the PMOS transistor in the precharge circuit can precharge the SAT node and the SAC node in the sense amplifier based on the values of the SAPC signal and the SAENX signal.

[0059] Next, the sense amplifier receives the bit line and the bit line complement values on the SAT node and the SAC node from the read multiplexer (step 802) and drives the signals on the SAT node and the SAC node based on the values of the bit line and the bit line complement (S804). During this operation, based on the difference in the voltages of the SAT node and the SAC node caused by the bit line and / or the bit line complement value (i.e., voltage), the sense amplifier drives / outputs the signals on the SAT node and the SAC node, that is, accordingly, senses the difference and outputs a value on the SAT node and the SAC node. The sense amplifier is enabled by the SAEN signal which is the logical complement of the SAENX signal. As a result, the SAPCX signal transitions to a high logic level to disable precharge when the sense amplifier is enabled, thus avoiding a potential short - circuit path in the sense amplifier.

[0060] The latch (e.g., latch 508) connected to the SAT node of the sense amplifier stores the value from the SAT node (step 806). For this operation, the input 3 state inverter of the latch is enabled by the SAEN signal, thus the input 3 state inverter drives the inverted version of the value onto the intermediate node of the latch (e.g., intermediate node 614) from the SAT node. From the intermediate node of the latch, the value is passed to the output as read data (via the output driver) (step 808). The latch 3 state inverter within the storage circuit element of the latch is disabled and the sense amplifier is enabled, i.e., it is enabled as SAEN transitions to a low logic level while SAEN is at a high logic level, thereby enabling the latch to store the value from the SAT node.

[0061] In some embodiments, at least one electronic device (e.g., electronic device 300, etc.) performs some or all of the operations described herein using code and / or data stored in a non - transitory computer - readable storage medium. More specifically, at least one electronic device reads the code and / or data from the computer - readable storage medium, executes the code when performing the described operations, and / or uses the data. The computer - readable storage medium can be any device, medium, or combination thereof that stores the code and / or data used by the electronic device. For example, the computer - readable storage medium can include, but is not limited to, volatile and / or non - volatile memory (e.g., flash memory, random access memory (e.g., eDRAM, RAM, SRAM, DRAM, DDR4 SDRAM, etc.), non - volatile RAM (e.g., phase - change memory, ferroelectric random access memory, spin - transfer torque random access memory, magnetic - resistance random access memory, etc.), read - only memory (ROM), and / or magnetic or optical storage media (e.g., disk drive, magnetic tape, CD, DVD, etc.)).

[0062] In some embodiments, one or more hardware modules execute the operations described herein. For example, the hardware modules may include, but are not limited to, one or more processors / cores / central processing units (CPUs), application specific integrated circuit (ASIC) chips, neural network processors or accelerators, field programmable gate arrays (FPGAs), compression and / or encoding subsystems, computing units, embedded processors, graphics processors (GPUs) / graphics cores, accelerated processing units (APUs), functional blocks, controllers, accelerators, and / or other programmable logic circuits. When the circuits (e.g., integrated circuit elements, discrete circuit elements, etc.) within such hardware modules are activated, the circuits execute some or all of the operations. In some embodiments, the hardware modules include general-purpose circuits such as execution pipelines, computing units, or processing units that execute operations when executing instructions (program code, firmware, etc.). In some embodiments, the hardware modules include application-specific circuits or dedicated circuits configured to execute the operations, and in some cases, circuits that execute some or all of the operations without executing instructions.

[0063] In some embodiments, the data structure represents some or all of the functional blocks, and the circuit elements described herein (e.g., electronic device 300 or portions thereof) can be read by an electronic device and used directly or indirectly to manufacture hardware including the functional blocks and circuit elements, and are stored in a non-transitory computer-readable storage medium including a database or other data structure. For example, the data structure can be an operational-level description of hardware functions or a register-transfer level (RTL) description in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to generate a netlist including a list of gate / circuit elements representing the functions of the hardware including the structures and mechanisms described above from a synthesis library. Next, the netlist may be arranged or routed to generate a dataset describing the geometric shapes to be applied to the mask. Then, the mask can be used in various semiconductor manufacturing steps to manufacture one or more semiconductor circuits (e.g., integrated circuits) corresponding to the structures and mechanisms described above. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, or, optionally, Graphic Data System (GDS) II data.

[0064] As used herein, variables or unspecified values (i.e., general descriptions without specific examples of values) are represented by letters such as N, M, and X. Although the same letters may be used in different places as used herein, the variables and unspecified values in each case are not necessarily the same, i.e., there may be different variable quantities and values intended for some or all of the general variables and unspecified values. In other words, the N and any other letters used to represent variables and unspecified values in this description are not necessarily related to each other.

[0065] The expression "etc." or "and the like", as used herein, is intended to indicate the case of "and / or", i.e., corresponding to "at least one" of the elements in the list associated with "etc.". For example, in the sentence "The electronic device performs a first operation, a second operation, etc.", the electronic device performs at least one of the first operation, the second operation, and other operations. In addition, the elements in the list associated with "etc." are merely examples from a series of examples, and at least some of the examples may not appear in some embodiments.

[0066] The foregoing description of the embodiments has been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the embodiments to the disclosed form. Accordingly, many modifications and variations will be apparent to those skilled in the art. Furthermore, the foregoing disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.

Claims

1. A read path for reading data from a memory in an electronic device, a sense amplifier including a sense amplifier data (SAT) node and a sense amplifier data complement (SAC) node, a latch, and the latch includes an input three-state inverter, an output driver, and the input three-state inverter includes a first PMOS transistor and a second PMOS transistor coupled between VDD and an intermediate node, a first NMOS transistor and a second NMOS transistor coupled between VSS and the intermediate node, each gate connection of the first PMOS transistor and the first NMOS transistor is coupled to the SAT node, the source connection of the first PMOS transistor is coupled to VDD, the source connection of the first NMOS transistor is coupled to VSS, the output driver has an output driver input coupled to the intermediate node and an output driver output coupled to a data output node, a read path.

2. Further comprising a load distribution circuit including a load distribution three-state inverter, the load distribution three-state inverter includes a third PMOS transistor and a fourth PMOS transistor, a third NMOS transistor and a fourth NMOS transistor coupled between VDD and VSS, each gate connection of the third PMOS transistor and the third NMOS transistor is coupled to the SAC node, the source connection of the third PMOS transistor is coupled to VDD, the source connection of the third NMOS transistor is coupled to VSS, each gate connection of the fourth PMOS transistor and the fourth NMOS transistor is coupled to a disabling input for maintaining the fourth PMOS transistor and the fourth NMOS transistor in an off state, the read path of Claim 1.

3. a precharge circuit in the sense amplifier, the precharge circuit being coupled to the SAT node and the SAC node and configured to precharge the SAT node and the SAC node, a precharge circuit, a precharge control circuit, and the precharge control circuit includes a sense amplifier precharge (SAPC) input, Sense amplifier enable complement (SAENX) input, and a sense amplifier precharge complement (SAPCX) output coupled to the precharge circuit and configured to control when the precharge circuit precharges the SAT node and the SAC node, wherein the precharge control circuit drives a signal on the SAPCX output based on values of the SAPC input and the SAENX input, including the SAPCX output, The read path of claim 1.

4. The precharge control circuit includes a NAND logic gate having a first input coupled to the SAPC input, a second input coupled to the SAENX input, and a first output coupled to the SAPCX output, a third PMOS transistor coupled between VDD and the SAC node, a fourth PMOS transistor coupled between VDD and the SAT node, a fifth PMOS transistor coupled between the SAT node and the SAC node and having gate connections for the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor coupled to the SAPCX output, including The read path of claim 3.

5. The latch includes a gate connection of the second PMOS transistor coupled to a sense amplifier enable complement (SAENX) input, and a gate connection of the second NMOS transistor coupled to a sense amplifier enable (SAEN) input, and each drain connection of the second PMOS transistor and the second NMOS transistor is coupled to the intermediate node, The read path of claim 1.

6. The latch further includes a memory circuit element, The memory circuit element includes a latch inverter having a latch inverter input coupled to the intermediate node and a latch inverter output coupled to a latch node, a latch three-state inverter including a third PMOS transistor and a fourth PMOS transistor coupled between VDD and the intermediate node, and a third NMOS transistor and a fourth NMOS transistor coupled between VSS and the intermediate node, The latch three-state inverter includes ​ The gate connections of each of the third PMOS transistor and the third NMOS transistor coupled to the latch node, wherein the source connection of the third PMOS transistor is coupled to VDD, the source connection of the third NMOS transistor is coupled to VSS, the gate connections of each of the third PMOS transistor and the third NMOS transistor, and The gate connection of the fourth PMOS transistor coupled to the SAEN input, The gate connection of the fourth NMOS transistor coupled to the SAENX input, and The drain connections of the fourth PMOS transistor and the fourth NMOS transistor are coupled to the intermediate node. The read path of claim 5.

7. The sense amplifier A bit input coupled to the SAT node, A bit complement input coupled to the SAC node, An evaluation circuit coupled to the SAT node and the SAC node and configured to output a SAT signal on the SAT node and a SAC signal on the SAC node based on the values of the bit input and the bit complement input. The read path of claim 1.

8. Further comprising a plurality of bit outputs and bit complement outputs of a plurality of synchronous random access memory (SRAM) cells, The plurality of bit outputs and bit complement outputs are coupled to the bit input and the bit complement input, respectively, for the sense amplifier via a multiplexer. The read path of claim 7.

9. The evaluation circuit The third PMOS transistor and the third NMOS transistor coupled between VDD and the footer node having a SAC node coupled to a first intermediate node between the third PMOS transistor and the third NMOS transistor, and a SAT node coupled to the gate connections for the third PMOS transistor and the third NMOS transistor, The fourth PMOS transistor and the fourth NMOS transistor coupled between VDD and the footer node having a SAT node coupled to a second intermediate node between the fourth PMOS transistor and the fourth NMOS transistor, and a SAC node coupled to the gate connections for the fourth PMOS transistor and the fourth NMOS transistor, A fifth NMOS transistor having a gate connection for the sense amplifier enable (SAEN) input, the fifth NMOS transistor coupled between the footer node and the VSS, The read path of claim 7.

10. A processing subsystem, A memory coupled to the processing subsystem, comprising: The memory includes at least one read path for reading data from the memory, The at least one read path is A sense amplifier including a sense amplifier data (SAT) node and a sense amplifier data complement (SAC) node, A latch, The latch is An input three-state inverter, An output driver, The input three-state inverter is A first PMOS transistor and a second PMOS transistor coupled between VDD and an intermediate node, A first NMOS transistor and a second NMOS transistor coupled between VSS and the intermediate node, The gate connections of each of the first PMOS transistor and the first NMOS transistor are coupled to the SAT node, The source connection of the first PMOS transistor is coupled to VDD, The source connection of the first NMOS transistor is coupled to VSS, The output driver has an output driver input coupled to the intermediate node and an output driver output coupled to a data output node. An electronic device.

11. The at least one read path further comprises a load sharing circuit comprising a load sharing three-state inverter, The load sharing three-state inverter is A third PMOS transistor and a fourth PMOS transistor, A third NMOS transistor and a fourth NMOS transistor coupled between VDD and VSS, The gate connections of each of the third PMOS transistor and the third NMOS transistor are coupled to the SAC node, The source connection of the third PMOS transistor is coupled to VDD, The source connection of the third NMOS transistor is coupled to VSS, The gate connections of each of the fourth PMOS transistor and the fourth NMOS transistor are coupled to a disabling input that maintains the fourth PMOS transistor and the fourth NMOS transistor in an off state. The electronic device of claim 10.

12. The at least one read path A precharge circuit within the sense amplifier, the precharge circuit being coupled to the SAT node and the SAC node and configured to precharge the SAT node and the SAC node; a precharge circuit; A precharge control circuit, further comprising: The precharge control circuit A sense amplifier precharge (SAPC) input; A sense amplifier enable complement (SAENX) input; A sense amplifier precharge complement (SAPC X) output coupled to the precharge circuit and configured to control when the precharge circuit precharges the SAT node and the SAC node, the precharge control circuit driving a signal on the SAPC X output based on values of the SAPC input and the SAENX input; an SAPC X output. The electronic device of claim 10.

13. The precharge control circuit A NAND logic gate having a first input coupled to the SAPC input, a second input coupled to the SAENX input, and a first output coupled to the SAPC X output; A third PMOS transistor coupled between VDD and the SAC node; A fourth PMOS transistor coupled between VDD and the SAT node; A fifth PMOS transistor coupled between the SAT node and the SAC node and having gate connections for the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor coupled to the SAPC X output. The electronic device of claim 12.

14. The latch The gate connection of the second PMOS transistor coupled to the sense amplifier enable complement (SAENX) input; The gate connection of the second NMOS transistor coupled to the sense amplifier enable (SAEN) input, wherein the drain connections of each of the second PMOS transistor and the second NMOS transistor are coupled to the intermediate node, the gate connection of the second NMOS transistor, and A third PMOS transistor coupled between VDD and the SAC node, A fourth PMOS transistor coupled between VDD and the SAC node, A fifth PMOS transistor coupled between the SAT node and the SAC node, having gate connections for the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor coupled to the SAPCX output, including The electronic device of claim 10.

15. The latch further includes a memory circuit element, The memory circuit element is A latch inverter having a latch inverter input coupled to the intermediate node and a latch inverter output coupled to the latch node, A third PMOS transistor and a fourth PMOS transistor coupled between VDD and the intermediate node, and a latch three-state inverter including a third NMOS transistor and a fourth NMOS transistor coupled between VSS and the intermediate node, The latch three-state inverter is The gate connections of each of the third PMOS transistor and the third NMOS transistor coupled to the latch node, wherein the source connection of the third PMOS transistor is coupled to VDD and the source connection of the third NMOS transistor is coupled to VSS, the gate connections of each of the third PMOS transistor and the third NMOS transistor, and The gate connection of the fourth PMOS transistor coupled to the SAEN input, The gate connection of the fourth NMOS transistor coupled to the SAENX input, including The drain connections of the fourth PMOS transistor and the fourth NMOS transistor are coupled to the intermediate node. The electronic device of claim 14.

16. The sense amplifier is A bit input coupled to the SAT node, A bit complement input coupled to the SAC node, An evaluation circuit coupled to the SAT node and the SAC node and configured to output a SAT signal on the SAT node and a SAC signal on the SAC node based on values of the bit input and the bit complement input. The electronic device of claim 10.

17. The memory includes a plurality of bit outputs and bit complement outputs of a plurality of synchronous random access memory (SRAM) cells. The plurality of bit outputs and bit complement outputs are each coupled to the bit input and the bit complement input for the sense amplifier via a multiplexer. The electronic device of claim 16.

18. The evaluation circuit includes: A SAC node coupled to a first intermediate node between a third PMOS transistor and a third NMOS transistor, and a SAT node coupled to a gate connection for the third PMOS transistor and the third NMOS transistor, the third PMOS transistor and the third NMOS transistor coupled between VDD and a footer node. A SAT node coupled to a second intermediate node between a fourth PMOS transistor and a fourth NMOS transistor, and a SAC node coupled to a gate connection for the fourth PMOS transistor and the fourth NMOS transistor, the fourth PMOS transistor and the fourth NMOS transistor coupled between VDD and a footer node. A fifth NMOS transistor coupled between the footer node and VSS and having a gate connection for a fifth NMOS transistor coupled to a sense amplifier enable (SAEN) input. The electronic device of claim 16.

19. One or more first bank SRAM cells, a first bank sense amplifier coupled to the one or more first bank SRAM cells, and a first bank shared latch input 3-state inverter coupled to the sense amplifier (SAT) output of the first bank sense amplifier via a transistor having a source connection coupled to either VDD or VSS, wherein an evaluation circuit of the first bank sense amplifier and the first bank shared latch input 3-state inverter is controlled by a first bank sense amplifier enable (SAEN) signal and / or a first bank sense amplifier enable complement (SAENX) signal, the first bank of the memory. One or more second bank SRAM cells, a second bank sense amplifier coupled to the one or more second bank SRAM cells, and a second bank shared latch input 3-state inverter coupled to the SAT output of the second bank sense amplifier via a transistor having a source connection coupled to either VDD or VSS, wherein an evaluation circuit of the second bank sense amplifier and the second bank shared latch input 3-state inverter is controlled by a second bank SAEN signal and / or a second bank SAENX signal, the second bank of the memory. A shared latch including a shared latch storage element having a back-to-back pair of a shared latch inverter and a shared latch 3-state inverter, wherein a shared latch inverter input of the shared latch inverter is coupled to outputs of both the first bank shared latch input 3-state inverter and the second bank shared latch input 3-state inverter, and the shared latch 3-state inverter is controlled by a shared latch enable (SLEN) signal and a shared latch enable complement (SLENX) signal, and the SLEN signal is generated based on a logical combination of the first bank SAEN signal and the second bank SAEN signal, and the SLENX signal is generated based on a logical combination of the first bank SAENX signal and the second bank SAENX signal, the shared latch. Integrated circuit. Claim 20 A first bank precharge circuit in the first bank sense amplifier, the first bank precharge circuit being controlled by a first bank sense amplifier precharge complement (SAPC X) signal generated based on a logical combination of a first bank sense amplifier precharge (SAPC) signal and the first bank SAENX signal, the first bank precharge circuit; A second bank precharge circuit in the second bank sense amplifier, the second bank precharge circuit being controlled by a second bank SAPC X signal generated based on a logical combination of a second bank SAPC signal and the second bank SAENX signal, the second bank precharge circuit; and further comprising. The integrated circuit of claim 19.

21. A first bank load dispersion circuit, the first bank load dispersion circuit being coupled to a sense amplifier complement (SAC) output of the first bank sense amplifier via a transistor having a source connection coupled to either VDD or VSS, and configured to approximately balance a first capacitive load presented at the SAT output of the first bank sense amplifier by the first bank shared latch input 3-state inverter, the first bank load dispersion circuit; A second bank load dispersion circuit, the second bank load dispersion circuit being coupled to an SAC output of the second bank sense amplifier via a transistor having a source connection coupled to either VDD or VSS, and configured to approximately balance a second capacitive load presented at the SAT output of the second bank sense amplifier by the second bank shared latch input 3-state inverter, the second bank load dispersion circuit; and further comprising. Transistors of the first bank shared latch input 3-state inverter and the second bank shared latch input 3-state inverter coupled to corresponding signals among the first bank SAEN signal, the first bank SAENX signal, the second bank SAEN signal, and the second bank SAENS signal are coupled via a drain connection to either an intermediate node of the first bank shared latch input 3-state inverter or an intermediate node of the second bank shared latch input 3-state inverter. The integrated circuit of claim 19.

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