Non-volatile memory device, non-volatile memory element, and method for manufacturing the same

Abstract

The present invention provides a non-volatile storage element and a non-volatile storage device that use a ferroelectric material, can be embedded in advanced CMOS logic, and are excellent in low power consumption and high reliability, and especially in data rewriting endurance. The non-volatile storage element at least has a first conductive layer, a second conductive layer, and a ferroelectric layer that is constituted by a metal oxide and is located between the first and second conductive layers, and a buffer layer having oxygen ion conductivity is present between the ferroelectric layer and the first conductive layer and / or the second conductive layer. Further, the non-volatile storage element has an interfacial layer constituted by a single layer film or a multiple layer film between the first conductive layer and the ferroelectric layer, the interfacial layer as a whole has permittivity higher than that of a silicon oxide, and the interfacial layer is present between the first conductive layer and the buffer layer when the buffer layer is present between the first conductive layer and the ferroelectric layer. The non-volatile storage device is at least provided with a control circuit, and a memory cell array formed by two-dimensionally or three-dimensionally arranging ferroelectric storage elements having low power consumption. The ferroelectric layer, which can be scaled to 10 nm or less, is manufactured at a low temperature of 400˚C or less and is subjected to low-temperature thermal annealing at 400˚C or less after formation of the buffer layer to improve reliability.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory device, particularly a non-volatile ferroelectric memory device, a non-volatile ferroelectric memory element, and a method for manufacturing the same.

Background Art

[0002] Towards the realization of a smart society, with the explosive increase in information in the future and the accompanying exponential increase in the information processing capacity and memory capacity to handle such information, research and development of IoT / AI edge devices in the edge area with respect to the cloud have been activated. Under such circumstances, there is a demand for the realization of a non-volatile memory device with high speed, large capacity, low power consumption, and high reliability, particularly a non-volatile memory and a non-volatile working memory with low power consumption and high reliability.

[0003] In addition, with the progress of the miniaturization of transistors, the increase in power consumption due to the increase in leakage current in the standby state of existing volatile memories such as DRAM and SRAM has become a major problem. For this reason, research and development for replacing volatile memories with non-volatile memories capable of suppressing the leakage current of transistors in order to reduce the standby power of volatile memories have been activated.

[0004] Therefore, particularly in the case of a logic hybrid non-volatile memory, as a new non-volatile memory excellent in miniaturization based on a storage operation principle different from that of a flash memory using a conventional FG (Floating Gate) type or MONOS (Metal / Oxide / Nitride / Oxide / Silicon) type flash memory and a flash memory using a new material, ReRAM (Resistive Random Access Memory), PCRAM (Phase Change Random Access Memory), MRAM (Magnetic Random Access Memory), etc. are being studied worldwide.

[0005] In these new non-volatile memories, in principle, the standby current becomes zero and the standby power can be reduced to zero. However, the problem has been that the operating power for writing information is relatively large. On the other hand, FeRAM (Ferroelectric Random Access Memory) has been studied as a non-volatile memory that is expected to have low operating power even when compared with the above-mentioned new non-volatile memories in terms of voltage driving. The existing ferroelectric memory (FeRAM) using materials such as existing PZT that utilize the polarization reversal of ferroelectric materials in the operating principle as a memory has been put into practical use as a non-volatile memory for high speed and low power consumption at nodes of 130 nm or more. However, there have been problems including materials that are difficult to handle such as lead, and it has been difficult to thin-film below 100 nm due to the size effect that exhibits ferroelectricity. As a result, there has been a problem that it has been difficult to scale down to the 90 nm generation and below. For this reason, it has only been put into practical use in limited applications such as small-scale low-power consumption applications equipped with small-scale memories such as RFID (Radio Frequency Identification) cards.

[0006] Under such circumstances, as a ferroelectric material that does not contain lead like the PZT material, enables miniaturization scaling below 90 nm, and enables low-voltage operation and low power consumption, hafnium oxide (HfO2) film has been reported (Non-Patent Document 1). After that, the research and development of ferroelectric memories using this ferroelectric hafnium oxide film has been active since 2011.

[0007] As a metal oxide of the same fluorite-type orthorhombic crystal (orthorhombic crystal) as the ferroelectric of hafnium oxide, especially a metal oxide containing hafnium, zirconium, or two of these, and these hafnium-based metal oxides, a ferroelectric of a metal oxide further containing at least one metal element selected from aluminum, silicon, strontium, barium, and rare earth elements, and a ferroelectric thin film have also been reported to exhibit ferroelectricity with a thin film thickness similar to that of hafnium oxide.

[0008] On the other hand, as a non-volatile working memory for replacing volatile memory in order to reduce the power consumption of volatile working memory, research and development of STTMRAM has been carried out, but the problem that the write power of information is relatively large has become apparent. In particular, in the application of non-volatile working memory, improvement of reliability, especially the number of data rewrites (Endurance), has become a major issue.

[0009] As described above, since the hafnium oxide-based non-volatile ferroelectric memory exhibits ferroelectricity even when thinned, it is scalable and expected to be a non-volatile ferroelectric memory that can be mixed and mounted in the backend such as CMOS. However, in order to realize a low-power non-volatile working memory that can replace existing SRAM etc., improvement of reliability, especially the rewrite characteristics (Endurance), is an issue. As a highly reliable hafnium oxide-based ferroelectric memory, Hf embedded with Al nanoclusters using the sub-monolayer doping technique 0.5 Zr 0.5 O2 ferroelectric film has been reported (Non-Patent Document 2). However, the rewrite characteristics of the ferroelectric film in Non-Patent Document 1 are on the order of 10 4 ~10 5 times, which is still insufficient compared to existing volatile memories such as DRAM and SRAM.

Prior Art Documents

Non-Patent Documents

[0010]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0011] Therefore, the present invention provides a voltage-driven, non-volatile ferroelectric memory with low power consumption, a non-volatile memory having reliability that can replace existing volatile memories such as SRAM and DRAM, particularly data rewrite characteristics (Endurance), and a method for manufacturing the same. Preferably, further provided is a non-volatile ferroelectric memory that can be manufactured even at a process temperature of 400 °C or lower that can be mixed with advanced CMOS and has sufficient heat resistance to the advanced CMOS process temperature, a non-volatile ferroelectric memory that enables high-speed operation and low cost, and a method for manufacturing the same.

Means for Solving the Problems

[0012] The present invention provides a structure and manufacturing method of a non-volatile memory element and a non-volatile memory device that improve reliability, particularly the number of data rewrites, which is an important issue in a voltage-driven, non-volatile ferroelectric memory, particularly a hafnium oxide-based ferroelectric memory that can be scaled and exhibits ferroelectricity even when thinned.

[0013] (Aspect 1) A first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer In a non-volatile memory element having at least, A non-volatile memory element, characterized in that a buffer layer, which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences, exists between the ferroelectric layer and the first conductive layer and / or the second conductive layer. (Aspect 2) There is an interface layer composed of a single-layer film or a multi-layer film between the first conductive layer and the ferroelectric layer. The entire interface layer has a dielectric constant higher than that of silicon oxide. When the buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer is present between the first conductive layer and the buffer layer. The non-volatile memory element according to aspect 1, characterized in that. (Aspect 3) The chemical potential of oxygen in the buffer layer is greater than the chemical potential of oxygen in the ferroelectric layer. The non-volatile memory element according to aspect 1 or 2, characterized in that. (Aspect 4) The oxygen vacancy defect density in the buffer layer is smaller than the oxygen vacancy defect density in the ferroelectric layer. The non-volatile memory element according to any one of aspects 1 to 3, characterized in that. (Aspect 5) The buffer layer is composed of cerium oxide, zirconium oxide, titanium oxide, yttria-stabilized zirconia or rare earth element oxide. The non-volatile memory element according to any one of aspects 1 to 4, characterized in that. (Aspect 6) The buffer layer is composed of cerium oxide. The non-volatile memory element according to aspect 5, characterized in that. (Aspect 7) The film thickness of the buffer layer is 0.1 nm or more, preferably 10 nm or less. The non-volatile memory element according to any one of aspects 1 to 6, characterized in that. (Aspect 8) The interface layer has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side. The non-volatile memory element according to any one of aspects 2 to 7, characterized in that. (Aspect 9) The interface layer has a dielectric constant greater than that of silicon nitride, and is composed of an oxide, a metal oxide or a silicate, particularly yttrium oxide or yttrium silicate. The non-volatile memory element according to any one of aspects 2 to 8, characterized in that. (Aspect 10) The non-volatile memory device according to any one of aspects 1 to 9, characterized in that the metal of the metal oxide constituting the ferroelectric layer contains hafnium (Hf), zirconium (Zr), or both of these two metals, or hafnium (Hf), zirconium (Zr), or both of these two metals and at least one metal element selected from the group consisting of aluminum (A1), silicon (Si), strontium (Sr), barium (Ba), and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). (Aspect 11) The non-volatile memory device according to any one of aspects 1 to 10, characterized in that the first conductive layer is a metal silicide or metal disilicide having a fluorite structure, or a metal nitride, or Si or Ge containing impurities, or SOI (Silicon on Insulator). (Aspect 12) The non-volatile memory device according to any one of aspects 1 to 11, characterized in that the second conductive layer has a two-layer structure of a barrier metal and a metal nitride that is connected to the buffer layer and suppresses oxygen migration, particularly W and TiN. (Aspect 13) i) An array in which non-volatile memory devices each having at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer are arranged two-dimensionally or three-dimensionally, ii) A control circuit A non-volatile memory device comprising at least, A non-volatile memory device, characterized in that a buffer layer, which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences, exists between the ferroelectric layer and the first conductive layer and / or the second conductive layer. (Aspect 14) There is an interface layer composed of a single-layer film or a multi-layer film between the first conductive layer and the ferroelectric layer of the non-volatile memory element. As a whole, the interface layer has a dielectric constant higher than that of silicon oxide. When the buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer is present between the first conductive layer and the buffer layer. The non-volatile memory device according to aspect 13, characterized in that. (Aspect 15) The buffer layer is composed of cerium oxide, zirconium oxide, titanium oxide, yttria-stabilized zirconia or rare earth element oxide. The non-volatile memory device according to aspect 13 or 14, characterized in that. (Aspect 16) The buffer layer is composed of a cerium oxide film. The non-volatile memory device according to aspect 15, characterized in that. (Aspect 17) The interface layer has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side. The non-volatile memory device according to any one of aspects 14 to 16, characterized in that. (Aspect 18) The interface layer has a dielectric constant greater than that of silicon nitride, and is composed of an oxide, a metal oxide or a silicate, particularly yttrium oxide or yttrium silicate. The non-volatile memory device according to any one of aspects 14 to 17, characterized in that. (Aspect 19) The metal of the metal oxide constituting the ferroelectric layer is hafnium (Hf), zirconium (Zr) or contains these two metals, or hafnium (Hf), zirconium (Zr) or these two metals and aluminum (A1), silicon (Si), strontium (Sr), barium (Ba) and at least one metal element selected from the group consisting of rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu). The non-volatile memory device according to any one of aspects 13 to 18, characterized in that. (Aspect 20) The nonvolatile memory device according to any one of aspects 13 to 19, wherein the first conductive layer is a metal silicide or metal disilicide having a fluorite structure, or a metal nitride, or Si or Ge containing impurities, or SOI (Silicon on Insulator). (Aspect 21) The array is composed of ferroelectric memory cells each including at least the nonvolatile memory element, and the ferroelectric memory cell includes any one of structures of a 1-transistor type, a 1-transistor 1-capacitor type, a 2-transistor 2-capacitor type, a 2-transistor 1-capacitor type, a 1-transistor 2-capacitor type, and a ferroelectric tunnel junction (FTJ) type. The nonvolatile memory device according to any one of aspects 13 to 20. (Aspect 22) The array is composed of a NOR type array, a two-dimensional NAND type array, a three-dimensional NAND type structure, or a cross-point type array. The nonvolatile memory device according to any one of aspects 13 to 21. (Aspect 23) The nonvolatile memory element is arranged as a single ferroelectric element or an array in a back-end wiring region located above a logic circuit and is connected to a part of the logic circuit. The nonvolatile memory device according to any one of aspects 13 to 22. (Aspect 24) In the connection between the nonvolatile memory element and the logic circuit, a selection element is arranged between the connection wiring of the nonvolatile memory element and the logic circuit. The nonvolatile memory device according to aspect 23. (Aspect 25) The first conductive layer, The second conductive layer, and A ferroelectric layer made of a metal oxide between the first conductive layer and the second conductive layer A method for manufacturing a nonvolatile memory element having at least, Forming a buffer layer, which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences, between the ferroelectric layer and the first conductive layer and / or the second conductive layer, and The ferroelectric layer is formed on top of the first conductive layer at a temperature of 400 °C or lower, such that the ferroelectric layer exhibits ferroelectricity before the second conductive layer is formed on top of the ferroelectric layer. A method for manufacturing a non-volatile memory device, characterized by the above. (Aspect 26) The method for manufacturing a non-volatile memory device according to Aspect 25, characterized in that the ferroelectric layer, which already exhibits ferroelectricity, is subjected to thermal annealing treatment in an inert gas atmosphere at 400 °C or lower. (Aspect 27) The method for manufacturing a non-volatile memory device according to Aspect 25 or 26, characterized in that the interface layer, the ferroelectric layer, and the buffer layer are continuously formed on the first conductive layer, where the buffer layer may be located above and / or below the ferroelectric layer, within the same chamber. (Aspect 28) The method for manufacturing a non-volatile memory device according to any one of Aspects 25 to 27, characterized in that the ferroelectric layer is formed on the first conductive layer, which serves as a bottom electrode, using atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, or self-assembly methods. (Aspect 29) A first conductive layer, A second conductive layer, A ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer, characterized by being composed of the above, and having a buffer layer, which is a metal oxide containing a metal with oxygen ion conductivity and multiple valences, between the ferroelectric layer and the first conductive layer and / or the second conductive layer, and the ferroelectric layer is composed of polycrystals having multiple polarization orientations, with the orientation having the largest component perpendicular to the film surface. Only crystals A method for operating a non-volatile memory device, characterized in that the operating voltage of the device is the voltage at which the polarization having the largest component perpendicular to the film surface reverses.

Advantages of the Invention

[0014] The effects of the present invention are disclosed in other parts of this specification and the drawings, and include, but are not limited to, for example, the following. In a hafnium oxide-based ferroelectric memory composed of a ferroelectric layer formed between a first conductive layer and a second conductive layer on a substrate, between the ferroelectric layer and the first conductive layer and / or the second conductive layer, CeO x A non-volatile memory device or a memory apparatus having a buffer layer which is a metal oxide containing a metal having a plurality of valences having an oxygen ion supply ability such as etc. is provided.

[0015] Also, by a low-temperature formation ferroelectric thin film manufacturing technique capable of setting the process temperature to 400 °C or lower, it can be formed in the back-end wiring layer of advanced CMOS, and it enables co-integration with fine CMOS of 90 nm or less which was impossible with conventional ferroelectric memories using PZT etc.

[0016] In the memory device and the memory apparatus of the present invention, oxygen ions are supplied from the buffer layer to oxygen defects formed in the ferroelectric layer or at the electrode interface due to electric field stress during data rewriting to repair the oxygen defects in the ferroelectric layer or at the interface, improving the leakage current, the ferroelectric film quality, etc. As a result, the number of data rewritings is significantly improved, for example, 10 11 times or more, and also 10 12 times or more of data rewriting can be realized.

[0017] Furthermore, by adopting a first conductive layer having a fluorite structure similar to that of the hafnium-based ferroelectric layer, for example, NiSi2, a higher-quality ferroelectric layer is realized, and by inserting an interface layer such as Y silicate, Hf silicate, Zr silicate, Y2O3, etc. having a relatively higher dielectric constant than the silicon oxide film between the first conductive layer and the ferroelectric layer, it becomes possible to apply a polarization inversion electric field to the ferroelectric layer at a low voltage. As a result, it has a unique effect that the number of rewritings is significantly improved with low power consumption.

Brief Description of the Drawings

[0018]

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DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, without intending to limit the embodiments and forms of implementation of the present invention, an explanation will be given with reference to the drawings. 〔Example 1; Ferroelectric Memory Element with Buffer Layer〕 Example 1 of the present invention provides a non-volatile memory element having at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer, wherein there is a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences between the ferroelectric layer and the first conductive layer and / or the second conductive layer.

[0020] According to the non-volatile memory element of Example 1 of the present invention, due to the presence of a buffer layer having oxygen ion conductivity between the ferroelectric layer and the first conductive layer and / or the second conductive layer (hereinafter, also simply referred to as the conductive layer), the leakage current can be reduced and the data rewriting characteristics can be improved. A ferroelectric memory element that uses the polarization of a ferroelectric composed of a metal oxide for storage is driven by voltage, so the writing current is extremely small, and since it is a non-volatile memory element, it can be of low power consumption. However, the leakage current mainly caused by defects, especially the breakthrough of reliability, especially the data rewriting characteristics (Endurance), has been a problem. Since the ferroelectric memory element stores information by reversing the polarization of the metal oxide ferroelectric, the generation of oxygen defects in the ferroelectric layer or at the interface between the conductor layer and the ferroelectric layer due to the electric field stress during data rewriting is considered to be the cause of problems in the leakage current, especially reliability and data rewriting characteristics. Without intending to be bound by theory, in Example 1 of the present invention, by providing a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences between the ferroelectric layer and the conductive layer, oxygen ions are supplied from the buffer layer to the metal oxide ferroelectric layer or the interface between the conductor layer and the ferroelectric layer, the amount of oxygen defects is controlled, and the film quality is improved. As a result, it is considered that the leakage current is prevented and the reliability and data rewriting characteristics of the ferroelectric memory element are improved.

[0021] Figs. 1(a), 1(b), and 1(c) schematically show cross-sectional views of an example of the nonvolatile memory element according to Embodiment 1 of the present invention. In Figs. 1(a), 1(b), and 1(c), 1 is a ferroelectric layer, 2 is a first conductive layer, 3 is a second conductive layer, and 4 is a buffer layer. In Fig. 1(a), the buffer layer 4 is between the dielectric layer 1 and the second conductive layer 3, but as shown in Fig. 1(b), it may be between the dielectric layer 1 and the first conductive layer 2, and further, as shown in Fig. 1(c), it may be between both the dielectric layer 1 and the first conductive layer 2 and between the dielectric layer 1 and the second conductive layer 3. In these cases, in particular, the first conductive layer 2 may be a lower electrode and the second conductive layer 3 may be an upper electrode. However, the first conductive layer 2 may be an upper electrode and the second conductive layer 3 may be a lower electrode. The position of the buffer layer 4 may be on either electrode side, and the desired effects of the present invention can be obtained. If there are two, a synergistic effect can be obtained.

[0022] In the present invention, the ferroelectric layer 1 exhibits ferroelectricity. A ferroelectric is a substance in which electric dipoles are aligned even without an external electric field, and the orientation of the dipoles can be controlled by an electric field. Referring to the polarization - electric field hysteresis curve of FIG. 2, for a ferroelectric, when a voltage +VCC is applied to the electrodes as the electric field E, the positive polarization at point C is achieved. Even when the electric field E is returned to zero from point C, the positive polarization A remains (residual polarization A). Then, when a negative electric field E is applied to the ferroelectric having the residual polarization A, the polarization becomes zero at the electric field -B (anti - electric field B), and when the voltage -VCC is further applied, the negative polarization at point D is achieved. Even when the electric field E is returned to zero from point D, the negative polarization -A remains (residual polarization A). When a positive electric field E is applied to the ferroelectric having the negative residual polarization A, the polarization becomes zero at the positive electric field B (anti - electric field B), and when the voltage VCC is further applied as the electric field E, the positive polarization at point C is achieved. Therefore, by applying positive and negative electric fields larger than the anti - electric field B to the ferroelectric, even when the electric field is returned to zero, positive and negative polarizations (residual polarizations) can be left in the ferroelectric. A ferroelectric having positive and negative polarizations has electrical characteristics asymmetric in the polarization direction, so the alignment direction (positive or negative polarization) of its electric dipoles can be electrically read from the outside. When a memory element is configured using this ferroelectricity, since the positive or negative polarization is retained even when no electric field is applied, a non - volatile memory element can be configured, and it is possible to reduce power consumption. Also, the data rewriting of the ferroelectric memory element is voltage - driven by voltage application. For this reason, compared with other emerging memories that are current - driven using current, the write current of the ferroelectric memory element is extremely small, and as a result, it is possible to reduce the power consumption during the write operation.

[0023] In the present invention, the ferroelectric layer 1 is a ferroelectric layer composed of a metal oxide. The ferroelectric layer 1 is preferably composed of a ferroelectric composed of a fluorite-type orthorhombic phase metal oxide. In particular, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these, preferably hafnium (Hf), zirconium (Zr) or a combination of these two elements, whether doped or undoped, can form a ferroelectric showing a fluorite-type orthorhombic phase, and thus is suitable. Also, an undoped ferroelectric can be formed depending on the fabrication conditions. Further, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these, preferably hafnium (Hf), zirconium (Zr) or a combination of these two, and at least one metal element (additive metal) selected from the group consisting of aluminum (Al), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) is suitable. Hereinafter, a metal oxide containing these additive metals and containing hafnium, zirconium or cerium may also be referred to as a hafnium-based metal oxide (or hafnium oxide-based metal oxide). In particular, a hafnium-based metal oxide ferroelectric exhibits excellent ferroelectric properties even with a thin film thickness of 10 nm or less, is scalable as a ferroelectric memory element, enables high density of a memory array, and can be fabricated at a temperature of 400 °C or less, further less than 300 °C, 200 °C or less, and with a thermal history, thus having the effect of enabling co-integration with advanced logic devices such as CMOS.

[0024] In hafnium-based metal oxides, the main metal oxides may be simple oxides such as hafnium oxide, zirconium oxide, and cerium oxide, or solid solutions between these metal oxides. When the hafnium-based metal oxide contains a dopant metal, the amount of the dopant metal depends on the types of the main metal oxide and the dopant metal, but it may be an amount that forms a ferroelectric. Generally, the molar number of the dopant metal, with the total of all metals in the metal oxide containing the dopant metal being 100 mol%, is preferably 10 mol% or less, more preferably 0.1 to 10%, and may also be 4 to 9 mol%. If the amount of the dopant metal is small, there is a risk of stabilizing the fluorite-type structure with a monoclinic phase. On the other hand, if the amount of the dopant metal is large, there is a risk of stabilizing the fluorite-type structure with a tetragonal phase or a cubic phase, and there is a risk of losing ferroelectricity. For example, typical hafnium-based ferroelectric materials include Y-doped HfO 2、 Si-doped HfO 2、 Al-doped HfO 2、 La-doped HfO2, and HZO (Hf 0.5 Zr 0.5 O2), etc.

[0025] The ferroelectric layer 1 may be a crystal that exhibits ferroelectricity, and may be polycrystalline, but may also be a uniaxially oriented crystal thin film, or even an epitaxial film. When another crystal film grows on a certain crystal substrate, when one crystal axis of the crystal film and the crystal substrate substantially coincides during growth, it is called a uniaxially oriented layer, and when two crystal axes of the crystal substantially coincide during growth, it is called an epitaxial layer. It is also possible to form a layer with "local epitaxial growth" in which epitaxial growth occurs for each crystal grain, or an epitaxial layer of a single crystal in which the epitaxially grown crystal grains have a substantial size. Also, although the uniaxially oriented crystal layer originally refers to the crystal orientation in relation to the crystal substrate, based on the specific crystal orientation of the obtained uniaxially oriented crystal layer, the crystal orientation in the crystal layer alone separated from the crystal substrate may also be referred to as uniaxially oriented.

[0026] The film thickness of the ferroelectric layer 1 is not particularly limited as a suitable film thickness is adopted according to the application of the non-volatile memory element. For example, it may be 1 nm or more, further 5 nm or more, 10 nm or more. Also, the upper limit is not restricted either, and for example, it may be 5 μm or less, 3 μm or less, 1 μm or less. In a preferred embodiment of the present invention, the film thickness of the ferroelectric layer 1 may be 1 nm to 100 nm, more preferably 2 nm to 50 nm, still more preferably 3 nm to 20 nm or 3 nm to 10 nm. The above-mentioned hafnium-based metal oxide exhibits excellent ferroelectricity even with a thin film thickness such as 20 nm or less compared with conventional ferroelectrics such as PZT, and thus is scalable and suitable as a ferroelectric layer for non-volatile memory elements.

[0027] FIG. 3 shows a chart obtained by X-ray diffraction analysis of a Y7%-HfO2 layer after sputter deposition on a NiSi2 substrate at room temperature, after annealing at 200° C., and after annealing at 350° C., as an example of the ferroelectric layer 1. From FIG. 3, it is confirmed that all of the Y7%-HfO2 thin films have one diffraction peak observed near 30°, are fluorite-type orthorhombic crystals, and are ferroelectrics (see also FIG. 5).

[0028] The first conductive layer 2 and the second conductive layer 3 act as electrodes for applying a voltage to the ferroelectric layer 1 and can be made of metal, conductive ceramics, conductive semiconductors, etc. Metals include tungsten, titanium, gold, silver, copper, platinum, aluminum, etc. Conductive ceramics include conductive silicides such as nickel disilicide (NiSi2), conductive nitrides such as titanium nitride (TiN), conductive oxides such as indium tin oxide (ITO), and pyrochlore structures such as Bi2Ru2O7, R2Ru2O7 (R is a rare earth element), Bi2Ir2O7, and rare earth iridium oxides R2Ir2O7 (R is a rare earth element). Also, doped or intrinsic silicon semiconductors, various compound semiconductors, etc. can be cited as conductive semiconductors. The first conductive layer 2 and the second conductive layer 3 only need to be electrically connected to the ferroelectric layer 1. Also, as the conductive layer (upper electrode) formed on the ferroelectric layer 1, tungsten, TiN, and a multi-layer electrode of TiN / W are preferable.

[0029] In one preferred embodiment, the first conductive layer 2 and the second conductive layer 3 have an oxygen barrier property that suppresses oxygen migration on the interface side with the ferroelectric layer 1, particularly on the interface side of the second conductive layer (upper electrode) 3 with the ferroelectric layer 1 when the second conductive layer 3 is formed on the ferroelectric layer 1. A conductive material having an oxygen barrier property, such as tungsten (W), may be formed as a barrier layer. By the first conductive layer 2 and the second conductive layer 3 having an oxygen barrier layer, there are effects of suppressing the diffusion and leakage of oxygen ions from the buffer layer and the ferroelectric layer 1 to generate oxygen defects, preventing leakage current, and improving the performance of the non-volatile memory element of the present invention. The thickness of the barrier layer is preferably 0.1 nm or more, and may further be 0.5 nm or more, 1 nm or more, 1.5 nm or more. Also, the film thickness of the buffer layer 4 is desirably 10 nm or less, and may further be 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less. The second conductive layer preferably has a two-layer structure of a barrier metal and a metal nitride that are connected to the buffer layer and suppress oxygen migration, particularly W and TiN.

[0030] When the first conductive layer 2 is a lower electrode serving as a substrate on which the ferroelectric layer 1 is deposited, it is preferably a conductive layer having a fluorite structure, such as a metal silicide or a metal disilicide such as nickel disilicide (NiSi2). When the first conductive layer serving as a substrate is a metal silicide or a metal disilicide such as nickel disilicide (NiSi2), the crystal quality of the hafnium-based metal oxide deposited thereon can be excellent, so that the characteristics of the ferroelectric layer and the ferroelectric layer interface can be excellent. Also, in the case of a two-terminal cell such as a capacitor, a nitride electrode such as TiN, while in the case of a one-transistor cell, a conductive layer obtained by doping a semiconductor layer such as Si with impurities is also possible.

[0031] In the non-volatile memory element of the present invention, there is a buffer layer 4 which is a metal oxide containing a metal having oxygen ion conductivity and multiple valences between the ferroelectric layer 1 and the first conductive layer 2 and / or the second conductive layer 3. Here, there is no difference between the first conductive layer 2 and the second conductive layer 3. In short, the buffer layer 4 exists between at least one of the two conductive layers and the ferroelectric layer 1. The buffer layer 4 preferably exists in direct contact with the ferroelectric layer 1.

[0032] The buffer layer 4 is made of a paraelectric material (insulating material) which is a metal oxide containing a metal having oxygen ion conductivity and multiple valences. The buffer layer 4 is a paraelectric material (insulating material) but has oxygen ion conductivity. The buffer layer 4 is composed of a metal oxide containing a metal having multiple valences. By being composed of a metal oxide containing a metal having oxygen ion conductivity with multiple valences, it can supply and receive, especially supply, oxygen with the ferroelectric layer 1, and has a function of preventing or repairing oxygen defects caused by electric field stress during data rewriting at the ferroelectric layer 1 or the interface between the ferroelectric layer 1 and the conductive layer, thereby reducing the leakage current, improving the ferroelectric characteristics, reducing the breakdown electric field, and improving the rewriting characteristics, etc., and exhibits excellent effects. In the present invention, the buffer layer 4 must exhibit oxygen ion conductivity to prevent or repair oxygen defects, but by being a metal oxide containing a metal having multiple valences, it can be excellent in oxygen ion conductivity for this purpose.

[0033] The oxygen chemical potential of the buffer layer 4 is preferably higher than the oxygen chemical potential of the ferroelectric layer 1. When the oxygen chemical potential of the buffer layer 4 is higher than the oxygen chemical potential of the ferroelectric layer 1, oxygen ions can easily move from the buffer layer 4 into the ferroelectric layer 1 by diffusion or drift or the like, and the amount of oxygen defects at the ferroelectric layer 1 or the interface between the ferroelectric layer 1 and the conductive layer can be controlled.

[0034] The chemical potential of oxygen in the buffer layer and the ferroelectric layer is determined by the material and can be obtained either if it is known or by calculation using theoretical methods such as the molecular orbital method or first-principles calculations. In the present invention, it is determined that when the chemical potential of oxygen in the buffer layer is higher than that in the ferroelectric layer, oxygen ions can diffuse from the buffer layer into the ferroelectric layer and move by drift or other principles. In that case, the valence of the metal element having a plurality of valences constituting the buffer layer changes in the direction of supplying oxygen ions.

[0035] The oxygen vacancy defect density of the buffer layer 4 is preferably smaller than the oxygen vacancy defect density of the ferroelectric layer 1. When the oxygen vacancy defect density of the buffer layer 4 is smaller than the oxygen vacancy defect density of the ferroelectric layer 1, oxygen ions can easily diffuse from the buffer layer 4 into the ferroelectric layer 1 and move by drift or other principles, preventing or repairing oxygen defects at the interface between the ferroelectric layer 1 or the ferroelectric layer 1 and the conductive layer.

[0036] The oxygen vacancy defect density of the buffer layer and the ferroelectric layer can be measured, for example, by electron energy-loss spectroscopy (EELS) using an image observed by a transmission electron microscope (TEM). Also, since the presence of oxygen deficiency causes a deviation from the stoichiometric composition corresponding to the oxygen deficiency, for example, the sample surface is sputtered in the depth direction while performing glow discharge, and glow discharge spectroscopy (GDS) that ionizes by glow discharge and performs mass spectrometry is used to perform composition analysis in the depth direction, and the oxygen vacancy defect density may be measured. Furthermore, the oxygen vacancy defect density can also be evaluated using the non-Rutherford inelastic resonance scattering method and the laser Raman spectroscopy method.

[0037] As the dielectric material (insulating material) showing the oxygen ion conductivity of the buffer layer 4 and containing a metal having a plurality of valences, for example, a cerium oxide film (CeO x(x = 1.5 - 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0)), in addition, a zirconium oxide film, a titanium oxide film, a yttria-stabilized zirconia film, or a rare earth element oxide film, etc. can be applied. In particular, when the ferroelectric layer 1 is a hafnium oxide film, a zirconium oxide film (Zr), or an oxide of hafnium and zirconium, or these are doped with aluminum (A1), silicon (Si), yttrium (Y), strontium (Sr), barium (Ba), etc. to exhibit ferroelectricity, as the buffer layer 4, a cerium oxide film (CeO x (x = 1.5 - 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0)) is preferred. The cerium oxide film as the buffer layer 4 is a paraelectric material.

[0038] The film thickness of the buffer layer 4 is preferably 0.1 nm or more, and may further be 0.5 nm or more, 1 nm or more, 1.5 nm or more. Also, the film thickness of the buffer layer 4 is desirably 10 nm or less, and may further be 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less. The buffer layer 4 only needs to have a layer thickness capable of supplying oxygen ions into the ferroelectric layer 1. On the other hand, since the buffer layer 4 is an insulator material, it is preferably a layer thickness that does not significantly impair conductivity.

[0039] After forming the ferroelectric layer 1 and the buffer layer 4, an activation annealing (AA annealing) treatment at 400 °C or lower may be performed, and an improvement in the characteristics of the ferroelectric layer 1 and the non-volatile memory element can be observed. The activation annealing treatment after forming the buffer layer 4 may be before or after forming an electrode on the upper part of the formed buffer layer 4. However, in one preferred embodiment, it can be before forming an electrode on the upper part of the buffer layer 4, and in another preferred embodiment, it can be after forming an electrode on the upper part of the buffer layer 4.

[0040] In the non-volatile memory element of Example 1 of the present invention, when a buffer layer 4 is inserted between the ferroelectric layer 1 and the first conductive layer 2 and / or the second conductive layer 3, the leakage current decreases, and particularly the rewriting characteristics (number of rewrites) of the non-volatile memory element are 1011 times or more, particularly 10 12 It was confirmed that it can be improved 10 times or more. Further, when the buffer layer 4 is present, it was also confirmed that there are effects of reducing the leakage current, improving the data rewrite characteristics, and improving the room temperature data retention characteristics.

[0041] In the nonvolatile memory element of Example 1 of the present invention, the ferroelectric layer 1 can have at least two types of orientations (orientation I with a small orientation angle and orientation II with a large orientation angle) with different orientation angles, and not only can both orientation I and orientation II be switched by increasing the applied voltage (operating voltage), but it is also possible to switch only orientation I by making the applied voltage (operating voltage) lower than that, and it was found that when only orientation I is switched, the number of data rewrites in the rewrite characteristics can be improved compared to the case where both orientation I and orientation II are switched. Here, the two types of orientations I and II mean that there are at least two types of orientations, and there may be three or more types of orientation distributions.

[0042] The existence of Orientation I and Orientation II can be confirmed from the fact that the curve representing the amount of accumulated charge Q with respect to the applied voltage (operating voltage) V has two peaks and that the two peaks can be decomposed into two independent peaks by waveform analysis. From the waveforms of Orientation I and Orientation II obtained by decomposition, the orientation angle of the crystal grains in the ferroelectric layer can be estimated. Orientation I having a peak at a low applied voltage (operating voltage) has a smaller orientation angle θ than Orientation II having a peak at a high applied voltage. Here, the orientation angle θ is defined as the angle of the orientation axis with respect to the direction perpendicular to the film surface of the ferroelectric layer (see Fig. 13(a)). Although the crystal grains of Orientation II cannot be switched, it is possible to switch only Orientation I by using a voltage at which the crystal grains of Orientation I can be switched. At this time, both Orientation I and Orientation II are not a group of crystal grains having exactly the same orientation angle θ, but as shown in Fig. 13(b), an aggregate of a group of crystal grains having a peak at a specific orientation angle θ and shoulders on both sides of the orientation angle θ (particularly a normal distribution) (not an aggregate of physically integrated crystal grains in the ferroelectric layer. It is a theoretical aggregate based on the orientation angle distribution among the crystal grains that may be scattered in the ferroelectric layer).

[0043] Therefore, according to the operation method of the ferroelectric capacitor element that switches only this Orientation I, the rewriting characteristics (number of rewritings) are improved as compared with the operation method that switches Orientation II (and Orientation I). Thus, according to the present invention, there is provided an operation method of a non-volatile memory element which is a ferroelectric capacitor element having the buffer layer of the present invention. When the ferroelectric layer 1 is polycrystalline, it has two types of first and second orientations with different orientation angles. Among these orientations, there is provided an operation method of a ferroelectric capacitor element that switches only the first orientation with a small orientation angle of the ferroelectric layer as an operation voltage. Needless to say, the operation method of the present invention is also applicable when the ferroelectric layer 1 is composed of polycrystals having two or more types of peaks. When there are three or more types of orientation distributions, paying attention to one of the orientations having a peak at a lower applied voltage (operation voltage) compared to any other orientation, preferably paying attention to the orientation having a peak at the lowest applied voltage (operation voltage) (the orientation having the largest component perpendicular to the film surface), and driving the element at that lower applied voltage (operation voltage), it is possible to improve the number of data rewritings in the rewriting characteristics as compared with the case of driving all orientations.

[0044] Examples of the electrical characteristics of the non-volatile memory element of Example 1 of the present invention are shown in FIGS. 4 to 9. FIG. 4 shows the current-voltage characteristics of a ferroelectric element (ferroelectric capacitor) evaluated using a microcurrent measuring device with the presence or absence of a buffer layer as a parameter. By inserting the buffer layer, the leakage current for the same voltage is reduced, and the breakdown voltage of the element is increased. Since this leakage current is greatly contributed by the defect current component flowing through the defects of the ferroelectric element, it is presumed that the defect density before applying the data rewrite stress is reduced by inserting the buffer layer. Also, the increase in the breakdown voltage of the element suggests that the breakdown voltage of the element is increased and the reliability of the element is improved.

[0045] Figure 5 shows the hysteresis characteristics with the presence or absence of a buffer layer of the ferroelectric element. The ferroelectricity of the Y7%-HfO2 ferroelectric layer 1 is shown. Also, by inserting the buffer layer, the ferroelectric characteristics are improved. In particular, the coercive electric field is reduced and the hysteresis characteristics are improved. For the ferroelectric layer 1 in this example, a room-temperature formed Y7%-HfO2 layer is used. As the next step, CeO x (x = 1.5 to 2.0) is formed, and annealing treatment (activation annealing) is performed after forming the upper electrode.

[0046] Figure 6 shows the activation annealing temperature dependence of the spontaneous polarization Pr width (2Pr). Compared with the as-depo ferroelectric element, the spontaneous polarization increases when subjected to low-temperature activation annealing treatment at 200 to 350 °C, indicating the effectiveness of the activation annealing treatment (see also Figure 20).

[0047] Figure 7 shows the activation annealing (AA) temperature dependence of the rewrite characteristics (rewrite cycle dependence of the 2Pr window width) of the ferroelectric capacitor element measured at a voltage of 2.5 V and 1 MHz. When the AA annealing temperature rises from 200 °C to 400 °C, regarding the data rewrite characteristics between 300 °C and 400 °C compared with 200 °C, the Pr window is almost constant up to 10 9 cycles, no narrowing is observed, and stable and good characteristics are obtained.

[0048] Figure 8 shows the room-temperature data retention characteristics after 10 rewrites at a voltage of 2.5 V. It was found that the Pr window width is almost constant and stable with respect to the retention time, and the data retention characteristics are also excellent. 4 Figure 9 shows the data rewrite characteristics at a voltage of 2.2 V and 2 MHz. No narrowing of the Pr window is observed, and stable rewrite characteristics are obtained, and it was found that the number of rewrite cycles exceeds 10

[0049] Figure 9 shows the data rewrite characteristics at a voltage of 2.2 V and 2 MHz. No narrowing of the Pr window is observed, and stable rewrite characteristics are obtained, and it was found that the number of rewrite cycles exceeds 10 11 cycles.

[0050] When the buffer layer exists between the second conductive layer (upper electrode) and the ferroelectric layer, it is defined as buffer layer structure A; when it exists between the first conductive layer (lower electrode) and the ferroelectric layer, it is defined as buffer layer structure B. Hereinafter, it will be demonstrated that the essence of the present invention is functionally effective for improving the reliability of the ferroelectric non-volatile memory element, particularly the data rewriting characteristics, whether it is buffer layer structure A or buffer layer structure B.

[0051] Figs. 10(a) and (b) show structural examples of the non-volatile memory element (ferroelectric capacitor element) of Example 1. The buffer layer structure A shown in Fig. 10(a) is a non-volatile memory element having a buffer layer 4 between the ferroelectric layer 1 and the second conductive layer (upper electrode) 3, and the buffer layer structure B shown in Fig. 10(b) is a non-volatile memory element having a buffer layer 4 between the first conductive layer (lower electrode) 2 and the ferroelectric layer 1. In either case, the ferroelectric layer 1 is a layer made of 5% yttrium-doped hafnium oxide (Y:HfO2) with a film thickness of 7.5 nm, and the buffer layer 4 is a layer made of CeOx with a film thickness of 1 nm. The lower electrode 2 is a multilayer film of a titanium (Ti) layer 2-1 with a film thickness of 5 nm and a tungsten (W) layer 2-2 with a film thickness of 10 nm.

[0052] On the other hand, the upper electrode 3 is a multilayer film of a tungsten (W) layer 3-2 with a film thickness of 30 nm and a titanium nitride (TiN) layer 3-1 with a film thickness of 10 nm. As will be described later, the lower electrode 2 and the upper electrode 3 can be fabricated by sputtering, and the ferroelectric layer 1 and the buffer layer 4 can be fabricated by atomic layer deposition (ALD). Activation annealing may be performed after electrode fabrication. It goes without saying that the materials and film thicknesses of these layers are examples and not limiting.

[0053] Figure 11 shows the voltage-polarization hysteresis characteristics of the non-volatile memory element of Example 1 having the buffer layer structures A and B as shown in FIGS. 10(a) and (b), compared with the voltage-polarization hysteresis characteristics of the corresponding non-volatile memory element without a buffer layer. Also, the film thickness of the buffer (CeOx) layer 4 is changed to 0.6 nm, 1 nm, and 2 nm. FIG. 11(a) shows the hysteresis characteristics (control example) of the non-volatile memory element without a buffer layer, and FIGS. 11(b-1), (b-2), and (b-3) show the hysteresis characteristics of the non-volatile memory element having the buffer (CeOx) layer on the upper electrode side (the second conductive layer 3 side in FIG. 1), and FIGS. 11(c-1), (c-2), and (c-3) show the hysteresis characteristics of the ferroelectric capacitor element having the buffer (CeOx) layer on the upper electrode side (the first conductive layer 2 side in FIG. 1). FIGS. 11(b-1) and (c-1) show the case where the thickness of the buffer (CeOx) layer is 0.6 nm, FIGS. 10(b-2) and (c-2) show the case where the thickness of the buffer (CeOx) layer is 1 nm, and FIGS. 11(b-3) and (c-3) show the hysteresis characteristics of the non-volatile memory element where the thickness of the buffer (CeOx) layer is 2 nm. In any case, after forming the upper electrode, post-annealing for activating the non-volatile memory element was performed at 500° C. for 1 minute. The ferroelectric capacitor element of Example 1 has oxygen ion conductivity, and even if the buffer layer 4 containing a metal oxide containing a metal having a plurality of valences is on the second conductive layer 3 side or the first conductive layer 2 side of the ferroelectric layer 1, it can be seen that if the film thickness is 1 nm or more, it exhibits good voltage-polarization hysteresis characteristics as a non-volatile memory element.

[0054] Figure 12 shows the data rewriting characteristics at a voltage of 2.2 V and a frequency of 2 MHz of the non-volatile memory element having the buffer (CeOx) layer with a thickness of 1 nm shown in FIGS. 11(b-2) and (c-2). It has been shown that the non-volatile memory element of Example 1 can obtain excellent data rewriting characteristics compared with the case without a buffer layer, regardless of whether the buffer layer 4 is on the second conductive layer 3 side or the first conductive layer 2 side of the ferroelectric layer 1. From the above, it was found that the buffer layer structure A or the buffer layer structure B of the present invention exhibits a specific effect in improving the reliability of the ferroelectric non-volatile memory element, particularly in improving the data rewriting characteristics.

[0055] Figs. 13(a), (b), and (c) are a schematic diagram of the orientation of Y:HfO2 crystal grains (Fig. 13(a)), a diagram showing the amount of stored charge Q with respect to the operating voltage V (Fig. 12(b)), and a diagram showing the rewritable characteristics (Fig. 13(c)) for a non-volatile memory element having a 2-nm-thick ferroelectric layer composed of 5% yttrium-doped hafnium oxide (Y:HfO2) and a buffer layer composed of CeOx (see Fig. 1(a)) as an example of Example 1.

[0056] The ferroelectric layer of the non-volatile memory element of the present invention, preferably a hafnium-based ferroelectric layer, can have two crystal grain groups with different orientation angles, and when operating to switch only the crystal grain group with a small orientation angle, the number of rewrite cycles of the non-volatile memory element can be improved.

[0057] Fig. 13(a) shows the orientation angle θ I of Y:HfO2 crystal grains of orientation I and the orientation angle θ II (>θ I ) of Y:HfO2 crystal grains of orientation II in the ferroelectric layer of such a non-volatile memory element schematically.

[0058] Referring to Fig. 13(b), this non-volatile memory element (ferroelectric capacitor element) has two peaks in the amount of stored charge Q at around 2.3 V and around 3 V along the applied voltage (operating voltage) V.

[0059] When the waveform analysis is performed on this amount of stored charge Q, it is confirmed that it is a composite waveform of the waveform of orientation I and the waveform of orientation II shown in the figure, and the orientation angles are θ I and θ IIIt is confirmed that it corresponds to Y:HfO2 crystal grains having []. Therefore, although it is insufficient to switch the orientation II, when an applied voltage (operating voltage) of ±2.50 V, which is large enough to switch the orientation I, is used, it is possible to switch only the Y:HfO2 crystal grains of the orientation I. Further, if a higher applied voltage (operating voltage) of ±3.25 V, which can switch the orientation II, is used, it is possible to switch the Y:HfO2 crystal grains of both the orientation I and the orientation II.

[0060] FIG. 13(c) shows the rewriting characteristics of the ferroelectric capacitor element when switching is performed at an applied voltage (operating voltage) of ±2.50 V and an applied voltage (operating voltage) of ±3.25 V. According to the operation method of switching only the orientation I at an applied voltage (operating voltage) of ±2.50 V, compared with the case of switching both the orientation I and the orientation II at an applied voltage (operating voltage) of ±3.25 V, it can be seen that even when the number of rewritings increases, the decrease in polarization (accumulated charge amount) is small and the rewriting characteristics are improved.

[0061] (Manufacturing method of the nonvolatile memory element of Example 1) For the nonvolatile memory element of Example 1, first, the first conductive layer 2 is prepared. The first conductive layer 2 only needs to have conductivity, and the conductive layer may be a substrate. For example, it may be a semiconductor layer or a semiconductor region doped with impurities and having conductivity. Alternatively, the first conductive layer 2 may be formed by depositing a conductive layer on a semiconductor layer or an insulating layer. The method of depositing the conductive layer may be any of film formation methods (deposition methods) such as sputtering, evaporation, CVD method, PLD (Pulsed Laser Deposition) method, ALD (Atomic Layer Deposition) method, and plating method.

[0062] Here, optionally, a buffer layer 4 may be formed on the first conductive layer 2. The buffer layer 4 is usually an oxide and a ferroelectric, and may be formed by any of a wide range of film formation methods known for oxides and ferroelectrics. Sputtering, evaporation, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition) methods are preferred. The formation of the buffer layer 4 may be carried out in an inert atmosphere such as argon, at room temperature or with substrate heating, preferably under reduced pressure. The deposition temperature may be room temperature or a high temperature of 400 °C or higher, and is not limited, but in one preferred embodiment, it is 400 °C or lower, less than 300 °C, or less than 250 °C.

[0063] Next, if the first conductive layer 2 is the lower electrode, or if the buffer layer 4 is formed on the first conductive layer 2, a ferroelectric layer 1 is formed on the buffer layer 4. Since the method for forming the ferroelectric layer is known, a known method or the method disclosed in Patent Document 1 can be used. The ferroelectric layer 1 may be formed by a film formation method (deposition method) such as the sol-gel method, CVD (Chemical Vapor Deposition) method, pulsed CVD method, PLD (Pulsed Laser Deposition) method, ALD (Atomic Layer Deposition) method, or self-assembly method, but those by the ALD method, sputtering method, or hydrothermal method are preferred. The ferroelectric layer can be formed at a temperature of less than 300 °C by the sputtering method or the hydrothermal method.

[0064] According to one preferred embodiment, in particular, the ferroelectric layer 1 composed of a hafnium-based metal oxide is formed by the sputtering method, and according to the sputtering method, it can also be formed at a temperature of 400 °C or lower, particularly less than 300 °C. A target made of a raw material metal oxide or its constituent element or oxide is sputtered in an inert atmosphere or an oxidizing atmosphere to deposit a target metal oxide layer on a substrate having the first conductive layer 2 on its surface. According to the sputtering method, the ferroelectric layer can be deposited on a substrate heated to room temperature or a low temperature of less than 300 °C, but optionally, an activation annealing treatment may be performed at a temperature of 400 °C or lower after deposition.

[0065] Further, when the metal oxide layer deposited by sputtering, ALD method, CVD method or other deposition methods is not a ferroelectric, an annealing treatment may be performed after deposition to form a ferroelectric layer. The annealing treatment temperature is usually 800 °C or lower, for example, it may be 200 to 800 °C.

[0066] Also, the ferroelectric layer may be formed by producing a monoclinic or tetragonal paraelectric thin film composed of a hafnium-based metal oxide at a temperature of less than 300 °C, and applying an electric field larger than the electric field that generates an electric-field-induced phase transition to the paraelectric thin film under a temperature rise at room temperature or 800 °C or lower, preferably less than 300 °C, to convert the paraelectric thin film into a rhombohedral ferroelectric thin film.

[0067] When the ferroelectric layer is deposited particularly at room temperature or a low temperature, the crystal quality may be improved or the ferroelectric characteristics may be improved by performing an activation annealing treatment after deposition. The temperature of the activation annealing treatment is 400 °C or higher, for example, 400 to 800 °C, 400 to 700 °C is also possible, or it may be 400 °C or lower. In one aspect, 400 °C or lower, further less than 300 °C, and 250 °C or lower are preferable.

[0068] After forming the ferroelectric layer 1, a buffer layer 4 is optionally formed on the ferroelectric layer 1. In the present invention, the buffer layer 4 is formed on at least one of the first conductive layer 2 or the ferroelectric layer 1. The buffer layer 4 is usually an oxide and is a paraelectric, and may be formed by any of a wide range of film formation methods known for oxides and paraelectrics. Sputtering method, evaporation method, CVD method, PLD (Pulsed Laser Deposition) method, ALD (Atomic Layer Deposition) method are preferable. The formation of the buffer layer 4 may be carried out in an inert atmosphere such as argon, at room temperature or under substrate heating, preferably under reduced pressure. The deposition temperature is not particularly limited, and may be room temperature or a high temperature, but 400 °C or lower, preferably less than 300 °C, is preferable.

[0069] When fabricating the buffer layer 4 on the ferroelectric layer 1, after depositing the buffer layer 4 (it may also be after fabricating the element or device), if the buffer layer 4 exists only under the ferroelectric layer 1 and not on the ferroelectric layer 1, after depositing the ferroelectric layer 1 (it may also be after fabricating the element or device), activation annealing (AA annealing) treatment of the ferroelectric layer 1 and the buffer layer 4 may be performed. The AA annealing treatment may be carried out, for example, at a temperature of 400 °C or higher, or at a temperature of 400 °C or lower, further at a temperature of 200 °C or higher and lower than 300 °C, preferably under reduced pressure, in an inert atmosphere such as argon. The activation annealing treatment time depends on the annealing temperature, but for example, it may be 60 minutes or less, and 0.2 to 20 minutes is preferred. By performing activation annealing (AA annealing) treatment after depositing the buffer layer 4, the crystallinity of the ferroelectric layer 1 and the interface characteristics between the ferroelectric layer 1 and the buffer layer 4 can be improved, and the ferroelectric characteristics can be improved. Also, if it is an activation annealing treatment at 400 °C or lower, especially when including a semiconductor device together with a non-volatile memory element (ferroelectric capacitor), there is an advantage that there is no adverse effect on other components of the semiconductor device, impurity diffusion regions, wirings, etc. after fabricating the semiconductor device including the non-volatile memory element.

[0070] As an example, after cleaning the surface of the Si semiconductor base layer formed on the surface of the Si semiconductor substrate by press patterning in an argon atmosphere for 30 minutes, nickel (Ni) was deposited on the Si semiconductor base layer by sputtering. Then, the Si semiconductor substrate was heated to 350 °C in an argon atmosphere to silicidize the nickel (Ni) on the Si semiconductor base layer, and the first conductive layer (lower electrode) 2 of nickel silicide (NiSi2) was formed. On the semiconductor substrate on which the first conductive layer 2 was formed, a Y7%-HfO2 layer was formed by the method described in Patent Document 1. In a sputtering apparatus, after reducing the pressure in the vacuum chamber, the semiconductor substrate temperature was set at room temperature (25 °C), and a voltage was applied between the semiconductor substrate and the target (Y7%-HfO2) in an argon atmosphere with an argon flow rate of 100 sccm, oxygen of 0 sccm, and a pressure of 50 mmTorr. With a power of 50 W, the Y7%-HfO2 layer 1 was formed to a thickness of 10 nm on the first conductive layer 2 of the semiconductor substrate. Further, the deposited Y7%-HfO2 layer at room temperature was annealed at 200 to 350 °C for 10 minutes.

[0071] Charts obtained by performing X-ray diffraction analysis on the Y7%-HfO2 layer 1 obtained after deposition and after annealing are shown in FIG. 3. From FIG. 3, it is confirmed that all of the Y7%-HfO2 thin films have one diffraction peak observed near 30°, are fluorite-type orthorhombic crystals, and are ferroelectrics.

[0072] Next, for the Y7%-HfO2 layer 1 for 30 minutes on , in an argon atmosphere with 100 sccm of argon, 0 sccm of oxygen, and a pressure of 50 mTorr, at room temperature (25 °C), CeO x (x = 1.5 - 2.0) was deposited with a 50 W electron beam to form the buffer layer 4 to a thickness of 2 nm. Then, a TiN layer (upper electrode) 3 was sputter-deposited on the buffer layer 4. For comparison, an example without forming the buffer layer 4 (comparative example) was also prepared, and the TiN layer (upper electrode) 3 was deposited. For some of the obtained elements, an AA annealing treatment was performed at 200 to 400 °C. For comparison, a comparative example was prepared in the same manner as above except that the buffer layer 4 was not formed. The electrical characteristics of the obtained ferroelectric memory elements are shown in FIGS. 4 to 9.

[0073] The matters described above as the method for manufacturing the nonvolatile memory element of Example 1 are common matters in the methods for manufacturing memory elements and memory devices of all embodiments of the present invention as long as the nonvolatile memory element of Example 1 is included. According to the nonvolatile memory element of Example 1, by having a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences, in a nonvolatile memory element using a ferroelectric layer composed of a metal oxide, leakage current is prevented, the reliability of the ferroelectric memory element is improved, and particularly, the data rewriting characteristics which were a conventional problem are remarkably improved. Further, when a ferroelectric layer composed of a hafnium-based metal oxide is formed at a temperature of 400° C. or lower, preferably less than 300° C., and the deposited ferroelectric layer is subjected to activation annealing at a temperature of 400° C. or lower, not only can the characteristics of the ferroelectric layer and the ferroelectric memory element be improved, but particularly activation annealing (AA annealing) can be preferably carried out after manufacturing the memory element and the memory device because it can be carried out at a temperature of 400° C. or lower. It is particularly suitable when the memory element and the memory device include a copper wiring or an impurity diffusion semiconductor region. However, the manufacturing of the advanced CMOS back-end hybrid memory (FeRAM) in the present invention is not limited to 400° C. or lower.

[0074] Also, by continuously depositing the ferroelectric layer 1 and the buffer layer 4 by atomic layer deposition (ALD), excellent commercial productivity can be achieved. However, this example does not limit the nonvolatile memory element and its manufacturing method, and it goes without saying that the type of material, layer thickness, film formation conditions, etc. can be appropriately changed.

[0075] 〔Example 2; Advanced Buffer Layer Structure Ferroelectric Memory Element〕 In Example 2 of the present invention, in a non-volatile memory element having at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer, there is a buffer layer 4 which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences between the ferroelectric layer and the first conductive layer and / or the second conductive layer, and there is an interface layer composed of a single-layer film or a multilayer film between the ferroelectric layer and the first conductive layer. The interface layer as a whole has a dielectric constant higher than that of silicon oxide. When a buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer exists between the first conductive layer and the buffer layer. A non-volatile memory element is provided.

[0076] Also in the non-volatile memory element of Example 2 of the present invention, by providing a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences between the ferroelectric layer and the first conductive layer 2 and / or the second conductive layer, leakage current is prevented, and the reliability and data rewrite characteristics of the ferroelectric memory element are improved. It is considered that the occurrence of oxygen defects in the ferroelectric layer or at the interface between the ferroelectric layer and the conductor layer due to the electric field stress during data rewriting is the cause of deteriorating the leakage current, particularly the reliability and data rewrite characteristics. However, by supplying oxygen ions from the buffer layer to the ferroelectric layer or the ferroelectric layer interface, the oxygen defects are compensated, and the film quality and the interface are improved.

[0077] FIG. 14(a) and (b) schematically show cross-sectional views of an example of the nonvolatile memory element according to Example 2 of the present invention. In FIGS. 14(a) and (b), 1 is a ferroelectric layer, 2 is a first conductive layer (lower electrode), 3 is a second conductive layer (upper electrode), 4 is a buffer layer, and 5 is an interface layer. In FIG. 14(a), the buffer layer 4 is between the ferroelectric layer 1 and the second conductive layer (upper electrode) 3, and the interface layer 5 is between the ferroelectric layer 1 and the first conductive layer (lower electrode) 2. In FIG. 14(b), the buffer layer 4 is between the ferroelectric layer 1 and the first conductive layer (lower electrode) 2, and the interface layer 5 is between the first conductive layer (lower electrode) 2 and the buffer layer 4. Although not shown in the figure, the buffer layer 4 may be between both the ferroelectric layer 1 and the second conductive layer (upper electrode) 3 and between the ferroelectric layer 1 and the first conductive layer (lower electrode) 2. In that case, the interface layer 5 is between the buffer layer 4 under the ferroelectric layer 1 and the first conductive layer (lower electrode) 2. The first conductive layer 2 may be one of the two electrodes sandwiching the ferroelectric layer 1 in the nonvolatile memory element. However, when the nonvolatile memory element has a conductive layer (electrode) on a semiconductor substrate (silicon substrate), it is preferable that the first conductive layer 2 exists as a lower electrode on the semiconductor substrate (silicon substrate) side.

[0078] In the non-volatile memory element of Example 2 of the present invention, in addition to the buffer layer 4, there is further an interface layer 5 composed of a single-layer film or a multi-layer film between the ferroelectric layer 1 and the first conductive layer 2, and the entire interface layer has a dielectric constant higher than that of silicon oxide. In particular, when the first conductive layer 2 is a silicon substrate or the like, in order to suppress the formation of a silicon oxide film between the silicon substrate and the ferroelectric layer 1, there is an interface layer 5 having a dielectric constant higher than that of silicon oxide between the ferroelectric layer 1 and the first conductive layer 2. As a result, compared with the case where the interface layer 5 does not exist, among the voltages applied between the first and second conductive layers 2 and 3 during data rewriting, a higher partial voltage is applied to the ferroelectric layer 1, so that a sufficient voltage can be applied to the ferroelectric layer 1 with a lower external voltage. Further, the interface layer 5 improves the ferroelectric characteristics with low-voltage operation as described above, and when the non-volatile memory element is a FeFET (see Fig. 222(b)), the tunnel current of electrons injected from the channel of the FeFET during writing is suppressed by relatively thickening the interface layer (tunnel insulating film), and as a result, deterioration of data rewrite characteristics can be improved.

[0079] The interface layer 5 has a dielectric constant larger than that of a silicon oxide film (relative dielectric constant of about 3.9). Preferably, it has a dielectric constant equal to or higher than that of a silicon nitride film (relative dielectric constant of about 7.8), and particularly preferably, it is an oxide film or a silicate film. Among the voltages applied between the first and second conductive layers 2 and 3, the ratio of the voltages distributed to the ferroelectric layer 1 and the interface layer 5 depends on the ratio of the dielectric constants of the ferroelectric layer 1 and the interface layer 5, and it is preferable that the higher the dielectric constant of the interface layer 5, the higher the partial voltage applied to the ferroelectric layer 1. The dielectric constant of the interface layer 5 is preferably larger than about 3.9 in terms of relative dielectric constant, more preferably about 5 or more, about 7.8 or more, further about 15 or more, and about 20 or more.

[0080] Such an interface layer 5 may be an insulator with a high dielectric constant (ordinary dielectric), but it is preferably an oxide of the metal that constitutes the metal oxide of the ferroelectric layer. For example, when the ferroelectric layer 1 is a yttrium-doped hafnium-based metal oxide (Y-HfO2; relative dielectric constant 25), yttrium silicate (YSio), hafnium silicate (HfSiO), yttrium oxide (Y2O3), etc. are preferable. Further, hafnium aluminate (HfAlO), yttrium aluminate YAlO3 (relative dielectric constant 16), lanthanum aluminate LaAlO3 (relative dielectric constant 25), yttrium-stabilized zirconia YSZ (relative dielectric constant 27) are also suitable.

[0081] The thickness of the interface layer 5 is not limited, but is preferably 4 nm or less, and may further be 2 nm or less, 1.5 nm or less, or 1 nm or less. Also, as long as the film thickness of the interface layer 5 has a dielectric constant higher than that of silicon, even a thin film is effective, and for example, it may be 0.2 nm or more. Further, it may be 0.3 nm or more and 0.5 nm or more. Since the interface layer 5 is a layer having a large dielectric constant in order to apply a sufficient voltage to the ferroelectric layer 1, a layer thickness for that purpose is sufficient. On the other hand, since the interface layer 5 is an insulating material, it is preferably a layer thickness that does not significantly impair conductivity.

[0082] The interface layer 5 preferably contacts the first conductive layer (lower electrode) 2 directly. However, since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode) 2, in that case, the surface oxide film may be considered as a part of the interface layer 5. When considering the surface oxide film as a part of the interface layer 5, the interface layer 5 is not a single-layer film but is composed of a multilayer film (composite film). However, as long as the portion other than the surface oxide film has a dielectric constant higher than that of silicon oxide and the composite film as a whole has a dielectric constant higher than that of silicon oxide. Needless to say, the main body of the interface layer itself other than the surface oxide film may also be a multilayer film.

[0083] The interface layer preferably has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side. Thereby, an effect of suppressing the generation of oxygen defects in the ferroelectric layer is expected.

[0084] Also, even if it is not the metal itself that constitutes the metal oxide of the ferroelectric layer, as the metal that constitutes the hafnium-based metal oxide containing an additive metal, the above-described metals, that is, hafnium (Hf), zirconium (Zr), cerium (Ce), aluminum (Al), silicon (Si), strontium (Sr), barium (Ba), or oxides or silicates of rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) may be used. The interface layer 5 may be an oxide of the metal that constitutes the hafnium-based metal oxide or a high dielectric (normal dielectric) that does not exhibit ferroelectricity. Such an interface layer 5 has chemical similarity to the ferroelectric layer 1, can have excellent interface characteristics, and can also have excellent film quality of the ferroelectric layer.

[0085] The ferroelectric layer 1 of Example 2 exhibits ferroelectricity. A ferroelectric is a substance in which electric dipoles are aligned even without an external electric field and the direction of the dipoles can be changed by an electric field. When a memory element is configured using a ferroelectric, polarization is retained even when no electric field is applied, so that a non-volatile memory element can be configured and power consumption can be reduced. Also, data rewriting of the ferroelectric memory element is of the voltage type performed by applying an electric field, and since the write and erase currents are significantly smaller compared to the current type, power consumption can be reduced.

[0086] In Example 2, the ferroelectric layer 1 is a ferroelectric layer made of a metal oxide. The ferroelectric layer 1 is preferably a ferroelectric composed of a metal oxide having a fluorite-type orthorhombic phase. In particular, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, preferably hafnium (Hf), zirconium (Zr) or two of these elements, whether doped or undoped, can form a ferroelectric showing a fluorite-type orthorhombic phase, so it is suitable. Even when undoped, a ferroelectric can be formed by oxygen vacancies. Furthermore, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, preferably hafnium (Hf), zirconium (Zr) or two of these elements, and at least one metal element selected from the group consisting of aluminum (A1), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) is suitable.

[0087] In hafnium-based metal oxides, the main metal oxides may be simple oxides such as hafnium oxide, zirconium oxide, and cerium oxide, or solid solutions between these metal oxides. When the hafnium-based metal oxide contains a dopant metal, the amount of the dopant metal depends on the types of the main metal oxide and the dopant metal, but it may be an amount that forms a ferroelectric. Generally, the number of moles of the dopant metal, with the total of the metals in the entire metal oxide containing the dopant metal being 100 mol%, is preferably 10 mol% or less, more preferably 0.1 to 10%, and may also be 4 to 9 mol%.

[0088] For example, typical hafnium-based ferroelectric materials include Y-doped HfO 2、 Si-doped HfO 2、 Al-doped HfO 2、 La-doped HfO2, and HZO (Hf 0.5 Zr 0.5 O2), etc.

[0089] The ferroelectric layer 1 may be a crystal that exhibits ferroelectricity, which may be polycrystalline, an uniaxially oriented crystal thin film, or even an epitaxial film.

[0090] The film thickness of the ferroelectric layer 1 is not particularly limited because a suitable film thickness is adopted according to the application of the non-volatile memory element. For example, it may be 1 nm or more, further 5 nm or more, 10 nm or more. Also, the upper limit is not restricted, and it may be 5 μm or less, 3 μm or less, 1 μm or less, for example. In a preferred embodiment, the film thickness of the ferroelectric layer 1 may be 1 nm to 100 nm, more preferably 1 nm to 50 nm, still more preferably 2 nm to 10 nm or 2 nm to 5 nm. The above-mentioned hafnium-based metal oxides exhibit excellent ferroelectricity even at a thin film thickness of 20 nm or less compared with conventional ferroelectrics such as PZT, so they are scalable and suitable as a ferroelectric layer for non-volatile memory elements.

[0091] The first conductive layer 2 and the second conductive layer 3 act as electrodes for applying a voltage to the ferroelectric layer 1 and can be made of metal, conductive ceramics, conductive semiconductors, etc. Metals include tungsten, titanium, gold, silver, copper, platinum, aluminum, etc. Conductive ceramics include conductive nitrides such as titanium nitride (TiN), conductive silicides such as nickel disilicide (NiSi2), conductive oxides such as indium tin oxide (ITO), and pyrochlore structures such as Bi2Ru2O7 and rare earth iridium oxides R2Ir2O7 (R is a rare earth element). Also, doped or intrinsic silicon semiconductors, various compound semiconductors, etc. can be cited as conductive semiconductors. The first conductive layer 2 and the second conductive layer 3 only need to be electrically connected to the ferroelectric layer 1. Also, as the conductive layer (upper electrode) formed on the ferroelectric layer 1, tungsten, TiN, and a multilayer electrode of TiN / W are preferred.

[0092] The first conductive layer serving as a substrate for depositing the ferroelectric layer is preferably a metal silicide or metal disilicide having a fluorite structure, or a metal nitride, or Si or Ge containing impurities, or SOI (Silicon on Insulator). When the (first) conductive layer serving as a substrate is nickel disilicide (NiSi2) having a fluorite structure, it is preferable because the crystal quality of the hafnium-based metal oxide deposited thereon can be excellent.

[0093] In one preferred embodiment, the first conductive layer 2 and the second conductive layer 3 may be formed with a conductive material having an oxygen barrier property that suppresses oxygen migration on the interface side with the ferroelectric layer 1, particularly on the interface side of the second conductive layer (upper electrode) 3 with the ferroelectric layer 1 when the second conductive layer 3 is formed on the ferroelectric layer 1. For example, tungsten (W) or the like may be used as a barrier layer. By the first conductive layer 2 and the second conductive layer 3 having a barrier layer, there are effects of suppressing oxygen ions from leaking from the ferroelectric layer 1 to generate oxygen defects and preventing leakage current, and improving the performance of the non-volatile memory element of the present invention. The thickness of the barrier layer is preferably 0.1 nm or more, and may further be 0.5 nm or more, 1 nm or more, 1.5 nm or more. Also, the film thickness of the buffer layer 4 is desirably 10 nm or less, and may further be 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less.

[0094] In the non-volatile memory element of the present invention, a buffer layer 4 having oxygen ion conductivity exists between the ferroelectric layer 1 and the second conductive layer 3. The buffer layer 4 is made of a paraelectric material (insulator material) of a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity. Since the buffer layer 4 is an insulator material of a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity, it can supply and receive, particularly supply, oxygen ions with the ferroelectric layer 1, and has a function of preventing or repairing oxygen defects caused by electric field stress during data rewriting at the interface between the ferroelectric layer 1 or the ferroelectric layer 1 and the conductive layer, thereby reducing leakage current, improving ferroelectric characteristics, reducing the anti-electric field, and improving rewriting characteristics, etc., and exhibiting excellent effects.

[0095] The chemical potential of oxygen in the buffer layer 4 is preferably higher than the chemical potential of oxygen in the ferroelectric layer 1. The oxygen vacancy defect density in the buffer layer 4 is preferably lower than the oxygen vacancy defect density in the ferroelectric layer 1. When the chemical potential of oxygen in the buffer layer 4 is higher than the chemical potential of oxygen in the ferroelectric layer 1, or when the oxygen vacancy defect density in the buffer layer 4 is lower than the oxygen vacancy defect density in the ferroelectric layer 1, oxygen ions can easily move from the buffer layer 4 into the ferroelectric layer 1, and the amount of oxygen defects at the interface between the ferroelectric layer 1 or the ferroelectric layer 1 and the conductive layer can be controlled.

[0096] Examples of the dielectric material (insulating material) of metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity in the buffer layer 4 include, for example, cerium oxide film CeO x (x = 1.5 - 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0). In addition, zirconium oxide film, titanium oxide film, yttria-stabilized zirconia film or rare earth element oxide film, etc. are applicable.

[0097] The film thickness of the buffer layer 4 is preferably 0.1 nm or more, and may further be 0.5 nm or more, 1 nm or more, 1.5 nm or more. Also, the film thickness of the buffer layer 4 is desirably 10 nm or less, and may further be 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less.

[0098] Regarding the electrical characteristics of the non-volatile memory element of Example 2 of the present invention, for the effects of having the buffer layer 4, FIGS. 4 to 9 in Example 1 can be referred to. FIGS. 15 to 20 show additional electrical characteristics of the non-volatile memory element of Example 2 (TiN / CeO2(4 nm) / Y-HfO2(9 nm) / IL(Y2O3; 2 nm) / NiSi2) annealed for activation at 350 °C after deposition). Also, the upper electrode is effective in the case of a TiN / W multi-layer electrode.

[0099] FIG. 15 shows the current-voltage characteristics of the ferroelectric capacitor element evaluated by the microcurrent measurement device. When the interface layer is inserted, the leakage current is reduced even on the high voltage side and the breakdown voltage of the element is increased as compared with the control example (Example 1) without the interface layer.

[0100] FIG. 16 shows the thickness dependence of the CeO x (x = 1.5 - 2.0) layer of the leakage current measured under the same conditions. The leakage current is reduced at all CeO x (x = 1.5 - 2.0) layer thicknesses as compared with the control example (Example 1), indicating the effectiveness of the interface layer of the buffer layer structure.

[0101] FIG. 17 shows the rewriting characteristics of the ferroelectric capacitor element measured at a voltage of 4.5 V and 1 MHz. The activation annealing is at 350°C. It was confirmed that the residual polarization width 2Pr after 10 10 rewriting cycles is increased as compared with the control example (Example 1).

[0102] FIG. 18 shows the room temperature data holding characteristics of the ferroelectric element after 10 10 rewriting cycles. The spontaneous polarization Pr window width is almost constant with respect to time within the measurement time, and good data holding characteristics are obtained. Further, as a result of performing room temperature extrapolation, a sufficient spontaneous polarization window width is obtained even after 10 years, and it is estimated that the readout of the written data is maintained at a possible level even after 10 years, and a prospect of a data holding time of 10 years is obtained.

[0103] FIG. 19 shows the data rewriting characteristics measured under the conditions of a voltage of 4.5 V and 1 MHz, and the residual polarization width 2Pr = 11 μC / cm 2 or more, and 10 11 rewriting cycles have been achieved.

[0104] FIG. 20 shows the data rewriting characteristics measured at a voltage condition of an electric field of 2 MV / cm and 2 MHz. In FIG. 20, the Pr window width is almost constant with respect to the number of rewritings, and the narrowing is small, and 10 12 or more data rewriting cycles have been achieved.

[0105] The features of the non-volatile memory element in Example 2 are common matters in the memory elements and memory devices of other embodiments of the present invention as long as the non-volatile memory element includes an interface layer.

[0106] (Manufacturing method of the non-volatile memory element of Example 2) In the non-volatile memory element of Example 2, the configuration other than the interface layer 5 and its manufacturing method can be the same as those of the non-volatile memory element of Example 1. Since the interface layer 5 is a ferroelectric (insulator), particularly an oxide, it can be formed by general deposition methods for ferroelectrics and oxides, such as sputtering, evaporation, CVD, PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition).

[0107] As an example of the non-volatile memory element of Example 2, after cleaning the surface of the Si semiconductor base layer formed on the surface of the Si semiconductor substrate by pre-sputtering in an argon atmosphere for 30 minutes, nickel (Ni) is deposited on the Si semiconductor base layer by sputtering, and then the Si semiconductor substrate is heated to 350 °C in an argon atmosphere to silicidize the nickel (Ni) on the Si semiconductor base layer, thereby forming the first conductive layer (lower electrode) 2 of nickel disilicide (NiSi2). Next, on the first conductive layer 2, yttrium oxide (Y2O3) is deposited as the interface layer 5 with a layer thickness of 2 nm by sputtering in an argon atmosphere.

[0108] On the semiconductor substrate on which the interface layer 5 was formed, the Y7%-HfO2 layer was deposited by the method described in Patent Document 1. In a sputtering apparatus, after evacuating the inside of the vacuum chamber, with the semiconductor substrate temperature at room temperature (25°C), in an argon atmosphere with an argon flow rate of 100 sccm, oxygen 0 sccm, and a pressure of 50 mTorr, a voltage was applied between the semiconductor substrate and the target (Y7%-HfO2), and the Y7%-HfO2 layer 1 was deposited on the first conductive layer 2 of the semiconductor substrate to a thickness of 10 nm at a power of 50 W. After deposition, the Y7%-HfO2 layer 1 was subjected to X-ray diffraction analysis respectively, and it was confirmed that all the Y7%-HfO2 thin films were polycrystalline, were fluorite-type orthorhombic crystals, and were ferroelectrics.

[0109] Next, on the Y7%-HfO2 layer 1, a CeO x (x = 1.5 - 2.0) film was deposited to a thickness of 2 - 6 nm by electron beam evaporation to form the buffer layer 4. Next, a TiN layer (upper electrode) 3 was sputter-deposited on the buffer layer 4. Thereafter, activation annealing treatment (AA treatment) was performed at 200°C to 400°C. The additional electrical characteristics of the obtained ferroelectric memory element are shown in FIGS. 15 to 20. The comparative examples shown in FIGS. 15 to 20 are Example 1.

[0110] One preferred example of the manufacturing method of the non-volatile memory element of Example 2 will be described with reference to FIG. 21. In this example, by continuously depositing the interface layer 5, the ferroelectric layer 1, and the buffer layer 4 of the ferroelectric capacitor by atomic layer deposition (ALD), excellent commercial productivity can be achieved. However, the example in FIG. 21 does not limit the manufacturing method of the non-volatile memory element of Example 2, and the types of materials, layer thicknesses, film formation conditions, etc. can be appropriately changed.

[0111] Referring to FIG. 21, the lower electrode 2 made of titanium nitride (TiN), which may itself be a substrate or be formed on top of another substrate, is used as the substrate. By atomic layer deposition (ALD), first, adsorption is performed by irradiating the surface of the Si semiconductor substrate multiple times with (iPrCp)3Y as the yttrium source, and then oxidation is performed in sequence with a mixed gas of plasma-oxygen and argon, thereby depositing yttrium oxide (Y2O3). By performing this cycle multiple times, an interface layer 5 of 1 nm is deposited. Next, also by ALD, TDMAH is adsorbed onto the Y2O3 film of the interface layer 5 as the hafnium source, and oxidation is performed with a mixed gas of plasma-oxygen and argon, and this cycle is repeated to deposit a hafnium oxide film. During this process, an yttrium oxide film is inserted by adsorbing yttrium atoms by irradiating multiple times with (iPrCp)3Y as the yttrium source and then oxidizing with irradiation of a mixed gas of plasma-oxygen and argon, thereby depositing a ferroelectric 1 made of 5% yttrium-doped hafnium oxide (Y5%-HfO2) of 7.5 nm. Further, also by ALD, adsorption onto the 5% yttrium-doped hafnium oxide film with (iEtCp)3Ce as the cerium source and the cycle of oxidation with a mixed gas of plasma-oxygen and argon are repeated to deposit a buffer layer 4 made of cerium oxide (CeOx; x = 1.6 to 1.9) of 1 nm. Then, a tungsten layer 3-2 of 5 nm and a titanium nitride (TiN) layer 3-1 of 30 nm are deposited on the buffer layer 4 by sputtering to form a multilayer second conductive layer 3 made of TiN / W.

[0112] The features in the manufacture of the nonvolatile memory element of Example 2 are common matters in the manufacture of the memory elements and memory devices of other embodiments of the present invention as long as the nonvolatile memory element includes an interface layer. In particular, a ferroelectric layer composed of a hafnium-based metal oxide can be formed at a temperature of 400°C or lower, preferably lower than 300°C. When the deposited ferroelectric layer is subjected to activation annealing at a temperature of 400°C or lower, the characteristics of the ferroelectric layer and the ferroelectric memory element can be improved. In particular, since the activation annealing can be preferably performed at a temperature of 400°C or lower, it can be preferably performed after manufacturing the memory element and the memory device. It is particularly suitable when the memory element and the memory device include copper wiring or an impurity diffusion semiconductor region.

[0113] 〔Example 3; Memory Cell and Memory Cell Array〕 Example 3 of the present invention provides a semiconductor memory device including a memory cell in which a ferroelectric memory element is combined with a transistor. For example, it includes a 1-transistor type memory cell (1T type FeRAM) FeFET, a 1-transistor 1-memory cell (1T type 1C type FeRAM), a 2-transistor 2-memory cell (2T type 2C type FeRAM), and a memory cell array in which these memory cells are arranged two-dimensionally or three-dimensionally, such as a NOR type memory cell array. Further, it may include peripheral circuits such as a control circuit for controlling the memory cell array.

[0114] (First Embodiment: 1T Type Memory Cell) The semiconductor memory device according to the first embodiment of Example 3 is a 1-transistor memory cell (1T-type FeRAM) FeFET. This semiconductor memory device (1-transistor memory cell) has, for example, a semiconductor layer (first conductive layer), an upper electrode (second conductive layer), and a ferroelectric layer composed of a metal oxide between the semiconductor layer which is the first conductive layer and the upper electrode which is the second conductive layer. There is a buffer layer which is a metal oxide having oxygen ion conductivity between the ferroelectric layer and the upper electrode and containing a metal having a plurality of valences. Preferably, there is an interface layer composed of a single-layer film or a multilayer film between the ferroelectric layer and the semiconductor layer. The interface layer has a dielectric constant higher than that of silicon oxide as a whole. The semiconductor layer exists below the ferroelectric layer and, if present, the interface layer. The upper electrode serves as a gate electrode, and the ferroelectric layer and, if present, the interface layer serve as a gate insulating film. It is characterized by having a channel below the gate insulating film of the semiconductor layer, and a source (region) and a drain (region) on both sides thereof. In this semiconductor memory device, the source region or the drain region of the semiconductor layer is the first conductive layer, but the source region or the drain region can be connected to a so-called source electrode or drain electrode, and in some cases, the source electrode or the drain electrode is referred to as a lower electrode.

[0115] Examples of the 1-transistor memory cell are schematically shown in cross-sectional views in FIGS. 22(a) and (b). FIG. 17(a) shows an example where the interface layer 5 does not exist, and FIG. 22(b) shows an example where the interface layer 5 exists. In FIGS. 22(a) and (b), 1 is a ferroelectric layer, 2s is a semiconductor layer (first conductive layer), 3g is a gate electrode (second conductive layer), 4 is a buffer layer, 5 is an interface layer, 6 is a source (region), and 7 is a drain (region). Source electrodes 6e and drain electrodes 7e may be provided on the source (region) 6 and the drain (region) 7 of the semiconductor layer 2s, respectively. In FIG. 22(b), the buffer layer 4 is between the ferroelectric layer 1 and the gate electrode (second conductive layer) 3g, but may be between the interface layer 5 and the ferroelectric layer 1, or may be in both of them. Hereinafter, the description will be mainly based on the 1-transistor memory cell in which the buffer layer 4 is between the ferroelectric layer 1 and the gate electrode (second conductive layer) 3g, but it will be appropriately changed for the case where the buffer layer 4 is between the interface layer 5 and the ferroelectric layer 1.

[0116] This one-transistor memory cell is a field-effect transistor (FET) using a ferroelectric layer as a gate insulating film. The conductance of the channel of the FET is controlled by the direction of polarization of the ferroelectric layer, and the state of the threshold voltage (Vth) of the FET is memorized by controlling the remnant polarization of the ferroelectric. The operating principle is shown in FIGS. 23(a) and (b). After applying positive and negative pulse voltages to the gate, the polarization direction of the ferroelectric layer constituting the gate insulating film can be polarized in one direction, and the direction of polarization differs depending on whether the voltage applied to the gate is positive or negative. In the direction of polarization in FIG. 23(a), the Vth of the FET shifts in the positive direction (Vth1) relatively due to the negative charges at the gate insulating film and semiconductor interface. On the other hand, in the direction of polarization in FIG. 23(b), the Vth shifts in the negative direction (Vth2) relatively due to the positive charges at the gate insulating film and semiconductor interface. Here, when the read voltage (Vr) is set to an intermediate voltage between Vth1 and Vth2, since Vth2 < Vthr < Vth1, a channel is formed in the Vth2 state and the current of the FET flows, while the current does not flow in the Vth1 state. Therefore, the threshold voltage of the FeFET changes depending on the direction of polarization in FIGS. 23(a) and (b). Thus, the on-state and off-state of the FET can be realized at the same gate voltage depending on the direction of polarization of the ferroelectric gate insulating film, and information can be memorized. When the drain current-gate voltage characteristics of this transistor are illustrated, a hysteresis characteristic as shown in FIG. 23(c) is obtained. This hysteresis characteristic indicates that the threshold voltage of the transistor changes due to the polarization of the ferroelectric. The shift amount of the threshold voltage (the width of the hysteresis in the drain current-gate voltage characteristics) is called the memory window, and it can be seen that two or more values of the drain current can be taken for the voltages within this memory window.

[0117] The memory element of this one-transistor memory cell is a ferroelectric memory element, which enables non-volatile memory by applying an electric field, so that power consumption can be reduced. The ferroelectric layer 1 is preferably a ferroelectric layer made of a fluorite-type orthorhombic metal oxide. The metal oxide of the ferroelectric layer 1 is preferably a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, particularly hafnium (Hf), zirconium (Zr) or a metal oxide containing these two elements. Also, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, particularly hafnium (Hf), zirconium (Zr) or these two elements, and at least one metal element (additive element) selected from the group consisting of aluminum (A1), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) is suitable.

[0118] When the hafnium-based metal oxide contains an additive metal, the amount of the additive metal may be any amount that forms a ferroelectric, and generally, the number of moles of the additive metal is preferably 10 mol% or less, more preferably 0.1 to 10%, and may also be 4 to 9 mol% with respect to the total of the metals in the entire metal oxide containing the additive metal as 100 mol%.

[0119] The film thickness of the ferroelectric layer 1 is not particularly limited because a suitable film thickness is adopted according to the use of the non-volatile memory element. However, in a preferred embodiment, the film thickness of the ferroelectric layer 1 may be 1 nm to 100 nm, more preferably 2 nm to 50 nm, further 2 nm to 20 nm or 2 nm to 5 nm. The hafnium-based metal oxide exhibits excellent ferroelectricity even at a thin film thickness of 10 nm or less compared with conventional ferroelectrics such as PZT, so it is scalable and suitable as a ferroelectric layer for non-volatile memory elements.

[0120] The second conductive layer 3 acts as an electrode for applying a voltage to the ferroelectric layer 1 and can be made of metal, conductive ceramics, conductive semiconductors, etc. Metals include tungsten, titanium, gold, silver, copper, platinum, aluminum, etc. Conductive ceramics include conductive nitrides such as titanium nitride (TiN), conductive silicides such as nickel disilicide (NiSi2), and conductive oxides such as indium tin oxide (ITO). Further, the conductive layer (semiconductor layer 2s) on the side opposite to the second conductive layer 3 may be a doped or intrinsic semiconductor, and examples thereof include silicon and compound semiconductors.

[0121] In this semiconductor memory device, there is a buffer layer 4 having oxygen ion conductivity between the ferroelectric layer 1 and the gate electrode 3g. The buffer layer 4 is made of a paraelectric material (insulating material) of a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity. By being a paraelectric material (insulating material) of a metal oxide containing a metal having oxygen ion conductivity and a plurality of valences, the buffer layer 4 has a function of preventing or repairing oxygen defects due to electric field stress during data rewriting at the ferroelectric layer 1 or at the interface between the ferroelectric layer 1 and the conductive layer, thereby reducing the leakage current, improving the ferroelectric characteristics, reducing the anti-electric field, and improving the rewriting characteristics, etc., and exhibits excellent effects.

[0122] The chemical potential of oxygen in the buffer layer 4 is large preferably lower than that of oxygen in the ferroelectric layer 1. The oxygen vacancy defect density of the buffer layer 4 is preferably smaller than that of the ferroelectric layer 1. When the chemical potential of oxygen in the buffer layer 4 is large lower than that of oxygen in the ferroelectric layer 1, or the oxygen vacancy defect density of the buffer layer 4 is smaller than that of the ferroelectric layer 1, oxygen ions can easily move from the buffer layer 4 into the ferroelectric layer 1, and oxygen defects at the ferroelectric layer 1 or at the interface between the ferroelectric layer 1 and the conductive layer can be prevented or repaired.

[0123] As the ferroelectric material (insulating material) of the buffer layer 4 that exhibits oxygen ion conductivity and contains a metal having multiple valences, for example, a cerium oxide film (CeO x ;x = 1.5 - 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0), in addition to this, a zirconium oxide film, a titanium oxide film, a yttria-stabilized zirconia film, or a rare earth element oxide film, etc. can be applied.

[0124] The film thickness of the buffer layer 4 is preferably 0.1 nm or more, and may further be 0.5 nm or more, 1 nm or more, 1.5 nm or more. Also, the film thickness of the buffer layer 4 is desirably 10 nm or less, and may further be 6 nm or less, 5 nm or less, 4 nm or less, 3 nm or less.

[0125] Also, in a preferred embodiment of this semiconductor memory device, further, an interface layer 5 composed of a single-layer film or a multilayer film is provided between the semiconductor layer 2s (first conductive layer; lower electrode) and the ferroelectric layer 1, and the interface layer 5 has a dielectric constant higher than that of silicon oxide as a whole interface layer. However, when the buffer layer 4 exists between the ferroelectric layer 1 and the semiconductor layer 2s (first conductive layer; lower electrode), the interface layer 5 exists between the semiconductor layer 2s (first conductive layer; lower electrode) and the buffer layer 4. By the presence of the interface layer 5 between the ferroelectric layer 1 and the semiconductor layer 2s, compared with the case where the interface layer 5 does not exist, Among the voltages applied between the two electrodes (first and second conductive layers) during data rewriting, a higher partial voltage is applied to the ferroelectric layer 1, so that a sufficient voltage capable of causing polarization reversal in the ferroelectric layer 1 can be applied with a smaller inter-electrode voltage.

[0126] The interface layer 5 is preferably made of a high dielectric material and has a dielectric constant greater than that of a silicon oxide film (relative dielectric constant of about 3.9), and particularly desirably is a high dielectric material having a dielectric constant equal to or greater than that of a silicon nitride film (relative dielectric constant of about 7.8). Also, it is particularly preferably an oxide film or a silicate film. The dielectric constant of the interface layer 5 is preferably greater than about 3.9 in terms of relative dielectric constant, and more preferably about 5 or more, about 7.8 or more.

[0127] The interface layer 5 is preferably in direct contact with the first conductive layer (lower electrode) 2. However, since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode) 2, in that case, the surface oxide film may be considered as part of the interface layer 5. When considering the surface oxide film as part of the interface layer 5, the interface layer 5 is not a single-layer film but is composed of a multilayer film (composite film). As long as the part other than the surface oxide film has a higher dielectric constant than silicon oxide and the composite film as a whole has a higher dielectric constant than silicon oxide, it is sufficient. Needless to say, the main body of the interface layer other than the surface oxide film itself may also be a multilayer film.

[0128] The interface layer 5 preferably has a function of suppressing the oxygen migration from the ferroelectric layer 1 to the first conductive layer 2 side. Thereby, an effect of suppressing the generation of oxygen defects in the ferroelectric layer 1 is expected.

[0129] The interface layer 5 is preferably an oxide of the metal constituting the metal oxide of the ferroelectric layer. For example, when the ferroelectric layer 1 is a yttrium-doped hafnium-based metal oxide (Y-HfO2), yttrium silicate (YSio), hafnium silicate (HfSiO), yttrium oxide (Y2O3), etc. are preferable. Also, even if it is not the metal itself constituting the metal oxide of the ferroelectric layer, as the metal constituting the hafnium-based metal oxide containing an additive metal, the above-mentioned metals, that is, hafnium (Hf), zirconium (Zr), cerium (Ce), aluminum (Al), silicon (Si), strontium (Sr), barium (Ba), or oxides or silicates of rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) may be used. With such an interface layer 5, there is chemical similarity to the ferroelectric layer 1, the characteristics of the interface can be excellent, and the film quality of the ferroelectric layer can also be excellent.

[0130] The semiconductor layer 2s, the source (region) 6, and the drain (region) 7 may have any configuration used in a conventional gate-insulated film type transistor. For example, the semiconductor layer 2s is a p-type silicon semiconductor doped with P, As, etc., and the source (region) 6 and the drain (region) 7 may be n + type doped regions doped with B or the like at a high concentration.

[0131] The present invention has a unique effect of being able to realize reduction of leakage current, improvement in reliability, particularly improvement in data rewriting characteristics in a ferroelectric memory 1 transistor memory cell. Further, in the case of operating in the direction of reducing the threshold voltage (Vth) by applying a positive voltage to the gate electrode, which is a unique problem of the reliability of the 1 transistor memory cell, electrons are injected from the channel region of the memory transistor into defects in the ferroelectric layer or the interface. It also has the effect of being able to reduce this phenomenon by optimizing the interface layer film thickness and interface characteristics. Further, although the memory transistor has been described by taking an nMOS transistor as an example, it goes without saying that by applying the present invention to a pMOS memory transistor, the same reliability as that of the nMOS transistor, particularly the effect of improving the data rewriting characteristics, can be obtained.

[0132] One preferred example of the memory cell of Example 3 will be described with reference to FIG. 22(b). In this example, the interface layer 5, the ferroelectric layer 1, and the buffer layer 4 are continuously deposited by atomic layer deposition (ALD), so that excellent commercial productivity can be achieved. However, this example does not limit the non-volatile memory element and its manufacturing method of Example 3, and the type of material, layer thickness, film formation conditions, etc. can be appropriately changed.

[0133] This example has a three-layer element structure of a buffer layer / ferroelectric layer / interface layer as shown in FIG. 22(b). Specifically, it is a transistor type memory cell (FeFET) having a structure composed of a gate electrode (upper electrode) 3g of a TiN / W multilayer structure / a buffer layer 4 of CeOx / a ferroelectric 1 of Y5%-HfO2 / an interface layer 5 of Y-Silicate (Y2Si2O7) / a lower electrode 2 including a source region 6 and a drain region 7 in a Si semiconductor substrate 2s.

[0134] Using an Si semiconductor substrate 2s in which a source region 6 and a drain region 7 are formed by a CMOS process as a substrate, first, by atomic layer deposition (ALD), adsorption by irradiating the surface of the Si semiconductor substrate with (iPrCp)3Y as a yttrium source a plurality of times and oxidation with a mixed gas of plasma-oxygen and argon are performed in order to deposit yttrium oxide (Y2O3). By performing this cycle a plurality of times, 1 nm of the interface layer 5 is deposited. Next, also by ALD, tetrakis(dimethylamino)hafnium (TDMAH) is adsorbed on the Y2O3 film of the interface layer 5 as a hafnium source, and oxidation is performed with a mixed gas of plasma-oxygen and argon, and by repeating this cycle, a hafnium oxide film is deposited. In the middle, by inserting a yttrium oxide film by adsorption of yttrium atoms by irradiating (iPrCp)3Y as a yttrium source a plurality of times and oxidation by irradiating a mixed gas of plasma-oxygen and argon, 7.5 nm of a ferroelectric body 1 made of 5% yttrium-doped hafnium oxide (Y5%-HfO2) is deposited. Further, also by ALD, by repeating the cycle of adsorption of (iEtCp)3Ce as a cerium source on the 5% yttrium-doped hafnium oxide film and oxidation with a mixed gas of plasma-oxygen and argon, 1 nm of a buffer layer 4 made of cerium oxide (CeOx; x = 1.6 to 1.9) is deposited. Then, a tungsten layer 3-2 of 5 nm and a titanium nitride (TiN) layer 3-1 of 30 nm are deposited on the buffer layer 4 by sputtering to form a multilayer second conductive layer 3 made of TiN / W.

[0135] Next, a stacked structure of a gate electrode (upper electrode) 3g / Ce0x buffer layer 4 / Y5%-HfO2 ferroelectric body 1 / Y-Silicate (Y2Si2O7) interface layer 5 having a TiN / W multilayer structure formed on the Si semiconductor substrate 2s is patterned by a reactive ion etching method to form a gate electrode on the channel region between the source region 6 and the drain region 7 formed on the Si semiconductor substrate 2s. Further, a source-drain electrode material is formed on the Si semiconductor substrate 2s and patterned by a reactive ion etching method to form a source electrode 6e and a drain electrode 7e.

[0136] After forming the source electrode 6e and the drain electrode 7e, post-annealing is performed at 500 °C for 1 minute in a forming gas atmosphere to activate the ferroelectric 1. The activation annealing of the ferroelectric 1 may be performed immediately after depositing the ferroelectric 1, but by performing it after forming the buffer layer 4 and further after forming the gate electrode 3g, the quality of the laminated structure of the interface layer 5, the ferroelectric 1, and the buffer layer 4 can also be improved.

[0137] Matters described in the manufacturing methods of the non-volatile memory elements of Example 1 and Example 2 are also common matters in the manufacturing method of the semiconductor memory device of the first embodiment of Example 3. In particular, it is effective when forming the ferroelectric memory transistor in the back end instead of the front end. A ferroelectric layer composed of a hafnium-based metal oxide can be formed at a temperature of 400 °C or lower, preferably less than 300 °C. When the deposited ferroelectric layer is subjected to activation annealing or activation annealing (AA annealing) at a temperature of 400 °C or lower, the characteristics of the ferroelectric layer and the ferroelectric memory element can be improved. In particular, AA annealing may be performed at a temperature of 400 °C or lower, so it can be preferably performed after manufacturing the memory element and the memory device. It is suitable when the memory device includes copper wiring or an impurity-diffused semiconductor region. However, in the first embodiment of Example 3, the activation annealing for phase-transitioning the ferroelectric layer composed of a hafnium-based metal oxide to ferroelectricity is not limited to 400 °C or lower, and it may be performed at a temperature of 400 °C or higher. In particular, when forming a transistor-type memory cell (FeFET) in the front end, the temperature of the activation annealing for phase-transitioning the metal oxide film to the ferroelectric layer may be 400 °C or higher.

[0138] (Second Embodiment: 1T1C-Type Memory Cell) The semiconductor memory device of the second embodiment of Example 3 is a 1-transistor 1-capacitor memory cell (1T1C type FeRAM) FeFET, and a memory cell is composed of one ferroelectric capacitor (ferroelectric memory element) and one selection transistor. The ferroelectric capacitor has at least a first conductive layer, a ferroelectric layer composed of a metal oxide, a second conductive layer, and a buffer layer which has oxygen ion conductivity and contains a metal having a plurality of valences and exists between the ferroelectric layer and the first conductive layer and / or the second conductive layer. Preferably, there is an interface layer composed of a single-layer film or a multilayer film between the ferroelectric layer and the first conductive layer. The interface layer has a dielectric constant higher than that of silicon oxide as a whole. When a buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer exists between the first conductive layer and the buffer layer. The selection transistor is characterized by being a transistor including a source, a drain, and a gate or a bipolar diode.

[0139] Fig. 24(a) schematically shows an example of a one-transistor one-capacitor memory cell in a cross-sectional view. In Fig. 24(a), 1 is a ferroelectric layer, 2b is a lower electrode (first conductive layer), 3u is an upper electrode (second conductive layer), 4 is a buffer layer, 5 is an optional interface layer (the interface layer may not be present), and these constitute a ferroelectric capacitor FC. 6 is a source region, 7 is a drain region, 8 is a gate electrode, and 8i is a gate insulating film, and these constitute a selection transistor ST. The first conductive layer 2 (or the second conductive layer 3) of the ferroelectric capacitor FC and the source region 6 (or the drain region 7) of the selection transistor ST are electrically connected by wiring. 11 is a semiconductor layer, 12 is an element isolation film (shallow trench isolation), and 13 is an interlayer insulating film. Needless to say, element isolation may also be performed using LOCOS isolation or other element isolation techniques. Also, regarding the plug on the drain diffusion layer and the structure of the ferroelectric capacitor, although it has a structure (off-plug structure) in which the ferroelectric capacitor is not disposed directly above the plug, an on-plug structure in which the ferroelectric capacitor is disposed directly above the plug may also be used. In Fig. 24(a), the buffer layer 4 of the ferroelectric capacitor FC is between the ferroelectric layer 1 and the upper electrode 3u, but it may be between the ferroelectric layer 1 and the interface layer 5, or it may be present in both of them. Hereinafter, a one-transistor one-capacitor memory cell having a ferroelectric capacitor FC in which the buffer layer 4 is mainly between the ferroelectric layer 1 and the upper electrode 3u will be described, but it will be appropriately changed when the buffer layer 4 is between the interface layer 5 and the ferroelectric layer 1.

[0140] Referring to Fig. 24(a), for example, a p-type semiconductor layer 11 is selectively oxidized to form an element isolation film 12. In the element region between the element isolation films 12, an n + -type source region 6 and an n + -type drain region 7 are formed by selective doping. The n + -type source region 6 and the n +On the surface of the semiconductor layer 11 in the channel formation region between the type drain regions 7, a gate insulating film 8i is formed, and a gate electrode 8 is formed thereon, constituting a MIS gate transistor. Note that even if the source and drain regions have an LDD structure having a low-concentration extension region or a halo structure for suppressing the punch-through effect, which is a short-channel effect of the FET, the essence of the present invention remains unchanged. The periphery of the gate insulating film 8i and the gate electrode 10 is covered with an insulating film such as a nitride film and insulated. An interlayer insulating film 13 is formed on the semiconductor layer 11 and the gate portion. The n + -type source region 6 and the n + -type drain region 7 are each an n + -type source extraction region and an n + -type drain extraction region, and are respectively connected to the upper bit line BL and the ferroelectric capacitor FC formed by vias formed in the interlayer insulating film 13. The ferroelectric capacitor FC is formed by laminating on the interlayer insulating film 13 and is composed of a lower electrode 2b, an interface layer 5, a ferroelectric layer 1, a buffer layer 4, and an upper electrode 3u. The interface layer 5 is optional and may not be provided. The configuration of the ferroelectric capacitor FC may be the same as that of the non-volatile memory element in the first embodiment. The ferroelectric capacitor FC is covered and insulated by the second interlayer insulating film 13. Above the second interlayer insulating film 13, the lower electrode 2b is connected to the ground (plate line) PL through a via. In FIG. 24(a), the source region 6 is connected to the upper electrode 3u, but it may be connected to the lower electrode 2b and the upper electrode 3u may be connected to the ground (plate line) PL. The gate electrodes 10 of the plurality of selection transistors ST are connected to each other by a word line WL.

[0141] Referring to the circuit diagram of the one-transistor one-capacitor memory cell in FIG. 24(b), the lower electrode 2w of the ferroelectric capacitor FC is connected by wiring to the source region 6 (or drain region 7) of the selection transistor ST, and the upper electrode 3u of the ferroelectric capacitor FC is connected to the plate line PL. Also, the drain region 7 (or source region 6) of the selection transistor ST is connected to the bit line BL, and the gate electrode 8 of the selection transistor ST is connected to the word line WL.

[0142] In this one-transistor one-capacitor memory cell, a voltage is applied to the ferroelectric capacitor FC to polarize the ferroelectric body. However, by controlling the voltage applied to the gate electrode 3g of the selection transistor ST to turn on and off the current between the source and drain, and by changing the relative polarity of the voltage applied to the ferroelectric capacitor FC, the direction of polarization of the ferroelectric body can be reversed, and information can be written. Also, for information reading, the amount of charge released when a voltage pulse is applied to the ferroelectric capacitor is converted into a voltage by the capacitance of the bit line and detected. Therefore, the direction of polarization of the ferroelectric layer in the ferroelectric memory cell can be controlled by the applied voltage to perform information writing, erasing, and reading. Since the direction of polarization of the ferroelectric layer is retained even during standby, this memory cell operates as a voltage-driven non-volatile memory cell. Since the direction of polarization of the ferroelectric layer is retained even when no current is flowing, this memory cell is a voltage-driven non-volatile memory cell. By arranging a large number of one-transistor one-capacitor memory cells vertically and horizontally and connecting them to each other by the plate line PL, bit line BL, and word line WL, data can be written, erased, and read for each bit line BL, each word line WL, or each selection transistor ST selected by the bit line BL and word line WL.

[0143] Even in this one-transistor one-capacitor memory cell, since the ferroelectric capacitor FC is voltage-driven and is a non-volatile memory element, it can be a memory cell with low power consumption. According to the ferroelectric memory element of the present invention, it is a metal oxide containing a metal having oxygen ion conductivity and having a plurality of valences between the ferroelectric layer and the electrode (conductive layer). By providing a buffer layer, the rewriting characteristics can be improved, for example, by 10 11 times or more, so that even conventional volatile memories such as DRAM and SRAM can be partially replaced.

[0144] The buffer layer is made of a paraelectric material (insulating material) of a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity. Since the buffer layer is a paraelectric material (insulating material) of a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity, it has a function of controlling the amount of oxygen defects due to electric field stress during data rewriting at the interface between the ferroelectric layer or the ferroelectric layer and the conductive layer, suppressing or repairing the generation of oxygen defects, thereby reducing the leakage current, improving the ferroelectric characteristics, reducing the anti-electric field, and improving the rewriting characteristics. It exhibits excellent effects such as being able to be small. It is preferable that the chemical potential of oxygen in the buffer layer is larger than the chemical potential of oxygen in the ferroelectric layer. It is preferable that the oxygen vacancy defect density of the buffer layer is smaller than the oxygen vacancy defect density of the ferroelectric layer. When the chemical potential of oxygen in the buffer layer is larger than the chemical potential of oxygen in the ferroelectric layer, or the oxygen vacancy defect density of the buffer layer is smaller than the oxygen vacancy defect density of the ferroelectric layer, oxygen ions can easily move from the buffer layer into the ferroelectric layer, suppressing or repairing the generation of oxygen defects at the interface between the ferroelectric layer or the ferroelectric layer and the conductive layer 3. According to the ferroelectric memory element of the present invention, by providing a buffer layer having oxygen ion conductivity between the ferroelectric layer and the electrode (conductive layer), the rewriting characteristics can be improved, for example, by 10 11 times or more, so there is a possibility of replacing some functions of conventional volatile memories such as DRAM and SRAM with a low-power non-volatile memory.

[0145] Examples of the dielectric material (insulating material) of metal oxide containing a metal having a plurality of valences indicating oxygen ion conductivity of the buffer layer include, for example, cerium oxide film (CeO x ;x = 1.5 - 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0). In addition, zirconium oxide film, titanium oxide film, yttria-stabilized zirconia film or rare earth element oxide film, etc. are applicable.

[0146] The ferroelectric layer is a ferroelectric layer made of a metal oxide. The ferroelectric layer preferably contains hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, particularly a metal oxide containing hafnium (Hf), zirconium (Zr) or two of these elements. Furthermore, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, particularly hafnium (Hf), zirconium (Zr) or two of these elements, and at least one metal element selected from the group consisting of aluminum (A1), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) is preferable.

[0147] When the hafnium-based metal oxide contains an additive element, the amount of the additive element may be an amount that forms a ferroelectric. Generally, the number of moles of the added metal element is preferably 10 mol% or less, more preferably 0.1 - 10%, and may also be 4 - 9 mol% with respect to the total of the metals in the entire metal oxide containing the added metal, assuming 100 mol%.

[0148] The film thickness of the ferroelectric layer is not particularly limited as a suitable film thickness is adopted according to the application of the non-volatile memory element. However, in a preferred embodiment, the film thickness of the ferroelectric layer 1 may be 1 nm to 100 nm, more preferably 2 nm to 50 nm, still more preferably 2 nm to 20 nm, or 2 nm to 10 nm. Compared with conventional ferroelectrics such as PZT, the hafnium-based metal oxide exhibits excellent ferroelectricity even at a thin film thickness of 10 nm or less, so it is scalable and suitable as a ferroelectric layer for non-volatile memory elements.

[0149] The interface layer is composed of a single-layer film or a multilayer film and has a dielectric constant higher than that of silicon oxide as a whole. The interface layer is composed of a paraelectric and preferably has a dielectric constant greater than that of a silicon oxide film (relative dielectric constant of about 3.9), particularly preferably a high dielectric constant of 7.8 or more (relative dielectric constant) of a silicon nitride film, and particularly preferably an oxide film or a silicate film. The interface layer 5 is preferably an oxide of the metal constituting the metal oxide of the ferroelectric layer. For example, when the ferroelectric layer 1 is a yttrium-doped hafnium-based metal oxide (Y-HfO2), yttrium silicate (YSio), hafnium silicate (HfSiO), yttrium oxide (Y2O3), etc. are preferred. With such an interface layer 5, there is chemical similarity to the ferroelectric layer 1, the characteristics of the interface can be excellent, the film quality of the ferroelectric layer is also excellent, and the ferroelectric characteristics can be improved with low voltage operation. Also, the interface layer suppresses the tunnel current of electrons injected from the channel of the FeFET during writing by relatively thickening the interface layer (tunnel insulating film), and as a result, it is possible to improve the deterioration of data rewriting characteristics.

[0150] The interface layer is preferably in direct contact with the first conductive layer (lower electrode). However, since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode), in that case, the surface oxide film may be considered as part of the interface layer. When considering the surface oxide film as part of the interface layer, the interface layer is not a single-layer film but is composed of a multilayer film (composite film), provided that the composite film as a whole has a dielectric constant higher than that of silicon oxide. Needless to say, the main body of the interface layer other than the surface oxide film itself may also be a multilayer film.

[0151] The interface layer preferably has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side. Thereby, an effect of suppressing the generation of oxygen defects in the ferroelectric layer is expected.

[0152] The electrode (conductive layer) can be made of a metal such as tungsten or titanium, a conductive ceramic, a conductive semiconductor, etc. In particular, the lower electrode of the ferroelectric layer is a preferable conductive material because a conductive silicide such as nickel disilicide (NiSi2) is excellent in the film quality of the hafnium-based metal oxide formed thereon. Also, a two-layer structure electrode such as TiN / W may be used.

[0153] The matters described in the manufacturing methods of the non-volatile memory elements of Example 1 and Example 2 are also common matters in the manufacturing method of the semiconductor memory device of the second embodiment of Example 3. A ferroelectric layer composed of a hafnium-based metal oxide can be formed at a temperature of 400°C or lower, preferably less than 300°C. When the deposited ferroelectric layer is subjected to activation annealing at a temperature of 400°C or lower, the characteristics of the ferroelectric layer and the ferroelectric memory element can be improved. In particular, since the activation annealing may be performed at a temperature of 400°C or lower, it can be preferably performed after manufacturing the memory element and the memory device. However, in the second embodiment of Example 3, the activation annealing is not limited to 400°C or lower, and it may be performed at a temperature of 400°C or higher.

[0154] (Third Embodiment: 2T2C-Type Memory Cell) The semiconductor memory device of the third embodiment of Example 3 is a 2-transistor 2-capacitor memory cell (2T2C type FeRAM) FeFET, which is a 2T2C type memory cell that stores one piece of data by pairing two 1T1C memory cells.

[0155] Referring to the circuit diagram of FIG. 25(a), the 2T2C type capacitor memory cell (2T2C type FeRAM) is composed of two 1T1C type memory cells on the left and right. Each of the two 1T1C type memory cells consists of a selection transistor ST and a ferroelectric capacitor FC. The 2-transistor 2-capacitor memory cell has one word line WL and two bit lines BL (a pair). One 1T1C type memory cell that shares the word line WL is connected to one bit line BL, and the other 1T1C type memory cell is connected to one bit line / BL.

[0156] Data with different polarities are written to the paired memory cells. For example, when a residual polarization in the "positive (plus)" direction is written to the cell of one bit line BL, a residual polarization in the "negative (minus)" direction is written to the cell of the other bit line / BL. When reading data from the 2T2C type memory cell, a voltage is applied to the word line WL. Then, polarization inversion will surely occur in only one of the capacitors. Along with the polarization inversion, the voltage of either one of the bit line BL and the other bit line / BL increases. A very excellent point of the 2T2C type is that the data reading is stable and it is strong against repeated operations (long operation life). The ferroelectric material has a unique property called fatigue in which the residual polarization becomes smaller when the polarization inversion is repeated, but the 2T2C type is less likely to experience fatigue.

[0157] FIG. 25(b) shows the write operation and read operation of the 2T2C type FeRAM. In FIG. 25(b), voltages are applied to the selected memory cell to the word line WL, the plate line PL, and the two bit lines BL and / BL as shown in the figure. V1 and V2 are the voltages applied to the ferroelectric capacitor FC1 and the ferroelectric capacitor FC2, respectively. t1 to t4 represent time (time).

[0158] Since the structure of this two-transistor two-capacitor memory cell is a structure in which one-transistor one-capacitor memory cells are connected to operate complementarily, FIG. 23 can be referred to for the structure of the memory cell itself.

[0159] Since the structure of this two-transistor two-capacitor memory cell is a structure in which one-transistor one-capacitor memory cells are asymmetrically connected, each one-transistor one-capacitor memory cell is the same as the memory cell of the second embodiment, and only the way of connection (wiring) between the memory cells is different. FIG. 23 can be referred to for the structure of the memory cell itself.

[0160] Also in this two-transistor two-capacitor memory cell, since the ferroelectric capacitor is a voltage-driven and non-volatile memory element, it can be a memory cell with low power consumption. The ferroelectric memory element is a metal oxide containing a metal having oxygen ion conductivity and multiple valences between the ferroelectric layer and the electrode (conductive layer) according to the present invention. By providing a buffer layer, it is possible to significantly improve the rewriting characteristics, and even some of the conventional volatile memories such as DRAM and SRAM can be replaced.

[0161] The buffer layer is made of a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity. By being a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity, the buffer layer has a function of preventing or repairing oxygen defects due to electric field stress during data rewriting at the interface between the ferroelectric layer or the ferroelectric layer and the conductive layer, thereby reducing the leakage current, improving the ferroelectric properties, reducing the coercive field, and improving the rewriting properties, etc., and exhibits excellent effects. It is preferable that the chemical potential of oxygen in the buffer layer is higher than the chemical potential of oxygen in the ferroelectric layer. It is preferable that the oxygen vacancy defect density in the buffer layer is smaller than the oxygen vacancy defect density in the ferroelectric layer. When the chemical potential of oxygen in the buffer layer is higher than the chemical potential of oxygen in the ferroelectric layer, or when the oxygen vacancy defect density in the buffer layer is smaller than the oxygen vacancy defect density in the ferroelectric layer, oxygen ions can easily move from the buffer layer into the ferroelectric layer to prevent or repair oxygen defects at the interface between the ferroelectric layer or the ferroelectric layer and the conductive layer 3.

[0162] Examples of the dielectric material (insulating material) that is a metal oxide containing a metal having a plurality of valences exhibiting oxygen ion conductivity in the buffer layer include, for example, a cerium oxide film (CeO x (x = 1.5 - 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0)), in addition to a zirconium oxide film, a titanium oxide film, a yttria-stabilized zirconia film, or a rare earth element oxide film, etc. are applicable.

[0163] The ferroelectric layer of the ferroelectric capacitor is a ferroelectric layer made of a metal oxide. The ferroelectric layer is preferably a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, preferably hafnium (Hf), zirconium (Zr) or a metal oxide containing these two elements. Furthermore, a metal oxide containing hafnium (Hf), zirconium (Zr), cerium (Ce) or two or more of these elements, preferably hafnium (Hf), zirconium (Zr) or these two elements, and at least one metal element selected from the group consisting of aluminum (A1), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu) is preferred.

[0164] When the hafnium-based metal oxide contains a dopant metal, the amount of the dopant metal may be any amount that forms a ferroelectric. Generally, the molar number of the dopant metal, with the total of the metals in the entire metal oxide containing the dopant metal being 100 mol%, is preferably 10 mol% or less, more preferably 0.1 to 10%, and may also be 4 to 9 mol%.

[0165] The film thickness of the ferroelectric layer is not particularly limited as a suitable film thickness is adopted according to the application of the non-volatile memory element. However, in a preferred embodiment, the film thickness of the ferroelectric layer 1 may be 1 nm to 100 nm, more preferably 2 nm to 50 nm, further 2 nm to 20 nm or 2 nm to 10 nm. Compared with conventional ferroelectrics such as PZT, the hafnium-based metal oxide exhibits excellent ferroelectric properties even at a thin film thickness of 10 nm or less, so it is scalable and suitable as a ferroelectric layer for non-volatile memory elements.

[0166] It is preferable to have an interface layer composed of a single-layer film or a multi-layer film between the ferroelectric layer of the ferroelectric capacitor and the electrode (conductive layer) on the opposite side of the buffer layer, and the interface layer preferably has a dielectric constant higher than that of silicon oxide as a whole. The interface layer is preferably a high-dielectric constant film having a dielectric constant larger than that of the silicon nitride film, particularly an oxide film or a silicate film. By having a high dielectric constant in the interface layer, the partial voltage applied to the ferroelectric layer among the applied voltages can be increased. Such an interface layer may be an insulator with a high dielectric constant. For example, when the ferroelectric layer is a yttrium-doped hafnium-based metal oxide (Y-HfO2), yttrium silicate (YSio), hafnium silicate (HfSiO), yttrium oxide (Y2O3), etc. are preferable.

[0167] The interface layer is preferably in direct contact with the first conductive layer (lower electrode). However, since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode), in that case, the surface oxide film may be considered as part of the interface layer. When considering the surface oxide film as part of the interface layer, the interface layer is not a single-layer film but is composed of a multi-layer film (composite film), as long as the composite film as a whole has a dielectric constant higher than that of silicon oxide. Needless to say, the main body of the interface layer other than the surface oxide film itself may also be a multi-layer film.

[0168] The interface layer preferably has a function of suppressing the oxygen migration from the ferroelectric layer to the first conductive layer side. Thereby, an effect of suppressing the generation of oxygen defects in the ferroelectric layer is expected.

[0169] The electrode (conductive layer) can be made of a metal such as tungsten or titanium, a conductive ceramic, a conductive semiconductor, etc. In particular, the lower electrode of the ferroelectric layer is preferably a conductive material such as nickel disilicide (NiSi2) because it has excellent film quality for the hafnium-based metal oxide formed thereon.

[0170] The matters described in the manufacturing methods of the nonvolatile memory elements of Example 1 and Example 2 are also common matters in the manufacturing method of the semiconductor memory device of the third embodiment of Example 3. A ferroelectric layer composed of a hafnium-based metal oxide can be formed at a temperature of 400°C or lower, preferably less than 300°C. When the deposited ferroelectric layer is subjected to activation annealing at a temperature of 400°C or lower, the characteristics of the ferroelectric layer and the ferroelectric memory element can be improved. In particular, since the activation annealing can be preferably performed at a temperature of 400°C or lower, it can be preferably carried out after manufacturing the memory element and the memory device. However, in the third embodiment of Example 3, the activation annealing is not limited to 400°C or lower, and it may be performed at a temperature of 400°C or higher.

[0171] (Fourth Embodiment: NOR-Type Memory Cell Array) The semiconductor memory device of the fourth embodiment of Example 3 is an example of a NOR-type memory cell array. Memory cell arrays are broadly classified into NOR-type and NAND-type. Mainly, the access method to the cells, the cell area, and the applications are different. NOR-type cells allow random access, but the cell area is larger compared to NAND. On the other hand, NAND cells do not allow random access and are serially accessed, but a very small cell area can be realized.

[0172] FIG. 26 shows the layout of a source-separated NOR-type cell assuming a 1T cell (FeFET). In the NOR-type cell in the figure, the word line WL is connected to the gate of the FeFET, the bit line BL is connected to the drain, and the source line SL is connected to the source. The source-separated type is characterized in that the source of the memory cell is common only in the selected source line SL, and the non-selected source lines can be independently controlled.

[0173] FIG. 27 shows a NOR-type cell with a plate structure. The plate line PL is common in block units, and the bit line BL can have a potential applied instead of being grounded.

[0174] In FIGS. 26 and 27, the memory cell is a 1T type memory cell, but it may also be a 1T1C type, 2T2C type, etc. The NOR type is inferior to the NAND type in terms of integration density, but since the access speed to the memory cell is faster than that of the NAND type, it is used as code storage in microcontrollers and the like.

[0175] Taking the FeFET as an example, by controlling the direction of polarization of the ferroelectric layer constituting the gate insulating film of the memory cell transistor by applying a gate voltage, the threshold voltage (Vth) of the FeFET can be controlled, so that information can be written and erased. On the other hand, for information reading, by comparing the applied voltage to the gate, that is, the read voltage, with the Vth of the FeFET, if the read voltage is greater than the Vth, current flows through the FeFET, and if it is smaller, no current flows through the FeFET. As a result, information can be read.

[0176] The ferroelectric memory cell constituting this NOR type memory cell array may be the semiconductor memory device of the first to third embodiments. Therefore, in a NOR type memory cell array using a ferroelectric material, by inserting a buffer layer which is a metal oxide having oxygen ion conductivity between the ferroelectric layer and the electrode (conductive layer) and containing a metal having a plurality of valences, damage to the ferroelectric layer due to voltage stress during writing can be repaired, leakage current can be reduced, and good device characteristics, particularly reliability, can be realized.

[0177] Also, when using a hafnium-based metal oxide as the ferroelectric material, excellent ferroelectricity can be exhibited even with a thin film thickness, so it is scalable, can reduce power consumption, and can also be mixed with advanced CMOS logic. Further, by inserting an interface layer of a high dielectric constant material (which may be composed of a single layer film or a multilayer film, but has a dielectric constant higher than that of silicon oxide as a whole) between the ferroelectric layer and the other electrode (conductive layer), even when the same gate applied voltage is applied, the applied voltage across the ferroelectric layer can be relatively increased, so the gate applied voltage can be relatively decreased, and there is an effect of reducing power consumption.

[0178] The memory cells constituting this NOR-type memory cell array may be any of the semiconductor memory devices of the first to third embodiments, and thus the details of the configuration are referred to the descriptions of the first to third embodiments. Needless to say, in the NOR-type memory cell of the present invention, multi-value storage capable of storing two or more bits of information in a one-transistor cell is also possible.

[0179] The matters described in the manufacturing methods of the nonvolatile memory elements of Example 1 and Example 2 are also common matters in the manufacturing method of the semiconductor memory device of the fourth embodiment of Example 3. A ferroelectric layer composed of a hafnium-based metal oxide can be formed at a temperature of 400 °C or lower, preferably less than 300 °C. When the deposited ferroelectric layer is subjected to activation annealing at a temperature of 400 °C or lower, the characteristics of the ferroelectric layer and the ferroelectric memory element can be improved. In particular, since the activation annealing may be performed at a temperature of 400 °C or lower, it can be preferably performed after manufacturing the memory element and the memory device. However, in the fourth embodiment of Example 3, the activation annealing for causing a phase transition to ferroelectricity in the ferroelectric layer composed of a hafnium-based metal oxide is not limited to 400 °C or lower, and it may be performed at a temperature of 400 °C or higher. In particular, when forming a transistor-type memory cell (FeFET) in the front end, the temperature of the activation annealing for causing a phase transition of the metal oxide film to the ferroelectric layer may be 400 °C or higher.

[0180] 〔Example 4: FeFET and 2D-FeNAND, 3D-FeNAND〕 Example 4 The semiconductor memory device according to this will be described with reference to the drawings (Figs. 22, 28 to 30). Example 4 In the configuration of the memory cell array according to this, an example will be described in which a 1T-type ferroelectric transistor (FeFET) is provided as a memory cell and a ferroelectric NAND (FeNAND) is provided as a memory cell array.

[0181] Fig. 28 shows a conceptual diagram of a FeNAND memory array. One NAND string is composed of FeFETs connected in series and two selection elements arranged at both ends of the string. Here, the selection element on the bit line side is denoted as SDG, and the selection element on the source line side is denoted as SGS. The figure shows an example in which 64 word lines WL are connected in series. Usually, MOS transistors are used as the selection elements, but selection elements with the same FeFET structure as the memory cells may also be used. In that case, the threshold voltage (Vth) of the FeFET is set for the selection elements. As for the NAND memory cell array, it may be a two-dimensional FeNAND in which NAND strings are arranged planar or a three-dimensional FeNAND in which the direction of the strings is arranged perpendicular to the substrate surface. Needless to say, the essence of the present invention is applicable.

[0182] The FeNAND memory chip includes a memory cell array based on NAND strings in which FeFETs are connected in series, and a peripheral circuit PC provided around the memory cell array. The memory cell array includes a plurality of memory blocks MBi arranged in one direction. Each of these memory blocks includes a plurality of pages. In the present embodiment, the data read process and write process are executed for each page, and the data erase process is executed for each memory block. The peripheral circuit PC generates a voltage according to an instruction received from the outside, applies it to the memory cell array, and executes data read process, write process, erase process, etc. for a specified page or memory block.

[0183] Note that this embodiment targets a two-dimensional NAND (Fig. 28) in which NAND memory cell strings and memory strings are arranged parallel in the substrate plane and a three-dimensional NAND (Figs. 29 and 30) in which memory cell strings are arranged perpendicular in the substrate plane.

[0184] In the FeFET memory cell as shown in Fig. 22, in the program state (write state), the threshold voltage Vth of the transistor is low, the voltage of the upper electrode is Vpp, and the voltage of the lower electrode is 0V. In the erase state, the threshold voltage Vth of the transistor is high, the voltage of the upper electrode is 0V, and the voltage of the lower electrode is Vpp. Referring to Fig. 22, the memory cell is a memory transistor FeFET including a semiconductor layer 2s functioning as a lower electrode region, a gate insulating film including a ferroelectric film 1, and a gate electrode 3g functioning as an upper electrode, and can store information of 1 bit (binary), 2 bits (quaternary), 3 bits (octal), and 4 bits (hexadecimal). Vpp means the write voltage or erase voltage of the FeFET. In the write state, the threshold (Vth) of the memory transistor is low, and in the erase state, Vth becomes relatively high. At the time of reading, a voltage intermediate between the Vths in the write state and the erase state is applied to the gate electrode as the read voltage, so that the current of the FeFET is OFF in the erase state and the current of the FeFET is ON in the write state, enabling the reading of information.

[0185] The ferroelectric layer of the FeFET element uses, for example, a Y-doped hafnium oxide film, but other ferroelectric materials, for example, a film mainly composed of hafnium (Hf) and oxygen (O) and added with at least one of silicon (Si), magnesium (Mg), aluminum (Al), barium (Ba), lanthanum (La), and zirconium (Zr) may also be used. Further, by devising the process conditions, a ferroelectric film can be formed even in the case of a hafnium oxide film not doped with an additive element.

[0186] Further, the buffer layer is an insulating film composed of a metal oxide containing a metal having a plurality of valences with oxygen ion conductivity. For example, in addition to the cerium oxide film (CeO x ;x = 1.5 to 2.0), it is composed of a zirconium oxide film, a titanium oxide film, a yttria-stabilized zirconia film, or a rare earth element oxide film.

[0187] Further, the interface layer may be composed of a single-layer film or a multilayer film, but as a whole, the interface layer has a higher dielectric constant than silicon oxide. For example, a high-dielectric-constant oxide film or a silicate film is desirable. When the ferroelectric layer is a Y-doped hafnium oxide film, a yttrium silicate film (YSio film), a Y2O3 film, or a hafnium silicate film (HfSiO film) is desirable.

[0188] The interface layer preferably contacts the first conductive layer (lower electrode) directly. Since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode), in that case, the surface oxide film may be regarded as part of the interface layer, and it is only necessary that the composite film as a whole has a higher dielectric constant than silicon oxide. The main body of the interface layer other than the surface oxide film itself may also be a multilayer film. The interface layer preferably has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side.

[0189] In the reliability evaluation of data rewriting (Endurance) of the FeFET element, it has been found that as the number of data rewrites increases, the data rewrite characteristics deteriorate, the threshold voltage (Vth) window width of the FeFET narrows and deteriorates, and the problem of inability to read information occurs. As a factor of this deterioration of data rewrite characteristics, when the number of rewrites increases, defects occur at the interface between the ferroelectric film, the ferroelectric film and the interface layer, or the interface layer and the lower electrode (Si channel formation region in the case of FeFET), and as a result, the data rewrite characteristics deteriorate due to the increasing leakage current of the FeFET element. Also, in the operation of lowering the Vth of the FeFET for writing, at the same time, the Vth increases due to electrons tunnel-injected into the ferroelectric layer of the FeFET from the channel, and in order to increase the Vth that decreased during writing, a hypothesis has been pointed out that deterioration of data rewrite characteristics occurs.

[0190] In this embodiment, in order to solve the above problems, a FeFET element having the advanced buffer layer structure described in Example 2 is provided in the memory cell. Referring to FIG. 22(b), the lower electrode is the Si substrate 2s, the interface layer 5 is a yttrium silicate film, the ferroelectric film 1 is a Y-doped hafnium oxide film, and the buffer layer 4 is cerium oxide (CeOx ) The film and the upper electrode 3g are W / TiN. In this embodiment, it has an advanced buffer layer structure with the interface layer 5 shown in Embodiment 2 inserted. As described in Embodiment 2, this interface layer 5 improves the ferroelectric characteristics in low-voltage operation and suppresses the tunnel current of electrons injected from the channel of the FeFET during writing by relatively thickening the interface layer (tunnel insulating film), and as a result, it is possible to improve the deterioration of data rewrite characteristics. Also, buffer layers 4 such as CeO x compensate for and reduce oxygen defects formed in the ferroelectric layer 1 or at the electrode interface due to the electric field stress generated during data rewriting as the number of data rewrites increases in the ferroelectric layer 1, for example, a Y-doped hafnium oxide film, and as a result, improve the data rewrite characteristics.

[0191] FIG. 28 shows an example of a memory string of FeNAND using FeFETs. FIG. 28 shows two memory strings. Each memory string is configured by connecting FeFET memory cells MC described in FIG. 22 in series, and both ends of the string are composed of selection transistors ST. The Vth of the memory cell MC changes according to the direction of the spontaneous polarization of the ferroelectric film. FeNAND is composed of a plurality of FeFET memory strings. Similar to NAND flash memory, the cell area is small and low cost can be expected, but it is limited to serial access and random access is not possible.

[0192] FIG. 29 shows a conceptual diagram of the main circuit configuration of FeNAND. FIG. 29 assumes a three-dimensional structure of FeNAND. Word lines WL are connected to the gate electrodes of a plurality of memory cells belonging to the memory string MU, respectively. These word lines WL are commonly connected to all the memory strings MU in one memory finger MF. Also, in one memory block, the plurality of word lines connected to one memory finger MF are commonly connected to the plurality of word lines connected to the remaining memory fingers MF, respectively. Incidentally, in one memory finger MF, the plurality of memory cells commonly connected to one word line WL constitute a page.

[0193] The selection transistors (STD, STS) are field effect transistors each including a semiconductor layer functioning as a channel region, a gate insulating film, and a gate electrode. Selection gate lines (SGD, SGS) are respectively connected to the gate electrodes of the selection transistors (STD, STS). The selection gate lines (SGD, SGS) are commonly connected to all the selection transistors (STD, STS) in one memory finger MF. Also, a plurality of drain selection lines SGD in one memory block MBi are independently connected to the peripheral circuit PC for each memory finger MF. On the other hand, in one memory block MBi, a source selection line SGS connected to one memory finger MF is commonly connected to the source selection lines SGS connected to the remaining memory fingers MF.

[0194] FIG. 30 is a schematic perspective view showing the configuration of the memory finger MF. Also, FIG. 31 shows a cross-sectional structure of a main part of the 3D FeNAND.

[0195] As shown in FIG. 30, the memory finger MF is provided on a substrate 21. The memory finger MF includes a plurality of conductive layers 22 arranged in the Z direction, a semiconductor layer 23 extending in the Z direction and facing these plurality of conductive layers 22, and a gate insulating film 24 provided between these conductive layers 22 and the semiconductor layer 23. In this configuration, the intersection portions of the conductive layer 22 and the semiconductor layer 23 each function as a memory cell MC.

[0196] The substrate 21 is a semiconductor substrate made of, for example, single-crystalline silicon (Si) or the like. The substrate 21 has, for example, an n-type impurity layer on the upper surface of the semiconductor substrate, and further has a double-well structure having a p-type impurity layer in this n-type impurity layer. The conductive layer 22 is a plate-shaped conductive layer extending in the X direction, and is made of, for example, a laminated film of titanium nitride (TiN) and tungsten (W). The conductive layers 22 cover the side surfaces of the semiconductor layer 23 from the X direction and the Y direction, respectively, and function as word lines WL and gate electrodes of memory cells MC, or selection gate lines (SGD, SGS) and gate electrodes of selection transistors (STD, STS). The conductive layers 22 are connected to contacts 31 and 32 extending in the Z direction at the ends in the X direction, respectively, and are connected to the peripheral circuit PC via these contacts 31 and 32.

[0197] The semiconductor layer 23 is a substantially columnar or substantially cylindrical semiconductor layer extending in the Z direction, and is made of, for example, polysilicon (p-Si) or the like. The semiconductor layer 23 functions as a channel region of memory cells and selection transistors (STD, STS). The upper end of the semiconductor layer 23 is connected to a bit line BL extending in the Y direction via a contact 22. The lower end of the semiconductor layer 23 is connected to the surface of the substrate 21 and a source line SL extending in the Y direction via a wiring LI extending in the Z direction and the X direction. In the illustrated example, the lower end of the semiconductor layer 203 is connected to the wiring LI via the upper surface of the substrate 21, but it may be connected through other wirings or the like.

[0198] FIG. 31 is a cross-sectional structure diagram of a 3D FeNAND. A bit line (BL) is arranged at the upper part and a source line (SL) is arranged at the lower part. A ferroelectric film is embedded along the hole. The plus and minus notations conceptually indicate the polarization directions of the ferroelectric material. Compared with a 3D NAND flash memory, the write / erase voltage of FeNAND is significantly reduced, so low power consumption is expected.

[0199] In the non-volatile memory device of the present invention, oxygen defects formed in the ferroelectric layer or at the electrode interface due to electric field stress during data rewriting are controlled by supplying oxygen ions from the buffer layer to control the amount of oxygen defects in the ferroelectric layer or at the interface, thereby improving the leakage current, the ferroelectric layer film quality, etc. As a result, the number of data rewrites is significantly improved.

[0200] Furthermore, as a first conductive layer having a fluorite structure similar to the hafnium oxide-based ferroelectric layer, an interface layer such as a high-dielectric silicate or a high-dielectric dielectric film having a relatively higher dielectric constant than the silicon oxide film is inserted between the lower conductive layer and the ferroelectric layer, so that it becomes possible to apply a polarization inversion electric field to the ferroelectric layer at a low voltage. As a result, the voltage stress applied to the ferroelectric film is reduced, and there is a unique effect that the number of rewrites is significantly improved with low power consumption.

[0201] 〔Example 5: FTJ Element and Cross-Point Type Memory〕 The semiconductor memory device according to this will be described with reference to the drawings (Fig. 32). Also, This example in this, an FTJ memory including a ferroelectric tunnel junction (FTJ) element as a memory cell and a cross-point type memory cell array will be described with reference to the drawings (Figs. 33 to 36).

[0202] The principle conceptual diagram of the FTJ memory is shown in FIG. 32. The basic structure is a three-layer structure of a bottom electrode / ferroelectric thin film / top electrode (M / FE / M). The ferroelectric thin film FE is thinned to 10 nm or less and also functions as a tunnel insulating film. Non-volatile memory operation is performed by utilizing the physical phenomenon in which the potential barrier for tunnel electrons at the interface between the ferroelectric thin film FE and the metal electrode M is modulated by the polarization direction of the ferroelectric film FE. Specifically, the polarization direction of the ferroelectric film FE is changed according to the polarity of the voltage applied to the metal electrode M to write / erase information, and information is read as the difference in the tunnel current value flowing through the ferroelectric film FE of the element due to the voltage application to the electrode M. Therefore, the FTJ element is characterized by being a non-destructive read ferroelectric memory, and the readout of the ferroelectric capacitor constituting the conventional 1T1C type and 2T2C type ferroelectric memories being a destructive readout is an advantage of the FTJ element.

[0203] Regarding the data rewriting characteristics (Endurance) of the FTJ element, the factors causing the deterioration of the data rewriting characteristics are schematically shown in FIG. 33 as the number of data rewritings increases. In the FTJ element, as shown in FIG. 33, a silicon oxide (SiO2) film may be used as an interface layer between the ferroelectric layer and the bottom electrode. When the number of rewritings increases, defects occur in the ferroelectric film due to tunnel electrons, and as a result, a leakage current occurs in the ferroelectric film through the generated defects, and a hypothesis has been proposed that this causes deterioration of the data rewriting characteristics.

[0204] In this embodiment, the memory cell includes the FTJ element having the advanced buffer layer structure shown in FIG. 14 described in Embodiment 2. For example, the bottom electrode 2 is a NiSi2 electrode, the interface layer 5 is a yttrium silicate (YSiO silicate) film, the ferroelectric film 1 is a Y-doped hafnium oxide (YHO) film, and the buffer layer 4 is a cerium oxide (CeO x ) film, and the top electrode 3 is a W / TiN or TiN film. Note that the YHO film 1 with a thickness of 10 nm or less is carefully formed by an atomic layer deposition (ALD) method, a sputtering method, a pulsed CVD method, or the like.

[0205] In this embodiment, in the basic structure of the FTJ element shown in FIG. 14, a structure is adopted in which an interface layer 5 of a high-dielectric film is inserted. As described in Embodiment 2, this interface layer 5 improves ferroelectric characteristics at a low voltage and can increase the potential barrier of tunnel electrons because the tunnel barrier has a two-layer film structure, so that the OFF current during reading can be reduced. As a result, the ON / OFF ratio of the read current of the FTJ element can be greatly improved.

[0206] FIG. 34 shows a conceptual diagram of a cross-point memory CPM. The cross-point memory CPM has a peripheral circuit PC and a memory cell array MCi. In the cell layout of the memory cell array MCi, a cross-point structure is adopted in which memory cells MC are arranged at cross-points where bit lines BL and word lines WL are two-dimensionally arranged vertically. It is one of the memory cell array structures that can be laid out with the minimum dimensions. In the FTJ element shown in this embodiment, since the FTJ element exhibits diode-like rectifying characteristics due to the insertion of the interface layer, a memory cell having self-rectifying characteristics without using a separate selection element can be realized by the FTJ element itself. Therefore, it is possible to suppress the leakage current flowing through non-selected elements, which is a major problem of the cross-point type memory shown in FIG. 34. In addition, although the layout shown in FIG. 34 has a two-dimensional configuration in a parallel method in the plane, it is also possible to realize a three-dimensional cross-point memory in which FTJ elements are stacked in the Z direction perpendicular to the plane. This three-dimensional cross-point memory can reduce the substantial cell area with respect to the two-dimensional cross-point memory cell, so it also has the effect of further reducing the bit cost. In addition, in the memory cell, it is also possible to realize a cross-point memory with a 1S1F type memory cell that separately includes a rectifying element such as a diode in addition to the FTJ element. Furthermore, the ON / OFF characteristics of the memory cell can be improved, and a large-capacity cross-point memory can be realized.

[0207] The ferroelectric layer applied to the FTJ memory cell is shown as a Y-doped hafnium oxide film. Other examples include HZO (Hf 0.5 Zr 0.5It may also be a film or the like mainly composed of hafnium (Hf) and oxygen (O), such as O2), HSO(SiHfO), etc., with at least one of silicon (Si), magnesium (Mg), aluminum (Al), barium (Ba), lanthanum (La), and zirconium (Zr) added.

[0208] The buffer layer is an insulating film that is a metal oxide containing a metal having a plurality of valences with oxygen ion conductivity. The cerium oxide film (CeO x ; x1.5~2.0) In addition to this, it is composed of a zirconium oxide film, a titanium oxide film, a yttria-stabilized zirconia film, a rare earth element oxide film, or the like.

[0209] The interface layer may be composed of a single-layer film or a multilayer film. As a whole, the interface layer has a higher dielectric constant than silicon oxide. For example, a high-dielectric-constant oxide film or a silicate film is desirable. When the ferroelectric layer is a Y-doped hafnium oxide film, a yttrium silicate film (YSio), a hafnium silicate film, a yttrium hafnium silicate film (YHSiO), a Y203 film, etc. are desirable.

[0210] The interface layer preferably directly contacts the first conductive layer (lower electrode). Since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode), in that case, the surface oxide film may be considered as part of the interface layer, and it is sufficient if the composite film as a whole has a higher dielectric constant than silicon oxide. The main body of the interface layer other than the surface oxide film itself may also be a multilayer film. The interface layer preferably has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side.

[0211] Fig. 35 shows the cross-point memory device according to this embodiment. It includes at least a memory cell array MCi and a peripheral circuit PC provided around the memory cell array MCi. The memory cell array includes a plurality of word lines WL, a plurality of bit lines BL intersecting these plurality of word lines WL, and a plurality of memory cells MC connected to these wirings. Incidentally, the plurality of memory cells MC connected to one word line WL constitute a page.

[0212] The peripheral circuit PC generates a voltage in response to a command received from the outside, applies it to the memory cell array MCi, and executes data writing, reading, erasing, re-wake-up processing, etc. for a specified page or the like.

[0213] FIG. 36 shows a conceptual diagram of an application of a brain-type memory (neuromorphic memory) as a specific application example of a cross-point memory. It is possible to mimic an ultra-low power consumption analog computing function mimicking information processing in the human brain with a cross-point memory. FIG. 36 shows an analogy between the computing function of a human nerve cell and a cross-point memory. The cross-point memory cell array corresponds to one neuron, the word line corresponds to the axon, and the bit line corresponds to the dendrite. The human brain operates in ultra-parallel. However, in a normal von Neumann type digital memory, since usually one word line outputs to one or several bit lines, it is difficult to mimic the brain type. Therefore, in neuromorphic operation, a plurality of word lines are simultaneously activated, and the output current to the bit line is analogously sensed by a sense amplifier as the sum of the currents from all the FTJ elements connected to the bit line, and is output as an input signal to the next neuron.

[0214] Also in this case, by using an FTJ element having an advanced buffer layer structure with a high dielectric interface layer shown in FIG. 14, it is possible to improve the leakage current and the number of data rewrites of the cross-point cell array.

[0215] From the above, in the non-volatile memory device of this embodiment, oxygen ions are supplied from the buffer layer to oxygen defects formed in the ferroelectric layer or at the electrode interface due to electric field stress during data rewriting, and the oxygen defects in the ferroelectric layer or at its interface are repaired by recombination, thereby improving the leakage current, the ferroelectric layer film quality, etc. As a result, it is possible to increase the ON / OFF ratio during reading and significantly improve the number of data rewrites.

[0216] Furthermore, by using a NiSi2 electrode with a fluorite structure similar to the hafnium oxide ferroelectric layer and inserting an interface layer such as yttrium silicate (YSiO), hafnium silicate (HfSiO), Y2O3, etc., which has a relatively higher dielectric constant than the silicon oxide film, between the lower conductive layer and the ferroelectric layer as the first conductive layer, it becomes possible to apply a polarization inversion electric field to the ferroelectric layer at a low voltage. As a result, the stress during data rewriting is reduced, and there is a unique effect that the number of rewrites is significantly improved with low power consumption. In the application of the brain-type memory of this embodiment, although an example using an FTJ element as the ferroelectric element has been described, it goes without saying that the present invention is applicable even when a ferroelectric capacitor having a buffer layer structure or an advanced buffer layer structure shown in the present invention, or an FeFET is applied to the brain-type memory.

[0217] 〔Example 6: Non-volatile Logic, Non-volatile Power Gating〕 Example 6 A semiconductor memory device according to this will be described with reference to the drawings (Figs. 37 to 43). In this embodiment, examples of applying a buffer layer structure ferroelectric element, such as a capacitor, an FTJ element, an FeFET, etc., to non-volatile logic, which is a low power consumption technology for logic, are shown mainly for non-volatile SRAM, non-volatile latches / flip-flops, non-volatile power gating, etc., and an example of applying it to an ultra-low power consumption microcontroller is also shown.

[0218] In a SoC (System on Chip) fabricated with fine CMOS, the leakage current during standby of the transistors constituting the SRAM, which is the on-chip working memory, and the logic circuit has become a major factor in increasing the power consumption of the entire SoC. For this reason, attempts have been made to reduce the power consumption by turning off the power supply of the logic circuit that is not operating during standby. In a volatile memory such as SRAM, there is a problem that the stored data is lost when the power is turned off. For this reason, a low power consumption technology has been proposed in which data is stored in a non-volatile memory element from a volatile memory before power-off, and the data is recalled and returned to the SRAM before operating again to cut off the power supply of the logic during standby.

[0219] Furthermore, in order to further reduce the power consumption of the SoC, it is important to integrate a non-volatile memory with CMOS to shorten the data transfer distance and at the same time reduce the operating power during writing and erasing to the non-volatile memory from the logic. As a non-volatile memory with low operating power, a voltage-operated non-volatile ferroelectric memory has attracted attention. In order to reduce the operating power, it is important to improve the reliability and lower the operating voltage of a hafnium oxide-based ferroelectric memory to which a fine CMOS process that is difficult to scale with conventional PZT-based materials can be applied. In this embodiment, a non-volatile logic using a buffer layer structure ferroelectric capacitor will be described.

[0220] Here, an example in which a hafnium oxide-based ferroelectric capacitor is arranged in the back-end wiring layer of the upper layer of the logic transistor portion formed in the front-end portion will be described, but the arrangement position of the capacitor is not limited to the back-end.

[0221] As a high-speed operable data storage circuit, there is a latch circuit in which the inputs and outputs of a pair of inverters are cross-connected. The latch circuit is used for an element circuit constituting a flip-flop, a memory cell of an SRAM, etc. Such a latch circuit is a volatile data storage circuit itself, and when the power supply is cut off, the stored data is lost. Therefore, a non-volatile data storage circuit has been proposed.

[0222] FIG. 37 shows the basic concept of a non-volatile SRAM using a ferroelectric capacitor and the data flow. The non-volatile SRAM cell is composed of a volatile SRAM (6T SRAM) cell part consisting of six logic transistors and a non-volatile ferroelectric memory element (e.g., a capacitor) part. In the normal operating state with power supply, data is held in the SRAM part, and in the SRAM part, this data is READ / WRITE accessed in the same way as a standard SRAM. Before voltage cutoff for low power consumption by power gating, the data in the SRAM part is copied to the ferroelectric capacitor combined in the store operation. When the power supply of the SRAM is restored to enter the operating mode again, the value stored in this ferroelectric element is returned to the SRAM part by the recall operation.

[0223] FIG. 38 shows the circuit part of the non-volatile SRAM. It is composed of a 6-transistor SRAM cell, two ferroelectric capacitors, and two selection transistors. When the power supply is turned on, the two gate-controlled selection transistors separate the ferroelectric capacitors from the SRAM part.

[0224] Normally, a high-speed operable memory circuit used in CMOS logic loses the stored content due to power-off, but by adding a non-volatile memory element to such a bistable memory circuit, data can be retained even when power-off is performed. When the CMOS logic is performing normal operations, it operates as a normal bistable memory circuit without using non-volatile memory, and is characterized in that non-volatile memory is performed only when power-off is performed. Thereby, non-volatile power gating (NVPG) can be executed, which can reduce energy with high efficiency without affecting normal operations.

[0225] For the ferroelectric, for example, a capacitor, preferably the advanced buffer layer structure capacitor described in Example 2 is used. A Y-doped hafnium oxide film is used, but the ferroelectric layer may be, for example, HZO (Hf 0.5 Zr 0.5Films such as O2), HSO(SiHfO), etc., which mainly contain hafnium (Hf) and oxygen (O) and to which at least one of lanthanum (La), silicon (Si), magnesium (Mg), aluminum (Al), barium (Ba), and zirconium (Zr) is added, may also be used. Further, a hafnium oxide film without doping may also be used.

[0226] The buffer layer is an insulating film that is a metal oxide containing a metal having a plurality of valences with oxygen ion conductivity. For example, a cerium oxide film (CeO x ; x = 1.5 to 2.0, preferably 1.6 - 2.0, more preferably 1.7 - 2.0, particularly 1.8 - 2.0), etc. The interface layer is preferably, for example, a high dielectric constant oxide film or a silicate film. When the ferroelectric layer is a Y-doped hafnium oxide layer, a Y silicate film, a Y203 film, or a HfSiO silicate film is desirable.

[0227] The interface layer may be composed of a single-layer film or a multilayer film, but as a whole, it has a dielectric constant higher than that of silicon oxide. For example, a high dielectric constant oxide film or a silicate film is desirable. When the ferroelectric layer is a Y-doped hafnium oxide film, a yttrium silicate film (YSiO), a hafnium silicate (HfSiO), a yttrium hafnium silicate film (YHfSiO), a Y203 film, etc. are desirable. Since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode), in that case, the surface oxide film may be considered as part of the interface layer, and it is sufficient that the composite film as a whole has a dielectric constant higher than that of silicon oxide. The interface layer preferably has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side.

[0228] In this embodiment, it is necessary to store the data of the SRAM, which is a volatile memory, in the ferroelectric capacitor when the power is off and rewrite the data to the SRAM when the power is on. For this reason, it is necessary that the number of data rewrite cycles (Endurance cycles) of the ferroelectric element, for example, the capacitor, is large.

[0229] However, the number of data rewrites of hafnium oxide-based ferroelectric devices, such as capacitors, has still been limited. In this embodiment, oxygen ions are supplied from the buffer layer to oxygen defects formed in the ferroelectric layer or at the electrode interface due to the electric field stress during data rewriting, so as to control the amount of oxygen defects in the ferroelectric layer or at the interface, improve the leakage current, film quality, etc. As a result, the electric field stress applied to the ferroelectric film is reduced, and the number of data rewrites of ferroelectric devices, such as capacitors, is significantly improved.

[0230] Furthermore, by inserting an interface layer such as a yttrium silicate film (YSiO), hafnium silicate film (HfSiO), yttrium hafnium silicate film (YHfSiO), Y2O3 film, etc. with a relatively high dielectric constant compared to the silicon oxide film between the ferroelectric layer, a polarization inversion electric field can be applied to the ferroelectric layer at a lower voltage. As a result, it has the unique effect that the number of rewrites can be improved with low power consumption.

[0231] As modified examples of FIG. 38, FIGS. 39 and 40 show a non-volatile SRAM composed of four transistors and two ferroelectric capacitors in a 6T-type transistor SRAM, and a non-volatile SRAM of a type in which four ferroelectric capacitors are directly connected without passing through a selection transistor in a 6T-type SRAM. In FIG. 39, the number of transistors is increased to further improve the reliability. On the other hand, in FIG. 40, since no selection transistor is used, there is an advantage that the number of transistors can be reduced and the area of the memory cell can be made smaller.

[0232] In the non-volatile ferroelectric device used in the non-volatile SRAM of this embodiment, oxygen ions are supplied from the buffer layer to oxygen defects formed in the ferroelectric layer or at the electrode interface due to the electric field stress during data rewriting, so as to control the amount of oxygen defects in the ferroelectric layer or at the interface, improve the leakage current, film quality, etc. As a result, the number of data rewrites is significantly improved.

[0233] Furthermore, by inserting an interface layer such as yttrium silicate film (YSiO), hafnium silicate film (HfSiO), yttrium hafnium silicate film (YHfSiO), Y2O3, etc., which has a relatively higher dielectric constant than the silicon oxide film, between the ferroelectric layer, a polarization inversion electric field can be applied to the ferroelectric layer at a lower voltage. As a result, it has a unique effect that the power consumption can be reduced and the number of rewrite cycles can be improved.

[0234] Next, as a non-volatile logic, an example of applying the ferroelectric capacitors shown in Examples 1 and 2 to a non-volatile latch circuit is shown. FIG. 41 shows a latch circuit in which the inputs and outputs of a pair of inverters are cross-connected as a high-speed operable data storage circuit. The latch circuit is used as an element circuit constituting a flip-flop or as a memory cell of SRAM. Such a latch circuit is a volatile data storage circuit itself, and when the power supply is cut off, the stored data is lost. Therefore, a non-volatile data storage circuit has been proposed.

[0235] As a non-volatile data storage circuit, a circuit in which a ferroelectric element such as a capacitor is connected as a variable capacitor to the storage node of a latch circuit constituting a memory cell of SRAM has been proposed. FIG. 41 is a circuit diagram of such a memory cell. It is a method that does not use the selection transistors of the latch circuit part and the ferroelectric element part. This memory cell is composed of a latch circuit in which the input and output terminals of a CMOS inverter are cross-connected, a transfer gate in which the gate is connected to the word line WL and one of the source and drain is connected to the bit lines BL and BLX, and ferroelectric capacitors FC1 and FC2 connected to a pair of storage nodes of the latch circuit. The opposite electrodes of the ferroelectric capacitors FC1 and FC2 are connected to the plate line PL. The latch circuit composed of a pair of inverters loses data when the power supply is cut off. However, by connecting the ferroelectric capacitors FC1 and FC2 to a pair of storage nodes, the polarization direction of the ferroelectric film of the ferroelectric capacitor can be controlled according to the voltage level of the storage node, and such a polarization direction is maintained as a residual polarization even after the power supply is cut off.

[0236] In this embodiment, it is preferable to apply the non-ferroelectric capacitors shown in Examples 1 and 2 to the ferroelectric capacitors of the non-volatile logic device. Therefore, in this non-volatile logic device, oxygen ions are supplied from the buffer layer to oxygen defects formed in the ferroelectric layer or at the electrode interface due to the electric field stress during data transfer, so as to control the amount of oxygen defects in the ferroelectric layer or at the interface, improve the leakage current, film quality, etc. As a result, the number of data rewrites is significantly improved.

[0237] Furthermore, by inserting an interface layer such as yttrium silicate film (YSiO), hafnium silicate film (HfSiO), yttrium hafnium silicate film (YHfSiO), Y2O3, etc. with a relatively higher dielectric constant than the silicon oxide film between the ferroelectric layer, a polarization inversion electric field can be applied to the ferroelectric layer at a lower voltage. As a result, it has the unique effect that the number of rewrites can be improved with low power consumption. In the non-volatile logic application of this embodiment, although the ferroelectric capacitor or the FTJ element is used as the ferroelectric element for illustration, it goes without saying that the present invention is also applicable when an FeFET having the buffer layer structure or the advanced buffer layer structure shown in the present invention is applied to non-volatile logic as the ferroelectric element.

[0238] Examples of applying the low-power ferroelectric memory element described so far to a low-power ferroelectric memory and a non-volatile microcontroller applying non-volatile logic technology will be briefly described below.

[0239] This Example The semiconductor device in will be described with reference to the drawings. In this embodiment, together with the ultra-low-power ferroelectric memory, power management technologies centered on non-volatile power gating technology and normally-off technology are applied to the logic part, achieving ultra-low power consumption.

[0240] FIG. 42 is a diagram showing the configuration concept of the semiconductor chip in the present embodiment. FIG. 42 is a plan view showing a semiconductor chip forming a microcontroller (MCU), and is a diagram showing the layout configuration of each element formed on the semiconductor chip. In FIG. 42, the semiconductor chip has a CPU (Central Processing Unit) 41, a RAM (Random Access Memory) 42, an analog circuit 43, and a ferroelectric memory 44. The semiconductor chip further has a plurality of pad electrodes (external connection terminals) PD which are input / output terminals to the outside.

[0241] The CPU (circuit) 41 is also called a central processing unit and corresponds to the heart of a computer or the like. This CPU 41 reads and decodes instructions from a storage device and performs various types of calculations and controls based on them, and high processing speed is required. Therefore, among the elements formed on the semiconductor chip, the MOS transistors constituting the CPU 41 require relatively high-speed operation and low power consumption. The MOS transistor circuit constituting the CPU is made to consume less power by the non-volatile power gating (PG) technology shown in this embodiment.

[0242] The RAM (circuit) 42 is a memory that can randomly read the stored information, that is, read the stored information at any time, and newly write the stored information, and is also called a memory that can be written and read at any time. Here, SRAM using a static circuit is usually used, but in this embodiment, non-volatile SRAM is applied, and the basic operation is the same as that of SRAM, but the power consumption is made lower.

[0243] The analog circuit 43 is a circuit that handles voltage and current signals that change continuously over time, i.e., analog signals, and is composed of, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, a power supply circuit, etc. These analog circuits 43 are formed of high breakdown voltage MOS transistors. The ferroelectric memory 44, as shown in Examples 1 and 2, is an ultra-low power consumption non-volatile memory composed of a 1T1C FeRAM array, a FeFET array, etc. with a buffer layer structure or an advanced buffer layer structure.

[0244] Fig. 43 shows a conceptual diagram of a stacked low power consumption non-volatile LSI chip as an example of an IoT / AI edge device for image intelligent recognition processing (including AI processing). In Fig. 43(a), an image sensor array 51 and a two-layer stacked device 52 with a mixed-mounted low power consumption ferroelectric memory are shown, and in Fig. 43(b), a three-layer stacked type of an image sensor array 61, an ultra-low power consumption non-volatile ferroelectric memory 62, and an ultra-low power consumption logic 63 are shown. Also, for the vertical connection of the two-layer structure and the three-layer structure, technologies such as silicon through electrode (TSV) connection technology and connection technology between Cu pads are applicable. The connection between Cu pads is a technology for achieving electrical conduction by connecting the Cu pads of the upper chip and the lower chip when stacking the upper chip and the lower chip.

[0245] In the memory part of the stacked LSI, the low power consumption dielectric memory shown in this embodiment is applied, and in the logic part, a non-volatile logic memory technology using non-volatile power gating, etc. is applied. As a result, AI processing in IoT / edge devices in the edge area where ultra-low power consumption is required becomes possible.

[0246] In this non-volatile logic device, oxygen ions are supplied from the buffer layer to oxygen defects formed in the ferroelectric layer or at the electrode interface due to electric field stress during data transfer to control the amount of oxygen defects in the ferroelectric layer or at the interface, thereby improving leakage current, film quality, etc. As a result, the data rewrite count is significantly improved with low power consumption.

[0247] Furthermore, by inserting an interface layer such as yttrium silicate film (YSiO), hafnium silicate film (HfSiO), yttrium hafnium silicate film (YHfSiO), Y2O3, etc., which has a relatively higher dielectric constant than silicon oxide film, between the ferroelectric layer, a polarization inversion electric field can be applied to the ferroelectric layer at a lower voltage. As a result, it has a unique effect that the electric field stress during data rewriting is reduced, and the number of rewrites can be improved with low power consumption.

[0248] The interface layer preferably directly contacts the first conductive layer (lower electrode). Since a very thin surface oxide film is likely to be formed on the surface of the first conductive layer (lower electrode), in that case, the surface oxide film may be considered as part of the interface layer, and it is only necessary that the composite film as a whole has a dielectric constant higher than that of silicon oxide. The main body of the interface layer other than the surface oxide film itself may also be a multilayer film. The interface layer preferably has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side.

[0249] In this embodiment, so far, as non-volatile logic, the application of low-power ferroelectric memory elements to logic elements to make logic circuits non-volatile and low-power has been mainly described. On the other hand, for power consumption reduction of system LSIs (SoCs) such as microcontrollers, it is also effective to lower the power supply voltage and operating voltage of logic transistors. As a method, it is effective to use a Silicon on Insulator (SOI) substrate process instead of a bulk Si substrate.

[0250] Therefore, in the present invention, for example, in the device structure diagrams such as FIGS. 22, 23, and 24, although described on a bulk Si substrate, the usefulness remains unchanged even in the case of ferroelectric memory elements and devices using an SOI substrate. In that case, in addition to power consumption reduction by the non-volatile ferroelectric memory element, the synergistic effect of power consumption reduction of logic transistors is added, and further power consumption reduction of the system LSI is possible.

[0251] In addition, the essence of the present invention is applicable to a Silicon On Thin Buried Oxide (SOTB) process that can realize and fabricate an SOI process and a bulk Si process on the same Si substrate.

[0252] In addition, with the miniaturization of advanced CMOS transistors, it is expected that logic transistors will evolve from a two-dimensional planar structure to a three-dimensional solid structure, specifically a Fin-type transistor and a nanowire transistor. Needless to say, the present invention is applicable even to such an advanced CMOS transistor process.

Explanation of Signs

[0253] 1 Ferroelectric layer 2 First conductive layer 2s Semiconductor layer 2b Lower electrode 3 Second conductive layer 3u Upper electrode 3g Gate electrode 4 Buffer layer 5 Interface layer 6 Source region 7 Drain region 11 Semiconductor layer 12 Element isolation film 13 Interlayer insulating film 21 Substrate 22 Conductive layer 23 Semiconductor layer 24 Gate insulating film 31, 32 Contact 41 CPU 42 RAM 43 Analog circuit 44 Ferroelectric memory 51 Image sensor array 52 Low-power ferroelectric memory integrated device 61 Image sensor array 62 Ultra-low-power non-volatile ferroelectric memory 63 Ultra-low-power logic ST, STD, STS Selective transistor SGD, SGS Select Gate Line FC Ferroelectric Capacitor WL Word Line BL, / BL Bit Line PL Plate Line (Ground) SL Source Line MBi Memory Cell Array MC Memory Cell MF Memory Finger MU Memory String PC Peripheral Circuit CPM Cross Point Memory

Claims

1. a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer In a non-volatile memory device having at least, Between the ferroelectric layer and the first conductive layer and / or the second conductive layer, there is a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences, and Between the first conductive layer and the ferroelectric layer, there is an interface layer composed of a single layer film or a multilayer film, and the interface layer as a whole has a dielectric constant higher than that of silicon oxide. When the buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer exists between the first conductive layer and the buffer layer. A non-volatile memory device characterized by this.

2. The non-volatile memory device according to claim 1, wherein the chemical potential of oxygen in the buffer layer is higher than the chemical potential of oxygen in the ferroelectric layer.

3. The non-volatile memory device according to claim 1 or 2, wherein the oxygen vacancy defect density of the buffer layer is smaller than the oxygen vacancy defect density of the ferroelectric layer.

4. The non-volatile memory device according to any one of claims 1 to 3, wherein the buffer layer is composed of cerium oxide, zirconium oxide, titanium oxide, yttria-stabilized zirconia or rare earth element oxide.

5. The non-volatile memory device according to claim 4, wherein the buffer layer is composed of cerium oxide.

6. The non-volatile memory device according to any one of claims 1 to 5, wherein the film thickness of the buffer layer is 0.1 nm or more, preferably 10 nm or less.

7. The non-volatile memory device according to any one of claims 1 to 6, wherein the interface layer has a function of suppressing oxygen movement from the ferroelectric layer to the first conductive layer side.

8. The non-volatile memory device according to any one of claims 1 to 7, wherein the interface layer is composed of an oxide, a metal oxide or a silicate, particularly yttrium oxide or yttrium silicate, having a dielectric constant higher than that of silicon nitride.

9. The non-volatile memory device according to any one of claims 1 to 8, characterized in that the metal of the metal oxide constituting the ferroelectric layer contains hafnium (Hf), zirconium (Zr) or two kinds of these metals, or hafnium (Hf), zirconium (Zr) or two kinds of these metals and at least one metal element selected from the group consisting of aluminum (Al), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu).

10. The non-volatile memory device according to any one of claims 1 to 9, characterized in that the first conductive layer is a metal silicide or metal disilicide having a fluorite structure, or a metal nitride, or Si or Ge containing impurities, or SOI (Silicon on Insulator).

11. The non-volatile memory device according to any one of claims 1 to 10, characterized in that the second conductive layer has a two-layer structure of a barrier metal and a metal nitride that is connected to the buffer layer and suppresses oxygen migration, particularly a two-layer structure of W and TiN.

12. i) An array in which non-volatile memory elements each having at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer are arranged two-dimensionally or three-dimensionally, ii) A control circuit A non-volatile memory device comprising at least: A buffer layer that has oxygen ion conductivity and is a metal oxide containing a metal having a plurality of valences exists between the ferroelectric layer and the first conductive layer and / or the second conductive layer, and A non-volatile memory device, characterized in that an interface layer composed of a single-layer film or a multilayer film exists between the first conductive layer and the ferroelectric layer of the non-volatile memory element, the interface layer as a whole has a higher dielectric constant than silicon oxide, and when the buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer exists between the first conductive layer and the buffer layer.

13. The non-volatile memory device according to claim 12, characterized in that the buffer layer is composed of cerium oxide, zirconium oxide, titanium oxide, yttria-stabilized zirconia or rare earth element oxide.

14. The non-volatile memory device according to claim 13, wherein the buffer layer is composed of a cerium oxide film.

15. The non-volatile memory device according to any one of claims 12 to 14, wherein the interface layer has a function of suppressing oxygen migration from the ferroelectric layer to the first conductive layer side.

16. The non-volatile memory device according to any one of claims 12 to 15, wherein the interface layer is composed of an oxide, a metal oxide or a silicate having a dielectric constant larger than that of silicon nitride, particularly yttrium oxide or yttrium silicate.

17. The non-volatile memory device according to any one of claims 12 to 16, wherein the metal of the metal oxide constituting the ferroelectric layer contains hafnium (Hf), zirconium (Zr) or two kinds of these metals, or hafnium (Hf), zirconium (Zr) or two kinds of these metals and at least one metal element selected from the group consisting of aluminum (A1), silicon (Si), strontium (Sr), barium (Ba) and rare earth elements (Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu).

18. The non-volatile memory device according to any one of claims 12 to 17, wherein the first conductive layer is a metal silicide or metal disilicide having a fluorite structure, or a metal nitride, or Si or Ge containing impurities, or SOI (Silicon on Insulator).

19. The non-volatile memory device according to any one of claims 12 to 18, wherein the array is composed of ferroelectric memory cells each including at least the non-volatile memory element, and the ferroelectric memory cells include any one of structures of a 1-transistor type, a 1-transistor 1-capacitor type, a 2-transistor 2-capacitor type, a 2-transistor 1-capacitor type, a 1-transistor 2-capacitor type, and a ferroelectric tunnel junction (FTJ) type.

20. The non-volatile memory device according to any one of claims 12 to 19, wherein the array is composed of a NOR type array, a two-dimensional NAND type array, a three-dimensional NAND type structure, or a cross-point type array.

21. The non-volatile memory element is arranged as a ferroelectric element single body or an array in a back-end wiring region located above a logic circuit, and is connected to a part of the logic circuit. The non-volatile memory device according to any one of claims 12 to 20, characterized in that.

22. In the connection between the non-volatile memory element and the logic circuit, a selection element is arranged between the connection wiring of the non-volatile memory element and the logic circuit. The non-volatile memory device according to claim 21, characterized in that.

23. A first conductive layer, A second conductive layer, and A ferroelectric layer composed of a metal oxide between the first conductive layer and the second conductive layer A method for manufacturing a non-volatile memory element having at least, A buffer layer, which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences, is formed between the ferroelectric layer and the first conductive layer and / or the second conductive layer. An interface layer composed of a single layer film or a multilayer film is formed between the first conductive layer and the ferroelectric layer. Here, the interface layer has a dielectric constant higher than that of silicon oxide as a whole, and when the buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer exists between the first conductive layer and the buffer layer, and The ferroelectric layer is formed on the first conductive layer at a temperature of 400 ° C or lower so that the ferroelectric layer exhibits ferroelectricity before forming the second conductive layer above the ferroelectric layer. A method for manufacturing a non-volatile memory element, characterized in that.

24. The method for manufacturing a non-volatile memory element according to claim 23, characterized in that the ferroelectric layer already exhibiting ferroelectricity is heat-annealed in an inert gas atmosphere at 400 ° C or lower.

25. On the first conductive layer, the interface layer, the ferroelectric layer, and the buffer layer are continuously formed in the same chamber, where the buffer layer may be above and / or below the ferroelectric layer. The method for manufacturing a non-volatile memory element according to claim 23 or 24, characterized in that.

26. The ferroelectric layer is formed using an atomic layer deposition method (ALD method), a CVD method, a sputtering method, or a self-assembly method with the first conductive layer as a lower electrode. The method for manufacturing a non-volatile memory element according to any one of claims 23 to 25, characterized in that.

27. A first conductive layer, A second conductive layer, A ferroelectric layer made of a metal oxide between the first conductive layer and the second conductive layer, and A method for operating a non-volatile memory device, characterized by comprising: Having a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences between the ferroelectric layer and the first conductive layer and / or the second conductive layer; The ferroelectric layer is composed of polycrystals having a plurality of polarization orientations, and the operating voltage of the device is set to the operating voltage at which the crystal having the largest component perpendicular to the film surface among the crystals having the largest component perpendicular to the film surface undergoes polarization reversal. And the non-volatile memory device has an interface layer composed of a single-layer film or a multilayer film between the first conductive layer and the ferroelectric layer, and the interface layer as a whole has a dielectric constant higher than that of silicon oxide. When the buffer layer exists between the first conductive layer and the ferroelectric layer, the interface layer exists between the first conductive layer and the buffer layer. A method for operating a non-volatile memory device characterized by this.

28. A first conductive layer, A second conductive layer, A ferroelectric layer made of a metal oxide between the first conductive layer and the second conductive layer, and A method for operating a non-volatile memory device, characterized by comprising: Having a buffer layer which is a metal oxide having oxygen ion conductivity and containing a metal having a plurality of valences between the ferroelectric layer and the first conductive layer and / or the second conductive layer, and The ferroelectric layer is composed of polycrystals having a plurality of polarization orientations, and the operating voltage of the device is set to the operating voltage at which only the crystal having the largest component perpendicular to the film surface among the crystals having the largest component perpendicular to the film surface undergoes polarization reversal. A method for operating a non-volatile memory device characterized by this.

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