Method for Remotely Monitoring Timing Performance of PTP Slave

Abstract

In some embodiments, the method is performed after a first clock of a computing device is locked and synchronized with a second clock associated with the first device, and a difference between the first clock and the second clock is determined during locking. The method measures a path delay to the second device based on sending a message to the second device including a first timestamp of the first clock and receiving a message from the second device including a second timestamp of a third clock. A third message is sent to the second device including a third timestamp of the first clock locked to the second clock, the third message including the path delay. The third timestamp and the path delay enable the second device to analyze the lock quality of the first clock relative to the second clock based on the time of the third clock.

Description

Technical Field

[0001] Cross - reference to Related Applications This disclosure claims priority to U.S. Provisional Application No. 62 / 821,114, filed on March 20, 2019, entitled "A METHOD OF REMOTELY MONITORING THE TIMING PERFORMANCE OF A PTP SLAVE", the entire contents of which are incorporated herein by reference.

Background Art

[0002] High - precision time protocol (PTP) clocks perform frequency and phase recovery based on time stamps received from and requested by a master clock. To perform the recovery, a PTP slave device located within a network locks to a PTP master device. The locking process locks the PTP slave clock to the PTP master clock, thereby synchronizing the PTP slave clock with the PTP master clock. In a timing distribution system, it is important that the timing performance of the PTP slave clock can be monitored. There are several factors that can affect the locking quality of the PTP slave clock to the PTP master clock. For example, packet delay variation (PDV) within the network can affect the locking quality between the PTP master clock and the PTP slave clock. Also, the delay asymmetry between the PTP master device and the PTP slave device can affect the locking quality. Further problems can include a hold - over state where the PTP slave cannot reach the PTP master device, and the hold - over state means that the PTP slave clock is not locked to the PTP master clock.

Brief Description of the Drawings

[0003] With respect to the considerations according to the drawings, and in particular with respect to the considerations regarding the drawings, it is emphasized that the details shown represent examples for illustrative considerations and are presented to provide an explanation of the principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show more details of the implementation examples than what is necessary for a basic understanding of the present disclosure. The considerations according to the drawings, together with the drawings, will make it clear to those skilled in the art how embodiments according to the present disclosure can be practiced. The same or similar reference numbers can be used to identify the same or similar elements in the various drawings and the supporting descriptions, or otherwise refer to such elements.

[0004]

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DETAILED DESCRIPTION OF THE INVENTION

[0005] This specification describes techniques for a timing synchronization system. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of several embodiments. Some embodiments defined by the claims may include some or all of these examples alone, or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

[0006] A slave device, such as a high-precision time protocol (PTP) slave device, may include a slave clock that synchronizes with a master clock located within a master device, such as a PTP master device. A protocol such as PTP may be a timing system that can be used in applications such as within a cable network having remote PHY (RPHY) devices. PTP may be implemented based on Institute of Electrical and Electronics Engineers (IEEE) standards (such as IEEE Standard 1588-2008). The PTP protocol distributes time and frequency over a network such as a packet network. Time synchronization is the synchronization of time between slave devices and master devices within the network, and frequency synchronization is the synchronization of the frequency of the slave clock with the master clock. This protocol creates a master-slave relationship between the grand master clock and slave devices over the network.

[0007] In some embodiments, a slave device may lock its slave clock to the master clock of an operating master device. Then, to test the locking quality of the slave clock to the master clock, the slave device may communicate with a probe master device that includes a probe master clock. The probe master device may be located within a network (e.g., the last network hop or the last few hops to the slave device), such as near the slave device. Thereby, packet delay variation and the impact of asymmetry between the slave device and the probe master device can be reduced. The slave device may receive a synchronization message from the probe master device along with a time stamp referred to as time T1. The slave device may note the time at which the synchronization message is received as time T2. The slave device transmits a delay request message that includes a time stamp of the slave clock, referred to as time T3. The slave device receives a delay response from the probe device along with a time stamp of the probe master clock, referred to as time T4. From the delay request and the delay response, the slave device may then calculate the path delay between the slave device and the probe device. For example, the path delay is ((T2 - T1)+(T4 - T3)) / 2.

[0008] Next, the slave device sends a delay request to the probe master device along with the T3 time and the path delay. The slave device may insert the path delay into a field of the delay request message, such as the T3 correction field. The probe master device may appropriately monitor the clock of the slave device using the T3 time and the calculated path delay inserted into the delay request. For example, the probe master device can then verify the lock quality of the slave clock with the operating master clock using the T3 time and the path delay. That is, T3 time + path delay = the current time of the slave clock. The probe master device can compare the current time of the slave clock with the current time of the probe master clock. As described above, the slave clock can be monitored without the need for an interface for the PTP probe, such as a 1 pulse per second (PPS) interface for the PTP probe, or without the slave device operating as a master clock and synchronizing with the probe slave clock via PTP. Also, the path delay is inserted into a field existing in the PTP protocol, and the PTP probe device is configured to calculate the current time of the slave clock using the correction field.

[0009] System Overview Figure 1 illustrates a simplified system 100 for implementing timing synchronization according to some embodiments. System 100 includes a master device 104 operating in PTP, switches 106-1 to 106-N, a PTP slave device 102, and a PTP probe master device 108. The Precision Time Protocol is used to synchronize timing across the network. Although the Precision Time Protocol is considered, it will be understood that other protocols for synchronizing timing across the network can be used.

[0010] The master device 104 during PTP operation may be a device including the master clock 112-1. The master clock 112-1 may be based on a reference clock such as a Global Navigation Satellite System (GNSS) clock or another time source. The master clock 112-1 may be the master clock in operation used by the PTP slave device 102 to synchronize the slave clock 114.

[0011] The PTP slave device 102 may be located within the network. There is a path #1 110-1 between the PTP slave device 102 and the master device 104 during PTP operation. In some embodiments, the PTP slave device 102 may be located within the network and be remotely located from the master device 104 during PTP operation. The switches 106-1 to 106-N may be network devices that can connect the master device 104 during PTP operation to the PTP slave device 102 via the path #1 110-1 within the network.

[0012] The PTP probe master device 108 can be used to test the quality of the lock of the slave clock 114 with the operating master clock 112-1. The quality of the lock is measured by the difference between the adjusted time of the slave clock 114 and the time of the timing source connected to the probe master clock 112-2 connected to the timing source used by the operating master clock 112-1. As will be discussed in more detail below, the PTP probe master device 108 includes a probe master clock 112-2 that is used to check the lock quality of the slave clock 114. In some embodiments, the PTP probe master device 108 is connected to the PTP slave device 102 at a location closer to the PTP slave device 102 than the location of the PTP master device 104 during PTP operation with respect to the PTP slave device 102. For example, the PTP probe master device 108 can be connected to the PTP slave device 102 via one of the switches 106-1 to 106-N. In some embodiments, the PTP probe master device 108 is connected to the last hop switch 106-N to the PTP slave device 102 within path #2 110-2. The PTP probe master device 108 can be illustrated as being at the last hop within path #1 110-1 or connected to the switch 106-N, but the PTP probe master device 108 can be located elsewhere and need not be located within path #1 110-1. However, the PTP probe master device 108 can be located at a location where packet delay variation and asymmetry in the request and response processes are minimized. For example, by locating the PTP probe master device 108 within the switch 106-N, a single hop between the switch 106-N and the PTP slave device 102 can limit packet delay variation and asymmetry within path #2 110-2 compared to path #1 110-1 that passes through multiple switches 106-1 to 106-N that can cause more packet delay variation and asymmetry.

[0013] Before checking the lock quality, the PTP slave device 102 first locks the slave clock 114 to the operating master clock 112-1. To synchronize the slave clock 114 with the operating master clock 112-1, the PTP slave device 102 may calculate the round-trip delay between the PTP slave device 102 and the master device 104 in PTP operation. For example, the PTP slave device 102 may receive a synchronization message from the master device 104 in PTP operation along with T1 time from the operating master clock 112-1, which is the timestamp when the synchronization message was sent. The master device 104 in PTP operation may determine the time based on a timing source such as a GNSS clock. The PTP slave device 102 may note the time when the synchronization message is received as time T2. The PTP slave device 102 sends a delay request message including the timestamp of the slave clock 114, referred to as time T3. The PTP slave device 102 receives a delay response from the master device 104 in PTP operation along with the timestamp of the operating master clock 112-1, referred to as time T4, when the delay request was received. From these times, the slave device may then calculate the path delay between the master device 104 in PTP operation and the PTP slave device 102. For example, the path delay in path #1 110-1 is ((T2 - T1) + (T4 - T3)) / 2. As can be seen, the PTP slave device 102 assumes that the path delay is symmetric in both directions. Although this method of determining the path delay is described, other methods may be recognized.

[0014] The PTP slave device 102 can determine the correct time at which it needs to set the slave clock 114 using the path delay. For example, adding the path delay to the time of the operating master clock 112-1 is the correct time of the operating master clock 112-1. The PTP slave device 102 can lock the slave clock 114 to the correct time of the operating master clock 112-1. For example, during PTP operation, the master device 104 can send a synchronization message using the time used by the PTP slave device 102 to lock the time of the slave clock 114. Therefore, the PTP slave device 102 can adjust the slave clock 114 based on the difference between the time of the slave clock 114 and the time of the operating master clock 112-1. The PTP slave device 102 ultimately locks the slave clock 114 to the operating master clock 112-1. The phase of the clock frequency can also be adjusted in the locking process. Once locked, the time and phase of the slave clock 114 are locked to the time and frequency of the operating master clock 112-1.

[0015] As discussed above, the PTP slave device 102 needs to check the locking quality of the slave clock 114. That is, the PTP slave device 102 can check whether the synchronized timing and frequency of the slave clock 114 are accurate. To perform this check, the PTP slave device 102 communicates with the PTP probe master device 108.

[0016] In the conventional method, the PTP slave device 102 can check the lock quality of the slave clock 114 using different methods. For example, the PTP slave device 102 can output the slave clock 114 to an external probe using a dedicated interface such as a 1 pulse / second interface. The probe compares the time and phase of the slave clock 114 with its master clock. This is usually done by connecting the lobe master clock to the same reference clock as the operating master clock 112-1. This method can monitor the slave clock 114, but the PTP slave device 102 needs to have an external probe interface such as a 1PPS interface. Also, the PTP slave device 102 and the PTP probe master device 108 need to be accessed to install the connection, which can be difficult if the PTP slave device 102 is located remotely from the headend or core, such as within a remote physical device or a small cell device.

[0017] In a second approach, the PTP slave device 102 may function as a boundary clock that operates the slave clock 114 as a master clock for the PTP slave device 102 to communicate with a PTP probe including the slave clock. The PTP probe compares the frequency and phase of its slave clock with the master clock of the PTP slave device 102. The PTP probe is connected to the same reference clock as the operating master clock 112-1 to check the timing of the master clock of the PTP slave device 102. However, there is a problem that the PTP slave device 102 may not support acting as a boundary clock. That is, the PTP slave device 102 may not be able to act as a master clock. Further, the PTP probe is remotely located from the PTP slave device 102, and the path may suffer from asymmetry and packet delay variations that can affect the accuracy of the test of the master clock of the PTP slave device 102. Due to the above factors, it is important to monitor the accuracy of the PTP slave clock compared to the PTP master clock and to identify any of the above problems without using the PPS interface and without operating the PTP slave device 102 as a boundary device.

[0018] In the prior art, there is no implementation example for transmitting timestamp information to monitor the slave clock in the transmission delay request message. Similarly, IEEE 1588 describes a method for measuring link propagation delay, but IEEE 1588 does not address measuring delay at the path level including intermediate nodes in the path, while IEEE 1588 is limited to measuring the delay of the link connecting adjacent nodes.

[0019] To overcome the above drawbacks, some embodiments use a PTP probe master device 108 to test the lock quality of the slave clock 114. The PTP slave device 102 does not attempt to lock the slave clock 114 to the probe master clock 112-2. Instead, the PTP probe master device 108 monitors the lock quality of the slave clock 114 with respect to the operating master clock 112-1. The PTP slave device 102 can communicate with the PTP probe master device 108 to calculate the path delay based on the T1 time, T2 time, T3 time, and T4 time. For example, the PTP slave device 102 may receive a synchronization message from the PTP probe master device 108 along with the T1 time from the probe master clock 112-2, which is the timestamp when the synchronization message was sent. The PTP probe master device 108 can determine the time based on a timing source such as a GNSS clock. The PTP slave device 102 may note the time when the synchronization message is received as the T2 time. The PTP slave device 102 sends a delay request message including the timestamp of the slave clock 114, referred to as the T3 time. The PTP slave device 102 receives a delay response from the PTP probe master device 108 along with the timestamp of the probe master clock 112-2, referred to as the T4 time, when the delay request is received. From these times, the PTP slave device 102 can then calculate the path delay between the PTP probe master device 108 and the PTP slave device 102. For example, the path delay within path #2 110-2 is ((T2 - T1) + (T4 - T3)) / 2. The PTP slave device 102 can calculate the path delay over several delay request / delay response round trips. The path delay is assumed to be symmetric in both directions, but since the PTP probe master device 108 may be located closer to the PTP slave device 102, packet delay variation and asymmetry can be limited.

[0020] When calculating the path delay, the PTP slave device 102 adds the path delay between the slave clock 114 and the probe master clock 112-2 to the delay request. In some embodiments, the PTP slave device 102 adds the path delay to a correction field of the delay request that includes the T3 time. The correction field may be a field that cannot normally be used when checking the lock quality. The correction field can usually be used by a clock such as a transparent clock of 1588 to add corrections to time stamps due to internal delays within the clock. The transparent clock may be within a switch. The correction field is not normally used in the slave clock. However, the PTP probe master device 108 can be configured to use the T3 time and the path delay within the correction field to determine the adjusted time for the slave device 114 in order to check the quality of the lock on the slave clock 114. For example, the PTP probe master device 108 adds the path delay to the T3 time to calculate the current time of the slave clock 114. That is, the time T3 at which the delay request is transmitted in addition to the path delay needs to be the current time. Next, the PTP probe master device 108 compares the current time of the probe master clock 112-2 with the calculated current time for the slave clock 114. Based on the comparison, the PTP probe master device 108 can check the quality of the slave clock 114. For example, since the PTP probe master device 108 is connected to the same reference clock as the master device 104 during PTP operation, any timing inaccuracies in the slave clock 114 can be determined by the comparison. Since the path delay is used and path #2 110-2 may suffer from minimal packet delay variation or asymmetry, the path delay may be an accurate reading of the path delay. Therefore, the adjusted time for the slave clock 114 may result in an accurate current time that is close to the time and phase of the probe master clock 112-2 or the same time and phase as the probe master clock 112-2.If the difference between the adjusted current time of the slave clock 114 and the current time of the probe master clock 112-2 meets a threshold (e.g., is below the threshold), the PTP probe master device 108 may verify the accuracy of the slave clock 114.

[0021] Connecting the PTP probe master device 108 to the PTP slave device 102 without the need for a direct physical connection relaxes the requirement that the PTP slave device 102 includes an interface for the slave clock 114, and also eliminates the need for the PTP slave device 102 to operate as a boundary clock to inform its clock to a remote PTP slave probe. The only requirement is that the PTP slave device 102 inserts the T3 time into the delay request message along with the path delay in the correction field, which the PTP slave device 102 has the ability to perform based on communication with the operating master clock 112-1. Here, the process will be described in more detail below.

[0022] PTP slave device FIG. 2 illustrates a more detailed example of the PTP slave device 102 according to some embodiments. The PTP slave device 102 includes a plurality of ports for connecting to the master device 104 during PTP operation and the PTP probe master device 108. For example, the PTP slave device 102 includes a slave port #1 206-1 for connecting to the master device 104 during PTP operation. Also, the PTP slave device 102 includes a slave port #2 206-2 for connecting to the PTP probe master device 108.

[0023] The clock performance manager 202 can select a port depending on whether the PTP slave device 102 locks to the operating master clock 112-1 or tests the quality of the lock with the probe master clock 112-2. For example, the clock performance manager 202 can use the slave port #1 206-1 to lock the slave clock 114 to the operating master clock 112-1. Then, the clock performance manager 202 can use the slave port #2 206-2 to test the lock quality of the slave clock 114 with the probe master clock 112-2. The clock performance manager 202 can be configured so that the slave port #2 206-2 is not used in the algorithm for selecting the optimal master clock. Some ways may be, for example, configuring the slave port #2 206-2 with a lower priority, or setting a clock class / quality value for the probe master clock 112-2 so that it is not selected. Rather, the clock performance manager 202 uses the slave port #2 206-2 to test the lock quality of the slave clock 114 and does not lock the time of the slave clock 114 to the probe master clock 112-2.

[0024] Figure 3 illustrates a simplified flowchart 300 of a process for configuring the port 206 on the PTP slave device 102 to lock to the operating master clock 112-1 according to some embodiments. At 302, the PTP slave device 102 is configured with two PTP slave ports 206-1 and 206-2. At 304, the PTP slave device 102 configures the slave port #2 206-2 so that it cannot be selected as the master clock.

[0025] At 306, the clock performance manager 202 connects the slave port #1 206-1 to the operating master clock 112-1 to perform a locking process. At 308, the clock performance manager 202 calculates the path delay of path #1 110-1. This path delay takes the round-trip time from the PTP slave device 102 and the master device 104 operating in PTP and divides the round-trip time by 2. After determining the path delay, at 310, the PTP slave device 102 uses the path delay of path #1 110-1 to lock the slave clock 114 to the operating master clock 112-1. When locked to the operating master clock 112-1, the time of the slave clock 114 is adjusted based on the time of the operating master clock 112-1, and path delays such as the path delay are added to the time T4 from the operating master clock 112-1 to determine the correct current time (for example, time T4 + path delay = current time). The slave clock 114 can ignore the value of the correction field that the probe master device copies from the delay request message to the correction field when the probe master device receives the T4 timestamp in the delay response message and does not use the correction field to correct the T4 time.

[0026] Lock quality test After locking the slave clock 114 to the operating master clock 112-1, the clock performance manager 202 may test the lock quality. FIG. 4 illustrates a simplified flowchart 400 for testing the lock quality of the slave clock 114 according to some embodiments. At 402, the PTP slave device 102 connects to the probe master clock 112-2 through the slave port #2 206-2. At 404, the PTP slave device 102 calculates the path delay in path #2 between the PTP slave device 102 and the PTP probe master device 108.

[0027] At 406, the PTP slave device 102 adds the T3 time from the slave clock 114 into the delay request message. At 408, the PTP slave device 102 updates the correction field of the delay request message to include the path delay. At 410, the PTP slave device 102 transmits the delay request message.

[0028] The PTP probe master device 108 can receive the T3 time and the path delay and test the locking quality of the slave clock 114. For example, the PTP probe master device 108 uses the T3 time and the path delay to adjust the time of the slave clock 114 to take into account the path delay for transmitting a delay request. This results in the current time of the slave clock 114. Next, the PTP probe master device 108 compares the current time of the probe master clock 112-2 with the adjusted T3 time (e.g., the current time of the slave clock 114) to determine the accuracy of the slave clock 114. For example, if the adjusted T3 time is similar to the time of the probe master clock 112-2, the locking quality of the slave clock 114 is high. However, if the adjusted T3 time is not close to the time of the probe master clock 112-2, the PTP probe master device 108 determines that the locking quality is low. The PTP probe master device 108 can test the locking quality using a threshold. For example, if the difference between the adjusted T3 time and the time of the probe master clock 112-2 exceeds the threshold, the PTP probe master device 108 may determine that the locking quality is not good, and if the difference is below the threshold, the PTP probe master device 108 may determine that the locking quality is good.

[0029] The PTP probe master device 108 can output the result of the comparison. Note that the above process can be performed multiple times over time to test the lock quality of the slave clock 114. For example, the lock quality check can be performed one or more times. The result can be based on a summary of the comparison, such as the average of the differences or the number of times the difference exceeds or falls below a threshold, but various methods can be used. Then, after determining the lock quality, the process can be performed after another interval, such as one hour later.

[0030] FIG. 5 illustrates a simplified flowchart 500 of a method for testing the quality of the slave clock 114 in the PTP probe master device 108 according to some embodiments. At 502, after the PTP slave device 102 calculates the path delay, the PTP probe master device 108 receives a delay request message along with the T3 time and the path delay in the correction field.

[0031] At 504, the PTP probe master device 108 calculates the adjusted slave clock time based on the T3 time and the path delay located within the correction field. For example, the PTP probe master device 108 can add the path delay to the T3 time to determine the adjusted T3 time. At 506, the PTP probe master device 108 compares the master clock time with the adjusted time.

[0032] At 508, the PTP probe master device 108 can output the result of the comparison. For example, the PTP probe master device 108 can compare the result of the comparison with a threshold to determine the quality or accuracy of the slave clock 114.

[0033] [Example 1] Hereinafter, an example of testing the lock quality of the slave clock 114 will be described. The test can use the following parameters. · D-ds-o → The actual downstream (DS) nominal delay between the operating master clock 112-1 and the slave clock 114, ·D-us-o → The actual upstream (US) nominal delay between the slave clock 114 and the operating master clock 112-1, ·Asym-o → The difference in the asymmetric path between the operating master clock 112-1 and the slave clock 114, ·D-ds-p → The downstream delay between the probe master clock 112-2 and the slave clock 114, ·D-us-p → The upstream delay between the slave clock 114 and the probe master clock 112-2, ·Asym-o → The difference in the asymmetric path between the probe master clock 112-2 and the slave clock 114, ·T-m-o → The time of the operating master clock 112-1, ·Tsa-p → The time of the slave clock 114 analyzed by the PTP probe master device 108, and ·Ts → The time of the slave clock 114 locked to the operating master clock 112-1.

[0034] Assuming there is an asymmetry in the path between the slave clock 114 and the operating master clock 112-1, the PTP slave device 102 calculates the path delay from the operating master clock 112-1 as follows, without knowing the asymmetry factor. Ts = Tm-o + (D-ds-o + D-us-o + A-asym-o) / 2

[0035] The PTP slave device 102 calculates the nominal average path delay without including the unknown asymmetry value and, accordingly, adjusts its slave clock 114, which leads to a delay asymmetry error that includes half of the path asymmetry value. Ts = Tm-o + (A-asym-o / 2)

[0036] Note that the slave clock 114 is inaccurate compared to the operating master clock 112-1, which includes half of the path asymmetry value. This error is due to the two path delays in the upstream and downstream directions being asymmetric. The calculation of the path delay assumes that these delays are symmetric.

[0037] Here, assume that there is a very small path asymmetry between the PTP slave device 102 and the PTP probe master device 108. The PTP slave device 102 can accurately calculate the path delay from the PTP probe master device 108 as follows. Ts=(D - ds - p + D - us - p) / 2 = D - us - p

[0038] In this embodiment, the PTP slave device 102 transmits its time (T3) to the PTP probe master device 108 and embeds the calculated path delay in the correction field. The PTP probe master device 108 can receive the following information from the delay request (T3, correction field), which corresponds to (Ts, D - us - p) including D - us - p (actual path delay). Therefore, the time of the slave clock 114 analyzed by the PTP probe master device 108 is as follows. Tsa - p=(Ts - D - us - p)+D - us - p = Tm - o+(A - asym - o / 2)

[0039] The probe reflects half of the operating asymmetry value as the offset measured between the slave clock 114 and the operating master clock 112 - 1.

[0040] Therefore, the performance of the slave clock 114 locked to the operating master clock 112 - 1 can be monitored by a clock probe that exchanges IEEE 1588 standard messages with the slave clock 114. The PTP probe master device 108 operates as a master clock and uses the timestamp values in the messages to determine the performance of the slave clock 114. As the path asymmetry and packet delay variation are minimized, the quality of performance monitoring increases. The operating master clock 112 - 1 and the probe master clock 112 - 2 share a common timing source, such as a GNSS timing source, to triangulate the performance of the slave clock 114.

[0041] As disclosed, the performance of a slave clock can be remotely monitored using the timestamps within the standard IEEE 1588 message. Also, the PTP probe master device 108 may or may not be present within the message transfer data path between the operating master clock 112-1 and the slave clock 114. The operating master clock 112-1 and the PTP probe master device 108 share a common remote timing source to triangulate the performance of the slave clock.

[0042] By providing a method for monitoring the performance of a clock, it may be possible to troubleshoot the timing distribution in a packet network. As more packet-based services, including 5G wireless services, are deployed, it would be beneficial to be able to monitor clock performance and detect problems as quickly as possible. The disclosed technology enables remote monitoring of a packet slave clock by using the timestamps within the standard message and probing the data path from the master clock to the slave clock to remotely monitor the slave clock. With the demand for packet clock performance, the need for monitoring continues to grow with the deployment of 5G.

[0043] Exemplary embodiments

[0044] In some embodiments, the method is performed after locking a first clock of a computing device and synchronizing it with a second clock associated with a first device, the difference between the first clock and the second clock being determined during the locking, and the method includes transmitting, by the computing device, one or more messages including one or more first timestamps of the first clock to a second device, and receiving, from the second device, one or more messages including one or more second timestamps of a third clock, measuring a path delay to the second device based thereon, and transmitting, by the computing device, a third message to the second device including a third timestamp of the first clock locked to the second clock, the third message including the path delay, and based on the third timestamp and the path delay, the second device can analyze the locking quality of the first clock with respect to the second clock based on the time of the third clock.

[0045] In some embodiments, the path delay is inserted into the third message in a correction field of the third message.

[0046] In some embodiments, the second device adjusts a third timestamp of the first clock locked to the second clock by the path delay to generate an adjusted third timestamp, and compares the adjusted third timestamp with the time of the third clock.

[0047] In some embodiments, the third clock and the second clock are connected to the same timing source.

[0048] In some embodiments, the first clock is adjusted by the difference between the first clock and the second clock to lock the first clock to the second clock.

[0049] In some embodiments, the second device is located closer to the computing device compared to the first device.

[0050] In some embodiments, the second device is located at the last hop in the path between the first device and the computing device.

[0051] In some embodiments, the second device is not physically connected to the computing device via an interface.

[0052] In some embodiments, the computing device does not act as a master clock for the third clock of the second device.

[0053] In some embodiments, measuring the path delay to the second device includes calculating the round-trip delay between the computing device and the second device and dividing the round-trip delay by two.

[0054] In some embodiments, the second device analyzes the lock quality of the first clock with respect to the second clock by adding the path delay to a third timestamp to determine an adjusted third timestamp and comparing the adjusted third timestamp to the time of the third clock.

[0055] In some embodiments, the second device analyzes the lock quality of the first clock with respect to the second clock by comparing the difference between the adjusted third timestamp and the time of the third clock to a threshold and outputting the result of the comparison.

[0056] In some embodiments, an alert is output when the difference exceeds the threshold.

[0057] In some embodiments, a non-transitory computer-readable storage medium includes instructions that are executed after locking a first clock of a computing device and synchronizing it with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, and the instructions, when executed, cause the computing device to send one or more messages including one or more first timestamps of the first clock to a second device, and measure a path delay to the second device based on receiving one or more messages including one or more second timestamps of a third clock from the second device, and send a third message to the second device including a third timestamp of the first clock locked to the second clock, the third message including the path delay, and based on the third timestamp and the path delay, the second device can analyze a locking quality of the first clock with respect to the second clock based on the time of the third clock.

[0058] In some embodiments, the path delay is inserted into the third message in a correction field of the third message.

[0059] In some embodiments, the second device adjusts a third timestamp of the first clock locked to the second clock by the path delay to generate an adjusted third timestamp, and compares the adjusted third timestamp with the time of the third clock.

[0060] In some embodiments, the third clock and the second clock are connected to the same timing source.

[0061] In some embodiments, the first clock is adjusted by a difference between the first clock and the second clock to lock the first clock to the second clock.

[0062] In some embodiments, the second device is located at the last hop between the first device and the computing device in the path.

[0063] In some embodiments, the apparatus comprises one or more computer processors and a computer-readable storage medium containing instructions for locking a first clock of the apparatus and controlling the one or more computer processors after synchronizing with a second clock associated with the first device. The difference between the first clock and the second clock is determined to be operable to measure the path delay to the second device based on transmitting one or more messages including one or more first timestamps of the first clock to the second device during locking and receiving one or more messages including one or more second timestamps of a third clock from the second device, and transmitting a third message to the second device including a third timestamp of the first clock locked to the second clock. The third message includes the path delay, and based on the third timestamp and the path delay, the second device can analyze the locking quality of the first clock relative to the second clock based on the time of the third clock.

[0064] System FIG. 5 illustrates an example of a dedicated computer system 500 according to some embodiments. The computer system 500 includes a bus 502, a network interface 504, a computer processor 506, a memory 508, a storage device 510, and a display 512.

[0065] Bus 502 can be a communication mechanism for communicating information. Computer processor 506 can execute a computer program stored in memory 508 or storage device 510. Any suitable programming language can be used to implement the routines of some embodiments, including C, C++, Java (registered trademark), assembly language, etc. Different programming techniques, such as procedural or object-oriented, can be employed. The routines can be executed on a single computer system 500 or multiple computer systems 500. Additionally, multiple computer processors 506 can be used.

[0066] Memory 508 can store instructions, such as source code or binary code, for implementing the above-described techniques. Memory 508 can also be used to store variables or other intermediate information during the execution of instructions executed by processor 506. Examples of memory 508 include random access memory (RAM), read-only memory (ROM), or both.

[0067] Storage device 510 can also store instructions, such as source code or binary code, for implementing the above-described techniques. Storage device 510 can additionally store data used and manipulated by computer processor 506. For example, storage device 510 can be a database accessed by computer system 500. Other examples of storage device 510 include random access memory (RAM), read-only memory (ROM), hard drive, magnetic disk, optical disk, CD-ROM, DVD, flash memory, USB memory card, or any other medium readable by a computer.

[0068] Memory 508 or storage device 510 may be an example of a non-transitory computer-readable storage medium for use by or in connection with computer system 500. The non-transitory computer-readable storage medium includes instructions for controlling computer system 500 so that it is configured to perform the functions described by some embodiments. The instructions, when executed by one or more computer processors 506, may be configured to perform what is described in some embodiments.

[0069] Computer system 500 includes a display 512 for displaying information to a computer user. Display 512 may display a user interface used by the user to interact with computer system 500.

[0070] Computer system 500 also includes a network interface 504 for providing a data communication connection via a network such as a local area network (LAN) or a wide area network (WAN). A wireless network may also be used. In any such implementation, network interface 504 transmits and receives electrical, electromagnetic, or optical signals carrying digital data streams representing various types of information.

[0071] Computer system 500 may send and receive information through network interface 504 via a network 514, which may be an intranet or the Internet. Computer system 500 may interact with other computer systems 500 through network 514. In some examples, client-server communication is performed through network 514. Also, implementations of some embodiments may be distributed across computer system 500 through network 514.

[0072] Some embodiments may be implemented in a non-transitory computer-readable storage medium for use by or in connection with an instruction execution system, apparatus, system, or machine. The computer-readable storage medium includes instructions for controlling a computer system to implement the methods described by some embodiments. The computer system may include one or more computing devices. The instructions may be configured to implement what is described in some embodiments when executed by one or more computer processors.

[0073] As used in the description herein and throughout the following claims, the words "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the following claims, the meaning of "in" includes "in" and "on" unless the context clearly dictates otherwise.

[0074] The above description illustrates various embodiments, along with examples of how aspects of some embodiments may be implemented. The above examples and embodiments should not be considered the only embodiments, but are presented to illustrate the flexibility and advantages of some embodiments defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be employed without departing from the scope of this specification as defined by the claims. Some aspects of the present invention are described below. [Aspect 1] A method performed after locking a first clock of a computing device and synchronizing it with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, and the method comprises transmitting, by the computing device, one or more messages including one or more first timestamps of the first clock to a second device, and measuring a path delay to the second device based on receiving, from the second device, one or more messages including one or more second timestamps of a third clock transmitting, by the computing device, a third message to the second device including a third timestamp of the first clock locked to the second clock, wherein the third message includes the path delay, and based on the third timestamp and the path delay, the second device can analyze a locking quality of the first clock with respect to the second clock based on a time of the third clock. [Aspect 2] The method according to aspect 1, wherein the path delay is inserted into the third message in a correction field of the third message. [Aspect 3] The method according to aspect 1, wherein the second device adjusts the third timestamp of the first clock locked to the second clock by the path delay to generate an adjusted third timestamp, and compares the adjusted third timestamp with the time of the third clock. [Aspect 4] The method according to aspect 1, wherein the third clock and the second clock are connected to the same timing source. [Aspect 5] The method according to aspect 1, wherein the first clock is adjusted by the difference between the first clock and the second clock so as to lock the first clock to the second clock. [Aspect 6] The method according to aspect 1, wherein the second device is located closer to the computing device compared to the first device. [Aspect 7] The method according to aspect 1, wherein the second device is located at the last hop in the path between the first device and the computing device. [Aspect 8] The method according to aspect 1, wherein the second device is not physically connected to the computing device via an interface. [Aspect 9] The method according to aspect 1, wherein the computing device does not act as a master clock for the third clock of the second device. [Aspect 10] Measuring the path delay to the second device, Calculating a round-trip delay between the computing device and the second device, and Dividing the round-trip delay by 2, the method according to aspect 1. [Aspect 11] The second device determines the lock quality of the first clock with respect to the second clock by Adding the path delay to the third timestamp to determine an adjusted third timestamp, and Analyzing the adjusted third timestamp by comparing it with the time of the third clock, the method according to aspect 1. [Aspect 12] The second device determines the lock quality of the first clock with respect to the second clock by Comparing the difference between the adjusted third timestamp and the time of the third clock with a threshold, and Outputting the result of the comparison, the method according to aspect 11. [Aspect 13] The method according to aspect 12, wherein when the difference exceeds the threshold, an alert is output. [Aspect 14] A non-transitory computer-readable storage medium including instructions to be executed after locking a first clock of a computing device and synchronizing it with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, and the instructions, when executed, Based on sending one or more messages including one or more first timestamps of the first clock to a second device and receiving one or more messages including one or more second timestamps of a third clock from the second device, measuring a path delay to the second device. To cause the computing device to be operable to perform: sending a third message to the second device including a third timestamp of the first clock locked to the second clock, the third message including the path delay, and the third timestamp and the path delay enabling the second device to analyze a lock quality of the first clock relative to the second clock based on a time of the third clock, a non-transitory computer-readable storage medium. [Aspect 15] The non-transitory computer-readable storage medium of aspect 14, wherein the path delay is inserted into the third message in a correction field of the third message. [Aspect 16] The non-transitory computer-readable storage medium of aspect 14, wherein the second device adjusts the third timestamp of the first clock locked to the second clock by the path delay to generate an adjusted third timestamp and compares the adjusted third timestamp with the time of the third clock. [Aspect 17] The non-transitory computer-readable storage medium of aspect 14, wherein the third clock and the second clock are connected to the same timing source. [Aspect 18] The non-transitory computer-readable storage medium of aspect 14, wherein the first clock is adjusted by the difference between the first clock and the second clock to lock the first clock to the second clock. [Aspect 19] The non-transitory computer-readable storage medium of aspect 14, wherein the second device is located at a last hop of a path between the first device and the computing device. [Aspect 20] An apparatus comprising: one or more computer processors; a computer-readable storage medium including instructions for controlling the one or more computer processors after locking a first clock of the apparatus and synchronizing with a second clock associated with a first device, wherein a difference between the first clock and the second clock is during the locking Transmitting to the second device one or more messages including one or more first timestamps of the first clock, and measuring a path delay to the second device based on receiving from the second device one or more messages including one or more second timestamps of a third clock; Determined to be operable to perform transmitting a third message to the second device including a third timestamp of the first clock locked to the second clock, the third message including the path delay, and the third timestamp and the path delay enabling the second device to analyze a locking quality of the first clock with respect to the second clock based on the time of the third clock.

Claims

1. A method to be performed after locking a first clock of a computing device and synchronizing it with a second clock associated with a first device, wherein a difference between the first clock and the second clock is determined during the locking, and the method comprises: transmitting, by the computing device, one or more messages including one or more first timestamps of the first clock to a second device, and measuring a path delay to the second device based on receiving, from the second device, one or more messages including one or more second timestamps of a third clock; transmitting, by the computing device, a third message including a third timestamp of the first clock locked to the second clock to the second device; wherein the third message includes the path delay; wherein the second device can analyze a locking quality of the first clock with respect to the second clock based on the third timestamp and the path delay, based on a time of the third clock.

2. The method according to claim 1, wherein the path delay is inserted into the third message in a correction field of the third message.

3. The method according to claim 1, wherein the second device adjusts the third timestamp of the first clock locked to the second clock by the path delay to generate an adjusted third timestamp, and compares the adjusted third timestamp with the time of the third clock.

4. The method according to claim 1, wherein the third clock and the second clock are connected to the same timing source.

5. The method according to claim 1, wherein the first clock is adjusted by the difference between the first clock and the second clock to lock the first clock to the second clock.

6. The method according to claim 1, wherein the second device is located closer to the computing device compared to the first device.

7. The method according to claim 1, wherein the second device is located at a last hop of a path between the first device and the computing device.

8. The method according to claim 1, wherein the second device is not physically connected to the computing device via an interface.

9. The method according to claim 1, wherein the computing device does not act as a master clock with respect to the third clock of the second device.

10. Measuring the path delay to the second device comprises Calculating a round-trip delay between the computing device and the second device, and Dividing the round-trip delay by 2, the method according to claim 1.

11. The second device determines the lock quality of the first clock with respect to the second clock by Adding the path delay to the third timestamp to determine an adjusted third timestamp, and Analyzing the adjusted third timestamp by comparing it with the time of the third clock, the method according to claim 1.

12. The second device determines the lock quality of the first clock with respect to the second clock by Comparing the difference between the adjusted third timestamp and the time of the third clock with a threshold value, and Analyzing the result of the comparison by outputting the result, the method according to claim 11.

13. The method according to claim 12, wherein when the difference exceeds the threshold value, an alert is output.

14. A computer-readable storage medium storing instructions executed by a computing device, the instructions being executed after locking a first clock of the computing device and synchronizing it with a second clock associated with a first device, wherein the difference between the first clock and the second clock is determined during the locking, and when the instructions are executed, Causing the computing device to transmit one or more messages including one or more first timestamps of the first clock to a second device, and measuring a path delay to the second device based on receiving one or more messages including one or more second timestamps of a third clock from the second device, and Causing the computing device to transmit a third message including a third timestamp of the first clock locked to the second clock to the second device. The third message includes the path delay, A computer-readable storage medium in which the second device can analyze the lock quality of the first clock with respect to the second clock based on the time of the third clock by the third timestamp and the path delay. **Claim 15** The computer-readable storage medium according to claim 14, wherein the path delay is inserted into the third message in a correction field of the third message. **Claim 16** The computer-readable storage medium according to claim 14, wherein the second device adjusts the third timestamp of the first clock locked to the second clock by the path delay to generate an adjusted third timestamp, and compares the adjusted third timestamp with the time of the third clock. **Claim 17** The computer-readable storage medium according to claim 14, wherein the third clock and the second clock are connected to the same timing source. **Claim 18** The computer-readable storage medium according to claim 14, wherein the first clock is adjusted by the difference between the first clock and the second clock so as to lock the first clock to the second clock. **Claim 19** The computer-readable storage medium according to claim 14, wherein the second device is located at the last hop of the path between the first device and the computing device. **Claim 20** An apparatus, One or more computer processors, A computer-readable storage medium including instructions executed by the one or more computer processors after locking the first clock of the apparatus and synchronizing it with a second clock associated with a first device, the instructions determining a difference between the first clock and the second clock during the locking; Transmitting one or more messages including one or more first timestamps of the first clock to a second device; Measuring a path delay to the second device based on receiving one or more messages including one or more second timestamps of a third clock from the second device Causing the one or more computer processors to send a third message to the second device including a third timestamp of the first clock locked to the second clock; An apparatus, wherein the third message includes the path delay, and based on the third timestamp and the path delay, the second device can analyze the locking quality of the first clock with respect to the second clock based on the time of the third clock.

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