Semiconductor device and impedance matching circuit

Abstract

To solve the problem in which: a signal loss caused by an impedance matching circuit becomes large in a conventional semiconductor device.SOLUTION: A semiconductor device has: a first terminal P1 connected with an antenna ANT; a second terminal P2 connected with an input terminal Prx of a reception circuit 10; a third terminal P3 connected with an output terminal Ptx of a transmission circuit 20; a first inductor L1 provided on a signal path from the first terminal P1 to the second terminal P2; and a second inductor L2 provided on a signal path from the first terminal P1 to the third terminal P3. The first inductor L1 and the second inductor L2 are formed so as to be at least partially overlapped with each other in a plan view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an impedance matching circuit, and more particularly, to an impedance matching circuit used for an antenna and a semiconductor device including the impedance matching circuit.

Background Art

[0002] In recent years, wireless communication has become widespread, and many devices have been equipped with antennas and signal transmission / reception circuits for wireless communication. For example, Patent Document 1 discloses a technique related to a transmission / reception device including an impedance matching circuit that matches the impedance of an antenna and the impedance of a transmission / reception circuit.

[0003] The impedance matching circuit of the transmission / reception circuit described in Patent Document 1 is an on-chip matching circuit that shares one inductor in a transceiver. Thereby, in Patent Document 1, the circuit area required for the inductor that increases the circuit area is reduced.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the technique described in Patent Document 1, since the switch SW0 for switching the usage method of one inductor generates signal loss in any operation mode of the reception mode and the transmission mode, there is a problem that the signal gain cannot be increased.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, a semiconductor device and an impedance matching circuit include a first terminal connected to an antenna, a second terminal connected to an input terminal of a receiving circuit, a third terminal connected to an output terminal of a transmitting circuit, a first inductor provided in a signal path from the first terminal to the second terminal, and a second inductor provided in a signal path from the first terminal to the third terminal, and the first inductor and the second inductor are formed such that at least a part of them overlaps in a plan view.

Advantages of the Invention

[0008] According to the above embodiment, the semiconductor device and the impedance matching circuit can reduce the circuit area while preventing a decrease in signal gain.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] For the sake of clarity of explanation, the following descriptions and drawings have been appropriately omitted and simplified. Also, in each drawing, the same elements are denoted by the same reference numerals, and redundant explanations are omitted as necessary.

[0011] FIG. 1 shows a circuit diagram of a semiconductor device according to Embodiment 1. As shown in FIG. 1, the semiconductor device 1 includes a reception circuit 10, a transmission circuit 20, and an impedance matching circuit 30. Then, the semiconductor device 1 realizes transmission and reception of radio signals using the antenna ANT.

[0012] The reception circuit 10 amplifies the signal received by the antenna ANT and transmits it to a subsequent circuit (for example, an internal circuit). The transmission circuit 20 amplifies the signal generated by the internal circuit and drives the antenna ANT to output a radio signal from the antenna ANT. Then, in the semiconductor device 1, the impedance of the antenna ANT and the impedance matching circuit 30 are used to match the impedances of the reception circuit 10 and the transmission circuit 20.

[0013] The receiving circuit 10 includes an input terminal Prx, a receiving amplifier 11, a power switch SW11, and a capacitor C1. The input terminal Prx is a terminal for receiving a signal from the impedance matching circuit 30. In the receiving circuit 10, the signal input from the input terminal Prx is supplied to the receiving amplifier 11 via the capacitor C1. The receiving amplifier 11 amplifies the supplied signal and outputs it to the internal circuit. Also, in the receiving circuit 10, power is supplied to the receiving amplifier 11 via the power switch SW11. The power switch SW11 switches the supply and cutoff of power to the receiving amplifier 11 according to an instruction from the amplifier control circuit 100.

[0014] The transmitting circuit 20 includes an output terminal Ptx, a transmitting amplifier 21, a power switch SW21, and a capacitor C2. The output terminal Ptx is a terminal for outputting a transmission signal that is output to the antenna ANT via the impedance matching circuit 30. In the transmitting circuit 20, the signal input from the internal circuit is amplified and output from the output terminal Ptx via the capacitor C2. The transmitting amplifier 21 amplifies the supplied signal and outputs it to the impedance matching circuit 30 and the antenna ANT. Also, in the transmitting circuit 20, power is supplied to the transmitting amplifier 21 via the power switch SW21. The power switch SW21 switches the supply and cutoff of power to the transmitting amplifier 21 according to an instruction from the amplifier control circuit 100.

[0015] The amplifier control circuit 100 operates the receiving amplifier 11 of the receiving circuit 10 and the transmitting amplifier 21 of the transmitting circuit 20 exclusively.

[0016] Here, in the semiconductor device 1 according to Embodiment 1, since the impedance matching circuit 30 has one of the features, the impedance matching circuit 30 will be described in detail below. The impedance matching circuit 30 includes an inductor 31 and a first variable capacitor Cp. The inductor 31 has a first terminal P1 connected to the antenna, a second terminal P2 connected to the input terminal Prx of the receiving circuit 10, and a third terminal P3 connected to the output terminal Ptx of the transmitting circuit 20. The impedance matching circuit 30 includes a first inductor L1 provided in the signal path from the first terminal P1 to the second terminal P2, and a second inductor P2 provided in the signal path from the first terminal P1 to the third terminal P3. In the impedance matching circuit 30, the first variable capacitor Cp is connected between the first terminal P1 and a fixed potential terminal (ground terminal in FIG. 1) whose potential is fixed alternately.

[0017] In the impedance matching circuit 30 according to Embodiment 1, by configuring the first inductor L1 and the second inductor L2 to have a mutual inductance M, reduction of the signal gain loss of the signal passing through the impedance matching circuit 30 and reduction of the circuit board area are realized.

[0018] Therefore, first, the structure of the inductor 31 will be described. FIG. 2 shows a diagram for explaining the layout of the inductor according to Embodiment 1. As shown in FIG. 2, the inductor 31 is formed with spiral wiring that forms the first inductor L1 and the second inductor L2 in a concentric circle shape. In the example shown in FIG. 2, the first inductor L1 is formed inside the second inductor L2, but the formation positions of the first inductor L1 and the second inductor L2 may be reversed. Also, in the example shown in FIG. 2, the first inductor L1 and the second inductor L2 are formed to be concentric circles, but the center positions of the first inductor L1 and the second inductor L2 may be shifted. That is, the first inductor L1 and the second inductor L2 only need to be formed so that at least a part thereof overlaps when the formed regions are viewed in plan view.

[0019] Also, in the example shown in FIG. 2, the first inductor L1 and the second inductor L2 are formed in the same wiring layer in the semiconductor device. In the example shown in FIG. 2, wiring is formed in a spiral shape counterclockwise from the position where the first terminal P1 is set. Then, the wiring starting from the first terminal P1 becomes the second inductor L2. Also, from the end on the side different from the first terminal P1 of the wiring constituting the second inductor L2, it is led out to the outside by a wiring 41 formed in a wiring layer different from the wiring constituting the second inductor L2, and the third terminal P3 is set. Also, the wiring constituting the first inductor L1 is formed in a counterclockwise spiral shape in the inner region of the wiring constituting the second inductor L2. One end of the wiring constituting the first inductor L1 is connected to a portion of the wiring constituting the second inductor L2 close to the first terminal P1 by a wiring 42 formed in a wiring layer different from the wiring layer in which the wiring constituting the first inductor L1 is formed. Also, the other end of the wiring constituting the first inductor L1 is led out to the outside by a wiring 43 formed in a wiring layer different from the wiring layer in which the wiring constituting the first inductor L1 is formed, and the second terminal P2 is set at the led-out portion.

[0020] Here, the winding directions of the first inductor L1 and the second inductor L2 will be described. When a current in the direction from the first terminal P1 to the second terminal P2 is passed through the first inductor L1 and a current in the direction from the first terminal P1 to the third terminal P3 is passed through the second inductor L2, the winding directions of the first inductor L1 and the second inductor L2 are set so that the electric fields generated in the first inductor L1 and the second inductor L2 are in a direction to reinforce each other. That is, the winding directions of the wirings of the first inductor L1 and the second inductor L2 are the same. By making the shape like this, the mutual conductance M between the first inductor L1 and the second inductor L2 becomes a positive conductance.

[0021] Note that the shape of the inductor 31 is not limited to that shown in FIG. 2. FIG. 3 shows a diagram for explaining another layout example of the inductor according to Embodiment 1. The inductor 31a shown in FIG. 3 is a flattened version of the inductor 31 in FIG. 2. Further, in the inductor 31b, a relatively large gap is formed between the wiring constituting the first inductor L1 and the wiring constituting the second inductor L2. Also, the lead-out directions of the first terminal P1 to the third terminal P3 can be appropriately changed according to the layout of other parts of the semiconductor device to which it is applied.

[0022] In the semiconductor device 1 according to Embodiment 1, as the inductor 31, by forming two inductors such that the regions to be formed overlap each other, it is possible to make the device smaller than the case of forming two inductors having the same inductance in separate regions. For example, when coils having the same inductance are created for the inductance of the first inductor L1 and the inductance of the second inductor L2, there is an area reduction effect of about 37% in one example.

[0023] Subsequently, the operation and signal gain of the semiconductor device 1 according to Embodiment 1 will be described. FIG. 4 shows a diagram for explaining the operation of the semiconductor device according to Embodiment 1 in the reception mode. As shown in FIG. 4, in the reception mode, the semiconductor device 1 according to Embodiment 1 sets the reception amplifier 11 to an operating state by turning on the power switch SW11 in the amplifier control circuit 100, while setting the transmission amplifier 21 to a stopped state by turning off the power switch SW21. When in such a state, the equivalent circuit of the semiconductor device 1 is as shown in the lower diagram of FIG. 4.

[0024] That is, in the equivalent circuit of the semiconductor device 1 in the reception mode, the antenna ANT serves as a signal source to generate the input voltage Vi to the impedance matching circuit 30. The impedance of the antenna ANT is represented as the resistance Ri. Also, the input impedance of the receiving amplifier 11 is represented as the output impedance Ro of the impedance matching circuit 30, and the signal input to the receiving amplifier 11 is represented as the output voltage Vo by this output impedance Ro. Further, since the transmitting amplifier 21 is in a stopped state, the capacitor C2 provided at the output portion of the transmitting amplifier 21 is connected between the third terminal P3 of the second inductor L2 and the ground terminal.

[0025] The frequency fnotch at which a notch occurs among the frequency characteristics of the impedance matching circuit 30 represented by such an equivalent circuit is expressed by Equation (1). [Equation] And from Equation (1), it can be seen that in the semiconductor device 1, the higher the mutual inductance M, the higher the frequency fnotch at which a notch occurs.

[0026] Also, FIG. 5 shows a diagram for explaining the operation of the semiconductor device according to Embodiment 1 in the transmission mode. As shown in FIG. 5, in the transmission mode, the semiconductor device 1 according to Embodiment 1 has the amplifier control circuit 100 turn on the power switch SW21 to put the transmitting amplifier 21 in an operating state, while turning off the power switch SW11 to stop the receiving amplifier 11. In such a state, the equivalent circuit of the semiconductor device 1 is as shown in the lower diagram of FIG. 5.

[0027] That is, in the equivalent circuit of the semiconductor device 1 in the transmission mode, the transmission amplifier 21 serves as a signal source and generates an input voltage Vi to the impedance matching circuit 30. Further, the output impedance of the transmission amplifier 21 is represented as a resistance Ri. Also, the impedance of the antenna ANT is represented as an output impedance Ro of the impedance matching circuit 30, and the voltage generated in the antenna ANT is represented as an output voltage Vo by this output impedance Ro. Furthermore, since the receiving amplifier 11 is in a stopped state, a capacitor C1 provided in the input portion of the receiving amplifier 11 is connected between the second terminal P2 of the first inductor L1 and the ground terminal.

[0028] Among the frequency characteristics of the impedance matching circuit 30 represented by such an equivalent circuit, the frequency fnotch at which a notch occurs is represented by Equation (2). [Number] And from Equation (2), it can be seen that in the semiconductor device 1, the higher the mutual inductance M, the higher the frequency fnotch at which a notch occurs.

[0029] As can be seen from Equations (1) and (2), in the semiconductor device 1 according to Embodiment 1, by configuring the inductor 31 so that the mutual inductance M occurs, the frequency at which a notch occurs can be increased. And when the frequency at which a notch occurs increases, for example, the gain at a frequency of 2.5 GHz defined by BLE (Bluetooth Low Energy: registered trademark) can be improved by about 1.0 dB in the receiving mode and 0.2 dB in the transmitting mode.

[0030] From the above description, in the semiconductor device 1 according to Embodiment 1, as the inductor 31, the first inductor L1 that transmits a signal from the antenna ANT to the receiving circuit 10 and the second inductor L2 that transmits a signal from the transmitting circuit 20 to the antenna ANT are formed so as to have a mutual inductance M with each other, whereby the signal loss in the impedance matching circuit 30 can be reduced.

[0031] Further, by forming the first inductor L1 and the second inductor L2 so as to overlap in a plan view, the circuit area required to form the two inductors can be reduced.

[0032] That is, the semiconductor device 1 according to the first embodiment can reduce the circuit area while increasing the signal gain.

[0033] Embodiment 2 In Embodiment 2, an impedance matching circuit 50, which is another form of the impedance matching circuit 30 of the semiconductor device 1 according to Embodiment 1, will be described. Therefore, FIG. 6 shows a circuit diagram of the semiconductor device 2 according to Embodiment 2.

[0034] As shown in FIG. 6, the impedance matching circuit 50 is obtained by adding a second variable capacitor Cs to the impedance matching circuit 30. One terminal of the second variable capacitor Cs is connected to both the node on the first terminal P1 side of the first variable capacitor Cp and the first terminal P1, and the other terminal is connected to the antenna ANT.

[0035] Here, a specific circuit configuration example of the second variable capacitor Cs will be described. FIG. 7 shows a circuit diagram of the second variable capacitor Cs according to Embodiment 2. As shown in FIG. 7, the second variable capacitor Cs has variable capacitor units connected in parallel, and at least one of the variable capacitor units is made effective by a selection signal EN. Each unit capacitor unit includes a capacitor Cb, a transistor Tr11, resistors Rpu1, and Rbg1.

[0036] The capacitor Cb has one end connected to the antenna ANT and the other end connected to the source of the transistor Tr11. The drain of the transistor Tr11 is connected to the first terminal P1 and the terminal on the first terminal P1 side of the first variable capacitor Cp. Also, a selection signal EN is applied to the gate of the transistor Tr11 via a resistor Rpu1. The back gate of the transistor Tr11 is connected to the ground terminal via a resistor Rbg1. In this way, by inserting resistors into the gate and the back gate respectively, even when the amplitude of the signal passing through the transistor Tr11 exceeds the ground voltage (or the AC-fixed potential Vb) or the high-level potential Vg of the selection signal EN in the state where the transistor Tr11 functions as a switch, the conduction state of the transistor Tr11 can be maintained.

[0037] And in the impedance matching circuit 50, by having the second variable capacitor Cs, the impedance variable range can be widened. Therefore, FIG. 8 shows an admittance chart for explaining the impedance variable range in the semiconductor device 2 according to the second embodiment. As shown in FIG. 8, as shown in FIG. 8, the impedance variable range with only the first variable capacitor Cp was within the range along one isoconductance line, but by adding the second variable capacitor Cs, the impedance variable range can be set to span a plurality of isoconductance lines.

[0038] From the above description, by using the impedance matching circuit 50 according to the second embodiment, an impedance tuning range wider than that of the first embodiment can be set, and the impedance adjustment ability can also be widened in the direction in which the impedance decreases.

[0039] Embodiment 3 In the second embodiment, an impedance matching circuit 60, which is another form of the impedance matching circuit 30 of the semiconductor device 1 according to the first embodiment, will be described. Therefore, FIG. 9 shows a circuit diagram of the semiconductor device 3 according to the third embodiment.

[0040] As shown in Fig. 9, the impedance matching circuit 60 is obtained by adding a switch circuit SWrx to the impedance matching circuit 30. The switch circuit SWrx switches between connecting and disconnecting the second terminal P2 and the input terminal Prx of the receiving circuit 10. Here, Fig. 10 shows a circuit diagram of the switch circuit SWrx used in the semiconductor device 3 according to the third embodiment.

[0041] As shown in Fig. 10, it has a transistor Tr21, resistors Rpu2, and Rbg2. The source of the transistor Tr21 is connected to the second terminal P2 of the inductor 31, and the drain is connected to the receiving circuit 10. Also, a switch control signal ENsw is applied to the gate of the transistor Tr21 via the resistor Rpu2. The back gate of the transistor Tr21 is connected to the ground terminal via the resistor Rbg2. In this way, by inserting resistors into the gate and the back gate respectively, the amplitude of the signal passing through the transistor Tr21 in the state where the transistor Tr21 functions as a switch can exceed the ground voltage (or the AC-fixed potential Vb), or the high-level potential Vg of the selection signal EN, and the conduction state of the transistor Tr11 can be maintained.

[0042] By providing the switch circuit SWrx in this way, the influence of the capacitor C2 provided on the receiving circuit 10 side during the transmission mode can be reduced. Also, in order to reduce the loss caused by the insertion of the switch circuit SWrx, it is preferable to select a transistor with a gate width that is somewhat thick. Also, by inserting resistors into the gate node and the back gate of the transistor Tr11, it is necessary to make it electrically floating. This resistor can reduce the parasitic capacitance of the counter gate and the counter back gate seen from the source and the drain.

[0043] Embodiment 4 In Embodiment 4, an impedance matching circuit 70, which is another form of the impedance matching circuit 30 of the semiconductor device 1 according to Embodiment 1, will be described. Therefore, Fig. 11 shows a circuit diagram of the semiconductor device 4 according to Embodiment 4.

[0044] As shown in Fig. 11, the impedance matching circuit 70 is obtained by adding a second variable capacitor Cs, a switch circuit SWrx, a third variable capacitor Crx, and a fourth variable capacitor Ctx to the impedance matching circuit 30. Here, since the second variable capacitor Cs has been described in Embodiment 2 and the switch circuit SWrx has been described in Embodiment 3, the description thereof will be omitted here. Therefore, the third variable capacitor Crx and the fourth variable capacitor Ctx will be described in detail.

[0045] The third variable capacitor Crx is connected between the input terminal Prx of the receiving circuit 10 and a fixed potential terminal (for example, a ground terminal) whose potential is fixed alternately. Also, the fourth variable capacitor Ctx is connected between the output terminal Ptx of the transmitting circuit 20 and the ground terminal. Note that the third variable capacitor Crx and the fourth variable capacitor Ctx have the same configuration as the second variable capacitor Cs.

[0046] In the semiconductor device 4 according to Embodiment 4, by providing the second variable capacitor Cs, the third variable capacitor Crx, and the fourth variable capacitor Ctx to the first terminal P1, the second terminal P2, and the third terminal P3, respectively, the variable range of the impedance can be further expanded more than that in Embodiment 2.

[0047] Embodiment 5 In Embodiment 5, an impedance matching circuit 80, which is another form of the impedance matching circuit 70 of the semiconductor device 4 according to Embodiment 4, will be described. Therefore, Fig. 12 shows a circuit diagram of the semiconductor device 5 according to Embodiment 5.

[0048] As shown in Fig. 12, the impedance matching circuit 80 connects the fourth variable capacitor Ctx to an intermediate position, excluding the ends, of the wiring forming the second inductor L1. Note that the other end of the fourth variable capacitor Ctx is also connected to a fixed potential terminal (for example, a ground terminal) in the impedance matching circuit 80. An inductor 31 having a branch wiring 81 connecting the second inductor L2 and the fourth variable capacitor Ctx is referred to as an inductor 32.

[0049] Here, regarding the layout of the inductor 32, FIG. 13 shows a diagram for explaining the layout of the inductor 32 according to the fifth embodiment. As shown in FIG. 13, the inductor 32 branches the branch wiring 81 from an intermediate position excluding the end of the wiring forming the second inductor L2. The branch wiring 81 is formed in a layer different from the wiring layer in which the wiring forming the second inductor L2 is formed.

[0050] In this way, the fourth variable capacitor Ctx can also be connected to the wiring forming the second inductor L2. Even with such a layout, since there is almost no characteristic difference from the fourth embodiment, it is also possible to adopt such a layout according to the convenience of the arrangement of other elements.

[0051] Embodiment 6 In Embodiment 6, another form of the semiconductor device 4 according to Embodiment 4 will be described. Therefore, FIG. 14 shows a circuit diagram of the semiconductor device 6 according to Embodiment 6. The receiving circuit 10, the transmitting circuit 20, and the impedance matching circuits 30, 50, 60, 70, 80 described in Embodiments 1 to 5 are all composed of only elements that can be formed on a semiconductor chip. Therefore, in Embodiment 6, an example is shown in which the receiving circuit 10, the transmitting circuit 20, and the impedance matching circuit 70 according to Embodiment 4 are formed on one semiconductor chip.

[0052] In this way, by forming the receiving circuit 10, the transmitting circuit 20, and the impedance matching circuit 70 on one semiconductor chip, the number of external components of the semiconductor chip for constituting the transceiver circuit can be reduced, and thus the stacking of the device including the transceiver circuit can be reduced.

[0053] Embodiment 7 In Embodiment 7, a semiconductor device 7 having an inductor 33, which is another form of the inductor 31, will be described. Therefore, FIG. 15 shows a circuit diagram of the semiconductor device according to Embodiment 7.

[0054] As shown in FIG. 15, the inductor 33 is obtained by adding a third inductor L3 to the inductor 31. The third inductor L3 is connected between the first terminal P1 and a common branch to which both the first inductor L1 and the second inductor L2 are connected. Here, FIG. 16 shows a diagram for explaining the layout of the inductor according to the seventh embodiment.

[0055] As shown in FIG. 16, in the inductor 33, the wiring forming the third inductor L3 is formed to be wound in the same direction as the first inductor L1 and the second inductor L2 so as to surround the wiring forming the second inductor L2. Also, in the inductor 33, the first terminal P1 of the third inductor L3 is set, and the first inductor L1 is formed so as to branch from the vicinity of the other end. Further, the second inductor L2 is formed to be continuous from the end of the third inductor L3.

[0056] When the third inductor L3 is required depending on the inductance or mutual inductance M of the inductor to be formed, by adopting the layout as shown in FIG. 16, the third inductor L3 can be formed and the mutual inductance M can be generated between the first inductor L1, the second inductor L2, and the third inductor L3.

[0057] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the gist thereof.

Description of Reference Numerals

[0058] 1 to 7 Semiconductor device 10 Receiving circuit 11 Receiving amplifier 20 Transmitting circuit 21 Transmitting amplifier 30, 50, 60, 70, 80, 90 Impedance matching circuit 31 to 33 Inductor 41 to 49 Wiring 81 Branch Wiring 100 Ampere Control Circuit L1 First Inductor L2 Second Inductor L3 Third Inductor P1 First Terminal P2 Second Terminal P3 Third Terminal Cp First Variable Capacitance Cs Second Variable Capacitance Crx Third Variable Capacitance Ctx Fourth Variable Capacitance Prx Input Terminal Ptx Output Terminal SWrx Switch Circuit ANT Antenna

Claims

1. A receiving circuit, A transmitting circuit, An amplifier control circuit that operates the receiving circuit and the transmitting circuit exclusively, An impedance matching circuit having a first terminal connected to an antenna, a second terminal connected to an input terminal of the receiving circuit, and a third terminal connected to an output terminal of the transmitting circuit, The impedance matching circuit, A first inductor provided in a signal path from the first terminal to the second terminal, A second inductor provided in a signal path from the first terminal to the third terminal, A semiconductor device in which, when the region formed by the first inductor and the second inductor is viewed in plan view, at least a part thereof has an overlap.

2. The semiconductor device according to claim 1, wherein when a current in a direction from the first terminal to the second terminal flows through the first inductor and a current in a direction from the first terminal to the third terminal flows through the second inductor, the winding directions of the first inductor and the second inductor are set such that the electric fields generated in the first inductor and the electric field generated in the second inductor are in a direction of reinforcing each other.

3. The semiconductor device according to claim 1, further comprising a first variable capacitor connected between the first terminal and a fixed potential terminal whose potential is fixed alternately.

4. The semiconductor device according to claim 3, further comprising a second variable capacitor having one terminal connected to both the node on the first terminal side of the first variable capacitor and the first terminal, and the other terminal connected to the antenna.

5. The semiconductor device according to claim 1, further comprising a switch circuit that switches between connecting and disconnecting between the second terminal and the input terminal of the receiving circuit.

6. A third variable capacitor connected between the input terminal of the receiving circuit and a fixed potential terminal whose potential is fixed alternately, A fourth variable capacitor connected between the output terminal of the transmitting circuit and the fixed potential terminal, The semiconductor device according to claim 1, further comprising.

7. A third variable capacitor connected between the input terminal of the receiving circuit and a fixed potential terminal whose potential is fixed alternately, A fourth variable capacitor having one end connected to an intermediate position, excluding the ends, of the wiring constituting the second inductor and the other end connected to the fixed potential terminal, The semiconductor device according to claim 1, further comprising.

8. It further has a third inductor connected between the first terminal and a common branch to which both the first inductor and the second inductor are connected. The semiconductor device according to claim 1, wherein the third inductor is formed to have a mutual inductance between the first inductor and the second inductor. **Claim 9** The semiconductor device according to claim 1, wherein the receiving circuit, the transmitting circuit, the amplifier control circuit, and the impedance matching circuit are formed on one semiconductor chip. **Claim 10** A first terminal connected to an antenna, A second terminal connected to an input terminal of a receiving circuit, A third terminal connected to an output terminal of a transmitting circuit, A first inductor provided in a signal path from the first terminal to the second terminal, A second inductor provided in a signal path from the first terminal to the third terminal, and An impedance matching circuit in which at least a part overlaps when the regions where the first inductor and the second inductor are formed are viewed in plan view.

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