Current source for reading a programmable resistive memory cell

Abstract

To provide a device which is a current source for reading a memory cell having a threshold switching selector, a method of operating a memory, and a memory system.SOLUTION: A current source for supplying current to a programmable resistive memory cell 401 operates in a first mode when a threshold switching selector 502 is turned on and operates in a second mode when voltages from both ends of the memory cell are sensed. The first mode allows the use of the full range of power supply voltages, whereby sufficient voltage is provided at both ends of the memory cell to turn on the threshold switching selector. In the second mode, the magnitude of the read current is less dependent on the voltages at both ends of the memory cell. Therefore, the second mode provides accurate sensing of the memory cell. The first mode may also be used when writing the memory cell, whereby sufficient voltage is provided at both ends of the memory cell to write the memory cell.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] (Claim of Priority) This application claims priority to U.S. Provisional Patent Application No. 63 / 504,428, filed May 25, 2023, by Petti et al., titled "CURRENT SOURCE FOR READ-OF PROGRAMMABLE RESISTANCE MEMORY CELLS", which is hereby incorporated by reference in its entirety.

Background Art

[0002] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal information terminals, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory enables information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0003] Memory cells may be present in a cross-point memory array. In a memory array having a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, a second set of conductive lines is formed over the first set of conductive lines, and extends over the substrate in a direction perpendicular to the first set of conductive lines. Memory cells are disposed at the cross-point junctions of the two sets of conductive lines.

[0004] A programmable resistive memory cell is formed from a material having a programmable resistance. In the binary approach, the programmable resistive memory cell can be programmed to one of two resistance states, namely a high resistance state (HRS) and a low resistance state (LRS). In some approaches, more than two resistance states may be used. One type of programmable resistive memory cell is a Magnetoresistive Random Access Memory (MRAM) cell. MRAM cells use magnetization to represent the data stored, as opposed to some other memory technologies that use electric charge to store data. Bits of data are written to the MRAM cell by changing the magnetization direction of a magnetic element (the "free layer") within the MRAM cell, and the bits are read by measuring the resistance of the MRAM cell.

[0005] In a cross-point memory array, each memory cell may include a threshold switching selector in series with a material having a programmable resistance. The threshold switching selector has a high resistance (off or non-conducting state) until it is biased by a voltage higher than its threshold voltage (Vt) or a current exceeding its threshold current, and until the voltage bias drops below Vhold (the "Voffset") or the holding current drops below the holding current Ihold. After Vt is exceeded and while Vhold is exceeded across the threshold switching selector, the threshold switching selector has a low resistance (on or conducting state). The threshold switching selector remains on until its current is decreased to Ihold which is less than the holding current, or the voltage is decreased to Vhold which is less than the holding voltage. When this occurs, the threshold switching selector returns to the off (high) resistance state. To read the memory cell, the threshold switching selector is activated by being turned on before the resistance state of the memory is determined. An example of a threshold switching selector is an Ovonic Threshold Switch (OTS).

[0006] In the forced current method for reading programmable resistance memory cells in a cross-point array, a current is driven through the memory cell selected for reading (the "selected memory cell"). The current charges the voltage across the selected memory cell until the threshold switching selector turns on. Then, while the read current is driven through the programmable resistance memory element of the selected memory cell, the voltage across the selected cell is sensed.

[0007] One method for reading programmable resistance memory cells is sometimes called global reference read. Global reference read may also be called midpoint read or midpoint reference read. Global reference read may use a reference voltage that is between the low resistance state (LRS) and the high resistance state (HRS). Here, LRS and HRS refer to the voltages that appear across the cell in response to the read current. For example, the midpoint reference can be a reference voltage that is midway between two voltages corresponding to sensing a cell having either LRS or HRS. In the forced current method, the state of the memory cell is determined based on whether the sensed voltage is higher or lower than the midpoint reference voltage.

[0008] Another technique for reading a programmable resistive memory cell is generally referred to as Self-Referenced Read (SRR). In SRR, instead of using an intermediate-point reference that is independent of the cell state, a reference is generated based on sensing the cell itself. In destructive SRR, the state of the memory cell may be changed (e.g., destroyed) by the SRR write operation. One SRR technique includes a first read (Read 1), a destructive write to a known state (e.g., HRS), and a second read (Read 2). The results of the two reads are compared to determine the original state of the cell. One technique for the first read is to apply a read current through the memory cell, resulting in a voltage across the cell having a magnitude representative of the resistance of the memory cell. The voltage is stored and may be adjusted (e.g., up or down by 150 mv) for comparison with the voltage sample from the second read. The voltage adjustment can be approximately half of the signal difference across the MRAM for each state. For example, if the MRAM low-resistance state (LRS) is 25 KΩ, the high-resistance state is 50 KΩ, and the read current is 15 ua, the difference from the state change is 375 mV, so an adjustment of approximately 180 mV can be made from the SRR Read 1 stored voltage. Determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage from SRR Read 1 is adjusted upward and the write was to HRS, if the cell was originally in HRS, the second sampled voltage from Read 2 should be approximately the same as Read 1 and thus lower than the first upward-adjusted voltage. However, if the cell was originally in LRS, the second sampled voltage from Read 2 should be higher than the upward-adjusted voltage from Read 1 due to the higher Read 2 voltage for HRS.

[0009] For both midpoint reading and SRR, the accuracy of the reading depends on the accuracy of the sensed voltage. As described above, the reading current should have a predetermined magnitude. However, due to limitations of the current source, the magnitude of the reading current may vary according to the voltage across the memory cell. Even a small variation in the reading current of a few percent can significantly reduce the reading margin.

Brief Description of the Drawings

[0010] Elements with the same reference numerals refer to common components in different figures.

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[0011] Techniques are disclosed for a system having a current source and a method of operating the current source when accessing a memory cell having a threshold switching selector, e.g., an Ovonyx threshold switch (OTS). In one embodiment, the current source operates in a first mode that is used when turning on the threshold switching selector and in a second mode that is used when sensing the voltage across the memory cell. The voltage across the memory cell required to turn on the threshold switching selector can exceed the voltage across the cell when sensing, regardless of whether the cell is in the HRS or the LRS. The first mode can enable the use of the full range of the power supply voltage, thereby providing sufficient voltage across the memory cell to turn on the threshold switching selector. However, if the first mode is used when sensing the memory cell, the magnitude of the read current may depend more on the cell voltage than desired, thereby reducing the read margin. In the second mode, the magnitude of the read current does not depend much on the voltage across the memory cell. Note that the voltage across the cell can appear at the output of the current source. Thus, the voltage at the output of the current source can be related to the voltage across the cell. The second mode provides a more accurate sensing of the memory cell.

[0012] In one embodiment, a current source is used to read programmable resistive memory cells present within a cross-point memory array. In a memory array having a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, and a second set of conductive lines is formed over the first set of conductive lines and extends over the substrate in a direction perpendicular to the first set of conductive lines. Memory cells are disposed at the cross-point junctions of the two sets of conductive lines. A cross-point memory array may also be referred to as a crossbar memory array. In one embodiment, each memory cell has a magnetoresistive memory element in series with an OTS, which may be referred to as an MRAM memory cell. However, the current source may be used with other types of memory cells. These elements of the memory cells may be changed to other technologies such as ReRAM, PCM, FeRAM, etc. Also, the threshold switching selector need not be an OTS, a back-to-back diode, or other things well known to those skilled in the art.

[0013] In some embodiments, the programmable resistive memory cells have magnetoresistive random access memory (MRAM) elements. As used herein, the magnetization direction is the direction in which the magnetic moment is oriented with respect to a reference direction set by another element of the MRAM (the "reference layer"). In some embodiments, low resistance is referred to as the parallel state, the P state, or the LRS, and high resistance is referred to as the antiparallel state, the AP state, or the HRS. MRAM can use the spin transfer torque effect to change the direction of magnetization from the P state to the AP state and vice versa, and a bipolar (bidirectional write) operation is typically required for writing. However, the SRR of the programmable resistive memory cells disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0014] FIG. 1 is a block diagram of one embodiment of a non-volatile memory system (or more simply, a "memory system") 100 connected to a host system 120. The memory system 100 can implement the techniques presented herein for a system having a current source and a method of operating the current source when accessing a memory cell having a threshold switch selector. In one embodiment, the memory cell has a programmable resistance memory element (e.g., an MRAM element) in series with a threshold switch selector such as an OTS. Many types of memory systems can be used with the techniques proposed herein. Exemplary memory systems include Dual In-line Memory Modules (DIMMs), solid state drives ("SSDs"), memory cards, and embedded memory devices. However, other types of memory systems can also be used.

[0015] The memory system 100 of FIG. 1 includes a memory controller 102, a memory 104 for storing data, and a local memory (e.g., MRAM, ReRAM, DRAM) 140. The local memory 140 may be non-volatile and can hold data after power-off. The local memory 140 may be volatile and it may not be expected to hold data after power-off. In one embodiment, the local memory 140 is MRAM. In one embodiment, the local memory MRAM does not need to hold data after power-off. However, the local memory MRAM may hold data even after power-off. In one embodiment, the memory controller 102 and / or the local memory controller 164 provides access to programmable resistive memory cells in the local memory 140. For example, the memory controller 102 may provide access within a cross-point array of MRAM cells in the local memory 140. In another embodiment, the memory controller 102 or the interface 126 or both are eliminated and the memory package is directly connected to the host 120 through a bus such as DDRn. Alternatively, they are connected to a host memory management unit (MMU). In another example, the memory controller 102 or part thereof is moved onto the memory 104 for direct connection of the memory 104 to the host, such as by providing parity bits, ECC, and wear-leveling on the memory together with a DDRn interface to / from the host or MMU. The term memory system as used throughout this specification is not limited to the memory system 100. For example, the local memory 140 or the combination of the local memory 140 and the local memory controller 164 can be considered a memory system. Similarly, the host memory 124 or the combination of the host processor 122 and the host memory 124 can be considered a memory system.

[0016] The components of the memory system 100 shown in FIG. 1 are electrical circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, and a local memory controller 164. The host interface 152 is connected to the host 120 and communicates with the host 120. The host interface 152 is also connected to a network on chip (NOC) 154. The NOC is a communication subsystem on the integrated circuit. The NOC can use synchronous and asynchronous clock domains or asynchronous logic that is not locked. NOC technology applies networking theory and methods to on-chip communication, resulting in significant improvements over conventional buses and crossbar interconnects. The NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and links of the NOC are shared by many signals. Since all links within the NOC can operate simultaneously on different data packets, a high level of parallelism is achieved. Thus, as the complexity of the integrated subsystem continues to increase, the NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, and local memory controller 164 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate and communicate with the local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed volatile memory 140 can be SRAM or another type of volatile memory.

[0017] The ECC engine 158 performs an error correction service. For example, the ECC engine 158 performs data encoding and decoding of parity bits provided on or off the memory as part of a codeword used for error correction of data fetched from the memory 140 or 104. In one embodiment, the ECC engine 158 is an electric circuit programmed by software. For example, the ECC engine 158 can be a processor that can be programmed. In other embodiments, the ECC engine 158 is a custom dedicated hardware circuit without any software. In one embodiment, the function of the ECC engine 158 is implemented by the processor 156. In one embodiment, the local memory 140 has an ECC engine regardless of the presence or absence of a wear-leveling engine. In one embodiment, the memory 104 has an ECC engine regardless of the presence or absence of a wear-leveling engine.

[0018] Processor 156 performs various controller memory operations such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom dedicated hardware circuit that has no software. Processor 156 also implements the conversion module as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is internally addressed to the storage system using physical addresses associated with one or more memory dies. However, the host system uses logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses, while the storage system can freely store the data as desired among the locations of one or more memory dies. To implement this system, memory controller 102 (e.g., the conversion module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory die. An exemplary implementation is to maintain a table (i.e., the above L2P table) that identifies the current translation between logical and physical addresses. Entries in the L2P table can include identifiers of logical addresses and corresponding physical addresses. The logical address-physical address table (i.e., the L2P table) includes the word "table" but does not necessarily have to be a literal table. Rather, the physical address-logical address table (i.e., the L2P table) can be any kind of data structure. In some examples, since the memory space of the storage system is very large, local memory 140 cannot hold all of the L2P table. In such cases, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables is cached in local high-speed memory 140 (L2P cache).

[0019] Memory interface 160 communicates with non-volatile memory 104. In one embodiment, non-volatile memory 104 includes programmable resistance memory cells of a cross-point array. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces may also be used. In some exemplary implementations, memory interface 160 (or another part of controller 102) implements a scheduler and buffer for transmitting and receiving data to and from one or more memory dies.

[0020] In one embodiment, local memory 140 has an ECC engine. Local memory 140 can perform other functions such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692 entitled "Memory Maintenance Operations During Refresh Window" and U.S. Patent No. 10,885,991 entitled "Data Rewrite During Refresh Window", both of which are hereby incorporated by reference in their entirety. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.

[0021] In one embodiment, memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Thus, memory controller 102 is connected to one or more memory dies. In one embodiment, the memory package can include a type of memory such as storage class memory (SCM) based on programmable resistance random access memory (ReRAM, MRAM, FeRAM, or RRAM, etc.) or phase change memory (PCM). In one embodiment, memory controller 102 provides access to the memory cells within the cross-point array within memory package 104.

[0022] The memory controller 102 communicates with the host system 120 via an interface 152 that implements a protocol such as CXL (Compute Express Link). Alternatively, such a controller can be removed and the memory package can be placed directly on a host bus, such as DDRn. To cooperate with the memory system 100, the host system 120 includes a host processor 122 connected along a bus 128, a host memory 124, and an interface 126. The host memory 124 is the physical memory of the host and can be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In one embodiment, the host memory 124 includes a cross-point array of programmable resistance memory cells, and each memory cell includes a programmable resistance memory element and a threshold switching selector in series with the programmable resistance memory element.

[0023] The host system 120 is external to the memory system 100 and is separate from the memory system 100. In one embodiment, the memory system 100 is embedded within the host system 120. The host memory 124 may be referred to herein as the memory system. The combination of the host processor 122 and the host memory 124 may be referred to herein as the memory system. In one embodiment, such a host memory can be a cross-point memory using MRAM.

[0024] FIG. 2 is a block diagram showing an example of a memory die 292 that can implement the technology described herein. In one embodiment, the memory die 292 is included in the local memory 140, and in an embodiment, the memory die 292 is included in the memory 104. In one embodiment, the memory die 292 is included within the host memory 124. The memory die 292 includes a memory array 202 that can include any of the memory cells described below. The array demarcation lines of the memory array 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations, including, for example, a diagonal pattern, can be implemented to save space. The memory die 292 includes a row control circuit 220, the output 208 of which is connected to each word line of the memory array 202. The row control circuit 220 receives a group of M row address signals and one or more various control signals from the system control logic circuit 260 and can typically include circuits such as a row decoder 222, a row driver 224, and a block selection circuit 226 for both read and write operations. The row control circuit 220 may also include a read / write circuit. In one embodiment, the row decode and control circuit 220 has a sense amplifier 228 that includes a circuit for sensing the state (e.g., voltage) of each word line of the memory array 202. In one embodiment, the state of the memory cells in the cross-point array is determined by sensing the word line voltage. The memory die 292 also includes a column decode and control circuit 210, the input / output 206 of which is connected to each bit line of the memory array 202. Although only a single block is shown for the array 202, the memory die can include multiple arrays or "tiles" that can be accessed individually. The column control circuit 210 receives a group of N column address signals and one or more various control signals from the system control 260 and can typically include circuits such as a column decoder 212, a column decoder or driver 214, a block selection circuit 216, and a read / write circuit and an I / O multiplexer.

[0025] System control logic 260 receives data and instructions from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and instructions from a separate controller circuit, provides output data to that controller circuit, and the controller circuit communicates with the host system. Such a controller system implements interfaces such as DDR, DIMM, CXL, PCIe. In another embodiment, these data and commands are sent and received directly from the memory package to the host without a separate controller, and any required controller is within each die or within a die added to the multi-chip memory package. In some embodiments, system control logic 260 can include a state machine 262 that provides die-level control of memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 is implemented entirely within hardware (e.g., an electrical circuit) without using software. In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. System control logic 260 can also include a power control module 264 that controls the power, current source current, and voltage supplied to the rows and columns of memory 202 during memory operation, and can include a charge pump and regulator circuit for generating regulated voltages, and each on / off control for word line bit line selection of memory cells. In some embodiments, power control 264 includes one or more current sources. The current source can be used to provide read current and / or write current. In one embodiment, the current source operates in a first mode when turning on the threshold switching selector and in a second mode when sensing memory cells, as described herein. System control logic 260 includes a storage device 266 that can be used to store parameters for operating memory array 202. System control logic 260 also includes refresh logic 272 and wear leveling logic 274.Such system control logic may be commanded by the host 120 or the memory controller 102 with respect to the refresh logic 272, and the refresh logic may load on-chip stored row and column addresses (pointers) that may be incremented after a refresh. Such address bits may simply be selected (to refresh the OTS). Alternatively, such addresses may be read, corrected by steering through the ECC engine 269, and then stored in a "spare" location, which is also effectively incremented with respect to the wear level (thus, all code words are periodically read, corrected, and relocated across the chip under the control of the wear leveling logic 274), and thus the use of each bit across the chip is more uniform. Such operations may be more directly controlled by an external controller, e.g., a host of a PCIe or CXL or DDRn controller located separately from the memory chip or on the memory die.

[0026] Commands and data are transferred between the memory controller 102 and the memory die 292 via a memory controller interface 268 (also referred to as the "communication interface"). Such an interface may be, for example, PCIe, CXL, DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 include a toggle mode interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a toggle mode interface that connects to the toggle mode interface of the memory interfaces 228 / 258 for the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input pins and / or output (I / O) pins that connect to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn such as DDR5 or LPDDR5, or a subset thereof having smaller pages and / or relaxed timing.

[0027] System control logic 260 located within a controller on a memory die within a memory package may include an Error Correction Code (ECC) engine 269. Since the ECC engine 269 is on the same semiconductor die as the memory cells, it may be referred to as an on-die ECC engine. That is, the on-die ECC engine 269 can be used to encode data to be stored in the memory array 202, decode the decoded data, and correct errors. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 269 can execute a decoding algorithm and be used to perform error correction. Thus, the ECC engine 269 can decode the ECC codeword. In one embodiment, the ECC engine 269 can decode data more quickly by directly decoding without iteration. Having the ECC engine 269 on the same die as the memory cells enables faster decoding. The ECC engine 269 can use a variety of decoding algorithms including, but not limited to, Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and Low-Density Parity-Check (LDPC).

[0028] In some embodiments, all of the elements of the memory die 292 that include the system control logic 260 can be formed as part of a single die. In other embodiments, some or all of the system control logic 260 can be formed on different dies.

[0029] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile or volatile memory cells in which multiple memory levels are formed on a single substrate such as a wafer. The memory structure can include any type of non-volatile or volatile memory that is monolithically formed on one or more physical levels of memory cells having an active area disposed on a silicon (or other type of) substrate. In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells.

[0030] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. For the purposes of the newly claimed embodiments proposed herein, no specific non-volatile memory technology is required. Other examples of technologies suitable for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of technologies suitable for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0031] As an example of ReRAM or MRAM cross-point memory, a programmable resistive switching element disposed in a cross-point array accessed by X and Y lines (e.g., word lines and bit lines) can be mentioned. In another embodiment of the cross-point, it is PCM in series with an OTS selector. In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization cell. The conductive bridge memory element can be used as a state change element based on the physical rearrangement of ions in a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes having a thin solid electrolyte film between the two electrodes, one of which is relatively inert (e.g., tungsten) and the other of which is electrochemically active (e.g., silver or copper). As the temperature increases, the mobility of the ions also increases, and the programming threshold of the conductive bridge memory cell decreases. Therefore, the conductive bridge memory element can have a wide range of programming thresholds with respect to temperature.

[0032] Magnetoresistive random access memory (MRAM) stores data using magnetic memory elements. The elements are formed from two ferromagnetic layers, each of which can retain magnetization, separated by a thin insulating layer. In field-controlled MRAM, one of the two layers is a permanent magnet set to a specific polarity. The magnetization of the other layer can be changed by applying an external field to store memory. Other types of MRAM cells are also possible. The memory device can be constructed from a grid of MRAM cells. MRAM-based memory embodiments are discussed in more detail below.

[0033] Phase change memory (PCM) utilizes the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase changes by simply changing the coordination state of germanium atoms with laser pulses (or optical pulses from another light source). The memory cell is programmed by current pulses that can change the coordination of the PCM material or switch it between the amorphous and crystalline states. The use of "pulses" in this document does not require square pulses but includes vibrations or bursts of sound (continuous or discontinuous), current, voltage, light, or other waves. Also, the current forced to flow for writing can be rapidly driven to a peak value, for example, and then linearly ramped down, for example, at an edge rate of 200 ns. Forcing such a peak current can be limited by zone-based voltage compliance that varies depending on the position of the memory cell along the word line or bit line. In one embodiment, the phase change memory cell has a phase change memory element in series with a threshold switching selector such as OTS.

[0034] Those skilled in the art will understand that this technology described herein is not limited to a single specific memory structure, memory construction, or material composition, but covers many related memory structures within the spirit and scope of the technology as described herein and understood by those skilled in the art.

[0035] The elements of FIG. 2 can be grouped into two portions of the peripheral circuitry that includes all of the memory structure 202 and other elements. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of the memory dies 292 provided in the memory structure 202. However, this either decreases the area of the memory dies available for the peripheral circuitry or increases the cost associated with the chip area. This can impose very stringent limitations on these peripheral elements. For example, the need to fit a sense amplifier circuit within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic 260, the decreased availability of area can limit the available functions that can be implemented on-chip. As a result, the amount of area allocated to the memory structure 202 and the amount of area allocated to the peripheral circuitry are a fundamental trade-off in the design of the memory die 292. Such a trade-off can result in more IR drop by using a larger x-y array of memory between the drive circuits on the word lines and bit lines, which can gain more benefits from the use of voltage limits and the zonalization of voltage compliance based on the memory cell positions along the word lines and bit lines.

[0036] Another area where the memory structure 202 and the peripheral circuitry often conflict is in the processes involved in the formation of these regions, because these regions often involve different process technologies and are a trade-off for having different technologies on a single die. For example, such sense amplifier circuits, charge pumps, logic elements within state machines, and other peripheral circuitry within the system control logic 260 often use PMOS devices. In some cases, the memory structure will be based on CMOS devices. The process operations for manufacturing a CMOS die are different in many respects from the process operations optimized for NMOS-only technology.

[0037] To improve these limitations, the embodiments described below can separate the elements of FIG. 2 onto separately formed dies, and then the dies are joined together. FIG. 3 shows an integrated memory assembly 270 having a memory structure die 280 and a control die 290. The memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuit elements including one or more control circuits are formed on the control die 290. For example, the memory structure die 280 can be formed of only memory elements such as an array of memory cells of MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuits can be moved to the control die later, even if they include elements such as decoders and sense amplifiers. This enables each semiconductor die to be individually optimized according to its technology. This allows for more space for the peripheral elements, and thus additional functions that could not be easily incorporated if limited to the margin of the same die holding the memory cell array can be incorporated. The two dies can then be bonded together in the joined multi-die integrated memory assembly, and the array on one die is connected to the peripheral elements on the other die. In the following, the focus is on an integrated memory assembly of one memory die and one control die, but other embodiments can use additional dies such as, for example, two memory dies and one control die.

[0038] Similar to 202 of FIG. 2, the memory die 280 of FIG. 3 can include a plurality of independently accessible arrays or "tiles". The system control logic 260, the row control circuit 220, and the column control circuit 210 are disposed within the control die 290. In some embodiments, all or part of the column control circuit 210 and all or part of the row control circuit 220 are disposed on the memory structure die 280. In some embodiments, a part of the circuits within the system control logic 260 are disposed on the memory structure die 280.

[0039] FIG. 3 shows column control circuit 210 on control die 290 coupled to memory structure 202 on memory structure die 280 through electrical path 293. For example, electrical path 293 may provide electrical connections between column decoder 212, driver circuit 214, and block selection section 216 and the bit lines of memory structure 202. The electrical path may extend through pads on control die 290 that are joined to corresponding pads on memory structure die 280 that are connected to the bit lines of memory structure 202 from column control circuit 210 within control die 290. Each bit line of memory structure 202 may have a corresponding electrical path within electrical path 293 that includes a pair of bond pads that connect to column control circuit 210. Similarly, row control circuit 220, which includes row decoder 222, row driver 224, block selection section 226, and sense amplifier 228, is coupled to memory structure 202 through electrical path 294. Each of electrical paths 294 may correspond to, for example, word lines. Additionally, additional electrical paths may be provided between control die 290 and memory structure die 280.

[0040] For the purposes of this document, the phrase "control circuit" can include one or more of memory controller 102 (or local memory controller 164, processor 156, system control logic 260, column control circuit 210, row control circuit 220, host processor 122, microcontroller, state machine, and / or other control circuits, or one or more of other similar circuits used to control non-volatile memory). The control circuit can include only hardware, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit can include a processor, FPGA, ASIC, integrated circuit, or other type of circuit. Such a control circuit can include a driver, such as direct drive by connection of nodes through transistors (from gate to power supply) that drive to a constant voltage, such as a power supply. Such a control circuit may include a current source driver.

[0041] As used herein, the term "device" can include, but is not limited to, one or more of memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, memory package 104, memory die 292, integrated memory assembly 270, and / or control die 290.

[0042] In the following description, memory arrays 202 of FIGS. 2 and 3 are discussed in the context of a cross-point architecture. In a cross-point architecture, it includes a first set of conductive lines or wires, such as word lines, running in a first direction with respect to the underlying substrate, and a second set of conductive lines or wires, such as bit lines, running in a second direction with respect to the underlying substrate. Memory cells are located at the intersections of the word lines and the bit lines. Memory cells at these cross-points can be formed according to any of several techniques including those described above. In the following description, embodiments based on a cross-point architecture using MRAM memory cells each arranged in series with a threshold switching selector, such as an ovonic threshold switch (OTS), to form selectable memory bits are mainly focused on. However, the embodiments are not limited to supplying current to a cross-point architecture having MRAM cells each having a magnetic memory element within a series OTS selector.

[0043] Figure 4A shows a perspective view of an embodiment of a portion of a memory array forming a cross-point architecture. The memory array 202 of FIG. 4A is an example of an implementation of the memory array 202 of FIG. 2 or FIG. 3, and the memory die 292 or the memory structure die 280 can include a plurality of such array structures. The memory array 202 can be included in the local memory 140 or the host memory 124. The bit lines BL1 to BL5 are arranged in a first direction (represented as extending within the page) with respect to a substrate (not shown) under the die, and the word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction. FIG. 4A shows that both the word lines WL1 to WL5 and BL1 to BL5 extend horizontally with respect to the substrate, while two of them, the memory cell shown at 401, is an example of a horizontal cross-point structure oriented such that the current (I cell as shown therein) flows in the vertical direction. In a memory array having additional layers of memory cells, as will be described below with respect to FIG. 4D, there are corresponding additional layers of bit lines and word lines.

[0044] As shown in FIG. 4A, the memory array 202 includes a plurality of memory cells 401. The memory cells 401 may include rewritable memory elements that can be implemented using ReRAM, MRAM, PCM, or other materials having programmable resistance. The memory cells 401 may be referred to herein as programmable resistance memory cells. One type of programmable resistance memory cell is called an MRAM cell, which is a memory cell that includes an MRAM memory element. The memory cells 401 may also include threshold switching selectors that can be implemented using an ovonic threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly non-linear dependence of current on a selected voltage. The following description focuses on memory cells composed of MRAM memory elements combined in series with an ovonic threshold switch, but much of the description can be applied more generally. The current in the memory cells at the first memory level is the arrow I cellAlthough shown as flowing upward as indicated by, the current can flow in either direction, as will be described in more detail below.

[0045] Figures 4B and 4C respectively show a side view and a top view of the cross-point structure of Figure 4A. The side view of Figure 4B shows one lower wire, namely word line WL1, and upper wires, namely bit lines BL1~BL n are shown. The cross-point between each upper wire and the lower wire is the MRAM memory cell 401, but PCM, ReRAM, FeRAM, or other technologies can also be used as the memory element. Figure 4C is a top view showing the cross-point structure of M lower wires WL1~WL M and N upper wires BL1~BL N . In a binary embodiment, the MRAM cell at each cross-point can be programmed to one of two resistive states, high or low. Embodiments of the MRAM memory cell design and techniques for their readout will be described in more detail below. In some embodiments, these sets of wires are continuously arranged as "tiles", and such tiles are paired so as to be adjacent in the word line (WL) direction and orthogonal in the bit line direction, and modules can be created. Such a module combines 2×2 tiles to form four tiles, and the WL driver between the tiles can be "centrally driven" such that the WL runs continuously across the driver at approximately the center of the line. Similarly, the BL driver may be located between pairs of tiles that are paired and centrally driven in the BL direction, whereby the driver and its area are shared between a pair of tiles.

[0046] The cross-point array of Figure 4A shows an embodiment having one layer of word lines and bit lines, and the MRAM or other memory cells are disposed at the intersections of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. An example of two layers is shown in Figure 4D.

[0047] FIG. 4D shows a perspective view of an embodiment of a portion of a two-level memory array forming a cross-point architecture. Similar to FIG. 4A, FIG. 4D shows the first layer 418 of memory cells 401 of array 202 connected at the cross-points of the first layer of word lines WL 1、1 ~WL 1、4 and bit lines BL1 to BL5. The second layer 420 of the memory cells is formed above the bit lines BL1 to BL5 and between these bit lines and a second set of word lines WL 2、1 ~WL 2、4 . FIG. 4D shows two layers 418 and 420 of memory cells, but this structure can extend upward through additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array of FIG. 4D can be biased for read or program operations such that current within each layer flows from the word line layer to the bit line layer, or vice versa. The two layers can be constructed by driver selection in the positive or negative direction such that they have current flow in the same direction within each layer for a given operation, or have current flow in opposite directions.

[0048] The use of a cross-point architecture enables an array with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross-point may be resistive-type memory cells, and the data values are encoded as different resistance levels. Depending on the embodiment, the memory cells may be binary values having either a low resistance state or a high resistance state, or may be multi-level cells (MLCs) that can have additional resistance intermediate the low resistance state and the high resistance state. The cross-point arrays described herein can be used in the memory die 292 of FIG. 2, the local memory 140 of FIG. 1, and / or the host memory 124 of FIG. 1. Resistive-type memory cells can be formed according to many of the above techniques, such as ReRAM, PCM, FeRAM, or MRAM. The following description is presented primarily in the context of a memory array using a cross-point architecture having binary value MRAM memory cells, but much of the description can be applied more generally.

[0049] FIG. 5 shows the structure of one embodiment of an MRAM cell. The MRAM cell can be used, for example, as the programmable resistive memory cell 401 in FIGS. 4A-4D. The MRAM cell includes a lower electrode 501, a spacer 512, a threshold switching selector 502, a spacer 514, a pair of magnetic layers (a reference layer 503 and a free layer 507) separated by a separation layer or tunnel layer of magnesium oxide (MgO) 505 in this example, and then an upper electrode 511 separated from the free layer 507 by a spacer 509. The spacer 509 can consist of an MgO capping layer in contact with the free layer 507. The spacer 509 can also include additional metal layers. In another embodiment, the locations of the reference layer 503 and the free layer 507 are switched such that the reference layer 503 is above the MgO 505 and the free layer 507 is below the MgO 505. In another embodiment, the position of the threshold switching selector 502 is between the free layer 507 and the upper electrode 511.

[0050] In some embodiments, the lower electrode 501 is referred to as a word line and the upper electrode 511 is referred to as a bit line. In other embodiments, the lower electrode 501 is referred to as a bit line and the upper electrode 511 is referred to as a word line. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 503 and the free layer 507. When the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low resistance state (LRS). When the two layers have opposite orientations, the memory cell is in an anti-parallel (AP) high resistance state (HRS). Embodiments of MLC include additional intermediate states. The orientation of the reference layer 503 is fixed and, in the example of FIG. 5, is oriented upward. The reference layer 503 is also known as a fixed layer or a pinned layer. The reference layer 503 can generally be composed of a plurality of ferromagnetic layers antiferromagnetically coupled in a structure called a synthetic antiferromagnet or abbreviated as SAF.

[0051] Data is written to the MRAM memory cell by programming the free layer 507 to have the same or opposite orientation as the reference layer 503. An array of MRAM memory cells can be placed in an initial or erased state by setting all of their free layers to a low resistance state having a magnetic field orientation that is the same as their respective reference layers. Each memory cell is then selectively programmed (also referred to as "written") by making its free layer 507 high resistance by inverting the magnetic field to the opposite side of the reference layer 503. The reference layer 503 is formed to maintain its orientation when programming the free layer 507. The reference layer 503 can have a more complex design that includes a synthetic antiferromagnetic layer and additional reference layers. For simplicity, the figures and description omit these additional layers and focus only on the fixed magnetic layer that is primarily involved in the tunneling magnetoresistance within the cell.

[0052] The threshold switching selector 502 has a high resistance (off or non-conducting state) until it is biased to a voltage higher than its threshold voltage or a current exceeding its threshold current, and until its voltage bias falls below Vhold (“Voffset”) or the current falls below Ihold. After exceeding Vt and while exceeding Vhold across the switching selector, the switching selector has a low resistance (on or conducting state). The threshold switching selector remains on until its current is reduced to Ihold which is less than the holding current, or the voltage is reduced to Vhold which is less than the holding voltage. When this occurs, the threshold switching selector returns to the off (high) resistance state. Thus, in order to program the memory cell at the cross-point, a voltage sufficient to turn on the associated threshold switching selector to set or reset the memory cell is applied, and in order to read the memory cell, it must be similarly activated by turning on the threshold switching selector before the resistance state of the memory cell can be determined. An example of a threshold switching selector is the ovonic threshold switching material of an ovonic threshold switch (OTS). Exemplary threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, with atomic percentages ranging from a few percent to over 90 percent for each element. In one embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 can also include an additional conductive layer on the interface with the reference layer 503. For example, the spacer 514 is shown between the switching selector 502 and the reference layer 503. The spacer layer 514 on the interface with the reference layer 503 can be a single conductive layer or can be composed of multiple conductive layers. The threshold switching selector 502 can also include an additional conductive layer on the interface with the lower electrode 501. For example, the spacer 512 is shown between the switching selector 502 and the reference layer 503. The spacer layer 512 on the interface with the lower electrode 501 can be a single conductive layer or can be composed of multiple conductive layers.Examples of the conductive layer adjacent to the OTS include carbon, carbon nitride, carbon silicide, carbon tungsten, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and the like. The threshold voltage switch has a threshold voltage (Vt), and when this threshold voltage is exceeded, the resistance of the device substantially changes from insulating or semi-insulating to conductive.

[0053] In one embodiment, a forced current technique is used to access the MRAM cell. The forced current technique can be used to read or write to the MRAM cell. In the forced current technique, an access current (e.g., I read or I write ) is driven through the lower electrode 501 by a current driver. The current is supplied by a current source. In one embodiment, the current driver may be part of a row driver circuit (e.g., array driver 224) for the electrode 501. However, alternatively, the current driver may be part of a column driver circuit (e.g., driver circuit 214) for the electrode 501. A voltage (e.g., V select ) is supplied to the upper electrode 511. In this specification, the terms "read current" (I read ) and "write current" (I write ) are used in relation to the access current driven through the MRAM cell (or other programmable resistance cell). The write current can change the state of the MRAM cell. As an example, a write current of about 30 μA is applied for 50 ns to RA10 Ωμm 2It can be used for MRAM cells having a critical dimension (CD) of about 20 nanometers, thereby switching the MRAM state from the P state to the AP state. The read current may be about half of the write current if it is a limited time such as less than 20 ns. The write current flowing in one direction through the MRAM cell changes the MRAM cell in the AP state from the AP state to the P state. The write current flowing in the reverse direction through the MRAM cell changes the MRAM cell in the P state from the P state to the AP state. Generally, it is preferable that the read current is set low enough and the read time is set short enough so as not to change the state of the MRAM cell from the P state to the AP state or from the AP state to the P state during reading. Typically, the absolute value of the write current required to switch the MRAM state from the P state to the AP state is larger than the write current required to switch the MRAM state from the AP state to the P state.

[0054] In some embodiments, the read current may be applied in the P2AP direction or alternatively in the AP2P direction. In some embodiments, the MRAM cell is read by performing a self-referenced-read (SRR). In one embodiment, the SRR has a first read (read 1 in the P2AP direction), a first write (write 1 to the AP state), and a second read (read 2 in the P2AP direction). Then, the original state of the cell can be restored by a second write (write-back to the P state for a bit that was initially in the P state).

[0055] The voltage level of the memory cell by the read 1 in the P2AP direction is stored, for example, on a capacitor or by a bit stored in a memory such as SRAM until used in an analog-to-digital converter or, for example, Read2, by converting it into a digital bit. The state stored in the capacitor can be adjusted, for example, to positive or negative 150 mv by forcing a voltage to flow through one terminal of the capacitor connected to the storage capacitor. Alternatively, the digital storage level can be adjusted by digitally adding or subtracting 150 mV to the stored bit. 150 mV can be adjusted to depend on the typical bit resistance. For example, if the bit low resistance state is 25 K ohms and the high resistance is 50 K, the difference is 25 K. If the read current is 15 ua, the differential voltage between the states is 25 K × 15 ua = 375 mV, which allows the selection of 150 mv, but suggesting 187 mV may be, for example, more optimal.

[0056] The above describes the read in the P2AP direction and the destructive write to the AP state (with a write-back to the P state), but in an alternative embodiment, the first SRR has a first read (read 1 in the AP2P direction), a destructive write (write 1 to the P state), and a second read (read 2 in the AP2P direction).

[0057] In one embodiment, the MRAM cell is read by applying, for example, 0V to the upper electrode 511 while driving a current of, for example, 15 microamperes (μA) through the lower electrode 501. This read current may flow from the lower electrode 501 to the upper electrode 511. Note that this read can be Read1 or Read2 in the P2AP direction. P2AP means that current flows in the direction of writing a bit from P to AP, or from AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to the upper electrode 511 while driving a write current of -30 μA through the lower electrode 501. This write current flows from the upper electrode 511 to the lower electrode 501. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to the upper electrode 511 while driving a current of 30 μA through the lower electrode 501. This write current flows from the electrode 501 to the electrode 511.

[0058] As an alternative to the method of FIG. 5, a select voltage can be applied to the lower electrode 501 and an access current can be applied through the upper electrode 511. In such an embodiment, the MRAM cell is read by applying, for example, 3V to the lower electrode 501 and passing a read current of, for example, -15 μA through the upper electrode 511. This read current may flow from the lower electrode 501 to the upper electrode 511.

[0059] In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, -3V to the lower electrode 501 while driving a write current of 30 μA through the upper electrode 511. This electron current flows from the lower electrode 501 to the upper electrode 511. In one embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0V to the lower electrode 501 while driving a current of -30 μA through the upper electrode 511. This electron current flows from the upper electrode 511 to the lower electrode 501. It is also understood in this description that the direction of the current polarity for switching the magnetization of the bit to the P state or the AP state can vary based on the reference layer design and the position of the reference layer relative to the free layer.

[0060] Some biasing techniques may apply a voltage across the unselected memory cells of an array and induce a current in the unselected memory cells. This wasted power consumption can be reduced to some extent by designing the memory cells to have a relatively high resistance level for both the high resistance state and the low resistance state, but this still results in an increase in current and power consumption and imposes additional design constraints on the design of the memory cells and the array. One approach to address this undesirable current leakage is to place a selector element in series with each MRAM memory cell or other resistive (e.g., ReRAM, PCM) memory cell. For example, a select transistor can be placed in series with each resistive memory cell element of FIGS. 4A-4D, such that the memory cell 401 can here be a composite of the select transistor and the programmable resistor. Such an architecture may be referred to as 1T1R. However, using a select transistor requires the introduction of additional control lines and cell area to turn on the corresponding transistor of the selected memory cell. In addition, since transistors are not often scaled in the same way as resistive memory elements, as the memory array changes to a smaller size, the use of transistor-based selectors can be a limiting factor, for example, in cost reduction. An alternative approach to the selector transistor is the use of a threshold switching selector (e.g., threshold switching selector 502) that is in series with the programmable resistive element. The two-terminal threshold switching selector does not require the aforementioned additional control lines and cell area to enable turning on the corresponding select transistor of the selected memory cell. In some embodiments, the memory system performs a read as disclosed herein to read a memory cell having a two-terminal threshold switching selector in series with a programmable resistive memory element.

[0061] Figures 6A and 6B show an embodiment for incorporating a threshold switching selector into an MRAM memory array having a cross-point architecture. The examples of Figures 6A and 6B show, in side view, two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer cross-point array as shown in Figure 4D. As shown in Figure 6A, by keeping the orientation of the MRAM layers the same for the layer 1 cell and the layer 2 cell, the manufacturing process can be made the same for each layer. Figures 6A and 6B show a lower first conductive line which is word line 1 600, an upper first conductive line which is word line 2 620, and an intermediate second conductive line which is bit line 610. In these figures, for ease of presentation, all of these lines are shown as extending left to right across the page, but in a cross-point array, these are more accurately represented by the perspective view of Figure 4D, where the word lines or first conductive lines or wires extend in one direction parallel to the surface of the underlying substrate, and the bit lines or second conductive lines or wires extend in a second direction parallel to the surface of the substrate which is substantially orthogonal to the first direction. The MRAM memory cells are also represented in a simplified form showing only the reference layer, free layer, and intermediate tunnel barrier, but in an actual implementation typically include the additional structures described above with respect to Figure 5.

[0062] An MRAM element 602 including a free layer 601, a tunnel barrier 603, and a reference layer 605 is formed over a threshold switching selector 609, and this series connection of the MRAM element 602 and the threshold switching selector 609 forms a layer 1 cell together between the bit line 610 and the word line 1 600. The series connection of the MRAM element 602 and the threshold switching selector 609 operates mainly as described above when the threshold switching selector 609 is turned on. However, initially, the threshold switching selector 609 needs to be turned on by applying a voltage that exceeds the threshold voltage V th of the threshold switching selector 609. Then, a bias current or voltage needs to be maintained sufficiently higher than the holding current or holding voltage of the threshold switching selector 609 so that it remains on during subsequent read or write operations.

[0063] In the second layer, the MRAM element 612 includes a free layer 611 and a tunnel barrier 613. The reference layer 615 is formed above the threshold switching selector 619. A layer 2 cell is formed between the bit line 610 and the word line 2 620 by a series connection of the MRAM element 612 and the threshold switching selector 619. The layer 2 cell operates for the layer 1 cell, but here the lower conductor corresponds to the bit line 610 and the upper conductor is the word line here, which is the word line 2 620. Additional pairs of layers may have patterns of WL1, BL1, WL2, WL3, BL2, WL4 and may similarly share another bit line therebetween, or may have separate bit lines in patterns such as WL1, BL1, WL2, BL2.

[0064] In the embodiment of FIG. 6A, the threshold switching selector 609 / 619 is formed under the MRAM element 602 / 612, but in an alternative embodiment, the threshold switching selector may be formed above the MRAM element of one or both layers. The MRAM memory cell has a directionality. In FIG. 6A, the MRAM elements 602 and 612 have the same orientation and the free layers 601 / 611 are above the reference layers 605 / 615 (with respect to the substrate not shown). Forming a layer between conductive lines having the same structure can have several advantages with respect to the process, since each of the two layers, and subsequent layers in embodiments having more layers, can be formed according to the same process sequence.

[0065] FIG. 6B shows an alternative embodiment arranged in the same manner as FIG. 6A, except that the locations of the reference layer and the free layer are reversed in the layer 2 cell. More specifically, between the word line 1 650 and the bit line 660 as in FIG. 6A, the layer cell 1 includes an MRAM element l having a free layer 651 formed on the tunnel barrier 653, the tunnel barrier 653 is formed on the reference layer 655, and the MRAM element 652 is formed on the threshold switching selector 659. The second layer of the embodiment of FIG. 6B also has an MRAM element 662 formed on the threshold switching selector 669 between the bit line 660 and the word line 2 670. However, compared with FIG. 6A, in the inverted state of the MRAM element 662, here it has a reference layer 661 formed on the tunnel barrier 663 and a free layer 665 formed under the tunnel barrier 663 here. Alternatively, the configuration of the MRAM element 662 may be used for the layer 1 cell and the configuration of the MRAM cell 652 may be used for the layer 2 cell.

[0066] The embodiment of FIG. 6B requires a different process sequence for forming the layers, but can have advantages in some embodiments. Specifically, during writing or reading in the same direction (with respect to the reference and free layers), the bit line is biased in the same way for both the lower and upper layers, and both word lines are biased in the same way, so the directionality of the MRAM structure can make the embodiment of FIG. 6B attractive. For example, when both the memory cells of layer 1 and layer 2 are sensed in the P2AP direction (with respect to the reference layer and the free layer), the bit line layer 660 is biased in the P2AP direction or the like, the bit line 660 is biased low (e.g., 0V) for both the upper and lower cells, and both the word line 1 650 and the word line 2 670 are biased to a higher voltage level. Similarly, for writing, to write to the high-resistance AP state, the bit line 660 is biased low (e.g., 0V) for both the upper and lower cells, and both the word line 1 650 and the word line 2 670 are biased to a higher voltage level.

[0067] To read data from or write data to an MRAM memory cell, it involves passing a current through the memory cell. In an embodiment where a threshold switching selector is arranged in series with the MRAM element, before the current can pass through the MRAM element, the threshold switching selector can be turned on by applying a sufficient voltage across both ends of the series combination of the threshold switching selector and the MRAM element.

[0068] FIG. 7 shows an embodiment of a memory array 202 having a cross-point architecture. The array 202 has a set of first conductive lines 706a - 706h and a set of second conductive lines 708a - 708d. In one embodiment, the set of first conductive lines 706a - 706h are word lines, and the set of second conductive lines 708a - 708b are bit lines. For ease of explanation, the set of first conductive lines 706a - 706h may be referred to as word lines, and the set of second conductive lines 708a - 708b may be referred to as bit lines. However, the set of first conductive lines 706a - 706h may be bit lines, and the set of second conductive lines 708a - 708b may be word lines.

[0069] The array 202 has several programmable resistive memory cells 401. Each memory cell 401 is connected between one of the first conductive lines 706 and one of the second conductive lines 708. In one embodiment, each memory cell 401 has a magnetoresistive random access memory (MRAM) element in series with a threshold switching selector. The threshold switching selector 502 is configured to become conductive with a lower resistance in response to the application of a voltage level exceeding the threshold voltage of the threshold switching selector 502, and remains conductive with a lower resistance until the current passing through the switching selector 502 is reduced below the selector holding current Ihold. The threshold switching selector 502 can be a two-terminal device. In one embodiment, the threshold switching selector 502 comprises an OTS.

[0070] For illustration purposes, memory cell 401a is selected for access. This can be a read or write access. The selected memory cell 401a is at the cross point of the selected word line 706g and the selected bit line 708b. To select the memory cell 401, a select voltage (V select_BL ) such as ground is supplied to the selected bit line (e.g., bit line 708b), and an access current (I access ) is driven (or forced) through the selected word line (e.g., word line 706g). A "selected word line" means that the word line is connected to at least one selected memory cell. The selected word line is typically connected to one or more non - selected memory cells. A "selected bit line" means that the bit line is connected to at least one selected memory cell. The selected bit line is typically connected to one or more non - selected memory cells. The selected memory cell is connected between the selected word line and the selected bit line.

[0071] In one embodiment, V select_BL has a magnitude such that the threshold switching selector 502 in the selected memory cell turns on, assuming that I access is applied to the selected word line. For example, V select_BL may be about 0V. On the other hand, V unsel_BL has a magnitude such that the threshold switching selector 502 in the non - selected memory cell does not turn on. For example, if the positive power supply is 3.3V, V select_BL may be about 1.65V. The access current (I access) is driven through at least a portion of the selected word line 706g. This access current can also flow through the selected memory cell 401a and into a portion of the selected bit line 708b after the OTS is turned on. Such a selected WL can be driven high, for example, by a current source having a compliance voltage of 3.3V, by 15 μa for reading, or by 30 μa for writing. To write with the opposite polarity, the selected word line is forced, for example, at -30 μa and the selected bit line is set to 3.3V.

[0072] Other memory cells are not selected for access (i.e., they are unselected memory cells). An "unselected memory cell" means that the memory cell is not currently selected for access (e.g., reading or writing). Unselected word lines are connected only to unselected memory cells. Unselected bit lines are connected only to unselected memory cells. Unselected word lines and bit lines are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, word lines and bit lines can be unselected by forcing them to a voltage that is not selected, for example, about half of the drive compliance voltage of 3.3V, such as Vmid of 1.65V. Unselected bit lines (e.g., bit lines 708a, 708c, 708d) are provided with an unselected voltage (V unsel_BL ). Unselected word lines (e.g., word lines 710a, 710b, 710c, 710d, 710e, 710f, and 710h) are provided with an unselected voltage (V unsel_BL ).

[0073] I access can flow in either direction through the selected word line (and the selected bit line). In one embodiment, no current other than leakage flows through unselected word lines (e.g., 706a, 706b, 706c, 706d, 706e, 706f, and 706h) by force.

[0074] In the example of FIG. 7, within the cross-point array, there are more word lines than bit lines. In one embodiment, within the cross-point array, there are more bit lines than word lines. In one embodiment, within the cross-point array, the number of bit lines is equal to the number of word lines. In the example of FIG. 7, there are twice as many word lines as bit lines within the cross-point array, but different ratios can also be used. Thereby, different tile sizes can be realized. For example, a tile can have 1024 BL×2048 WL, which can be configured into a module of 2048×4096 cells by centrally driving WL and BL among four tiles. In one embodiment, the reading is performed on a group of memory cells, for example, by selecting one memory cell in each of several tiles. In some embodiments, two or more memory cells can be selected from a tile for reading.

[0075] In some embodiments, the forced current technique is used to access the memory cells within the cross-point memory array. The threshold switching selector may be used in series with the memory cell. The threshold switching selector can be connected in series with the memory element between the word line and the bit line. Thus, any voltage across the switching selector reduces the voltage across the memory element. Typically, there is some variation in the offset or holding voltage between the switching selectors. The forced current technique can help reduce the offset voltage variation between the threshold switching selectors and minimize the selected cell current variation between cells.

[0076] FIG. 8 is a diagram of one embodiment of a system having a current source that supplies current to memory cells. Each memory cell 401 has a programmable resistive memory element 702 in series with a threshold switching selector 502. In one embodiment, the memory cell 401 is an MRAM cell in which the programmable resistive memory element 702 is a magnetoresistive memory element and the threshold switching selector 502 is an OTS. However, the memory cell may be a PCM cell, a ReRAM cell, or the like. The threshold switching selector 502 need not be an OTS. The voltage Vselect on the bit line (BL) is a voltage having a magnitude suitable for selecting the memory cell, for example, Vp of 3.6V. In one embodiment, Vselect is 0V. However, Vselect may be a higher voltage.

[0077] Current source 802 supplies a current (Isource) to the word line. During a read, the current can charge the word line until the threshold switching selector 502 switches on. After the threshold switching selector 502 switches on, Isource is driven through the memory cell. In one embodiment, current source 802 includes a cascode amplifier. In one embodiment, current source 802 has two operating modes. A control circuit 804 can be used to select between the two operating modes. In one embodiment, one mode is called the cascode mode and the other is called the non-cascode mode. In one embodiment, the non-cascode mode (e.g., cascade mode) is used during the initial portion of a read when the threshold switching selector 502 is switched on. After the threshold switching selector 502 is switched on, the cascode mode can be used to drive the current through the memory cell 401 for its reduced variation as the voltage on Iout changes (associated with the change in the MRAM resistance with the state change from LRS to HRS). Memory cell 401 can be sensed while current source 802 is operating in the cascode mode, which improves the accuracy of sensing. Further, operating the current source in the non-cascode mode allows for a large voltage across the memory cell 401, which facilitates the switching on of the threshold switching selector 502. In one embodiment, the current source is operated non-cascoded while writing to the memory cell 401. In one embodiment, current source 802 has a first output conductance when operating in a first mode and a second output conductance when operating in a second mode. In one embodiment, the second output (cascode) conductance is higher than the first output conductance. Having a higher output conductance when sensing the cell can improve the accuracy of sensing the memory cell but increases the voltage across the current sourcing element (headroom). In one embodiment, in the first mode, the output current changes at a first rate with the voltage at the output. However, in the second mode, the output current changes at a second rate, lower than the first rate, with the voltage at the output. Note that the voltage at the output of the current source can depend on the voltage across the memory cell.In one embodiment, since Isource is less dependent on the voltage at the current source output in the second mode (compared to the first mode), the accuracy of sensing the cell is improved. However, the first mode can allow for a larger voltage across the cell 401, which is useful for turning on the threshold switching selector 502 when the OTS Vth drifts higher, and for writing which can allow for a larger range of the voltage across the memory cell and the sense node voltage (on I_out) due to less drop in the current forcing element.

[0078] FIG. 9 is a flowchart of one embodiment of a process 900 for operating a current source when reading multiple programmable resistive memory cells in a cross-point array. Step 902 includes operating the current source 802 in a non-cascoded mode. Step 904 includes supplying an output current (Icurrent) to the selected memory cell. In one embodiment, a current such as 15 ua is supplied to the selected word line while a select voltage such as 0V is applied to the select bit line, when the CD of the mRAM is 20 nm.

[0079] Step 906 includes a determination of whether to remain in the non-cascode mode or change to the cascode mode. In one embodiment, the change is made after the threshold switching selector 502 switches on. This determination can be based on waiting for a predetermined time after initially supplying current to give the threshold switching selector sufficient time to switch on. In response to determining that the cascode mode should be entered, the current source 802 operates in the cascode mode in step 908. Step 910 includes driving an output current (Icurrent) through the selected memory cell while the threshold switching selector remains on. In one embodiment, this current has a magnitude suitable for reading the cell. In one embodiment, this current has a magnitude suitable for writing to the cell. Step 912 may include sensing the voltage across the selected memory cell while the current is being driven through the selected memory cell if this is a read operation. A write operation is also possible, in which case it should be noted that the current in step 910 can be increased relative to the current in step 904.

[0080] FIG. 10A is a schematic diagram of an embodiment of a system that operates current source 1000 in two modes when reading a programmable resistive memory cell having a threshold switch selector. Transistors T3 and T4 form a cascode circuit. A reference current I_Ref is input to T3 and T1 and mirrored by T2 and T4. Transistor T3 can be referred to as an input transistor, and transistor T4 can be referred to as an output transistor. Transistor T4 supplies an output current Isource to a memory array used for reading and writing. Alternatively, two circuits 1000 may be used, one for reading and a second for writing, which is a possible improvement to the latency that allows the desired current in the read-modify-write, i.e., read to write change. Transistor T1 is in series with T3. Transistor T2 is in series with T4. In one embodiment, circuit 1000 includes a cascode amplifier that may include T2, T4, and R2, sometimes referred to as a cascode current source. The cascode amplifier may have two stages referred to as an input stage and an output stage. In one embodiment, the input stage includes transistor T2, which may be referred to herein as a current mirror transistor having a gate to VCSN. In one embodiment, the input stage is an amplifier stage. In one embodiment, the gate of T4 VGN may be referred to as the input of the cascode amplifier output stage. The gate of T2 may be biased by a bias voltage VCSN generated by T1 using the reference current I_ref that flows after passing through cascode transistor T3. In one embodiment, the output stage includes transistor T4, sometimes referred to herein as an output transistor or a cascode output transistor. In one embodiment, the drain of T4 may be referred to as the output of the cascode amplifier. Current source 1000 is implemented within an embodiment of current source 802 of FIG. 8. The system includes a control circuit 804 that issues control signals for controlling current source 1000 via driver signals VGN and VGNR. In one embodiment, control circuit 804 is implemented within state machine 262 from FIG. 2 or FIG. 3, but is not limited thereto.One of the control signals is used to control the magnitude of the bias voltage VGN to select between two modes. In one embodiment, a relatively high bias voltage on VGN of about Vp~3.6V operates the current source 1000 in a non-cascode mode, and a lower bias voltage up to 1.5V operates the current source 1000 in a cascode mode. In one embodiment, applying 0V as VCSN or VGN disables the current source 1000, and thus the output current is close to 0 and approximately equal to the transistor leakage. When the current source 1000 is disabled, then a different current source can be used to provide current to the selected memory cell. Resistors R1 and R2 may be of the same size. Resistors R1 and R2 may be 0 ohms (i.e., removed) or more. A higher resistance for R1 and R2 may allow for a larger mismatch between T1 and T2 while still maintaining that the output current fluctuates above the target percentage. The voltage V_low may be ground, but does not have to be. Also, for a read current of 15ua, R1 and R2 may be 33K ohms, which can be realized by a transistor with its gate at Vp and its source-drain replacing the resistor terminals shown. The transistor L and W can be adjusted for the desired current or voltage drop. The currents in the right leg R2, T2, and T4 can be adjusted relative to I_REF by increasing or decreasing the sizes of R2, T2, and T4 proportionally to R1, T1, and T3. Each of R2, T2, and T4 was increased by the same multiple. The bias voltage VGN can be generated by a control circuit such as circuit R11, T22, T23, etc. Similarly, the equivalent voltage for T3 can be generated by R10, T20, T21, where R11 can be the same size as R10, T22 can be the same size as T20, and T23 can be the same size as T21. Or, the relative sizes can be adjusted to adjust the VGNR voltage relative to the voltage VGN to increase or decrease the voltage required for the cascode total voltage across the circuit. In one embodiment, R10 and R11 are each about 1M ohms. R12 and R13 are each about 100 kiloohms.

[0081] FIG. 10A also shows a control circuit that generates control signals Bypass, Enable, and Start. Circuit 1000 h12 has a start transistor T7 at the input. The start transistor T7 can be controlled to allow I_ref to pass through T3 or to prevent I_ref from passing through T3, thereby reducing power when the current source 802 of FIG. 8 is not used. The Enable signal is supplied to enable transistor T5 to enable the circuit. The Bypass signal is supplied to bypass transistor T6 to bypass T4. Transistors T5 and T6 are optional. Next, the operation of T5 and T6 will be described.

[0082] In an embodiment of circuit 1000 shown in FIG. 10A, the gate of T3 is biased by VGNR provided by the node between R10 and T20. FIG. 10B shows an alternative biasing technique where the gate of T3 in circuit 1020 is connected to the drain of T3 (the source of T7). FIG. 10C shows another alternative biasing technique where control circuit 804 supplies voltage VGNR to the gate of T3 in circuit 1040.

[0083] FIG. 11 is a graph showing output current versus voltage at the output node of one embodiment of a current source. Curve 1102 corresponds to the non-cascode mode of one embodiment of the current source. Curve 1104 corresponds to the cascode mode of one embodiment of the current source. Each curve has a relatively linear portion (1102a, 1104a) and a portion where the current depends much more strongly on the output voltage (1102b, 1104b). The cascode mode has much less variation in output current versus voltage over the useful operating range compared to the non-cascode mode. The cascade has a larger operating region for a given Vp. Line 1104a approximately corresponds to the operating region of the cascode mode where there is little variation in output current with respect to the voltage at the output. Line 1102a approximately corresponds to the operating region of the non-cascode mode where the variation in output current with respect to the voltage at the output is very small. Note that the non-cascode mode operates to a lower voltage than the cascode mode before saturation where the output current varies strongly with the output voltage, but the cascode mode has much less variation in output current versus voltage over the useful operating range. Also note that the non-cascode mode can be beneficial when the voltage across the memory cell can become larger, such as when turning on the threshold switching selector or writing to the memory cell. Since the write current is larger than the read current, the voltage across the memory cell can be larger during write than during read. In some embodiments, the write current is approximately twice the read current.

[0084] FIG. 12 is a schematic diagram of an embodiment of a system that operates current source 1200 in two modes when reading a programmable resistive memory cell having a threshold switching selector. Current source 1200 is similar to current source 1000 of FIG. 10A, but omits enable transistor T5. Current source 1200 is implemented within an embodiment of current source 802. Transistors having the same reference numbers (T1, T2, T3, T4) can operate in a manner similar to that described with reference to FIG. 10. In one embodiment, bypass transistor T6 can be used to bypass cascode transistor T4 to operate circuit 1200 in a non-cascode mode, or not to bypass cascode transistor T4 to operate circuit 1200 in a cascode mode. In one embodiment, bypass transistor T6 can be used to bypass T4 at the input stage of the cascode amplifier. Note that the input of the cascode amplifier (e.g., the gate of T4) is also bypassed. When a high voltage is applied to the gate of T6, T6 shorts across both ends of cascode transistor T4, thereby creating a non-cascode mode. A low voltage (e.g., 0V) applied to the gate of T6 turns T6 off, thereby creating a cascode mode. The system includes a control circuit 804 that issues control signals for controlling current source 1200. One of the control signals (Bypass) is applied to the gate of T6 to bypass or not bypass cascode transistor T4. As described in the description of FIG. 10, bias voltage VGN can be used to select between a cascode mode and a non-cascode mode. One option is to use a single copy of circuit 1200 for both the cascode mode and the non-cascode mode, but to use it at different times by using a bypass transistor. Bias voltage VGN can be maintained for biasing for the cascode mode for both states of bypass transistor T6. In one embodiment, the bias voltage VGNR to the gate of T3 is provided from the node between R10 and T20. However, the bias voltage VGNR to the gate of T3 can be provided as illustrated and described with respect to FIG. 10B or FIG. 10C.

[0085] In one embodiment, circuit 1200 is replicated such that one operates in a cascode mode (when enabled) and the other operates in a non-cascode mode (when its copy is enabled). Circuit 1300 can operate in either a non-cascode mode or a cascode mode based on bias voltage VGN with cascode transistor T4 not bypassed. Alternatively, circuit 1300 can be operated in either a non-cascode mode or a cascode mode based on whether cascode transistor T4 is bypassed using transistor T6 having a bypass high (Vp) or low (V_low).

[0086] FIG. 13 is a schematic diagram of an embodiment of a system that operates current source 1300 in two modes when reading a programmable resistive memory cell having a threshold switching selector. Current source 1300 is similar to current source 1000 of FIG. 10A, but with the addition of enable transistor T5. Current source 1300 is implemented within an embodiment of current source 802 of FIG. 8. Transistors having the same reference numbers (T1, T2, T3, T4) can operate in the same manner as described with reference to FIG. 10. In one embodiment, enable transistor T5 is used to enable (or select) current source 1300 or to disable (or deselect) current source 1300 by turning off current flow except for leakage. Current source 1300 has a cascode amplifier (which may include T2, T4, R2). In one embodiment, enable transistor T5 can be used to enable or disable the cascode amplifier, changing the driver circuit load to only a capacitance with low leakage for when it is not used. The system includes control circuit 804 that issues a control signal for controlling current source 1300. One of the control signals (Enable) is applied to the gate of T5 to enable / disable circuit 1300. As described in the description of FIG. 10, in one embodiment, bias voltage VGN can be used to select between cascode mode and non-cascode mode. In one embodiment, circuit 1300 is replicated such that one operates in cascode mode (when enabled) and the other operates in non-cascode mode (when enabled). Thus, the bias voltage VGN to each circuit can remain at a fixed value using the respective enable transistor T5 used to select one circuit or the other. In one embodiment, the bias voltage VGNR to the gate of T3 is provided from the node between R10 and T20. However, the bias voltage VGNR to the gate of T3 can be provided as illustrated and described with respect to FIG. 10B or FIG. 10C.

[0087] FIG. 14 is a schematic diagram of an embodiment of a system that operates a current source 1400 in two modes when reading a programmable resistive memory cell having a threshold switching selector. The current source 1400 is sometimes referred to as a current mirror cascode circuit (or “cascode current mirror”). Transistors T33 and T34 form a current mirror. A reference current I_Ref is input to T33 and mirrored by T34. Transistor T33 can be called the input transistor, and transistor T34 can be called the output transistor. Transistor T34 supplies an output current Isource to the memory array. Transistor T31 is in series with T33. Transistor T32 is in series with T34. In one embodiment, the circuit 1400 includes a cascode amplifier that may include T32, T34, and R32. The cascode amplifier may have two stages called an input stage and an output stage. In one embodiment, the input stage includes a transistor T32 that is sometimes referred to herein as a cascode transistor. In one embodiment, the gate of T32 can be called the input of the cascode amplifier. The gate of T32 can be biased by a bias voltage VG. In one embodiment, the output stage includes a transistor T34 that is sometimes referred to herein as the output transistor. In one embodiment, the drain of T34 can be called the output of the cascode amplifier. The current source 1400 is implemented within an embodiment of the current source 802. The system includes a control circuit 804 that issues a control signal for controlling the current source 1400. In one embodiment, the control circuit 804 is implemented within the state machine 262, but is not limited thereto. One of the control signals is used to control the magnitude of the bias voltage VG to select between two modes. In one embodiment, a relatively high bias voltage operates the current source 1400 in a non-cascode mode, and a lower bias voltage operates the current source 1400 in a cascode mode. In one embodiment, applying 0V as VG disables the current source 1000. When the current source 1400 is disabled, then a different current source can be used to provide current to the selected memory cell. Resistors R31 and R32 may be the same size.Resistors R31 and R32 may be 0 ohms (i.e., removed) or more. A higher resistance for R31 and R32 can allow for a greater mismatch between T31 and T32 while still maintaining that the output current fluctuates above the target percentage. Voltage V_low may be grounded, but does not need to be.

[0088] The circuit 1400 of FIG. 14 can be modified by adding a bypass transistor in parallel with T32 and / or adding an enable transistor in series with T32. Thus, T32 can be bypassed in a similar manner to bypassing T4 (see FIG. 12) to provide either a cascode mode or a non-cascode mode. Also, the circuit 1400 can be enabled / disabled using an enable transistor similar to the enable transistor T5 described for the circuit 1300 of FIG. 14.

[0089] FIG. 15 is a schematic diagram of one embodiment of a system that operates a current source 1500 in a non-cascode mode when reading a programmable resistive memory cell having a threshold switching selector. The current source 1500 is implemented within one embodiment of the current source 802. The current source 1500 has a current mirror formed by transistors T8 and T9. The start transistor T10 controls whether a reference current (I_ref) is provided as an input to the current source 1500. The enable transistor T11 enables / disables the current source 1500. The current source 1500 does not have a cascode transistor and does not operate in a cascode mode. In one embodiment, the current source 1500 is enabled for the non-cascode mode, and different current sources are enabled for the cascode mode, such as by enabling a version of the circuit 1000, 1020, 1040, 1200, 1300, or 1400.

[0090] FIG. 16A is a schematic diagram of an embodiment of a system that operates a current source 1600 in two modes (e.g., cascode, non-cascode) when reading a programmable resistance memory cell having a threshold switching selector. The current source 1600 is implemented within an embodiment of the current source 802. The circuit 1600 has p-channel transistors. The operation of the circuit 1600 may be similar to that of the n-channel circuit 1400. In one embodiment, the bypass signal within the circuit 1600 to the gate of T17 can be low for the non-cascode mode (providing a short across T16) and high for the cascode mode (where the output current flows through a series of T13, T15, and T16). In one embodiment, the p-channel transistors within the circuit 1600 are larger than the n-channel transistors within the circuit 1400 considering the mobility (drive) of the n-channel transistors which is larger than that of the p-channel transistors. In one embodiment, the p-channel transistors within the circuit 1600 are about twice the size of the n-channel transistors within the circuit 1400. The circuits R15, T26, T27, R17, R14, T24, T25, R14 may be used to bias VGPR or VGP, or such biasing may be provided by the control circuit 804 of FIG. 8.

[0091] In the embodiment of the circuit 1600 shown in FIG. 16A, the gate of T14 is biased by VGPR provided by the node between R16 and T25. FIG. 16B shows an alternative biasing technique where the gate of T14 within the circuit 1620 is connected to the node between T14 and T18. FIG. 16C shows another alternative biasing technique where the control circuit 804 supplies the voltage VGPR to the gate of T14 within the circuit 1640.

[0092] In one embodiment, a cascode transistor (e.g., T4, T16) is either bypassed to operate in a non-cascode mode or not bypassed to operate in a cascode mode. FIG. 17 is a flowchart of one embodiment of a process 1700 that involves determining whether to bypass a cascode transistor to control between a non-cascode mode and a cascode mode. Process 1700 provides further details regarding one embodiment of process 900. Process 1700 involves bypassing a cascode transistor. Process 1700 can use any of circuits 1300, 1400, or 1600, but is not limited thereto. Step 1702 includes bypassing a cascode transistor in a current source. In one embodiment, a voltage is applied to the gate of bypass transistor T6 to turn on bypass transistor T6 and short-circuit past cascode transistor T4. [For circuit 1600 of FIGS. 16A, 16B, or 16C, the bypass signal can be applied to bypass transistor T17. In circuit 1400 of FIG. 14, a bypass transistor can be added across T32.] Step 1702 is one embodiment of step 902 of process 900 that operates a current source in a non-cascode mode.

[0093] Step 1704 includes supplying an output current (Icurrent) to a selected memory cell. In one embodiment, a current is supplied to a selected word line while a select voltage is applied to a selected bit line. Step 1704 is one embodiment of step 904 of process 900.

[0094] Step 1706 includes determining whether the threshold switching selector is turned on. This determination can be based on waiting for a predetermined time after initially supplying current to give sufficient time for the threshold switching selector to switch on. If the threshold switching selector is not yet on, the system remains in the non-cascode mode. After the threshold switching selector is turned on, the system may switch to the cascode mode. Step 1706 is one embodiment of step 906 of process 900 for determining whether to operate in the non-cascode mode or the cascode mode.

[0095] In response to determining that the threshold switching selector is turned on, in step 1708, the bypass transistor can be turned off to stop bypassing the cascode transistor T4 (or T16 in FIG. 16 or T32 in FIG. 14). Step 1708 is one embodiment of step 908 of process 900 for operating the current source in the cascode mode. Step 1710 includes driving an output current (Icurrent) through the selected memory cell while the threshold switching selector remains on. Step 1712 includes sensing the voltage across the selected memory cell while the current is being driven through the selected memory cell.

[0096] In one embodiment, the system selects between two different circuits to provide either a non-cascode mode or a cascode mode. FIG. 18 is a flowchart of one embodiment of a process 1800 that involves selecting between two different circuits to control between a non-cascode mode and a cascode mode. Process 1800 provides further details regarding one embodiment of process 900. For purposes of explanation, one circuit is referred to as the cascode circuit and the other circuit is referred to as the non-cascode circuit. Current sources 1000, 1020, 1040, 1200, 1300, 1400, 1600, 1620, and 1640 each have the ability to operate as either a cascode circuit or a non-cascode circuit. Circuit 1500 of FIG. 15 may operate as a non-cascode circuit. This allows for a wide selection of combinations of cascode and non-cascode circuits.

[0097] Step 1802 includes disabling the cascode circuit. Step 1804 includes enabling the non-cascode circuit. An enable signal to T5 or T19 can be used in steps 1802 - 1804. In one embodiment, an enable transistor is added in series with T34 within circuit 1400 of FIG. 14. Steps 1802 - 1804 are both one embodiment of step 902 of process 900 for operating the current source in non-cascode mode. Step 1806 includes providing the output current (Icurrent) of the non-cascode circuit to a selected memory cell. In one embodiment, current is supplied to a selected word line while a select voltage is applied to the selected bit line. Step 1806 is one embodiment of step 904 of process 900 for operating the current source in non-cascode mode.

[0098] Step 1808 includes determining whether the threshold switching selector is on. This determination can be based on waiting for a predetermined time after initially supplying current to give the threshold switching selector sufficient time to switch on. If the threshold switching selector is not yet on, the system remains in non-cascoded mode. After the threshold switching selector is turned on, the system may switch to cascoded mode. Step 1808 is one embodiment of step 906 of process 900 for determining whether to operate in non-cascoded mode or cascoded mode.

[0099] In response to determining that the threshold switching selector is on, in step 1810, the cascode circuit is enabled. In step 1812, the non-cascoded circuit is disabled. Such changes may or may not be approximately simultaneous. The enable signal to T5 or T16 can be used in steps 1810 - 1812. Both steps 1810 - 1812 are one embodiment of step 908 of process 900 for operating the current source in cascoded mode. Step 1814 includes driving the output current of the cascode circuit through the selected memory cell while the threshold switching selector remains on. Step 1816 includes sensing the voltage across the selected memory cell while current is being driven through the selected memory cell.

[0100] In one embodiment, the bias voltage to the gate of the cascode transistor is used to select between a non-cascode mode and a cascode mode. FIG. 19 is a flowchart of one embodiment of process 1900 in which the control between the non-cascode mode and the cascode mode involves the magnitude of the bias voltage to the gate of the cascode transistor. Process 1900 provides further details regarding one embodiment of process 900. Process 1900 operates in both the non-cascode mode and the cascode mode, and can use one circuit that operates at different times. Process 1900 can use two different circuits, one operating in the cascode mode and the other operating in the non-cascode mode.

[0101] Step 1902 includes applying a high voltage to the gate of the cascode transistor in the current circuit. The current circuit can include, but is not limited to, current sources 1000, 1020, 1040, 1200, 1300, 1400, 1600, 1620, or 1640. The cascode transistor can include, but is not limited to, T4 in any of current sources 1000, 1020, 1040, 1200, or 1300, T16 in any of current sources 1600, 1620, or 1640, or T32 in current source 1400. When two circuits are used in process 1900, step 1902 can include turning on enable transistor T5 in the circuit to be used for the non-cascode mode and turning off enable transistor T5 in the circuit to be used for the cascode mode. Step 1902 is one embodiment of step 902 of process 900 that operates the current source in the non-cascode mode. Step 1904 includes supplying the output current of the current circuit to a selected memory cell. In one embodiment, current is supplied to the selected word line while a select voltage is applied to the selected bit line. Step 1904 is one embodiment of step 904 of process 900 that operates the current source in the non-cascode mode.

[0102] Step 1906 includes determining whether the threshold switching selector has been turned on. This determination can be based on waiting for a predetermined time after initially supplying current to give sufficient time for the threshold switching selector to switch on. If the threshold switching selector is not yet on, the system remains in the non-cascoded mode. After the threshold switching selector is turned on, the system may switch to the cascoded mode. Step 1906 is one embodiment of step 906 of process 900 for determining whether to operate in the non-cascoded mode or the cascoded mode.

[0103] In response to determining that the threshold switching selector has been turned on, in step 1908, a lower voltage is applied to the gate of the cascode transistor in the current circuit. This may be the same current circuit used in the non-cascoded mode or a different circuit. Step 1908 may also include turning on the enable transistor T5 in the circuit to be used for the cascoded mode and turning off the enable transistor T5 in the circuit used for the non-cascoded mode. Step 1908 is one embodiment of step 908 of process 900 for operating a current source in the cascoded mode. Step 1910 includes driving an output current through the selected memory cell while the threshold switching selector remains on. Step 1912 includes sensing the voltage across the selected memory cell while current is being driven through the selected memory cell.

[0104] Figure 20 is a flowchart of an embodiment of process 2000 for global reference read operation. The system operates the current source in two modes (e.g., non-cascoded mode and cascoded mode). In one embodiment, a programmable resistive memory cell having a threshold switching selector is read. In one embodiment, an MRAM cell having an OTS is read. However, the memory cell does not have to be MRAM, and the threshold switching selector does not have to be an OTS. Process 2000 will be described with reference to FIGS. 21A and 21B. FIG. 21A shows current versus time. FIG. 21B shows voltage versus time of the voltage across both ends of the selected memory cell.

[0105] Step 2002 includes applying a selection voltage to the selected bit line. Step 2004 includes operating the current source in non-cascoded mode to generate a selection current. The term "selection current" means a current having a magnitude of current and voltage suitable for turning on the threshold switching selector. Step 2006 includes driving the selection current to the selected word line to turn on the threshold switching selector. Referring to FIG. 21A, at time t1, the current increases to I source up to. Between t1 and t3, the current source operates in non-cascoded mode, but can operate in cascoded mode if sufficient supply voltage is available. Dashed line 2110 represents the selection current. Referring to FIG. 21B, the voltage across both ends of the memory cell increases from t1 to t2. The threshold switching selector is off between t1 and t2. Between t1 and t2, the word line voltage rises due to the current. The current also supports any leakage in the path. Once the voltage across the threshold switching selector reaches the threshold voltage V of the threshold switching selector 502 thWhen the threshold is reached, the threshold switching selector turns on and switches to the low resistance state (at t2). Therefore, the voltage between the series-connected x-y selection address selection transistor, the threshold switching selector element 502, and the resistive memory element ramps up between t1 and t2 because the threshold switching selector is off until t2. Referring to FIG. 21B, the threshold switching selector 502 remains on (low resistance state) between t2 and t3. Once the threshold switching selector 502 turns on (at t2), current flows through the selected memory cell 401. The voltage across the memory cell drops to a level that depends on the series resistance of the memory element 702 and the on-state resistance of the threshold switching selector 502, along with the address selection transistor and the metal resistance in the path. In a binary embodiment where the memory cell stores only two states, the memory cell has an HRS and an LRS. In response to the currents for the HRS and LRS, the resulting voltages across the series-connected memory element 702 and threshold switching selector 502 are shown as lines 2130 and 2140, respectively.

[0106] Step 2008 involves a decision of whether to stay in the selection stage or change to the sensing stage. The change is made after the threshold switching selector is switched on. This decision can be based on waiting for a predetermined time after initially supplying current to give sufficient time for the threshold switching selector to switch on. Step 2008 is an embodiment of step 906 of process 900 that determines whether to stay in the non-cascoded mode or change to the cascoded mode. In response to deciding to enter the sensing stage, the current source operates in the cascoded mode in step 2010 to generate a more accurate read current. Step 2012 involves driving a read current to the selected word line and forcing the read current to flow through the selected memory cell while the threshold switching selector remains on. Referring to FIG. 21A, the current source enters the cascoded mode at t3. Line 2120 represents the read current during the cascoded mode. The magnitude of the read current may be approximately the same as the magnitude of the selection current. For example, each current can be about 15 uA. However, the read current does not depend on the magnitude of the voltage across the memory cell (which affects the voltage at the output of the current source) more than the selection current. Thus, the magnitude of the read current will be very close to the target magnitude after t3 if it needs to be more accurate. Referring to FIG. 21B, the voltage across the memory cell can remain approximately the same after entering the cascoded mode. The threshold switching selector 502 remains in the on state. In response to the currents for HRS and LRS, the resulting voltages across the series-connected memory element 702 and the threshold switching selector 502 are shown as lines 2130 and 2140, respectively.

[0107] Step 2014 includes sensing the voltage across the selected memory cell while current is being driven through the selected memory cell. The memory cell can be sensed a short time after entering the cascode mode at t3. Step 2016 includes comparing the sensed voltage to a common reference voltage to determine the state of the memory cell. The "common reference voltage" is a reference voltage used as a comparison voltage for several different memory cells. This common reference voltage can be intermediate between the typical voltage of the HRS and the typical voltage of the LRS.

[0108] FIG. 22 is a flowchart of one embodiment of a process 2200 for a self-referential read operation. The system operates a current source in two modes (e.g., a non-cascode mode and a cascode mode). In one embodiment, a programmable resistive memory cell having a threshold switching selector is read. In one embodiment, an MRAM cell having an OTS is read. However, the memory cell need not be MRAM, and the threshold switching selector need not be an OTS. Process 2200 is described with reference to FIGS. 23A and 23B. FIG. 23A shows current versus time. FIG. 23B shows voltage versus time of the voltage across the selected memory cell.

[0109] Step 2202 includes performing a first read to select a cell to turn on the selected element using a non-cascoded mode, and then performing a read using a more accurate current in a cascoded mode with respect to the current source. The non-cascoded mode is used to turn on the threshold switching selector. The cascoded mode is used when sensing or reading a memory cell. In one embodiment, steps 2002-2014 of process 2000 are performed. Step 2204 includes storing the voltage from sensing the memory cell in the first read. Referring to FIG. 23A, the current increases at time t1. Between t1 and t3, the current source operates in a non-cascoded mode. Dashed line 2302 represents the selected current during the non-cascoded mode. Line 2304 represents the read current during the cascoded mode between t3 and t4. FIG. 23B shows the voltage across the memory cell between t1 and t4, which is similar to the voltage across the cell in FIG. 21B. Line 2310 represents the voltage of the HRS. Line 2312 represents the voltage of the LRS.

[0110] Step 2206 includes operating the current source in a non-cascoded mode to generate a write current. The term "write current" means a current having a magnitude suitable for changing the resistance of the memory cell programmable resistance memory element of the selected cell. Step 2208 includes driving the write current through the selected word line and through the selected cell while the threshold switching selector is still on. Referring to FIG. 23A, at time t4, the current is increased to I write up to. Between t4 and t5, the current source is operated in a non-cascoded mode and can be increased substantially, perhaps doubled, from the previous non-cascoded current selection. Dashed line 2306 represents the write current. Referring to FIG. 23B, the voltage across the cell increases to either line 2322 (LRS) or line 2320 (HRS) at t4. At some point between t4 and t5, if the cell was in the LRS, the cell switches to the HRS. Thus, by t5, the cell can always be within the HRS (line 2320).

[0111] Step 2210 includes operating the current source in cascode mode to generate a read current. Step 2212 includes driving the read current to the selected word line and forcing the read current to flow through the selected memory cell while the threshold switch selector remains on. Referring to FIG. 23A, the current source enters cascode mode at t5. Line 2308 represents the read current during cascode mode. Referring to FIG. 23B, since the magnitude of the read current is smaller than the write current, the voltage across the memory cell decreases. Line 2330 indicates that the memory cell is currently in HRS.

[0112] Step 2214 includes sensing the voltage across the selected memory cell while the read current is being driven through the selected memory cell. The memory cell can be sensed after a settling time after entering cascode mode at t5. Step 2216 includes comparing the sensed voltage with the stored voltage from the first read to determine the state of the memory cell. The stored voltage from the first read can be adjusted (e.g., can be adjusted up or down by 150 mv, the mram cd is 20 nm, its RA is 10, and the read current can be about 15 ua). The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sampled voltage is adjusted upward and the write is from HRS to HRS, if the cell was originally in HRS, the second sampled voltage should be lower than the first adjusted upward voltage. However, if the cell was originally in LRS, the second sampled voltage should be higher than the first adjusted upward voltage due to the higher voltage of HRS with a larger change in voltage of about 350 mV for a 150 mV adjustment of the first read voltage.

[0113] FIG. 24 is a flowchart of one embodiment of process 2400 of a write operation. The system may operate the current source in a non-cascoded mode. In one embodiment, a programmable resistive memory cell having a threshold switching selector is written. In one embodiment, an MRAM cell having an OTS is written. However, the memory cell need not be MRAM, and the threshold switching selector need not be an OTS.

[0114] Step 2402 includes applying a select voltage to the selected bit line. Step 2404 includes operating the current source in a non-cascoded mode to generate a select current. The term "select current" means a current having a magnitude and voltage suitable for switching on the threshold switching selector. Step 2406 includes driving the select current to the selected word line to switch on the threshold switching selector.

[0115] Step 2408 includes determining whether to stay in the select stage or change to the write stage. The change is made after the threshold switching selector has been switched on. This determination can be based on waiting for a predetermined time after initially supplying current to give the threshold switching selector sufficient time to switch on. In response to determining to enter the write stage, the current source continues to operate in a non-cascoded mode in step 2410 to generate a write current. However, the write current may have a magnitude greater than the select current. Step 2412 includes driving the write current to the selected word line while the threshold switching selector remains on to force the write current through the selected memory cell.

[0116] FIG. 25 is a flowchart of one embodiment of process 2500 of a global reference read operation. The system can operate a current source in cascode mode. In one embodiment, a programmable resistive memory cell having a threshold switching selector is read. In one embodiment, an MRAM cell having an OTS is read. However, the memory cell need not be MRAM, and the threshold switching selector need not be an OTS.

[0117] Step 2502 includes applying a select voltage to a selected bit line. Step 2504 includes operating a current source in cascode mode to generate a select current. The term "select current" means a current having a magnitude and voltage suitable for turning on a threshold switching selector. Step 2506 includes driving the select current to a selected word line to turn on the threshold switching selector.

[0118] Step 2508 includes a decision to stay in the select stage or change to the sense stage. The change is made after the threshold switching selector has been switched on. This decision can be based on waiting for a predetermined time after initially supplying current to give the threshold switching selector sufficient time to switch on. In response to deciding to enter the sense stage, the current source continues to be operated in cascode mode in step 2510 to generate a read current. Step 2512 includes driving the read current to the selected word line to force the read current through the selected memory cell while the threshold switching selector remains on.

[0119] Step 2514 includes sensing the voltage across the selected memory cell while current is being driven through the selected memory cell. Step 2516 includes comparing the sensed voltage to a common reference voltage to determine the state of the memory cell. The "common reference voltage" is a reference voltage used as a comparison voltage for several different memory cells. This common reference voltage can be intermediate between the typical voltage of the HRS and the typical voltage of the LRS.

[0120] In view of the above, according to one embodiment, it can be seen that the apparatus comprises a current source configured to be connected to a memory array. The current source has an output configured to supply an output current. The memory array includes a plurality of memory cells. Each memory cell includes a memory element in series with a threshold switch selector. The threshold switch selector of each memory cell has an on state for selecting the memory element of each memory cell and an off state for deselecting the memory cell of each memory cell. The apparatus comprises one or more control circuits coupled to the current source. The one or more control circuits are configured to be connected to the memory array. The one or more control circuits are configured to operate the current source in a first mode in which the output has a first conductance to supply the output current to a selected memory cell in order to turn on the threshold switch selector of the selected memory cell. The one or more control circuits are configured to operate the current source in a second mode in which the output has a second conductance to drive the output current through the memory element of the selected memory cell while the threshold switch selector of the selected memory cell remains on. The one or more control circuits are configured to sense the voltage across the selected memory cell while driving the output current through the memory element of the selected memory cell.

[0121] In a further embodiment, the one or more control circuits are further configured to operate the current source in the first mode after sensing the voltage across the selected memory cell in order to drive the output current through the memory element of the selected memory cell to write to the selected memory cell while the threshold switch selector of the selected memory cell remains on.

[0122] In a further embodiment, one or more control circuits are further configured to operate the current source in a second mode to drive an output current through the selected memory cell while the threshold switch selector of the selected memory cell remains on, after writing to the selected memory cell. One or more control circuits are further configured to sense a voltage across the selected memory cell while driving an output current through the memory element of the selected memory cell after writing to the selected memory cell. One or more control circuits are further configured to compare a sensed voltage before writing to the selected memory cell with a sensed voltage after writing to the selected memory cell.

[0123] In a further embodiment, the current source comprises a cascode current source having a cascode transistor coupled to the output to supply an output current. The current source has a bypass transistor coupled in parallel across the cascode transistor. The bypass transistor has a first state configured to create a short circuit bypass of the cascode transistor and a second state in which the bypass transistor is off. One or more control circuits are further configured to operate the current source in a first mode in which the bypass transistor is in the first state and the output current flows through the bypass transistor. One or more control circuits are further configured to operate the current source in a second mode in which the bypass transistor is in the second state and the output current flows through the cascode transistor, and the gate of the cascode transistor is the input of a cascode amplifier.

[0124] In a further embodiment, the current source comprises a cascode current source having a cascode transistor coupled to the output for supplying an output current. The one or more control circuits are further configured to apply a first voltage to the gate of the cascode transistor to operate the current source in a first mode, supply the output current to a selected memory cell, and turn on a threshold switching selector of the selected memory cell. The one or more control circuits are further configured to apply a second voltage to the gate of the cascode transistor while the threshold switching selector of the selected memory cell remains on, operate the current source in a second mode, and drive the output current through the memory element of the selected memory cell. The first voltage is greater than the second voltage.

[0125] In a further embodiment, the current source further comprises a first circuit having a first output transistor coupled to the output of the current source. The current source comprises a second circuit having a cascode current source having a cascode transistor coupled to the output of the current source. The one or more control circuits are further configured to enable the first circuit and disable the second circuit to operate the current source in a first mode to supply the output current from the first output transistor to a selected memory cell and turn on a threshold switching selector of the selected memory cell. The one or more control circuits are further configured to enable the second circuit and disable the first circuit to operate the current source in a second mode to drive the output current through the memory element of the selected memory cell from the cascode transistor.

[0126] In a further embodiment, the first circuit further comprises a first enable transistor coupled in series with the first output transistor. The second circuit further comprises a second enable transistor coupled in series with the cascode transistor. The one or more control circuits are further configured to operate the first enable transistor to connect the first output transistor to the output of the current source and to operate the second enable transistor to disconnect the cascode transistor from the output of the current source to operate the current source in a first mode. The one or more control circuits are further configured to operate the first enable transistor to disconnect the first output transistor from the output of the current source and to operate the second enable transistor to connect the cascode transistor to the output of the current source to operate the current source in a second mode.

[0127] In a further embodiment, the current source comprises a first current mirror having a first input mirror transistor coupled to a first input to receive a first reference current and a first output mirror transistor coupled to an output to mirror the first reference current to the output. The current source has a cascode transistor coupled in series with the first output mirror transistor. The current source has a first start transistor coupled in series with the first input mirror transistor. The current source comprises a second current mirror having a second input mirror transistor coupled to a second input to receive a second reference current and a second output mirror transistor coupled to the output to mirror the second reference current to the output. The current source has a second start transistor coupled in series with the second input mirror transistor. One or more control circuits are configured to operate the first start transistor to pass the first reference current to the first input mirror transistor when operating the current source in a first mode and to block the first reference current from the first input mirror transistor when operating the current source in a second mode. One or more control circuits are configured to operate the second start transistor to pass the second reference current to the second input mirror transistor when operating the current source in the second mode and to block the second reference current from the second input mirror transistor when operating the current source in the first mode.

[0128] In a further embodiment, the apparatus comprises a memory array. The memory element of each memory cell includes a programmable resistive memory element.

[0129] In a further embodiment, the threshold switching selector of each memory cell comprises an ovonic threshold switch (OTS).

[0130] In a further embodiment, the selected memory cell is the first memory cell. One or more control circuits are further configured to operate the current source in a first mode to supply an output current to a second selected memory cell to turn on the threshold switching selector of the second selected memory cell. One or more control circuits are further configured to continue to operate the current source in the first mode to drive the output current through the memory element of the second selected memory cell while the threshold switching selector of the selected memory cell remains on for writing to the second selected memory cell.

[0131] In a further embodiment, the selected memory cell is the first memory cell. One or more control circuits are further configured to operate the current source in a second mode to provide an output current to a second selected memory cell to turn on the threshold switching selector of the second selected memory cell. One or more control circuits are further configured to continue to operate the current source in the second mode to drive the output current through the memory element of the second selected memory cell while the threshold switching selector of the second selected memory cell remains on. Also, one or more control circuits are further configured to sense the voltage across the second selected memory cell while driving the output current through the memory element of the second selected memory cell.

[0132] One embodiment includes a method of operating a memory. The method includes applying a selection voltage to a selected bit line in a cross-point memory array, the selected bit line being connected to a selected programmable resistance memory cell in the cross-point memory array. The method includes operating a current source in a first mode, in which an output current supplied by the output of the current source changes at a first rate with a voltage at the output to generate a selection current. The method includes supplying the selection current to a selected word line connected to the selected programmable resistance memory cell to turn on a threshold switching selector of the selected programmable resistance memory cell. The method includes operating the current source in a second mode, in which the output current changes at a second rate with the voltage at the output to generate a read current, the second rate being lower than the first rate. The method includes driving the read current through a programmable resistance memory element of the selected programmable resistance memory cell while the threshold switching selector remains on. The method includes sensing a voltage across the selected programmable resistance memory cell while driving the read current through the programmable resistance memory element.

[0133] One embodiment includes a memory system having a cross-point memory array with programmable resistive memory cells. Each programmable resistive memory cell has a programmable resistive memory element in series with a threshold switching selector. The memory system includes a current source having a current mirror with a first transistor coupled to an input to receive a reference current and a second transistor coupled to an output of a current source to mirror the reference current to an output. The current source further includes a third transistor coupled in series with the first transistor and a fourth transistor coupled in series with the second transistor. The memory system has one or more control circuits coupled to the cross-point memory array and the current source. The one or more control circuits are configured to operate the current source in a first mode to generate a select current, including operating the fourth transistor in a non-cascoded mode. The one or more control circuits are configured to supply the select current to a selected memory cell in the cross-point memory array to turn on the threshold switching selector of the selected memory cell. The one or more control circuits are configured to operate the current source in a second mode to generate a read current, including operating the fourth transistor in a cascoded mode. The one or more control circuits are configured to drive the read current through the selected memory cell while the threshold switching selector remains on. The one or more control circuits are configured to sense a voltage across the selected memory cell while driving the read current through the selected memory cell.

[0134] For the purposes of this specification, references to "an embodiment", "one embodiment", "some embodiments" or "another embodiment" in the specification may be used to describe different embodiments or the same embodiment.

[0135] For the purposes of this specification, a connection can be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, this element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between this element and the other element. Two devices are in a "communication state" when they are directly or indirectly connected such that they can exchange electronic signals with each other.

[0136] For the purposes of this specification, the term "based on" can be read as "at least partially based on".

[0137] For the purposes of this specification, in the absence of additional context, the use of numerical terms such as "first", "second", and "third" objects does not imply an order of the objects, but instead may be used for identification purposes to distinguish different objects.

[0138] As may be used in this specification, the terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal", and forms thereof, are by way of example and for illustrative purposes only, and are not intended to limit the description of the technology as long as the referenced items can be interchanged in terms of position and orientation. Also, when used in this specification, the terms "substantially" and / or "about" mean that the specified dimension or parameter can vary within an acceptable tolerance for a given application.

[0139] The foregoing detailed description is presented for purposes of illustration and explanation. The foregoing detailed description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize the technology with various modifications suited to the particular uses contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. An apparatus comprising: a current source configured to be connected to a memory array, the current source having an output configured to supply an output current, the memory array comprising a plurality of memory cells, each memory cell comprising a memory element in series with a threshold switch selector, the threshold switch selector of each memory cell having an on state for selecting the memory element of the respective memory cell and an off state for deselecting the memory cell of the respective memory cell; and one or more control circuits coupled to the current source and configured to be connected to the memory array, the one or more control circuits operating the current source in a first mode in which the output has a first conductance to supply the output current to a selected memory cell to turn on the threshold switch selector of the selected memory cell; operating the current source in a second mode in which the output has a second conductance to drive the output current through the memory element of the selected memory cell while the threshold switch selector of the selected memory cell remains on; and one or more control circuits configured to sense a voltage across the selected memory cell while driving the output current through the memory element of the selected memory cell.

2. The apparatus of claim 1, wherein the one or more control circuits are further configured to operate the current source in the first mode after sensing the voltage across the selected memory cell to drive the output current through the memory element of the selected memory cell to write to the selected memory cell while the threshold switch selector of the selected memory cell remains on.

3. The apparatus of claim 1, wherein the one or more control circuits are configured to: operate the current source in the second mode after writing to the selected memory cell to drive the output current through the selected memory cell while the threshold switch selector of the selected memory cell remains on; and sense a voltage across the selected memory cell while driving the output current through the memory element of the selected memory cell after writing to the selected memory cell. ​ The apparatus according to claim 2, further configured to compare the sensed voltage before writing to the selected memory cell with the sensed voltage after writing to the selected memory cell.

4. The current source includes a cascode current source having a cascode transistor coupled to the output to supply the output current, the current source having a bypass transistor coupled in parallel across both ends of the cascode transistor, the bypass transistor having a first state configured to create a short-circuit bypass of the cascode transistor and a second state in which the bypass transistor is off. The one or more control circuits operate the current source in the first mode by setting the bypass transistor to the first state such that the output current flows through the bypass transistor. The one or more control circuits are further configured to operate the current source in the second mode by setting the bypass transistor to the second state such that the output current flows through the cascode transistor, wherein the gate of the cascode transistor is the input of a cascode amplifier. The apparatus according to claim 1.

5. The current source includes a cascode current source having a cascode transistor coupled to the output to supply the output current. The one or more control circuits apply a first voltage to the gate of the cascode transistor to operate the current source in the first mode, supply the output current to the selected memory cell to turn on the threshold switch selector of the selected memory cell. While the threshold switch selector of the selected memory cell remains on, apply a second voltage to the gate of the cascode transistor to operate the current source in the second mode to drive the output current through the memory element of the selected memory cell, the first voltage being greater than the second voltage. The apparatus according to claim 1.

6. The current source further includes a first circuit having a first output transistor coupled to the output of the current source. The current source includes a second circuit having a cascode current source having a cascode transistor coupled to the output of the current source. The one or more control circuits Enable the first circuit and disable the second circuit so that the current source operates in the first mode to supply the output current from the first output transistor to the selected memory cell to turn on the threshold switching selector of the selected memory cell. The second circuit is further configured to enable the second circuit and disable the first circuit so that the current source operates in the second mode to drive the output current through the memory element of the selected memory cell from the cascode transistor. The apparatus according to claim 1.

7. The first circuit further comprises a first enable transistor coupled in series with the first output transistor. The second circuit further comprises a second enable transistor coupled in series with the cascode transistor. The one or more control circuits are further configured to operate the first enable transistor to connect the first output transistor to the output of the current source and operate the second enable transistor to disconnect the cascode transistor from the output of the current source to operate the current source in the first mode. The one or more control circuits are further configured to operate the first enable transistor to disconnect the first output transistor from the output of the current source and operate the second enable transistor to connect the cascode transistor to the output of the current source to operate the current source in the second mode. The apparatus according to claim 6.

8. The current source includes a first current mirror having a first input mirror transistor coupled to a first input to receive a first reference current and a first output mirror transistor coupled to the output to mirror the first reference current to the output. The current source has a cascode transistor coupled in series with the first output mirror transistor, and the current source has a first start transistor coupled in series with the first input mirror transistor. The current source includes a second input mirror transistor coupled to a second input for receiving a second reference current, and a second output mirror transistor coupled to the output for mirroring the second reference current to the output, and the current source has a second start transistor coupled in series with the second input mirror transistor, The one or more control circuits are configured to operate the first start transistor to pass the first reference current to the first input mirror transistor when operating the current source in the first mode, and to block the first reference current from the first input mirror transistor when operating the current source in the second mode, The one or more control circuits are configured to operate the second start transistor to pass the second reference current to the second input mirror transistor when operating the current source in the second mode, and to block the second reference current from the second input mirror transistor when operating the current source in the first mode, The apparatus according to claim 1.

9. The apparatus further comprises the memory array, and the memory element of each memory cell comprises a programmable resistance memory element, the apparatus according to claim 1.

10. The threshold switching selector of each memory cell comprises an Ovonic Threshold Switch (OTS), the apparatus according to claim 9.

11. The selected memory cell is a first memory cell, and the one or more control circuits, operate the current source in the first mode to supply the output current to a second selected memory cell to turn on the threshold switching selector of the second selected memory cell, and are further configured to continue to operate the current source in the first mode to drive the output current through the memory element of the second selected memory cell while the threshold switching selector of the selected memory cell remains on to write to the second selected memory cell, the apparatus according to claim 1.

12. The selected memory cell is a first memory cell, and the one or more control circuits, Operating the current source in the second mode to provide the output current to a second selected memory cell, turning on the threshold switching selector of the second selected memory cell, While the threshold switching selector of the second selected memory cell remains on, continue to operate the current source in the second mode to drive the output current through the memory element of the second selected memory cell, The apparatus according to claim 1, further configured to sense a voltage across the second selected memory cell while driving the output current through the memory element of the second selected memory cell.

13. Applying a selection voltage to a selected bit line in a cross-point memory array, the selected bit line being connected to a selected programmable resistance memory cell in the cross-point memory array, Operating a current source in a first mode, in which the output current supplied by the output of the current source changes at a first rate with the voltage at the output to generate a selection current, Supplying the selection current to a selected word line connected to the selected programmable resistance memory cell to turn on the threshold switching selector of the selected programmable resistance memory cell, Operating the current source in a second mode, in which the output current changes at a second rate with the voltage at the output to generate a read current, and the second rate is lower than the first rate, Driving the read current through the programmable resistance memory element of the selected programmable resistance memory cell while the threshold switching selector remains on, Sensing the voltage across the selected programmable resistance memory cell while driving the read current through the programmable resistance memory element, A method of operating a memory, comprising.

14. Operating the current source in the first mode comprises bypassing a cascode transistor with a bypass transistor, the bypass transistor being coupled to the output to supply the selected current, and bypassing the cascode transistor resulting in the selected current varying with the voltage at the output at the first rate, Operating the current source in the second mode comprises operating the current source with the cascode transistor coupled to the output in a state where a read current varies with the voltage at the output at the second rate. The method according to claim 13.

15. Operating the current source in the first mode comprises enabling a first current mirror in which an output current varies with the voltage at the output of the first current mirror at the first rate while disabling a current mirror cascode circuit. Operating the current source in the second mode comprises disabling the first current mirror while enabling the current mirror cascode circuit from which the read current is supplied such that the output current varies with the voltage at the output of the current mirror cascode circuit at the second rate. The method according to claim 13.

16. Operating the current source in the first mode comprises applying a first voltage to a gate of a cascode transistor, the cascode transistor being coupled to the output to supply the selected current that varies with the voltage at the output at the first rate. Operating the current source in the second mode comprises applying a second voltage to the gate of the cascode transistor, the cascode transistor being coupled to the output to supply the read current that varies with the voltage at the output at the second rate, the second voltage having a magnitude lower than that of the first voltage. The method according to claim 13.

17. Operating the current source in the first mode to generate a write current; While the threshold switching selector of the selected memory cell remains on, driving the write current through the selected programmable resistive memory cell to write to the selected programmable resistive memory cell. Operating the current source in the second mode to generate a second read current. While the threshold switching selector of the selected memory cell remains on, driving the second read current through the selected programmable resistive memory cell. While driving the second read current through the selected programmable resistive memory cell, sensing the voltage across the selected programmable resistive memory cell. Comparing the sensed voltage before writing to the selected programmable resistive memory cell with the sensed voltage after writing to the selected programmable resistive memory cell. The method according to claim 13, further comprising. **Claim 18** A cross-point memory array having programmable resistive memory cells, each programmable resistive memory cell having a programmable resistive memory element in series with a threshold switching selector, the cross-point memory array. A current source, the current source comprising a current mirror having a first transistor coupled to an input of the current source to receive a reference current and a second transistor coupled to the output of the current source to mirror the reference current to the output of the current source, the current source further comprising a third transistor coupled in series with the first transistor and a fourth transistor coupled in series with the second transistor. One or more control circuits coupled to the cross-point memory array and the current source, the one or more control circuits. Operating the current source in a first mode to generate a select current, including operating the fourth transistor in a non-cascoded mode. Supplying the select current to a selected memory cell in the cross-point memory array to turn on the threshold switching selector of the selected memory cell. Operating the current source in a second mode to generate a read current, including operating the fourth transistor in a cascoded mode. While the threshold switch selector remains on, drive the read current through the selected memory cell, A memory system including one or more control circuits configured to sense the voltage across the selected memory cell while driving the read current through the selected memory cell. Memory system.

19. The current source includes a fifth transistor connected in parallel with the fourth transistor, Operating the current source in the first mode and operating the fourth transistor in the non-cascoded mode comprises bypassing the fourth transistor using the fifth transistor, and the selection current is from the fifth transistor and the second transistor connected in series. Operating the current source in the second mode and operating the fourth transistor in the cascoded mode comprises turning off the fifth transistor, and the read current is from the second transistor and the fourth transistor connected in series, and the gate of the fourth transistor is the input of a cascode amplifier. The memory system according to claim 18.

20. Operating the current source in the first mode and operating the fourth transistor in the non-cascoded mode comprises applying a first bias voltage to the gate of the fourth transistor. Operating the current source in the first mode and operating the fourth transistor in the non-cascoded mode comprises applying a second bias voltage lower than the first bias voltage to the gate of the fourth transistor. The memory system according to claim 18.

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