High-density spin-orbit magnetic random access memory

Abstract

A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element, such as a magnetic tunnel junction formed in a spin orbit torque layer. The vertical transistor structure selectively applies current to the spin orbit torque layer to switch the memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high currents required for spin orbit torque switching while consuming less wafer area. The vertical transistor structure may include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure, such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

Description

Technical Field of the Invention

[0001] The present invention relates to a spin-orbit torque (SOT) magnetic random access memory (MRAM), and more particularly to an SOT MRAM structure that employs a vertical transistor to supply a drive current to a spin-orbit torque layer.

Background Art

[0002] Random access memory (RAM) is a component found throughout modern digital circuit architectures. RAM can be an independent device or can be built into devices that use RAM, such as microprocessors, microcontrollers, application-specific integrated circuits (ASICs), and system-on-chips (SoCs). There are two types of RAM: volatile and non-volatile. Volatile RAM loses the stored information when the power is turned off. Non-volatile RAM can retain the stored content even when the power is turned off.

[0003] Magnetic random access memory (MRAM) is a non-volatile memory technology that has response (read and write) times comparable to those of volatile memories. The data stored in MRAM does not degrade over time, and the power consumption is very low compared to other RAM technologies. In contrast to conventional RAM technologies that store data as the flow of charge or current, MRAM uses magnetic memory elements. Thus, MRAM has several desirable characteristics that make it a candidate for universal memory, such as high speed, high density (i.e., small bit cell size), low power consumption, and extremely little degradation of logical states over time.

[0004] Despite having the above-mentioned characteristics, conventional MRAM devices are not perfect. Conventional memory elements (e.g., magnetic tunnel junctions (MTJs)) in spin-transfer torque MRAM (e.g., STT-MRAM) are two-terminal devices with a shared read path and write path. Since the read path and write path are shared, there are problems with read speed and write reliability. For writing, it is necessary for the barrier layer of the MTJ to be sufficiently thin (and have a relatively low resistance) in order to pass the current required for switching. However, if the barrier layer is thin, it is susceptible to the effects of dielectric breakdown due to repeated write operations. Also, the state of the MTJ may be unintentionally reversed by the read current. This is called "read disturbance". As the MTJ technology shrinks in physical size, the switching current tends to decrease. However, for high-speed read operations, usually more read current is required. Therefore, high-speed MRAM, especially deeply scaled MTJ devices, may be troubled by read disturbance. Therefore, it is difficult to meet the reliability requirements for both write durability (due to strain in the tunnel barrier within the MTJ) and read reliability.

[0005] MRAM devices based on spin-orbit torque exhibit switching speeds up to about 200 ps and can be used for L1 / L2 cache applications. Another important point about these devices is that since the current paths for reading and writing are separated, they are not troubled by durability problems. Generally, in two-terminal MRAM, the read current is one order of magnitude lower than the write current. By eliminating the large write switching current, SOT memory removes the large stress on the MgO barrier layer and improves reliability and durability.

[0006] However, such devices have drawbacks in terms of data density. First, since they are three-terminal devices, three transistors are required. Second, the write current density passing through the orbital torque material with such a structure can be as high as 1 - 2x108 A / cm2. For this reason, switching currents of several hundred microamperes (for example, about 100 - 400 microamperes) may be required in a general spin-orbit torque layer. As a result, the size of the transistor increases, raising the cost. Thus, reducing the cross-sectional area of the spin-orbit torque layer and the size of the transistor is of utmost importance in finding suitable applications. Overview

[0007] The present invention provides a spin-orbit torque data recording device including a magnetic memory element having a magnetic free layer. The conductive spin-orbit torque layer is adjacent to the magnetic free layer of the magnetic memory element. The vertical transistor structure is electrically connected to the spin-orbit torque layer and is configured to selectively supply current to the spin-orbit torque layer.

[0008] The vertical transistor structure can include a semiconductor pillar and a gate dielectric layer surrounding the semiconductor pillar. The conductive gate layer can be formed adjacent to the gate dielectric such that the gate dielectric layer separates the semiconductor pillar from the conductive gate layer. The semiconductor pillar layer can be formed to have first and second doped ends, both of which can be n+ doped regions. The semiconductor pillar structure can be an epitaxial growth semiconductor material, which can be a substantially single-crystalline semiconductor material.

[0009] The vertical transistor structure can be a write select transistor, and the data recording device can further include a read select transistor, which is electrically connected to the magnetic data recording element at an end opposite to the spin-orbit torque layer.

[0010] The magnetic memory element can be a magnetic tunnel junction element. The spin orbit torque layer can be formed of one or more of β-phase tungsten (W) and / or β-phase tantalum (Ta).

[0011] Spin orbit torque memory has the advantage of improved durability compared to other types of magnetic memory. This is because switching can be performed without repeatedly passing a large current through the magnetic element memory that stresses the barrier layer and leads to destruction of the barrier layer and degradation of the lifetime and reliability. However, the large current required to drive switching in a spin orbit torque device requires a sufficiently large and robust write selector transistor to handle the high write current.

[0012] By using a vertical transistor structure, advantageously, the high current required for spin orbit torque memory can be supplied to the spin orbit torque layer. Also, the vertical transistor can advantageously supply this large current while occupying a small area of the wafer.

[0013] These and other features and advantages of the present invention will become apparent by reading the following detailed description of embodiments, which is selected in combination with the figures showing like elements throughout by like reference numerals.

Brief Description of the Drawings

[0014] To more fully understand the nature and advantages of the present invention and its preferred modes of use, reference should be made to the following detailed description read in conjunction with the accompanying drawings (which are not to scale).

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[0021] The following description pertains to the presently contemplated best mode for carrying out the invention. This description is made for the purpose of explaining the general principles of the invention and is not intended to limit the inventive concept claimed herein.

[0022] FIG. 1 is a schematic diagram showing a spin-orbit torque memory structure 100 according to a possible embodiment. The memory structure 100 includes a spin-orbit torque memory element 102, and the spin-orbit torque memory element 102 includes a magnetic memory element 104 that can be a magnetic tunnel junction element (MTJ) and a spin-orbit torque layer 106. At the most basic level, the MTJ can include a magnetic reference layer 108, a magnetic free layer 110, and a thin non-magnetic barrier layer 112, which will be described in more detail below in this specification. The spin-orbit torque layer 106 can be composed of a conductive metal such as β-phase tungsten (W) and / or β-phase tantalum (Ta). The memory element 102 is a three-terminal element that can be electrically connected to a source line SL and selectively connected to a bit line BL. A pair of transistors 114, 116 can be used to respectively select a read mode and a write mode as described later. The transistor 114 is a write transistor and can be switched so as to be able to pass a write current through the spin-orbit torque layer 106 between the source line SL and the bit line BL. Hereinafter, in this specification, the switching mechanism of the memory element 102 will be described in more detail. The transistor switching device 116 is a read transistor that can pass a read current through the magnetic memory element 104 between the bit line and the source line.

[0023] FIG. 2 is an enlarged perspective, schematic view showing the structure and operation of the spin-orbit torque memory element 102 according to the embodiment. The memory element structure 102 includes the magnetic memory element 104 described above, which can be a magnetic tunnel junction element. By way of example, the MTJ element 104 can include a magnetic reference layer 108, which can be composed of a magnetic material such as NiFe, CoFe, but not limited thereto, and has a magnetization 202 fixed in a predetermined orientation that can be oriented parallel to the plane of the layer as shown in FIG. 2. The fixing of the magnetization 202 of the reference layer 108 can be facilitated by a synthetic antiferromagnetic structure 204, which can include a pair of magnetic layers 206, 208 exchange-coupled via a non-magnetic coupling layer 210 such as ruthenium. The magnetic layers 206, 208 can be exchange-coupled antiparallel such that the magnetizations of the layers 206, 208 are fixed in opposite directions as shown. Due to the exchange coupling between the synthetic antiferromagnetic structure 204 and the reference layer 108, the magnetization 202 of the reference layer 108 is reliably fixed in the desired direction.

[0024] The MTJ can also include a magnetic free layer 110 having a magnetization 204 that can move between magnetic directions that can also be oriented parallel to the plane of the magnetic free layer 110. The MTJ can be configured to have in-plane magnetic anisotropy such that the magnetization 212 can switch between two directions and then maintain a stable state in that direction. The magnetization 212 of the magnetic free layer 110 can be tilted in the stationary state to facilitate switching between the two states.

[0025] The switching of the magnetization 212 between two stable magnetic states can be achieved by spin-orbit coupling from the spin-orbit torque layer 106. When a current flows through the layer 106, the spin-orbit of the electrons passing through the spin-orbit torque layer 106 aligns as indicated by the line 208, and the electrons above the layer 106 are oriented in a first direction and the electrons below the layer 106 are oriented in the opposite direction. The spin-oriented electrons above the layer 106 apply a force to the magnetization 212 of the free layer 110 and switch the magnetization 212 in the desired direction. By generating a current in the opposite direction through the spin-orbit torque layer 106, the magnetization 212 can be switched in the opposite direction.

[0026] By using the spin-orbit torque layer 106 to switch the magnetization 212 of the magnetic free layer 110, the switching speed and durability in the memory system are improved. In switching without using the spin-orbit torque layer, it is necessary to apply a high switching current directly through the memory element 104 in a direction perpendicular to the plane of the layer. This can apply a high thermal stress to the barrier layer 112, causing the barrier layer to be destroyed, thereby potentially shortening the life of the memory element. Furthermore, switching by spin-orbit torque results in an improvement in switching speed compared to other switching mechanisms. For example, an MRAM device based on spin-orbit torque can exhibit a switching speed of up to about 200 picoseconds (ps) and can be used for L1 / L2 cache applications.

[0027] One issue shown by the spin-orbit torque MRAM system is that a large amount of current is required to pass through the spin-orbit torque layer 106 in order to switch the magnetization 212 of the free layer 110 as desired. This large current requires a corresponding large selector transistor. Using a conventional transistor in circulation requires a large wafer area to be able to handle the high current load, thus reducing the density of the memory system using such technology.

[0028] According to an embodiment, this issue can be overcome by using a vertical epitaxial selector transistor. Referring to the schematic diagram of FIG. 1, the selector transistor 114 schematically shown in FIG. 1 can be configured as a vertical transistor structure that can handle a large current load while consuming less area than a conventional transistor structure. Also, another selector transistor 116 can also be configured as a vertical transistor structure. However, since this transistor 116 does not need to handle the large current load of the transistor 114, the transistor 116 does not need to be configured as a vertical transistor structure.

[0029] Figures 3 and 4 show cross-sectional views of the transistor structure 114 according to the embodiment. FIG. 3 is a cross-sectional view along a plane parallel to the word line structure (WRITE WL), and FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 3. The selector transistor structure 114 is formed on a semiconductor substrate 302, which is preferably a silicon substrate, but can also be any other semiconductor material. The semiconductor substrate 302 includes an upper portion that can be doped to form a conductive source line layer 304. The source line layer 304 can be divided into individual source line structures by a dielectric trench isolation structure 306, which can be composed of an oxide such as silicon oxide or nitride.

[0030] On top of the source line layer 304 on the substrate 302, a semiconductor pillar 308 is formed. The semiconductor pillar is preferably an epitaxially grown semiconductor such as silicon or silicon germanium. The epitaxially grown semiconductor material has been found to have good crystallographic properties and excellent properties for conducting current. A method for constructing such an epitaxial semiconductor pillar 308 will be described in detail below in this specification. The semiconductor pillar 308 can be formed with doped regions 310 and 312 at the bottom and top of the pillar 308. The doped portions 310 and 312 can be n+ doped by implantation, annealing, etc., to provide the source and drain of the vertical semiconductor structure 114.

[0031] The semiconductor pillar 308 is surrounded by a gate dielectric layer 314 and a gate structure 316, and the gate dielectric layer 314 surrounds the pillar 308 and separates the semiconductor pillar 314 from the gate structure 316. The gate structure can include upper and lower dielectric layers 318 and a conductive gate line layer 320 located between the upper and lower dielectric layers 318. The upper and lower dielectric layers 318 can be composed of an oxide or nitride, and the conductive gate layer 320 can be composed of a highly doped semiconductor material such as highly doped silicon, for example. A conductive lead 322 can be formed at the upper end (opposite the source line layer 304) to provide an electrical connection between the semiconductor pillar 308 and the bit line (BL).

[0032] The semiconductor pillar 308 can be cylindrical, but can also have other shapes. For example, the semiconductor pillar can have an elongated oval or elliptical shape when viewed from above, or can be formed as a rectangular prism when viewed from above in FIGS. 3 and 4. As shown in FIGS. 3 and 4, the bottom of the semiconductor pillar 308 can have an inclined bottom. This can be advantageous during the formation of the pillar 308, as will be further described below in this specification. The semiconductor pillar 308, together with the gate dielectric layer 314 and the gate structure 316, forms a vertical CMOS selector transistor structure with the bottom 310 and the top 312 being source and drain regions. When a gate voltage is applied from the conductive gate layer 320 to the gate dielectric layer, the pillar 308 becomes conductive and can conduct current between the source line layer 304 and the bit line layer BL. Conversely, when the gate voltage is removed, the semiconductor pillar 308 becomes electrically insulating and can prevent current from flowing between the source line layer 304 and the bit line BL.

[0033] FIG. 5 is a perspective schematic view of a spin-orbit torque MRAM structure employing the vertical transistor structure 114 as described above. As seen in FIG. 5, the bit line BL is connected to a read selector transistor 116, which connects the bit line BL to a magnetic memory element 104, which may be a magnetic tunnel junction element (MTJ). Also connected to the bit line BL is a vertical selector transistor 114. The vertical selector transistor 114 is a write word line selector that selectively connects the bit line BL and the source line layer 304.

[0034] In the read mode, the read transistor 116 is open and the transistor 114 is closed. The read transistor 116 is controlled by a signal from a read word line WL that supplies a gate voltage to the read transistor 116. By applying a voltage to the memory element between the bit line BL and the source line SL, the stored state of the memory element 104 can be read.

[0035] In the write mode, the write selector transistor 114 is open, whereby the bit line BL and the source line SL are connected via the source line layer 304 formed on the substrate. The write selector transistor is controlled by a gate voltage applied by a write word line (WRITE WL). As a result, a current flows through the spin orbit torque layer 106. As described above, when a current flows through the spin orbit torque layer 106, electrons become spin-polarized in opposite directions at the upper and lower portions of the layer 106. Due to this polarization of the electron spins, the magnetization of the free layer of the memory element 104 is set in a desired direction depending on the direction of the current flowing through the spin orbit torque layer 106.

[0036] The vertical semiconductor structure 114 can advantageously handle a higher current load than a conventional transistor structure and can do so while consuming only a small area of the substrate 302. These advantages are further enhanced when the semiconductor pillars are formed by epitaxial growth on the substrate. FIGS. 6-16 are diagrams showing a part of a spin orbit torque MRAM system at various intermediate stages of manufacture for explaining a method of manufacturing a spin orbit torque MRAM structure having a vertical transistor structure. Referring particularly to FIG. 6, a semiconductor substrate 602 is provided. The substrate 602 may be a silicon wafer or may be another type of semiconductor material such as silicon germanium. The upper portion 604 of the substrate 602 can be doped (e.g., n+ doped) to form a high-concentration doped source layer. The doping can be performed by ion implantation or in-situ deposition of a doped semiconductor material. Optionally, a dielectric trench isolation structure 606 can be formed to separate the doped upper portion 604 into individual source layers. The trench isolation structure 606 can be formed by etching a trench and depositing a dielectric material such as silicon oxide or silicon nitride. A chemical mechanical polishing process can be performed to planarize the upper surfaces of the wafer doped source region 604 and the trench isolation structure 606.

[0037] Referring to FIG. 7, a series of layers are deposited to form a gate structure 702. The gate structure 702 includes a conductive gate layer 708 positioned between first and second dielectric gate dielectric layers 704, 706. The conductive gate layer 708 may be a highly doped semiconductor such as highly doped silicon, or may be some other type of conductive material. The first and second dielectric layers 704, 708 may be oxides or nitrides such as silicon oxide or silicon nitride.

[0038] Referring to FIG. 8, an opening 802 is formed in layers 704, 708, 706 and terminates at the doped source layer 604 of the substrate 602. The opening can be configured to have a shape that defines a silicon pillar structure and can be circular, elliptical, rectangular, etc. as desired. The opening 802 can be formed by masking and etching processes. Next, a gate dielectric layer 804 is deposited, and then a protective layer 806 is deposited. The gate dielectric layer can be a material such as silicon oxide or silicon nitride and is deposited to have a thickness at the sides of the opening 802 so as to provide a desired spacing between the (not yet formed) semiconductor pillar and the conductive gate layer 708. The protective layer can be a material selected to have an etching selectivity with respect to the gate dielectric layer 804, and the protective layer 806 can be removed by an etching chemistry that leaves the gate dielectric layer 804 substantially intact. The gate dielectric layer 804 and the protective layer 806 can be deposited by conformal deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0039] Next, referring to FIG. 9, an anisotropic material removal process such as ion milling is performed to preferentially remove the horizontally disposed portions of layers 804, 806, opening the bottom of the opening 802 to expose the underlying source line layer 604. By this material removal process, the gate dielectric layer 804 and the protective layer 806 remain inside the opening 802. The protective layer 806 protects the gate dielectric layer 804 during this material removal process (e.g., ion milling).

[0040] Next, referring to FIG. 10, selective etching is performed to remove the protective layer 806 while leaving the gate dielectric layer 804 inside the opening 802. This selective etching is reactive ion etching and can be performed using chemicals selected to remove the protective layer 806 without significantly removing the gate dielectric layer 804.

[0041] Referring to FIG. 11, a further etching process can be performed to remove a portion of the doped source line layer 604. This etching can be performed in a manner that forms an inclined surface 1102 on the exposed source layer 604, as shown in FIG. 11. This has been found to promote good crystal growth during subsequent epitaxial semiconductor deposition.

[0042] Next, referring to FIG. 12, a semiconductor material grows in the opening 802. The semiconductor 1202 can be silicon, silicon germanium, etc., and is preferably grown using selective epitaxial growth. By epitaxially growing the semiconductor material 1202, good crystallinity is obtained in the semiconductor material 1202. As described above, the inclined shape of the source line layer 604 at the bottom of the opening 802 further promotes excellent crystal characteristics in the epitaxially grown semiconductor material 1202. As a result, the semiconductor material 1202 can have a single-crystal or nearly single-crystal structure, resulting in low resistance in the completed transistor structure and enabling the transistor to handle the high current load required for driving the switching current in the spin-orbit torque MRAM system. As seen in FIG. 12, due to the deposition or growth of the semiconductor material, a portion of the semiconductor material can extend outside the opening 802. Alternatively, the semiconductor growth can be terminated before the semiconductor material 1202 reaches the top of the opening, after which, as will be seen later, the deposition of the doped semiconductor material can continue.

[0043] Next, referring to FIG. 13, a chemical mechanical polishing process can be performed to remove and planarize the semiconductor material 1202 protruding from the opening 802, leaving the semiconductor pillar 1202 as shown in FIG. 13. Further, the upper and lower portions of the semiconductor pillar 1202 can be doped to form upper and lower doped semiconductor regions 1302, 1304. The lower doped portion 1304 can be doped by annealing to diffuse dopant atoms from the source line layer 604 into the lower portion 1304 of the semiconductor material. The upper portion 1302 of the semiconductor pillar 1202 can be doped by ion implantation. Alternatively, the epitaxial growth of the semiconductor material 1202 can be terminated before reaching the upper portion of the opening 802, and then the upper portion 1302 of the semiconductor material 1202 can also be doped by performing in-situ deposition of the doped semiconductor material. The doped regions 1302, 1304 can be n+-doped. The doped regions 1302, 1304 form the source and drain of the semiconductor channel. After forming the semiconductor pillar 1202 and the doped source and drain regions 1302, 1304, the upper end of the semiconductor pillar 1202 can be connected to the bit line circuit BL.

[0044] FIG. 14 is an enlarged cross-sectional view taken along line 14-14 of FIG. 13. As shown in FIG. 14, the dielectric layer 1402 can be formed on the substrate 602 so as to extend from the end 1404 of the source line layer 604. On the dielectric layer 1402, a spin-orbit torque layer 1406 can be formed so as to overlap a part of the source line layer 604. The spin-orbit torque layer 1406 can be formed of a conductive metal such as β-phase tungsten (W) or β-phase tantalum (Ta). The magnetic memory element 1408 is formed in the spin-orbit torque layer 1406. The magnetic memory element 1408 is an MTJ memory element as described above, and can include a magnetic free layer 1410, a non-magnetic barrier layer 1412, and a magnetic reference layer 1414, and the magnetic free layer is adjacent to the spin-orbit torque layer 1406.

[0045] The semiconductor pillar structure 1202, the gate dielectric 804, and the gate structure 702 described above form a write select transistor 114 as described above with reference to FIG. 1. The gate structure 702 can be connected to a write word line (WRITE WL) circuit. As shown in the figure, the write select transistor 114 is electrically connected to the bit line circuit BL and is electrically connected to the spin orbit torque layer 1406 via the source line layer 604. Also, similar to the schematic diagram described above with reference to FIG. 1, the read transistor 116 is also connected to the bit line circuit BL and to the end of the magnetic memory element 1408.

[0046] During a write operation, the voltage applied by the WRITE WL circuit turns on the write transistor 114, allowing current to flow between the bit line BL and the source line circuit SL through the spin orbit torque layer 1406, as indicated by the dashed line 1416. In the write state, the read select transistor is switched to the off state. As described above, the flow of current results in spin polarization of electrons on the top and bottom surfaces of the spin orbit torque layer 1406. This spin polarization can be used to apply a spin orbit torque to the free layer 1410 of the memory element 1408, selectively setting the magnetization of the magnetic free layer 1410 in a desired direction. The direction of magnetization of the magnetic free layer 1410 can be switched to one of two directions depending on the direction of current flow through the spin orbit torque layer 1406. As described above, when the magnetization of the free layer 1410 is set in one direction, the magnetic memory element 1408 becomes a high resistance state, and when set in the opposite direction, the magnetic memory element 1410 becomes a low resistance state. In this way, the memory element reliably records a data bit according to its resistance state.

[0047] In the read mode, the write selector transistor 114 is switched to the off state, the read selector transistor 116 is switched to the on state, and an electrical connection between the bit line BL and the memory element 1408 becomes possible. The read selector transistor 116 is controlled by a read word line circuit (READ WL) that can selectively apply a gate voltage to the read selector transistor 116. When the switch of the read selector transistor 116 is turned on, a voltage can be applied to the magnetic memory element 1408 between the bit line BL and the source line SL, and using this, the resistance state of the magnetic memory element can be determined.

[0048] FIG. 15 is a diagram showing a spin-orbit torque MRAM according to an alternative embodiment. The embodiment of FIG. 15 is the same as that described above, except that the spin-orbit torque layer 1406 is in contact with the source layer 604 instead of overlapping the source line layer 604. This can be achieved by etching the source line layer 604 to deposit a conductive spin-orbit torque layer and then performing a chemical mechanical polishing process to planarize the structure before forming the selector transistor 114 and the magnetic memory element 1408. In this embodiment, during the write operation, current flows from the source line layer 604 to the spin-orbit torque layer and then to the source line circuit SL, as indicated by arrow 1502.

[0049] Although various embodiments have been described above, it should be understood that these are presented only by way of example and are not limiting. Other embodiments that fall within the scope of the present invention will also be apparent to those skilled in the art. Therefore, the breadth and scope of the present invention should not be limited by any of the above exemplary embodiments, but should be defined only based on the following claims and their equivalents.

Claims

1. A data recording device, comprising: a magnetic memory element having a magnetic free layer; a conductive spin-orbit torque layer formed on a semiconductor substrate and insulated from the semiconductor substrate by a dielectric layer, wherein the magnetic memory element is formed directly adjacent to the spin-orbit torque layer and on the spin-orbit torque layer, the spin-orbit torque layer; a conductive source line layer formed on or within the semiconductor substrate, wherein the spin-orbit torque layer overlaps a part of the source line layer, and the source line layer is electrically connected to the spin-orbit torque layer by the part overlapping the spin-orbit torque layer, the source line layer; a vertical transistor structure formed on the source line layer and electrically connected to the source line layer, the vertical transistor structure being configured to selectively supply current to the spin-orbit torque layer; A data recording device comprising the above.

2. The vertical transistor structure further comprises: a semiconductor pillar; a gate dielectric layer surrounding the semiconductor pillar; a conductive gate layer adjacent to the gate dielectric layer such that the gate dielectric layer separates the semiconductor pillar from the conductive gate layer, the conductive gate layer; The data recording device according to claim 1, further comprising the above.

3. The data recording device according to claim 2, wherein the semiconductor pillar has first and second doped ends.

4. The data recording device according to claim 2, wherein the semiconductor pillar has first and second n+ doped portions.

5. The data recording device according to claim 2, wherein the semiconductor pillar comprises an epitaxially grown semiconductor material.

6. The data recording device according to claim 2, wherein the semiconductor pillar comprises a substantially single-crystal semiconductor material.

7. The vertical transistor structure is a write selector transistor, The data recording device according to claim 1, further comprising a read selector transistor electrically connected to the magnetic memory element.

8. The data recording device according to claim 7, wherein the read selector transistor is connected to the magnetic memory element at an end opposite to the spin-orbit torque layer.

9. The data recording device according to claim 1, wherein the magnetic memory element is a magnetic tunnel junction element.

10. Further comprising a conductive bit line electrically connected to the read selector transistor and the write selector transistor, The data recording apparatus according to claim 7, wherein the spin orbit torque layer is electrically connected to the magnetic memory element.

11. The data recording apparatus according to claim 10, further comprising a write word line circuit electrically connected to the conductive gate layer of the vertical transistor structure.

12. The data recording apparatus according to claim 1, wherein the spin orbit torque layer comprises one or more of β-phase tungsten and β-phase tantalum.

13. A data recording apparatus, A semiconductor substrate, A source line layer formed on the semiconductor substrate, A vertical transistor structure formed on the source line layer, directly and electrically connected to the source line layer formed on the semiconductor substrate, A spin orbit torque layer formed on the semiconductor substrate adjacent to the source line layer, establishing a direct and electrical connection with the source line layer in the semiconductor substrate, Comprising a magnetic memory element formed on the spin orbit torque layer, A data recording apparatus.

14. The data recording apparatus according to claim 13, wherein the magnetic memory element is a magnetic tunnel junction element.

15. The magnetic memory element is a magnetic tunnel junction element including a magnetic free layer, The data recording apparatus according to claim 13, wherein the magnetic free layer is adjacent to the spin orbit torque layer.

16. The data recording apparatus according to claim 13, wherein the spin orbit torque layer comprises one or more of β-phase tungsten and β-phase tantalum.

17. The vertical transistor structure further comprises A semiconductor pillar having an upper doped region and a lower doped region, A gate dielectric layer formed on a side surface of the semiconductor pillar, A gate structure, wherein the gate dielectric layer is formed to separate the gate structure from the semiconductor pillar, Comprising The data recording apparatus according to claim 13.

18. The gate dielectric layer surrounds the semiconductor pillar, The data recording apparatus according to claim 17, wherein the gate structure further comprises a conductive layer positioned between the first and second dielectric layers.

19. The data recording apparatus according to claim 18, further comprising a write word line circuit electrically connected to the conductive layer of the gate structure.

20. A read transistor, a conductive bit line electrically connected to the vertical transistor structure and the read transistor and further comprising the data recording apparatus according to claim 19.

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