Method for manufacturing a wiring board

Abstract

To provide a method for manufacturing a wiring board in which a highly accurate MIM capacitor is formed on a glass substrate, and a wiring board.SOLUTION: A method for manufacturing a wiring board includes: a step A of forming a laser modification part by irradiating a laser beam from a first surface of a glass substrate toward the other surface; a step B of forming an MIM capacitor on the first surface of the glass substrate; a step C of forming a through hole in the laser modification part and forming a second surface facing the first surface of the glass substrate by subjecting a surface on the opposite side of the first surface to etching processing; and a step D of forming a through electrode in the through hole and forming a second surface wiring layer connected to ta first surface wiring layer on the second surface via the through electrode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to the manufacture of wiring boards. Method

Background Art

[0002] With the increasing functionality and miniaturization of electronic devices, the demand for higher density of wiring boards constituting semiconductor devices is growing. Among them, along with the miniaturization of circuit wiring, passive components such as resistors, capacitors, and inductors are also required to be further miniaturized. The requirement for further miniaturization is extremely high, and there is already a limit with only the miniaturization of these passive components and their high-density mounting on the substrate surface.

[0003] As a technology effective for increasing the density of wiring boards, as shown in Patent Document 1, forming a parallel-plate capacitor with a MIM (Metal-Insulator-Metal) structure on a circuit board can be mentioned. The MIM structure is a structure in which thin films of metal and dielectric are alternately laminated. A capacitor with a MIM structure (hereinafter referred to as a MIM capacitor) has a thin structure compared to a discrete-component capacitor, and also has the characteristics of small parasitic inductance and equivalent series resistance. Therefore, it has advantages such as being able to ensure high power supply stabilization performance and realizing a highly accurate LC circuit with high density.

[0004] On the other hand, as a substrate material, generally an organic material typified by glass epoxy resin is used. However, in recent years, with the progress of glass drilling technology, for example, it has become possible to form through-holes with a diameter of 100 μm or less at a pitch of 150 μm or less in a 300-μm-thick glass. For this reason, electronic circuit boards using glass materials have attracted attention. A circuit board using a glass material as a core (hereinafter referred to as a glass circuit board) has a low linear thermal expansion coefficient (CTE) of glass of 2 ppm to 8 ppm, which is compatible with a silicon chip, so it has high mounting reliability, and furthermore, due to its excellent flatness, high-precision mounting becomes possible.

[0005] ​In addition, because glass has excellent flatness, it also has excellent fine wiring formation properties and high-speed transmission properties. Furthermore, research has been conducted on the application of glass to electronic circuit boards by taking advantage of its transparency, chemical stability, high elasticity, and low cost, and productization of products such as interposers for semiconductor devices, circuit boards for imaging devices, and LC duplexers for communication equipment is expected. Since it is necessary to form decoupling capacitors, LC circuits, etc. in these electronic circuits with glass as the core, the demand for incorporating capacitors has been increasing.

[0006] Patent Document 2 discloses a technique of forming a MIM capacitor in the vicinity of a through hole after forming the through hole in a glass substrate.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] However, according to the study results of the present inventors, it has been found that forming a MIM capacitor in the vicinity of a through hole formed in a substrate may cause deterioration of the capacitor performance. The reason will be explained below.

[0009] FIG. 1 is a diagram showing a part of a process of forming a MIM capacitor in the vicinity of a through hole according to the prior art. Hereinafter, the manufacturing process of the prior art will be described. First, a through hole 2 is formed in a substrate 1, and a conductive layer 3 is formed on both surfaces of the substrate 1 and inside the through hole 2. Next, on one surface of the substrate 1, a dielectric layer 4 and a sputter seed layer 5 are formed on the conductive layer 3, and a dry film resist 6 is laminated on both surfaces of the substrate 1.

[0010] Part of the laminated dry film resist 6 enters the through hole 2 as shown in FIG. 1(a). At this time, the air in the through hole 2 may move to the surface side of the substrate 1. As a result, phenomena such as bubbles BB accumulating on the lower surface of the dry film resist 6 or the surface of the dry film resist 6 becoming wavy may occur. When patterning is performed as shown in FIG. 1(b) thereafter, the shape of the dry film resist 6 may collapse and partial defects MS may occur.

[0011] When plating treatment is performed on the substrate 1 having the dry film resist 6 with such defects MS, as shown in FIG. 1(c), plating is deposited at the location where the dry film resist 6 is missing. Thereafter, when the dry film resist 6 is removed, as shown in FIG. 1(d), the shape of the upper electrode 7 formed by the deposited plating becomes different from the designed shape. The MIM capacitor formed by such an upper electrode 7, the dielectric layer 4, and the conductive layer 3 may not be able to achieve the designed capacitance.

[0012] The present invention has been made in view of the above-described problems, and aims to provide a method for manufacturing a wiring board in which a high-precision MIM capacitor is formed on a glass substrate. Method for the purpose of providing.

Means for Solving the Problems

[0013] In order to achieve the above object, one of the typical manufacturing methods of the wiring board of the present invention is a step A of irradiating a laser beam from one surface of the glass substrate toward the other surface to form a laser-modified portion, Increasing the intensity of the laser beam and irradiating the first surface of the glass substrate to visibly form an alignment mark for pattern drawing a step B of forming a first surface wiring layer including an MIM capacitor on the first surface of the glass substrate, a step of bonding a glass carrier on the first surface wiring layer, on the surface opposite to the first surface, Hydrogen fluoride solutionBy performing an etching process using the above, a through hole is formed in the laser modified portion, and the glass substrate is thinned to form a second surface parallel to the first surface in step C. In step D, a through electrode is formed in the through hole, and a second surface wiring layer connected to the first surface wiring layer through the through electrode is formed on the second surface. It is achieved by having a step of removing the glass carrier from the first surface wiring layer.

Advantages of the Invention

[0015] According to the present invention, it is possible to provide a method for manufacturing a wiring substrate in which a high-precision MIM capacitor is formed on a glass substrate. Method It can be provided. Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

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Figure 7

Figure 8

BEST MODE FOR CARRYING OUT THE INVENTION

[0017] In the present disclosure, the "surface" may refer not only to the surface of a plate-like member but also to the interface of a layer substantially parallel to the surface of the plate-like member with respect to the layers included in the plate-like member. Further, the "upper surface" and "lower surface" mean the surface shown above or below in the drawing when the plate-like member or the layers included in the plate-like member are illustrated. Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited by this embodiment. In the description of the drawings, the same reference numerals are given to the same parts.

[0018] FIG. 2 is a diagram showing each step of the method for manufacturing a wiring board according to the present embodiment. Hereinafter, the method for manufacturing a wiring board according to the present embodiment will be described.

[0019] (Step 1) An alkali-free glass having a thickness of 500 μm is prepared, and contaminants on the surface are removed by ultrasonic cleaning or the like to obtain a glass substrate 11. Thereafter, the glass substrate 11 is irradiated with laser light from the first surface 11a side to form a laser modified portion 12 serving as a starting point of a through hole. The laser modified portion 12 extends downward from the first surface 11a, for example, in a vertical direction, and is formed such that the lower end remains within the glass substrate 11. In the present embodiment, the step of irradiating laser light from one surface of the glass substrate toward the other surface to form a laser modified portion is referred to as Step A. Step A corresponds to Step 1 described above, but the disclosure of Step 1 does not limit Step A.

[0020] At this time, for example, by changing the output of the laser or the like, increasing the intensity of the laser beam, irradiating the first surface 11a, deforming the glass surface into a concave or convex shape, and forming a visible alignment mark AM. By performing the alignment mark AM in the same process as the formation of the laser modification portion 12, man-hour reduction can be achieved.

[0021] (Step 2) Next, a hydrofluoric acid-resistant metal film 13 is formed on the first surface 11a of the glass substrate 11 by a sputtering method or the like in a range of 10 nm or more and 500 nm or less. Thereafter, a copper film 14 is formed on the hydrofluoric acid-resistant metal film 13 in a range of 100 nm or more and 500 nm or less by a sputtering method and an electroless plating method or the like. Thereby, a seed layer is formed on the first surface 11a of the glass substrate 11. The material of the hydrofluoric acid-resistant metal film 13 is appropriately selected from, for example, chromium, nickel, and nickel chromium.

[0022] (Step 3) Next, a photoresist for the pattern is formed. Specifically, using a dry photoresist (product name RD1225) manufactured by Showa Denko Materials Co., Ltd., laminating on the first surface 11a side, positioning by, for example, the alignment mark AM, drawing the pattern, and then developing to expose the seed layer. Further, power is supplied to the seed layer, and electrolytic copper plating with a thickness of 2 μm or more and 10 μm or less is performed to form the lower electrode 15. After plating, the unnecessary dry film resist is dissolved and peeled off. By using the alignment mark AM, the positioning of the lower electrode 15 can be accurately performed.

[0023] (Step 4) Next, a dielectric film 16 is formed on the lower electrode 15. As the formation of the dielectric film 16, for example, there is a method of forming SiN, SiO2, TaOx, etc. by plasma CVD, but it is not limited thereto.

[0024] (Step 5) Next, an upper electrode 17 is formed on the dielectric film 16. On the dielectric film 16, a copper film (Cu, Ti / Cu, etc.) is formed in a range of 100 nm or more and 500 nm or less by a sputtering method, an electroless plating method, or the like, and as shown in Fig. 2(a), lamination is performed on the first surface 11a side using a dry photoresist 18.

[0025] Thereafter, for example, after positioning by an alignment mark AM, drawing a pattern, and developing, a seed layer is exposed, power is supplied to the seed layer, and as shown in Fig. 2(b), electrolytic copper plating with a thickness of 2 μm or more and 10 μm or less is performed.

[0026] At this time, since no through holes are formed in the glass substrate 11, air does not accumulate on the lower surface of the dry photoresist 18 as in the prior art during the lamination of the dry photoresist 18, and a highly accurate shape of the plating after patterning can be ensured.

[0027] Furthermore, the unnecessary dry photoresist 18 after plating is dissolved and removed, and as shown in Fig. 2(c), a first surface wiring layer 19 including an MIM capacitor is formed. At this time, etching treatment is performed on the upper electrode 17, the dielectric film 16, the lower electrode 15, and the fluorine-resistant metal film 13.

[0028] Fig. 3 shows an example of the first surface 11a of the glass substrate 11 on which the first surface wiring layer 19 is formed in a plan view. In addition to the upper electrode 17, a copper layer 25 for wiring is formed on the first surface 11a. In the present embodiment, the step of forming a first surface wiring layer including an MIM capacitor on the first surface of the glass substrate is referred to as step B. Step B corresponds to steps 3 to 5 described above, but the disclosed content of steps 3 to 5 does not limit step B. However, step A may be performed after step B. In that case, the laser light is irradiated from the surface 11b side of the glass substrate 11.

[0029] Here, Cu can be removed by wet etching, the dielectric can be removed by dry etching, and Ti can be removed by both dry etching and wet etching. Further, the hydrofluoric acid-resistant metal film 13 can also be removed by wet etching corresponding to the metal film. The MIM capacitor is constituted by the upper electrode 17, the dielectric film 16, and the lower electrode 15.

[0030] (Step 7) Next, an insulating resin 24 (product name: ABF - GXT31) manufactured by Ajinomoto Fine - Techno Co., Inc. is laminated on the first - side wiring layer 19 with a thickness of 32.5 μm.

[0031] (Step 8) Next, a glass carrier 20 is attached onto the insulating resin 24. Specifically, the glass carrier 20 is bonded onto the first - side wiring layer 19 via an adhesive for temporary bonding (product name: Rebond Alpha, manufactured by Nitto Denko Corporation). Considering the transportability after thinning, the thickness of the glass carrier 20 is preferably in the range of 0.7 mm or more and 1.5 mm or less. The thickness of the glass carrier 20 may be appropriately set according to the thickness of the glass substrate 11. Also, although a glass carrier is exemplified as the support, the support may not be made of glass and may be made of metal, resin, or the like.

[0032] (Step 9) Next, an etching process is performed on the surface 11b of the glass substrate 11 on the side opposite to the first surface 11a with a hydrogen fluoride solution. The glass in the portion where the laser - modified portion 12 is not formed is etched by the hydrogen fluoride solution and thinned parallel to the first surface 11a of the glass substrate 11 as shown in Fig. 2(d). Thereby, the wiring substrate can be thinned and miniaturized. By using a hydrogen fluoride solution as the etching process, the processing damage to the MIM capacitor can be suppressed. In this embodiment, the step of forming a through - hole in the laser - modified portion and forming a second surface facing the first surface of the glass substrate by etching the surface opposite to the first surface is referred to as Step C. Step C corresponds to Step 9 described above, but the disclosure of Step 9 does not limit Step C.

[0033] When the hydrogen fluoride solution contacts the laser modification portion 12, the laser modification portion 12 is preferentially dissolved, and a through-hole 21 having a truncated cone shape is formed. As a result, the glass substrate 11 becomes thinner as the through-hole 21 is formed. That is, since the thinning and the formation of the through-hole 21 are performed in one etching process, the influence on the MIM capacitor can be minimized. The lower surface of the thinned glass substrate 11 becomes the second surface 11b'. The through-hole 21 has a truncated cone shape in which the diameter (or cross-sectional area) on the second surface 11b' side is larger than the diameter (or cross-sectional area) on the first surface 11a side. Preferably, the diameter of the through-hole 21 on the second surface 11b' side is 1.2 times or more and 4.0 times or less the diameter on the first surface 11a side. Such a magnification can be changed by adjusting the depth of the laser modification portion 12.

[0034] The etching amount by the hydrogen fluoride solution may be appropriately set according to the thickness of the glass device. For example, when the thickness of the glass substrate 11 used in Step 1 is 400 μm, the etching amount is desirably in the range of 100 μm or more and 350 μm or less. The thickness of the thinned glass substrate 11 is preferably 50 μm or more and 300 μm or less.

[0035] (Step 10) Next, as shown in FIG. 2(e), a copper film or the like is formed in the through-hole 21 in the range of 100 nm or more and 500 nm or less on the second surface 11b' of the glass substrate 11 by sputtering, electroless plating, or the like. Thereby, a seed layer is formed on the second surface 11b' side of the glass substrate 11.

[0036] (Step 11) Next, in the same manner as in Step 3, a pattern is formed with a dry film resist, power is supplied to the seed layer, electrolytic plating with a thickness of 2 μm or more and 10 μm or less is performed, and then the unnecessary dry film resist is dissolved and peeled off to form a through electrode 22 in the through-hole 21. Then, the unnecessary seed layer is removed, and an outer layer protective film such as an insulating resin or a solder resist is coated to form a second surface wiring layer 23. In this embodiment, the step of forming a through electrode in the through hole and forming a second surface wiring layer connected to the first surface wiring layer through the through electrode on the second surface is referred to as step D. Step D corresponds to steps 10 and 11 described above, but the disclosed content of steps 10 and 11 does not limit step D.

[0037] (Step 12) Thereafter, the glass carrier 20 temporarily adhered in step 8 is removed from the glass substrate 11.

[0038] (Step 13) Furthermore, a wiring layer is laminated on the first surface wiring layer 19. At this time, for example, as described in Japanese Patent Application Laid-Open No. 2021-7127, an inductor (coil) can be formed using the through electrode 22, and a thin LC circuit can be formed by combining this inductor with a MIM capacitor. However, the shape of the inductor is not limited, such as solenoid or spiral.

[0039] FIG. 4(a) is a plan view showing an example in which the through hole 2 and the MIM capacitor are formed on the glass substrate in this order by the manufacturing process of FIG. 1. FIG. 4(b) is a plan view showing an example in which the MIM capacitor and the through hole 21 are formed on the glass substrate in this order by the manufacturing process of FIG. 2.

[0040] In the example shown in FIG. 4(a), an abnormal shape is observed in the upper electrode 7 of the MIM capacitor. This is because the dry film resist used when forming the upper electrode 7 is distorted by the bubbles BB (FIG. 1). On the other hand, in the present embodiment shown in FIG. 4(b), the upper electrode 17 of the MIM capacitor, which is rectangular as designed, can be accurately formed without distorting the dry film resist.

[0041] Furthermore, according to the present embodiment, since patterning and the like are performed using the alignment mark AM, the position and shape of the lower electrode 15 and the like constituting the MIM capacitor can be accurately determined. Thereby, variations in the characteristics of the MIM capacitor can be suppressed.

[0042] Also, according to the present embodiment, since the diameter of the through hole 21 on the first surface 11a side is smaller than the diameter on the second surface 11b' side, the area of the wiring and the lower electrode 15 can be secured in the vacant space, ensuring the capacitance of the MIM capacitor, improving the characteristic variations, and reducing the size of the wiring board.

[0043] Furthermore, according to the present embodiment, since the glass carrier 20 is attached to the first surface wiring layer 19 and the etching process is performed, highly accurate processing can be carried out despite the thinness of the glass substrate 11. Also, after the etching process, by removing the glass carrier 20, a low-profile wiring board can be realized.

[0044] (Comparison with Comparative Examples) FIG. 5 is a cross-sectional view of a multilayer wiring board (Example 1) formed using the wiring board of the present embodiment. FIG. 6 is a cross-sectional view of a multilayer wiring board (Comparative Example 1) in which a through hole 21 is formed on the first surface 11a of the glass substrate 11 and then a MIM capacitor is formed on the first surface 11a. FIG. 7 is a cross-sectional view of a multilayer wiring board (Comparative Example 2) in which a through hole 21 is formed on the second surface 11b' of the glass substrate 11 and then a MIM capacitor is formed on the second surface 11b'.

[0045] The inventors conducted a comparative test on the capacitor characteristics and miniaturization for Example 1 and Comparative Examples 1 and 2. The results are shown in Table 1.

[0046]

Table 1

[0047] FIG. 8 is a graph showing the capacitance variation of the capacitor for Example 1 and Comparative Examples 1 and 2. According to FIG. 8, it can be seen that the capacitance variation of the capacitor occurs in Comparative Examples 1 and 2, while the capacitance variation of the capacitor is suppressed in Example 1.

[0048] In Table 1, regarding the capacitor characteristics, if the designed capacitance was satisfied, it was rated as good (〇), and if the designed capacitance was not met, it was rated as bad (×). Also, regarding miniaturization, if the maximum thickness was 0.2 mm or less, it was rated as good (〇), if the maximum thickness exceeded 0.2 mm and was 0.4 mm or less, it was rated as fair (△), and if the maximum thickness exceeded 0.4 mm, it was rated as bad (×).

[0049] As shown in Table 1, for Comparative Example 1, both the capacitor characteristics and miniaturization were rated as bad (×). Also, for Comparative Example 2, the capacitor characteristics were rated as bad (×), and the miniaturization was rated as fair (△). In contrast, for Example 1, both the capacitor characteristics and miniaturization were rated as good (〇), confirming the effectiveness of the present invention.

Explanation of Reference Signs

[0050] 11…Glass substrate 12…Laser modification part 13…Fluoride-resistant metal film 14…Copper film 15…Lower electrode 16…Dielectric film 17…Upper electrode 18…Dry photoresist 19…First-side wiring layer 20…Glass carrier 21…Through hole 22…Through electrode 23…Second-side wiring layer 25…Copper layer for wiring

Claims

1. Step A of irradiating a laser beam from one surface of a glass substrate toward the other surface to form a laser-modified portion; A step of increasing the intensity of the laser beam and irradiating the one surface of the glass substrate to visibly form an alignment mark for pattern drawing; Step B of forming a first-surface wiring layer including an MIM capacitor on the one surface of the glass substrate; A step of bonding a glass carrier onto the first-surface wiring layer; Step C of forming a through hole in the laser-modified portion and thinning the glass substrate to form a second surface parallel to the one surface by performing an etching process using a hydrogen fluoride solution on the surface opposite to the one surface; Step D of forming a through electrode in the through hole and forming a second-surface wiring layer connected to the first-surface wiring layer via the through electrode on the second surface; And a step of removing the glass carrier from the first-surface wiring layer. A method for manufacturing a wiring substrate, characterized by the above.

2. The step B is performed after the step A. A method for manufacturing a wiring substrate according to claim 1, characterized by the above.

3. The step A is performed after the step B. A method for manufacturing a wiring substrate according to claim 1, characterized by the above.

4. The diameter of the through hole on the second-surface side is larger than the diameter on the first-surface side. A method for manufacturing a wiring substrate according to any one of claims 1 to 3, characterized by the above.

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