Semiconductor device

Abstract

To improve the performance of a semiconductor device with a main MOSFET and a sense MOSFET having a double gate structure including a gate electrode and a field plate electrode in a trench.SOLUTION: A sense MOSFET 1SQ is formed at a position surrounded by a main MOSFET 1MQ and a source pad SP connected to the source region of the main MOSFET 1MQ in plan view. To the source region of the sense MOSFET 1SQ, the source potential is supplied through wiring SSW surrounded by the source pad SP in plan view, a field plate electrode formed together with the gate electrode in a trench D2, and wiring SW1 and SW2 formed outside the source pad SP.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a main MOSFET and a small-scale MOSFET for current detection.

Background Art

[0002] In a power MOSFET that requires high breakdown voltage, it may be required to accurately monitor the current value flowing through the device for the purpose of monitoring or controlling the internal state. As a structure for measuring the current value of the main MOSFET mounted on a semiconductor chip, it is known to mount a small-scale sense MOSFET for current detection on the semiconductor chip (hereinafter sometimes simply referred to as a chip).

[0003] Also, Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2013-12669) describes a structure in which a sense MOSFET is disposed at the center of a chip, and the source electrode of the sense MOSFET is drawn out by wiring formed on the surface of the chip.

[0004] Also, Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2020-92176) describes a structure in which a sense MOSFET is disposed at the center of a chip, and the source electrode of the sense MOSFET is routed inside a package having multilayer wiring and electrically taken out to the outside.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a reliability test that applies a thermal load to a semiconductor chip, since die bond cracks progress from the outer periphery of the chip, if there is a sense MOSFET near the outer periphery of the chip, the crack may progress to directly under the sense MOSFET, and the current sense ratio (hereinafter sometimes simply referred to as the sense ratio) may vary significantly. Therefore, it is desirable that the sense MOSFET be arranged at the center of the chip.

[0007] Therefore, it is conceivable to arrange the sense MOSFET at the center of the chip and use multilayer wiring on the semiconductor substrate to draw out the source pad of the sense MOSFET to a position different from that of the source pad of the main MOSFET. However, in this case, since it requires an increase in the manufacturing process of the semiconductor device and the mask for patterning, the manufacturing cost of the semiconductor device increases.

[0008] Also, in Patent Document 1, since the source pad (surface electrode, source electrode) of the main MOSFET is divided in the extraction region of the sense MOSFET, the shape of the source pad of the main MOSFET is distorted and the area of the source pad is reduced. Therefore, there are problems such as a decrease in the chip performance of the main MOSFET and the occurrence of restrictions on the bonding layout.

[0009] Also, in Patent Document 2, the above problems regarding the shape and area of the source electrode of the main MOSFET are improved. However, since it is necessary to use a multilayer wiring substrate, there is a problem that the manufacturing and material costs related to the package increase. Also, using a multilayer wiring substrate causes a problem that the size of the semiconductor device increases.

[0010] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0011] Among the embodiments disclosed in the present application, the outline of a representative one will be briefly described as follows.

[0012] In one embodiment, a semiconductor device forms a sense MOSFET at a position surrounded by a main MOSFET and a source pad connected to the source region of the main MOSFET in a plan view. Here, for the source region of the sense MOSFET, a source potential is supplied via a wiring surrounded by the source pad in a plan view, a field plate electrode formed together with a gate electrode in a trench, and a wiring formed outside the source pad.

Advantages of the Invention

[0013] According to one embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0014]

Figure 1

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Embodiments for Carrying Out the Invention

[0015] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a partial or entire modification, detail, supplementary explanation, etc. of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to the mentioned number, and it may be more or less than the mentioned number.

[0016] Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified and unless it is considered clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly not the case in principle, it includes those that are substantially approximate or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0017] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Also, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary.

[0018] In each of the following plan views (plane layouts) used in the description below, for ease of understanding the figures, hatching is applied to the contact plugs.

[0019] Here, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, MOS type field effect transistor) will be described as an example of the semiconductor device of the present application. A power MOSFET is a semiconductor device that can handle power of several watts or more. The semiconductor device of the present application has a trench gate power MOSFET among power MOSFETs. A trench gate power MOSFET has a gate electrode made of polysilicon or the like in a trench (a relatively long and narrow groove) formed on the upper surface (first main surface) of a semiconductor substrate, and a channel is formed in the thickness direction of the semiconductor substrate. In this case, usually, the upper surface side of the semiconductor substrate serves as the source, and the lower surface (back surface, second main surface) side serves as the drain.

[0020] Further, the semiconductor device of the present application has a double gate type power MOSFET in a trench among trench gate power MOSFETs. A double gate type power MOSFET in a trench has a field plate electrode below a gate electrode (intrinsic gate electrode) in the trench. The field plate electrode is an electrode that has the function of dispersing a steep potential gradient concentrated near the drain side end of the gate electrode and keeping the electric field constant, and is electrically connected to the source electrode. By keeping the electric field near the field plate electrode constant, the breakdown voltage of the element can be ensured.

[0021] (Embodiment 1) <Structure of Semiconductor Device> Hereinafter, the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 6.

[0022] As shown in FIG. 1, the semiconductor device of this embodiment is a semiconductor chip CHP1 provided with a semiconductor substrate. The semiconductor chip CHP1 has a main MOSFET 1MQ and a sense MOSFET 1SQ. FIG. 2 shows a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 shows a cross-sectional view taken along line B-B of FIG. 1. FIG. 4 shows a cross-sectional view taken along line C-C of FIG. 1. The semiconductor substrate has an upper surface (first main surface) and a lower surface (second main surface) opposite to the upper surface. In FIG. 1, the structure under the wiring formed on the upper surface of the semiconductor substrate is shown in a transmissive manner, and the illustration of insulating films such as the interlayer insulating film and the passivation film on the semiconductor substrate is omitted.

[0023] As shown in FIG. 2, the semiconductor substrate constituting the semiconductor device of this embodiment has a substrate SB made of, for example, single-crystalline Si (silicon) and a drift layer DF which is a semiconductor layer formed on the substrate SB by an epitaxial growth method or the like. The substrate SB constitutes an n + -type drain region DR. Although not shown, the lower surface of the substrate SB is covered with a drain electrode containing, for example, Au (gold), and the drain region DR is connected to the drain electrode. The drift layer DF is an n - -type semiconductor layer.

[0024] As shown in FIG. 1, on the upper surface of the semiconductor substrate, a plurality of trenches D2 and trenches D1 extending in the Y direction are formed side by side in the X direction. Specifically, two groups of trenches D1 arranged side by side in the X direction are formed side by side in the X direction, and between these two groups of trenches D1, a plurality of trenches D2 are formed side by side in the X direction. The main MOSFET 1MQ is formed in the vicinity of the trench D1. In the vicinity of the trench D2, the main MOSFET 1MQ, the sense MOSFET 1SQ, and the main MOSFET 1MQ are formed in order in the Y direction.

[0025] That is, a main MOSFET is formed around the sense MOSFET 1SQ. That is, the sense MOSFET 1SQ is located at the center of the semiconductor chip CHP1 in a plan view. The Y direction and the X direction are directions along the upper surface of the semiconductor substrate, respectively, and are directions orthogonal to each other in a plan view. Further, the Z direction orthogonal to each of the Y direction and the X direction is a height direction (thickness direction, vertical direction, longitudinal direction) perpendicular to the upper surface of the semiconductor substrate.

[0026] Further, a trench D3 is formed on the upper surface of the semiconductor substrate to surround, in a plan view, the periphery of the active region where the sense MOSFET 1SQ and the main MOSFET 1MQ are formed. As shown in FIG. 4, a conductive film CL is embedded in the trench D3 via an insulating film IF1, and this trench D1, insulating film IF1, and conductive film CL constitute a termination ring TR. The periphery of the active region is surrounded by an annular termination ring TR in a plan view (see FIG. 1). Although not shown here, a seal ring having the same structure as the termination ring TR may be formed in the vicinity of the peripheral edge of the semiconductor chip CHP1 so as to surround the periphery of the termination ring TR on the upper surface of the semiconductor substrate at the peripheral edge of the semiconductor chip CHP1. The active region includes a region 1A having an annular shape in a plan view where the main MOSFET is formed, and a region 1B surrounded by the annular region 1A where the sense MOSFET 1SQ is formed. In a plan view, the trench D3 surrounds the regions 1A, 1B, trenches D1 and D2.

[0027] As shown in FIGS. 2 to 4, inside each of the trenches D1 and D2, a gate wiring GW and a field plate electrode FP under the gate wiring GW are embedded via an insulating film IF1. Thus, the structure in which two electrodes are formed in the trench is herein referred to as a double gate structure (double gate type). In the active region, on the upper surface of the semiconductor substrate (the upper surface of the drift layer DF), a body layer PB which is a p-type semiconductor layer is formed in contact with the side surfaces of the trenches D1 and D2, respectively. The depth of the body layer PB is shallower than, for example, the depth of any of the trenches D1 and D2 and the gate electrode GE.

[0028] Also, in each of the regions 1A and 1B which are active regions, on the upper surface of the semiconductor substrate (the upper surface of the drift layer DF), an n + -type semiconductor region (n + diffusion layer), that is, a source region SR is formed in contact with the side surfaces of the trenches D1 and D2, respectively. That is, the source region SR is in contact with the upper surface of the semiconductor substrate. The depth of the source region SR is shallower than the depth of any of the body layer PB and the gate electrode GE. The lower surface of the source region SR is in contact with the body layer PB, and the lower surface of the body layer PB is in contact with the drift layer DF.

[0029] The source region SR, drain region DR, body layer PB, and gate electrode GE in the region 1A constitute an n-type main MOSFET 1MQ which is a vertical MOSFET. The source region SR, drain region DR, body layer PB, and gate electrode GE in the region 1B constitute an n-type sense MOSFET 1SQ which is a vertical MOSFET. Note that, among the gate electrodes GE in the trench D2, the gate electrode GE located in the region 1A outside the region 1B in the Y direction constitutes the main MOSFET 1MQ instead of the sense MOSFET 1SQ.

[0030] FIG. 5 is a plan layout showing an enlarged view of the vicinity of the formation region of the sense MOSFET 1SQ. In FIG. 5, the region where the source region SR of the sense MOSFET 1SQ is formed is shown with hatching, and the illustration of pads and wirings on the semiconductor substrate is omitted. As shown in FIG. 5, the formation region of the source region SR constituting the sense MOSFET 1SQ is surrounded by the formation region of the body layer PB in a plan view. That is, the source region SR of the sense MOSFET 1SQ formed between adjacent trenches D2 in the X direction is continuously covered by the body layer PB on both side surfaces and the bottom surface in the Y direction. Further, the side surfaces in the X direction of the source region SR of the sense MOSFET 1SQ are covered by the insulating film IF1 or the contact plug C4 in the trench D2. Therefore, the source region SR constituting the sense MOSFET 1SQ and the source region SR (not shown) constituting the main MOSFET 1MQ are separated from each other by the body layer PB.

[0031] As shown in FIGS. 1 to 4, on each of the semiconductor substrate, the gate electrode GE, the insulating film IF1, and the conductive film CL, a metal film (conductive film, source wiring) constituting the source pad SP, the wirings SSW, SW1, SW2, and the gate wiring GW are formed via the interlayer insulating film IL. The interlayer insulating film IL is mainly made of, for example, silicon oxide. The metal film (conductive film, source wiring) constituting the source pad SP, the wirings SSW, SW1, SW2, and the gate wiring GW are made of, for example, Al (aluminum), are located at the same height, and are spaced apart from each other.

[0032] A plurality of openings (through holes) are formed in the interlayer insulating film IL. In these openings, contact plugs (conductive connection portions) integrated with the metal film (source wiring) constituting the source pad SP, the wirings SSW, SW1, SW2, or the gate wiring GW are formed. Each contact plug extends along the extending direction (Y direction) of the trenches D1 and D2. Hereinafter, the source pad SP strictly refers to the portion of the upper surface of the metal film (source wiring) that is exposed from an insulating film (not shown) such as a passivation film, but hereinafter, the metal film is referred to as the source pad SP.

[0033] Specifically, the source pad SP is formed in region 1A and has an annular structure in plan view. The source pad SP is electrically connected to the source region SR and the body layer PB via the contact plug C1. The contact plug C1 reaches the middle depth of the body layer PB, which is a position deeper than the source region SR, and is in contact with the source region SR. In order to reduce the connection resistance between the contact plug C1 and the body layer PB, a p-type semiconductor region with a higher concentration than the body layer PB may be formed in the semiconductor substrate therebetween.

[0034] The gate wiring GW is formed adjacent to the outside of the source pad SP in the Y direction and extends in the X direction. A part of the gate wiring GW and another part thereof are arranged so as to sandwich the source pad SP in the Y direction. The gate wiring GW is electrically connected to the gate electrodes GE inside the trenches D1 and D2 via the contact plug C2. A part of the upper surface of the gate wiring GW constitutes the gate pad GP, and the gate potential is supplied to the gate electrode GE via the gate pad GP, the gate wiring GW, and the contact plug C2.

[0035] The source pad SP is electrically connected to the field plate electrode FP inside the trench D1 via the contact plug C3. That is, the field plate electrode FP inside the trench D1, which is separated from the region 1B in plan view, is electrically connected to the source pad SP. The contact plug C3 is formed in the region 1C, which is located at the center of the semiconductor chip CHP1 in the Y direction and extends in the X direction. The region 1C is a region that overlaps the regions 1A and 1B in plan view. In the region 1C, the gate electrodes GE are not formed inside the trenches D1 and D2 respectively. That is, inside each of the trenches D1 and D2 in the region 1C, the field plate electrode FP is embedded from the vicinity of the lower end to the vicinity of the upper end of each of the trenches D1 and D2. Further, the source pad SP is electrically connected to the conductive film CL constituting the termination ring TR via the contact plug C3.

[0036] The wiring (sense source wiring) SSW is formed in region 1B. That is, the wiring SSW is surrounded by the source pad SP in plan view. The wiring SSW is electrically connected to the source region SR and the body layer PB via the contact plug C4. The contact plug C4 reaches the mid-depth of the body layer PB, which is a position deeper than the source region SR, and is in contact with the source region SR. In order to reduce the connection resistance between the contact plug C4 and the body layer PB, a p-type semiconductor region with a higher concentration than the body layer PB may be formed in the semiconductor substrate therebetween.

[0037] Also, the wiring SSW is electrically connected to the field plate electrode FP in the trench D2 via the contact plug C5. The contact plug C5 is formed in region 1C that overlaps region 1B in plan view.

[0038] The wirings SW1 and SW2 are arranged side by side with region 1B in the Y direction, and are electrically connected to the field plate electrode FP in the trench D2 via the contact plug C6 respectively in two regions sandwiching the source pad SP and the gate wiring GW in plan view. In the two regions, the gate electrode GE is not formed in the trench D2. That is, in the trench D2 of those regions, the field plate electrode FP is embedded from the vicinity of the lower end to the vicinity of the upper end of the trench D2.

[0039] The wiring SW1 is drawn to the end of the semiconductor chip CHP1, and a part of the upper surface of the wiring SW1 at the end constitutes the sense source pad SSP. Also, the wiring SW2 is drawn to the end of the semiconductor chip CHP1, and a part of the upper surface of the wiring SW2 at the end constitutes the sense source pad SSKP. The sense source pad SSKP is a Kelvin pad that has the role of detecting the potential of the wiring SSW. The source potential is supplied to the source region SR that constitutes the sense MOSFET1SQ via the sense source pad SSP, the wiring SW1, the contact plug C6, the field plate electrode FP in the trench D2, the contact plug C5, the wiring SSW, and the contact plug C4.

[0040] Here, the operation of each MOSFET will be described. When the main MOSFET1MQ is in the on state, a channel (inversion layer) is formed in the body layer PB adjacent to the trench D2 provided with the gate electrode GE, and current flows from the drain region DR through the drift layer DF and the channel in the body layer PB to the source region SR (see the dashed arrow in Figure 2).

[0041] When the sense MOSFET1SQ is in the on state, a channel (inversion layer) is formed in the body layer PB adjacent to the trench D2 provided with the gate electrode GE, and current flows from the drain region DR through the drift layer DF and the channel in the body layer PB to the source region SR (see the dotted arrow in Figure 2). A part of the current of the sense MOSFET1SQ that has flowed into the source region SR flows to the sense source pad SSP via the wiring SSW, the field plate electrode FP in the trench D2, and the wiring SW1, as indicated by the dotted arrow in Figures 2, 3, and 4. Also, another part of the current of the sense MOSFET1SQ that has flowed into the source region SR flows to the sense source pad SSKP via the wiring SSW, the field plate electrode FP in the trench D2, and the wiring SW2.

[0042] Here, the source potential of the sense MOSFET 1SQ can be taken out from the central part of the semiconductor chip CHP1 in the Y direction to the sense source pad SSKP through the field plate electrode FP. Therefore, since the potential of the sense MOSFET 1SQ at the central part of the semiconductor chip CHP1 in the Y direction can be detected, more stable potential detection becomes possible.

[0043] Each MOSFET of this embodiment is a trench double-gate type power MOSFET, and by having a field plate electrode to which the source potential is applied in the trench, the parasitic capacitance of the MOSFET can be suppressed and the switching speed of the MOSFET can be increased.

[0044] Fig. 6 shows an equivalent circuit diagram of the semiconductor device of this embodiment. As shown in Fig. 6, the main MOSFET 1MQ and the sense MOSFET 1SQ share the drain D and each has a built-in diode. The built-in diode is composed of a pn junction between a body layer PB which is a p-type layer connected to the contact plug C1 or C4 shown in Fig. 2, and an n-type layer composed of a drift layer DF and a drain region DR. The source region of the sense MOSFET 1SQ is connected to the source S (sense source pad SSP) and the source SSK (sense source pad SSKP).

[0045] One of the main features of the semiconductor device of this embodiment is that the sense MOSFET 1SQ is formed at the central part of the semiconductor chip CHP1, and the sense MOSFET 1SQ is continuously surrounded by the source pad SP in plan view.

[0046] Another one of the main features of the semiconductor device of the present embodiment is that no multilayer wiring layer is formed on the semiconductor substrate. That is, no other wiring (wiring layer) is formed between each of the source pad SP, wiring SSW, SW1, SW2, and gate wiring GW, which are made of metal films of the same layer, and the semiconductor substrate. The wiring referred to here is wiring that extends planar in the X direction or Y direction in plan view, excluding the contact plugs C1 to C6 connected to those metal films and the semiconductor substrate, gate electrode GE, field plate electrode FP, or conductive film CL.

[0047] <Effects of the present embodiment> As described in the problems to be solved by the invention, in the reliability test in which a thermal load is applied to the semiconductor chip, the die bond crack progresses from the outer peripheral portion of the chip. For this reason, if a sense MOSFET is present near the outer peripheral portion of the chip, it is considered that the crack will progress to directly below the sense MOSFET. In this case, since the resistance of the sense MOSFET changes, the sense ratio fluctuates greatly, making it difficult to detect current using the sense MOSFET. Therefore, it is desirable that the sense MOSFET be arranged at the central portion of the chip.

[0048] Therefore, in the present embodiment, the sense MOSFET is formed at the central portion of the semiconductor chip. Here, the source potential is supplied to the source region of the sense MOSFET by using the field plate electrode in the trench. Therefore, although the region where the sense MOSFET is formed is cut out without forming a source pad here, unlike in Patent Document 1, it is not necessary to divide the source pad of the main MOSFET in order to draw out the source wiring of the sense MOSFET. That is, the sense MOSFET can be continuously surrounded by the source pad SP in plan view. Thereby, it is possible to prevent a decrease in the chip performance of the main MOSFET due to a reduction in the area of the source pad and the occurrence of restrictions on the bonding layout.

[0049] Also, in order to supply the source potential to the source region of the sense MOSFET at the center of the semiconductor chip, it is not necessary to add a wiring layer on the semiconductor substrate. That is, compared with the case where the sense MOSFET is disposed at the end of the semiconductor chip, neither an additional manufacturing process nor a patterning mask is required. Therefore, an increase in the manufacturing cost of the semiconductor device can be prevented. Also, since it is not necessary to use a multilayer wiring substrate, an increase in the size of the semiconductor device can be prevented.

[0050] That is, according to the present embodiment, malfunction of the sense MOSFET due to occurrence of die bond crack or the like can be prevented, and thus the performance of the semiconductor device can be improved while ensuring the reliability of the semiconductor device.

[0051] <Modification Example 1> In addition to the structure described above, a structure in which a bypass diode (protection diode) and a Kelvin pad of the main MOSFET are added will be described with reference to FIGS. 7 to 11.

[0052] In this modification example, unlike the structure described with reference to FIGS. 1 to 6, as shown in FIGS. 7, 8, and 10, in a region where regions 1B and 1C of the semiconductor chip CHP2 overlap each other, a contact plug C8 integrated with a wiring SSW is formed through an interlayer insulating film IL between adjacent contact plugs C5 in the X direction. The contact plug C8 is connected to a body layer PB formed on the upper surface of the semiconductor substrate between adjacent trenches D2. Since a source region SR is not formed in the region 1C, the contact plug C8 is not in contact with the source region SR. In other words, the contact plug C8 is separated from the source region SR.

[0053] The contact plug C8 is electrically connected to a bypass diode BD formed in the semiconductor substrate. In FIG. 8, the formation region of the sense MOSFET 1SQ is surrounded by a broken line, and the formation region of the bypass diode BD is surrounded by a one-dot chain line.

[0054] The bypass diode BD is connected in parallel between the source and drain of the sense MOSFET 1SQ. The bypass diode BD is composed of a pn junction between a body layer PB, which is a p-type layer connected to a contact plug C8 shown in FIG. 10, and an n-type layer composed of a drift layer DF and a drain region DR. As shown in FIG. 11, the bypass diode BD has its anode connected to the source S and its cathode connected to the drain D. The bypass diode has a role of ensuring the ESD (Electro-Static Discharge) tolerance of the semiconductor device. That is, if the bypass diode BD is formed, when, for example, static electricity is discharged to, for example, a wiring SSW, a current can flow to the drain through the bypass diode BD, preventing the semiconductor element from being damaged by a high voltage.

[0055] Also, as shown in FIGS. 7, 9, and 11, here, a source pad SKP, which is a Kelvin pad for detecting the source potential of the main MOSFET, is formed. A wiring SW3 having the source pad SKP on a part of its upper surface is a wiring located at the same height as the source pad SP, wirings SSW, SW1, SW2, and the gate wiring GW. The wiring SW3 is formed directly above the trench D1 at a position adjacent in the X direction to the wiring SW1 or SW2 at the location connected to the contact plug C6. The wiring SW3 is electrically connected to the field plate electrode FP in the trench D1 through the contact plug C7 outside the source pad SP and the gate wiring GW in the Y direction. As shown in FIG. 11, the source region of the main MOSFET 1MQ is connected to the source S (source pad SP) and the source SK (source pad SKP).

[0056] Thereby, the source potential of the main MOSFET 1MQ can be taken out from the central part in the Y direction of the semiconductor chip CHP2 through the field plate electrode FP. Therefore, since the potential of the main MOSFET 1MQ at the central part in the Y direction of the semiconductor chip CHP2 can be detected, a more stable potential detection becomes possible.

[0057] <Modification Example 2> FIG. 12 shows a planar layout in which bypass diodes BD are connected to all main MOSFETs 1MQ in region 1A of semiconductor chip CHP3. As shown in FIG. 12, outside the source pad SP and the gate wiring GW in the Y direction, contact plugs C9 are formed on the semiconductor substrate between adjacent trenches D1, between adjacent trenches D2, and between adjacent trenches D1 and D2. The contact plug C9 is connected to the body layer PB formed on the upper surface of the semiconductor substrate, similar to the contact plug C8, and the body layer PB constitutes the anode of the bypass diode BD. A plurality of contact plugs C9 arranged in the X direction are integrated with a wiring SW2 extending in the X direction. That is, those bypass diodes BD are electrically connected to the sense source pad SSKP via the contact plug C9 and the wiring SW2.

[0058] In this modification example, compared with the modification example 1, a bypass diode (protection diode) with a larger area can be formed, so that even a sense MOSFET with a small area can improve its ESD resistance.

[0059] (Embodiment 2) With reference to FIGS. 13 to 15, a structure provided with trenches for element isolation will be described. Each of FIGS. 13 to 15 is a planar layout showing an example of the semiconductor device of this embodiment.

[0060] As shown in FIG. 13, in semiconductor chip CHP4, a trench D4 extending in the Y direction is formed between the trench D2 in region 1B and the trench D1 in region 1A. The depth of trench D4 is the same as that of trenches D1 to D3. Trench D4 is connected to trench D3 at both ends in the Y direction. The structure in trench D4 may be the same as the structure in trenches D1 and D2, or may be the same as the structure in trench D3. That is, the number of electrodes in trench D4 may be one or two. The same applies to trenches D5 and D6 described later.

[0061] Although FIG. 13 does not show the contact plugs connected to the conductive film in the trench D4, contact plugs similar to the contact plugs C2, C3, and C5 may be connected to the conductive film. The same applies to the trench D5, which will be described later.

[0062] The source pads SP of the sense MOSFET 1SQ and the main MOSFET 1MQ and the sense source pad SSP need to be electrically independent. When the voltage applied to the semiconductor device is high and high breakdown voltage performance is required, in order to perform element isolation between the sense MOSFET 1SQ and the main MOSFET 1MQ, it is conceivable to ensure a certain distance between those elements. However, in that case, the size of the semiconductor device increases.

[0063] Therefore, in the present embodiment, the trench D4 is provided. The trench D4 is a pseudo trench provided to improve the insulation in the X direction between the sense MOSFET 1SQ and the main MOSFET 1MQ. The pseudo trench here means a trench that does not constitute the trench of the trench-type MOSFET. That is, the conductive film in the pseudo trench does not function as the gate electrode of the MOSFET. Here, compared with the case where the distance is increased without providing a trench between the sense MOSFET and the main MOSFET, an increase in the size of the semiconductor device can be prevented, and the insulation in the X direction between the sense MOSFET 1SQ and the main MOSFET 1MQ can be improved.

[0064] In FIG. 14, in the semiconductor chip CHP5, a trench D5 having the same structure as the trench D4 except for the planar layout is formed. That is, the trench D5 is different from the trench D4 in that it is not connected to the trench D3. In other words, the trench D5 is spaced apart from the trench D3, similar to the trenches D1 and D2. Further, here, a trench D6 extending in the X direction is formed between the region 1B and the region 1A in the Y direction. The trench D6 intersects a plurality of trenches D2 arranged in the X direction in a plan view and is connected to those trenches D2. The trench D6 is formed between the adjacent contact plugs C1 and C4 in the Y direction. The trench D6 is a pseudo trench provided for improving the insulation between elements, similar to the trenches D4 and D5.

[0065] Here, by providing the trench D5, the insulation between the sense MOSFET1SQ and the main MOSFET1MQ in the X direction is improved, and by providing the trench D6, the insulation between the sense MOSFET1SQ and the main MOSFET1MQ in the Y direction is improved.

[0066] Further, FIG. 15 shows a structure combining the structure shown in FIG. 13 and the structure shown in FIG. 14. That is, the semiconductor chip CHP6 shown in FIG. 15 has trenches D4 and D6. Since the trench D4 is connected to the trench D3, the insulation between the sense MOSFET1SQ and the main MOSFET1MQ in the X direction can be improved compared to the semiconductor chip CHP5 described with reference to FIG. 14.

[0067] (Embodiment 3) Since the field plate electrode has a small cross-sectional area and a large resistance, if the source potential is supplied to the source region of the sense MOSFET by a small number of field plate electrodes, the influence of the wiring resistance may occur.

[0068] Therefore, in the semiconductor chip CHP7 of the present embodiment, as shown in FIG. 16, some of the trenches D1 adjacent to the trench D2 in the X direction are connected to the trench D2 by a trench D7 extending in the X direction. In the trench D7, an insulating film IF1 and a field plate electrode FP are formed in the same manner as in the trench D2 in the region 1C. That is, the field plate electrode FP in the trench D2 and the field plate electrode FP in the trench D1 in the trench D1 arranged in parallel with the trench D2 are electrically connected via the field plate electrode FP in the trench D7. The trench D1 connected to the trench D7 is a trench that is separated from the region 1B and the wiring SSW in a plan view.

[0069] In this way, the field plate electrode FP in the trench D1 connected to the trench D2 is not connected to the source pad SP via the contact plug C3. That is, no contact plug C3 is formed directly above the trench D1. That is, the field plate electrode FP in the trench D1 connected to the trench D2 is insulated from the source pad SP. The trench D1 is electrically connected to the wirings SW1 and SW2 via the contact plug C6 outside the source pad SP and the gate wiring GW in the Y direction.

[0070] In the present embodiment, by connecting the trenches in the X direction, the number of field plate electrodes for extracting the source electrode of the sense MOSFET is increased. Thereby, the resistance of the wiring for supplying the source potential to the source region of the sense MOSFET can be reduced.

[0071] As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

[0072] For example, the polarities of the constituent parts of each MOSFET described in the above Embodiments 1 to 3 may be interchanged. That is, each MOSFET may be a p-type MOSFET.

Description of Symbols

[0073] 1MQ Main MOSFET 1SQ Sense MOSFET BD Bypass Diode C1~C9 Contact Plug CHP1~CHP7 Semiconductor Chip D1~D7 Trench DF Drift Layer DR Drain Region FP Field Plate Electrode GE Gate Electrode GP Gate Pad GW Gate Wiring PB Body Layer SB Substrate SKP, SP Source Pad SR Source Region SSKP, SSP Sense Source Pad SSW, SW1, SW2, SW3 Wiring TR Termination Ring

Claims

1. A semiconductor device having a semiconductor chip including a first field-effect transistor and a second field-effect transistor for current detection, comprising a first-conductivity-type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and having an annular first region and a second region surrounded by the first region in a plan view, a first trench formed to reach a middle depth of the semiconductor substrate from the first main surface of the semiconductor substrate, extending in a first direction along the first main surface of the semiconductor substrate, and arranged in a plurality in a second direction orthogonal to the first direction in a plan view, a first semiconductor region of a second conductivity type, which is different from the first conductivity type, formed in the semiconductor substrate in contact with side surfaces of the first trenches, a source region of the first conductivity type, which is in contact with side surfaces of each of the plurality of first trenches, the first main surface of the semiconductor substrate, and the first semiconductor region, a drain region of the first conductivity type formed in the semiconductor substrate including the second main surface of the semiconductor substrate, a gate electrode and a first electrode, which are formed via a first insulating film inside each of the plurality of first trenches and insulated from each other, a first wiring, a second wiring, and a source pad formed on the semiconductor substrate via an interlayer insulating film, and having, wherein the gate electrode, the source region, the drain region, and the first semiconductor region in the first region constitute the first field-effect transistor, the gate electrode, the source region, the drain region, and the first semiconductor region in the second region constitute the second field-effect transistor, the source region of the first field-effect transistor and the first electrode in the first trench spaced apart from the second region in a plan view are electrically connected to the source pad, a semiconductor device, wherein in a plan view, the source region of the second field-effect transistor is electrically connected to the second wiring located outside the source pad via the first wiring surrounded by the source pad and the first electrode in the first trench extending across the second region, the first region, and the outside of the first region.

2. The semiconductor device according to claim 1, wherein the first wiring is located at the same height as a metal film constituting the source pad.

3. The semiconductor device according to claim 1, A semiconductor device in which no wiring layer is formed between the metal film constituting the first wiring, the second wiring, and the source pad and the first main surface of the semiconductor substrate.

4. In the semiconductor device according to claim 1, the second field effect transistor is located at the central portion of the semiconductor chip in a plan view, the semiconductor device.

5. In the semiconductor device according to claim 1, further comprising a first diode formed by a pn junction between the first semiconductor region of the second region and the semiconductor substrate, the first wiring is connected to the first semiconductor region constituting the first diode via a first conductive connection portion, the semiconductor device.

6. In the semiconductor device according to claim 1, further comprising a second diode formed by a pn junction between the first semiconductor region located outside the source pad in a plan view and the semiconductor substrate, the second wiring is connected to the first semiconductor region constituting the second diode via a second conductive connection portion, the semiconductor device.

7. In the semiconductor device according to claim 1, further comprising a third wiring located outside the source pad in a plan view and formed on the semiconductor substrate with an interlayer insulating film therebetween, the first electrode in the first trench formed in the first region or the second region is electrically connected to the third wiring, a part of the third wiring constitutes an electrode pad for potential detection, the semiconductor device.

8. In the semiconductor device according to claim 1, in the second direction, further comprising a pseudo second trench formed on the first main surface of the semiconductor substrate between the first trench of the first region and the first trench of the second region and extending in the first direction, the semiconductor device.

9. In the semiconductor device according to claim 8, further comprising a third trench formed on the first main surface of the semiconductor substrate, surrounding the first region, the second region, and the plurality of first trenches, and having an annular structure in a plan view, both ends of the second trench are connected to the third trench in the second direction, the semiconductor device.

10. In the semiconductor device according to claim 1, further comprising a fourth trench formed on the first main surface of the semiconductor substrate, extending in the second direction, and connecting the first trench of the second region and the first trench of the first region adjacent to each other, The fourth trench has the first electrode formed therein via the first insulating film on the inner side, A semiconductor device, wherein the first electrode in the first trench of the first region connected to the fourth trench is insulated from the source pad, is electrically connected to the first electrode in the first trench of the second region via the first electrode in the fourth trench, and is electrically connected to the second wiring located outside the source pad.

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