Semiconductor device

Abstract

To provide a semiconductor device using an unipolar transistor capable of keeping power consumption low and preventing an amplitude of an output potential from being low.SOLUTION: A semiconductor device has: first wiring having a first potential; second wiring having a second potential; third wiring having a third potential; a first transistor and a second transistor having the same polarity; and a plurality of third transistors that select whether to give the first potential or the third potential to gates of the first and second transistors, and select whether or not to give the first potential to drain terminals of the first and second transistors. A source terminal of the first transistor is connected with the second wiring, and a source terminal of the second transistor is connected with the third wiring.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to circuits using unipolar transistors, semiconductor display devices using the above circuits, etc. , semiconductor devices.

Background Art

[0002] Semiconductor display devices such as liquid crystal display devices and EL display devices are preferably composed of unipolar semiconductors rather than CMOS in order to reduce the cost of the backplane (circuit board). In the following Patent Document 1 and Patent Document 2, techniques for configuring various circuits such as inverters and shift registers used in the drive circuit of a semiconductor display device with unipolar transistors are disclosed. disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, semiconductor display devices composed of transistors having amorphous silicon or oxide semiconductors can handle glass substrates of the fifth generation (1200 mm in width × 1300 mm in length) or more, and thus have the advantages of high productivity and low cost. However, transistors having amorphous silicon or oxide semiconductors are generally unipolar and tend to become normally-on. And in a circuit composed of unipolar transistors, the transistor When the transistor is in the normal-on state, there will be problems such as an increase in power consumption or a decrease in the amplitude of the output potential. Such problems occur.

[0005] For example, in the circuit described in FIG. 10 of Patent Document 2, the source terminal of the transistor Q2 is fixed to the low potential VSS. When the transistor Q2 is in the normal-off state, if the transistor Q2 is in the normal-on state, when a low potential VSS is applied to its gate, the gate voltage, which is the voltage between the gate and the source terminals with respect to the potential of the source terminal, remains higher than the threshold voltage of the transistor Q2. Therefore, the transistor Q2 does not turn off and remains in the conducting state (on). However, when the transistor Q2 is in the normal-on state, even when a low potential VSS is applied to its gate, the gate voltage, which is the voltage between the gate and the source terminals with respect to the potential of the source terminal, remains higher than the threshold voltage of the transistor Q2. As a result, the transistor Q2 does not turn off and remains in the conducting state (on). When the transistor Q2 is supposed to be off but turns on instead, an unnecessary current flows in the circuit, increasing the consumption current. Furthermore, due to the above unnecessary current, the current flowing through the wiring for supplying a potential (for example, in the case of FIG. 10 of Patent Document 2, the low-level potential VSS or the high-level potential VDD and the low-level potential VSS of the clock signal CLKA) to the circuit increases. And due to the resistance of the above wiring, the potential of the wiring to which the potential VDD is supplied decreases, and the potential of the wiring to which the potential VSS is supplied increases. As a result, the amplitude of the potential output from the circuit becomes smaller than the potential difference between the potential VDD and the potential VSS, which is the ideal potential difference.

[0006] When the transistor Q2 is supposed to be off but turns on instead, an unnecessary current flows in the circuit, increasing the consumption current. Furthermore, due to the above unnecessary current, the current flowing through the wiring for supplying a potential (for example, in the case of FIG. 10 of Patent Document 2, the low-level potential VSS or the high-level potential VDD and the low-level potential VSS of the clock signal CLKA) to the circuit increases. And due to the resistance of the above wiring, the potential of the wiring to which the potential VDD is supplied decreases, and the potential of the wiring to which the potential VSS is supplied increases. As a result, the amplitude of the potential output from the circuit becomes smaller than the potential difference between the potential VDD and the potential VSS, which is the ideal potential difference. Specifically, in the pixel portion of the semiconductor display device, a bus line connected to a plurality of pixels, called the current flowing through the wiring for supplying a potential (for example, in the case of FIG. 10 of Patent Document 2, the low-level potential VSS or the high-level potential VDD and the low-level potential VSS of the clock signal CLKA) to the circuit increases. And due to the resistance of the above wiring, the potential of the wiring to which the potential VDD is supplied decreases, and the potential of the wiring to which the potential VSS is supplied increases. As a result, the amplitude of the potential output from the circuit becomes smaller than the potential difference between the potential VDD and the potential VSS, which is the ideal potential difference. As a result, the amplitude of the potential output from the circuit becomes smaller than the potential difference between the potential VDD and the potential VSS, which is the ideal potential difference. It becomes smaller.

[0007] In particular, in the pixel portion of the semiconductor display device, a bus line connected to a plurality of pixels, called When supplying the potential output from a circuit to a wiring, such as a scanning line or a signal line, etc., from the circuit a transistor (for example, in the case of FIG. 10 of Patent Document 2, transistor Q2) that controls the output of the potential is required to have a large current supply capacity. Therefore, the channel width W of the transistor is designed to be a larger value than the channel width W of other transistors in the circuit in many cases. However, the drain current of the transistor is proportional to the channel width W. Therefore, when the channel width W of the transistor that is a normation is increased, the current flowing through the transistor when it should be turned off becomes larger than that of other transistors. Therefore, the unnecessary current flowing through the circuit increases, the power consumption increases, or the amplitude of the output potential becomes smaller, and the above-described phenomena are likely to occur significantly.

[0008] Under the above-described technical background, one of the problems of the present invention is to provide a semiconductor device with low power consumption. Alternatively, one of the problems of the present invention is to provide a semiconductor device that can prevent the amplitude of the output potential from becoming smaller.

Means for Solving the Problems

[0009] A semiconductor device according to one aspect of the present invention has a plurality of transistors, and by turning on or off each of the plurality of transistors, it is a circuit that selects and outputs either a high potential or a low potential. And in one aspect of the present invention, among the plurality of transistors, the wiring that applies a potential to the source terminal of the output-side transistor and the wiring that supplies a potential to the source terminal of the other transistors are configured to be different. Further, the other transistors of the From the wiring that supplies potential to the source terminal, potential is applied to the gate of the output - side transistor via the other transistor, so that the output - side transistor is turned off. It shall have a configuration in which, by applying potential to the gate of the output - side transistor, the output - side transistor is turned off. Let it be so.

[0010] With the above configuration, the gate of the output - side transistor and the source terminal can be electrically separated. Therefore, assuming that the output - side transistor is normally - on, even if the potential of the wiring for supplying potential to the source terminal of the transistor fluctuates, the potential of the wiring for supplying potential to the gate of the transistor is independent of the above - mentioned fluctuation. That is, it can be configured such that when the potential of the source terminal of the transistor fluctuates due to the drain current of the output - side transistor, the gate voltage of the transistor approaches the threshold voltage, that is, a configuration with negative feedback is applied. Therefore, even if the output - side transistor is normally - on, it can be turned off when it should be turned off.

Advantages of the Invention

[0011] In one aspect of the present invention, a semiconductor device using a unipolar transistor with low power consumption can be provided. Alternatively, in one aspect of the present invention, a semiconductor device capable of preventing the amplitude of the output potential from decreasing can be provided.

Brief Description of the Drawings

[0012]

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Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0014] Note that the present invention can be used in the fabrication of various semiconductor devices such as integrated circuits such as microprocessors, image processing circuits, DSPs (Digital Sign al Processors), microcontrollers, RF tags, and semiconductor display devices. Semiconductor display devices include a liquid crystal display device, a light-emitting device represented by an organic light-emitting element (OLED) provided in each pixel, an EL display device, an electronic paper, a DMD (Digital Micromirror De vice), a PDP (Plasma Display Panel), a FED (Fiel d Emission Display), etc., and other semiconductor display devices having circuit elements using a semiconductor film in a drive circuit are included in the scope.

[0015] In the present specification, the semiconductor display device refers to a panel in which display elements such as liquid crystal elements and light-emitting elements are formed in each pixel, and a module in a state where an IC including a controller is mounted on the panel. is included in the scope.

[0016] (Embodiment 1) FIG. 1(A) shows an example of a circuit configuration of a semiconductor device according to an aspect of the present invention. FIG. 1(A) The semiconductor device 100 shown includes a circuit 101 composed of a plurality of transistors, a transistor 102, and a transistor 103. In the semiconductor device 100 shown in FIG. 1(A) at least the transistor 102 and the transistor 103 have the same polarity. In FIG. 1 (A), the case where the transistor 102 and the transistor 103 are both n-channel type is illustrated.

[0017] The circuit 101 is supplied with a high-level potential VDD or a low-level potential VSS via the wiring 104 and the wiring 105. In FIG. 1(A), the potential V DD is supplied to the circuit 101 via the wiring 104, and the potential VSS is supplied to the circuit 101 via the wiring 105 is illustrated. Also, a signal potential Vin is supplied to the circuit 101 via the wiring 107.

[0018] The gate and drain terminals of transistor 102 are connected to circuit 101. Circuit 1 01 selects either the potential VDD or the potential VSS according to the potential Vin and applies it to the gate or drain terminal of transistor 1 02. The potential VSS of wiring 105 is applied to the source terminal of transistor 1 02.

[0019] Note that the source terminal of a transistor means the source region that is part of the active layer or the source electrode connected to the active layer. Similarly, the drain terminal of a transistor means the drain region that is part of the active layer or the drain electrode connected to the active layer.

[0020] Also, the gate and drain terminals of transistor 103 are connected to circuit 101. Circuit 101 selects either the potential VDD or the potential VSS according to the potential Vin and applies it to the gate or drain terminal of transistor 1 03. The source terminal of transistor 103 is supplied with the potential VEE via wiring 106. The potential VEE is a lower-level potential than the potential VDD. And the potential VEE is desirably at the same potential as the potential VSS or at a higher potential than that.

[0021] Note that the source and drain terminals of a transistor change their names depending on the polarity of the transistor and the levels of the potentials applied to the respective electrodes. Generally, in an n-channel type transistor, the electrode to which a lower potential is applied is called the source terminal, and the electrode to which a higher potential is applied is called the drain terminal. Also, in a p-channel type transistor, a lower potential ​​​​​​​The given electrode is called the drain terminal, and the electrode to which a high potential is applied is called the source terminal. In this specification, for the sake of convenience, it is assumed that the source terminal and the drain terminal are fixed, and the connection relationship of the transistor may be described. However, in reality, the names of the source terminal and the drain terminal are interchanged according to the above potential relationship.

[0022] Also, in this specification, "connection" means electrical connection, corresponding to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily refer to the state of direct connection, but also includes the state of indirect connection through elements such as wiring, conductive films, resistors, diodes, and transistors so that current, voltage, or potential can be supplied or transmitted.

[0023] Also, even if components that are independent on the circuit diagram are connected, in reality, for example, when a part of the wiring functions as an electrode, there may be a case where one conductive film has the functions of a plurality of components. In this specification, "connection" includes such a case where one conductive film has the functions of a plurality of components within its scope.

[0024] Also, it is assumed that the potential applied from circuit 101 to the gate of transistor 102 and the potential applied from circuit 101 to the gate of transistor 103 are the same potential. In FIG. 1(A), a case where the gate of transistor 102 and the gate of transistor 103 are connected is illustrated.

[0025] The semiconductor device 100 shown in FIG. 1(A) operates within circuit 101 according to the potential Vin of the above signal. A plurality of transistors, transistor 102 and transistor 103 are each turned on or off to select either the potential VDD or the potential VEE, and output it as the potential Vo ut to the wiring 108. Specifically, when the wiring 104 and the wiring 10 8 are connected by the circuit 101, the potential of the wiring 104 is output as the potential Vout. Also, when the wiring 106 and the wiring 108 are connected by the transistor 103, the potential of the wiring 106 is the potential Vout and output.

[0026] When supplying the potential Vout output from the semiconductor device 100 to a wiring called a bus line connected to a plurality of pixels, for example, a scanning line or a signal line, etc., the transistor 103 that controls the output of the potential Vout is required to have a large current supply capacity. Therefore, it is desirable to design the channel width W of the transistor 103 to be larger than the channel width W of the transistor in the circuit 101 or the transistor 1 02. 02.

[0027] When the transistor 102 is an n-channel type, the transistor 102 turns on when the potential VDD is applied to its gate from the circuit 101. Also, when the potential VSS is applied to its gate from the circuit 101, the gate voltage Vgs becomes 0V . Therefore, if the transistor 102 is normally off, that is, the threshold voltage Vth is higher than 0V , the transistor 102 turns off. However, if the transistor 102 is normally on , that is, the threshold voltage Vth is 0V or less, the transistor 102 remains on without turning off .

[0028] The transistor 103 also performs the same operation as the transistor 102. Specifically, the transistor​ When the transistor 103 is of the n-channel type, the transistor 103 turns on when the potential VDD is applied to its gate from the circuit 101. Also, when the potential VSS is applied to the gate of the transistor 103 from the circuit 101, the gate voltage Vgs = VSS - VEE, so the gate voltage Vgs becomes 0 V or less. Therefore, if the transistor 103 is normally off, that is, if the threshold voltage Vth is higher than 0 V, the transistor 103 turns off. However, if the transistor 103 is normally on, that is, if the threshold voltage Vth is 0 V or less, the transistor 103 may turn on without turning off. Hereinafter, the operation of the semiconductor device 100 shown in Fig. 1(A) when the transistors 102 and 103 are normally on will be described in detail.

[0029]

[0030] When VSS - VEE > Vth, when the potential VSS is applied to the gate of the transistor 103, the gate voltage Vgs of the transistor 103 is Vgs = VSS - VEE > Vth, so. Therefore, the transistor 103 turns on. Also, as described above, when the potential VSS is applied to the gate of the transistor 102, the transistor 102 turns on regardless of the value of the potential VEE.

[0031] And when the transistors 102 and 103 should be off but turn on instead, when the potential VDD is applied to the drain terminals of the transistors 102 and 103 from the circuit 101, a current flows through the wiring 105 via the transistor 102 and a current flows through the wiring 106 via the transistor 103. Therefore, the potential of the wiring 105 rises from the potential VSS to the potential VSS+Vα. Also, similarly, the potential of the wiring 106 rises from the potential VEE to the potential VEE+Vβ.

[0032] As described above, when the channel width W of the transistor 103 is larger than the channel width W of the transistor 102, even if the gate voltage Vgs is the same, the current flowing through the wiring 106 through the transistor 103 is larger than the current flowing through the wiring 105 through the transistor 102. Therefore, when the channel width W of the transistor 103 is larger than the channel width W of the transistor 102, the rise in the potential of the wiring 106 is larger than the rise in the potential of the wiring 105, and finally the potential VSS+Vα = the potential VEE+Vβ+Vth. Thus, since the gate voltage Vgs of the transistor 103 becomes low until it reaches the threshold voltage Vth, it becomes a state close to off. Therefore, even if the transistor 103 is normally on, it can be brought into a state close to off when the transistor 103 should be turned off.

[0033] On the other hand, when VSS-VEE≦Vth, when the potential VSS is applied to the gate of the transistor 103, the gate voltage Vgs = VSS-VEE≦Vth. Thus, in this case, the transistor 103 can be turned off even if it is normally on.

[0034] Note that when the potential VSS is applied to the gate of the transistor 102, it turns on regardless of the value of the potential VEE. Therefore, the potential of the wiring 105 rises from the potential VSS to the potential VSS+Vα. Since the potential of the wiring 105 is applied to the gate of the transistor 103 by the circuit 101, due to the rise in the potential of the wiring 105, The potential also rises from the potential VSS to the potential VSS + Vα.

[0035] Even if the potential applied to the gate of transistor 103 rises, the gate voltage Vgs = VSS If + Vα - VEE ≤ Vth, transistor 103 remains off. The gate voltage If Vgs = VSS + Vα - VEE > Vth, transistor 103 turns on. . However, in this case, when a current flows through wiring 106 via transistor 103, the potential of wiring 106 rises, and finally the potential VSS + Vα = potential VEE + Vγ + Vth is reached. Therefore, since the gate voltage Vgs of transistor 103 becomes lower before reaching the threshold voltage Vth, it is in a state close to off.

[0036] Thus, in the semiconductor device 100 according to one aspect of the present invention, by configuring the wiring 106 that applies a potential to the source terminal of the transistor 103 located on the output side and the wiring 105 that supplies a potential to the source terminal of a transistor other than transistor 103 (for example, transistor 102) to be different, when the drain current of transistor 103 is large, negative feedback can be applied so that the gate voltage of transistor 103 approaches the threshold voltage. Therefore, even if transistor 103 is normally on, transistor 103 can be turned off. Thus, even if the potential of wiring 104 decreases and the potential of wiring 105 rises due to the resistance of each wiring, the power consumption of the semiconductor device 100 can be suppressed to be small. Also, it is possible to prevent the amplitude of the potential Vout output from the semiconductor device 100 from becoming small. 03 approaches the threshold voltage, negative feedback can be applied. Therefore, even if transistor 103 is normally on, transistor 103 can be turned off. Thus, even if the potential of wiring 104 decreases and the potential of wiring 105 rises due to the resistance of each wiring, the power consumption of the semiconductor device 100 can be suppressed to be small. Also, it is possible to prevent the amplitude of the potential Vout output from the semiconductor device 100 from becoming small.

[0037] In FIG. 1(A), both transistor 102 and transistor 103 are n-channel Although the case of the L shape is exemplified, both the transistor 102 and the transistor 103 may be p-channel type. However, in this case, the wiring 105 connected to the source terminal of the transistor 102 and the wiring 106 connected to the source terminal of the transistor 103 are configured to be given a potential higher than that of the wiring 104. Also, in the semiconductor device shown in Fig. 1(A), the case where the transistor 103 on the output side that controls the output of the potential of the wiring 106 is normally on has been described. However, in one aspect of the present invention, even when the transistor on the output side that controls the output of the potential of the wiring 104 is normally on, it can be turned off when it should be turned off. Hereinafter, focusing on the transistor on the output side that controls the output of the potential of the wiring 104, the operation of the semiconductor device according to one aspect of the present invention will be described. Fig. 1(B) shows another example of the circuit configuration of the semiconductor device according to one aspect of the present invention. The semiconductor device 100 shown in Fig. 1(B) includes a circuit 101 composed of a plurality of transistors, a transistor 102, a transistor 103, a transistor 109, and a capacitive element 110. In the semiconductor device 100, at least the transistor 102, the transistor 103, and the transistor 109 have the same polarity. In Fig. 1(B), the case where the transistor 102, the transistor 103, and the transistor 109 are all n-channel type is exemplified. And, in the semiconductor device 100 shown in Fig. 1(B), unlike the case of Fig. 1(A), the transistor

[0038] Also, in the semiconductor device shown in Fig. 1(A), the case where the transistor 103 on the output side that controls the output of the potential of the wiring 106 is normally on has been described. However, in one aspect of the present invention, even when the transistor on the output side that controls the output of the potential of the wiring 104 is normally on, it can be turned off when it should be turned off. Hereinafter, focusing on the transistor on the output side that controls the output of the potential of the wiring 104, the operation of the semiconductor device according to one aspect of the present invention will be described. Also, in the semiconductor device shown in Fig. 1(A), the case where the transistor 103 on the output side that controls the output of the potential of the wiring 106 is normally on has been described. However, in one aspect of the present invention, even when the transistor on the output side that controls the output of the potential of the wiring 104 is normally on, it can be turned off when it should be turned off. Hereinafter, focusing on the transistor on the output side that controls the output of the potential of the wiring 104, the operation of the semiconductor device according to one aspect of the present invention will be described. In one aspect of the present invention, even when the transistor on the output side that controls the output of the potential of the wiring 104 is normally on, it can be turned off when it should be turned off. Hereinafter, focusing on the transistor on the output side that controls the output of the potential of the wiring 104, the operation of the semiconductor device according to one aspect of the present invention will be described. Hereinafter, focusing on the transistor on the output side that controls the output of the potential of the wiring 104, the operation of the semiconductor device according to one aspect of the present invention will be described. The operation of the semiconductor device according to one aspect of the present invention will be described.

[0039] Fig. 1(B) shows another example of the circuit configuration of the semiconductor device according to one aspect of the present invention. In Fig. 1(B), the semiconductor device 100 shown includes a circuit 101 composed of a plurality of transistors, a transistor 102, a transistor 103, a transistor 109, and a capacitive element 110. In the semiconductor device 100 shown in Fig. 1(B), at least the transistor 102, the transistor 103, and the transistor 109 have the same polarity. In Fig. 1(B), the case where the transistor 102, the transistor 103, and the transistor 109 are all n-channel type is exemplified. In the semiconductor device 100, at least the transistor 102, the transistor 103, and the transistor 109 have the same polarity. In Fig. 1(B), the case where the transistor 102, the transistor 103, and the transistor 109 are all n-channel type is exemplified. In Fig. 1(B), the case where the transistor 102, the transistor 103, and the transistor 109 are all n-channel type is exemplified. is exemplified.

[0040] And, in the semiconductor device 100 shown in Fig. 1(B), different from the case of Fig. 1(A), the transistor The gate of the transistor 103 is connected to the circuit 101, and the drain terminal of the transistor 103 is connected to the source terminal of the transistor 109 and the wiring 108. Also, the gate of the transistor 109 is connected to the circuit 101. The circuit 101 supplies either the potential VDD or the potential VSS to the gate of the transistor 103 according to the potential Vin, and supplies the other to the gate of the transistor 109. The potential VEE is supplied to the source terminal of the transistor 103 via the wiring 106. The potential VDD is supplied to the drain terminal of the transistor 109 via the wiring 104.

[0041] The capacitor element 110 has a function of holding the gate voltage of the transistor 109. However, when the parasitic capacitance of the gate of the transistor 109 is large or the gate voltage can be held without providing the capacitor element 110, it is not always necessary to provide the capacitor element 110.

[0042] Next, the operation of the semiconductor device 100 when the transistors 102, 103, and 109 are normally on will be described in detail.

[0043] When VSS - VEE > Vth, when the potential VDD is applied to the gates of the transistors 102 and 103, the transistors 102 and 103 turn on. On the other hand, when the potential VDD is applied to the gates of the transistors 102 and 103, the potential VSS is applied to the gate of the transistor 109. Therefore, since the gate voltage Vgs of the transistor 109 becomes Vgs = VSS - VEE > Vth, It turns on when it should originally be off. Therefore, a current flows between wiring 106 and wiring 104 through transistor 109 and transistor 103, the potential of wiring 104 decreases, and the potential of wiring 105 increases.

[0044] However, in one aspect of the present invention, as the potential of wiring 106 rises from potential VEE to potential VEE + Va, the gate voltage Vgs of transistor 109 remains low until it reaches the threshold voltage Vth, and finally transistor 109 becomes in a state close to off. Specifically, when VSS = potential VEE + Vα + Vth, transistor 109 turns off. Therefore, even if transistor 109 is normally on, it can be brought into a state close to off when it should be turned off.

[0045] On the other hand, when VSS - VEE ≤ Vth, when potential VSS is applied to the gate of transistor 109, the gate voltage Vgs = VSS - VEE ≤ Vth. Therefore, in this case, transistor 109 can be turned off even if it is normally on.

[0046] In this way, in the semiconductor device 100 according to one aspect of the present invention, by configuring wiring 106 that supplies a potential to the source terminal of transistor 103 located on the output side and wiring 105 that supplies a potential to the source terminal of a transistor other than transistor 103 (for example, transistor 102) to be different, when the drain current of transistor 109 is large, negative feedback can be applied so that the gate voltage of transistor 109 approaches the threshold voltage. Therefore, even if transistor 109 is normally on, transistor 109 can be turned off. ​​​​​​​​​​​Therefore, the potential of the wiring 104 drops due to the resistance of each wiring, and the potential of the wiring 105 Even if the temperature rises, the power consumption of the semiconductor device 100 can be kept low. This makes it possible to prevent the amplitude of the potential Vout output from the device 100 from becoming small.

[0047] In FIG. 1B, the transistor 102, the transistor 103, and the transistor 1 In the example shown, both the transistor 102 and the transistor 09 are n-channel type. The transistor 103 and the transistor 109 may both be p-channel types. In this case, the wiring 105 connected to the source terminal of the transistor 102 and the A higher potential than that of the wiring 104 is applied to the wiring 106 connected to the source terminal of the third transistor. The composition is as follows.

[0048] Next, a pulse generating circuit, which is one of the semiconductor devices according to one embodiment of the present invention, will be described. 2 shows an example of a pulse generating circuit according to one embodiment of the present invention.

[0049] The pulse generating circuit 200 shown in FIG. 2 includes a circuit 201 and transistors 202 to The circuit 201 corresponds to the circuit 101 shown in FIG. The transistor 202 and the transistor 203 are the same as the transistor 102 shown in FIG. The transistor 204 corresponds to the transistor 103 shown in FIG. In addition, various potentials are applied to the pulse generating circuit 200 from wirings 205 to 212. A potential is output to the wiring 213 and the wiring 214 .

[0050] A shift register can be configured by connecting the above pulse generating circuit 200 in multiple stages. It is possible.

[0051] When the transistors 202 and 203 are of the n-channel type, specifically, the wiring 205 is supplied with the potential VDD, the wiring 206 is supplied with the potential VSS, and the wiring 207 is supplied with the potential VEE. Also, the wiring 208 is supplied with the potential LIN, and the wiring 209 is supplied with the potential RIN. The potential LIN and the potential RIN correspond to the potential Vin in the semiconductor device 100 shown in FIG. 1(A).

[0052] Also, among the clock signals CL1 to CL4, the potentials of any three clock signals are respectively applied to the wirings 210 to 212. In FIG. 2, the potential of the clock signal CL1 is applied to the wiring 21 0, the potential of the clock signal CL2 is applied to the wiring 211, and the potential of the clock signal CL3 is applied to the wiring 21 2, and this case is illustrated as an example. 22.

[0053] The gate of the transistor 202 is connected to the gates of the transistors 203 and 204, its source terminal is connected to the wiring 206, and its drain terminal is connected to the circuit 201 . The source terminal of the transistor 203 is connected to the wiring 206, and its drain terminal is connected to the circuit 201. The source terminal of the transistor 204 is connected to the wiring 207, and its drain terminal is connected to the circuit 201 and the wiring 213 .

[0054] Also, the circuit 201 includes transistors 215 to 223, and capacitance elements 224 and 225. Specifically, the gate of the transistor 215 is connected to the wiring 208, its source terminal is connected to the drain terminal of the transistor 202, and its​ The drain terminal of is connected to wiring 205. The gate of transistor 216 is connected to wiring 211, its source terminal is connected to the drain terminal of transistor 218, and its drain terminal is connected to wiring 205. The gate of transistor 217 is connected to wiring 209, its source terminal is connected to the gates of transistors 202, 203, and 204, and its drain terminal is connected to wiring 205. The gate of transistor 218 is connected to wiring 212, and its source terminal is connected to the gates of transistors 202, 203, and 204. The gate of transistor 219 is connected to wiring 208, its source terminal is connected to wiring 206, and its drain terminal is connected to the gates of transistors 202, 203, and 204. The gate of transistor 220 is connected to wiring 205, and one of its source and drain terminals is connected to the source terminal of transistor 215 and the drain terminal of transistor 202, and the other is connected to the gate of transistor 221. The source terminal of transistor 221 is connected to wiring 214, and its drain terminal is connected to wiring 210. The gate of transistor 222 is connected to wiring 205, and one of its source and drain terminals is connected to the source terminal of transistor 215 and the drain terminal of transistor 202, and the other is connected to the gate of transistor 223. The source terminal of transistor 223 is connected to wiring 213, and its drain terminal is connected to wiring 210. Capacitor element 2 is connected to wiring 213, and its drain terminal is connected to wiring 210. Capacitor element 2 24 has one of its electrodes connected to the gate of transistor 221 and the other electrode connected to the wiring 214. One of the electrodes of capacitor element 225 is connected to the gate of transistor 223 and the other electrode is connected to the wiring 213.

[0055] The operation of the pulse generation circuit 200 shown in FIG. 2 will be described using the timing chart shown in FIG. 3.

[0056] As shown in FIG. 3, in period t1, the potential of the clock signal CL1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a high level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209

[0057] is at a low level. Therefore, in period t1, in the pulse generation circuit 200, transistors 202 to 204, transistor 216, transistor 218, transistor 220, and transistor 222 turn on. Also, transistors 215, 217, 219, transistor 221, and transistor 223 turn off. Therefore, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output from the wiring 214 as the potential SROUT.

[0058] Next, as shown in FIG. 3, in period t2, the potential of the clock signal C L1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a low level, the potential of the clock signal CL3 applied to the wiring 212 The potential LIN applied is at a high level, and the potential RIN applied to the wiring 209 is at a low level. .

[0059] Therefore, in the period t2, in the pulse generation circuit 200, the transistors 215, 218 to 223 turn on. Also, the transistors 202 to 204, 216, and 217 turn off. Thus, the potential of the wiring 210 is output from the wiring 213 as the potential GOUT and from the wiring 214 as the potential SROUT.

[0060] Next, as shown in FIG. 3, in the period t3, the potential of the clock signal CL1 applied to the wiring 210 is at a high level, the potential of the clock signal CL2 applied to the wiring 211 is at a low level, the potential of the clock signal CL3 applied to the wiring 212 is at a low level, the potential LIN applied to the wiring 208 is at a high level, and the potential RIN applied to the wiring 209 is at a low level. .

[0061] Therefore, in the period t3, in the pulse generation circuit 200, the transistors 215, 219, 221, and 223 turn on. Also, the transistors 202 to 204, 216 to 218, 220, and 222 turn off. Thus, the potential of the wiring 210 is output from the wiring 213 as the potential GOUT and from the wiring 214 as the potential SROUT.

[0062] Next, as shown in FIG. 3, in the period t4, the potential of the clock signal C applied to the wiring 210 The potential of L1 is at a high level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a low level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a low level. The potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a low level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a low level. Therefore, in the period t4, in the pulse generation circuit 200, the transistors 216, 221, and 223 are turned on. Also, the transistors 202 to 204, 215, 217 to 220, and 222 are turned off. Thus, the potential of the wiring 210 is output from the wiring 213 as the potential GOUT and from the wiring 214 as the potential SROUT. 。

[0063] Therefore, in the period t4, in the pulse generation circuit 200, the transistors 216, 221, and 223 are turned on. Also, the transistors 202 to 204, 215, 217 to 220, and 222 are turned off. Thus, the potential of the wiring 210 is output from the wiring 213 as the potential GOUT and from the wiring 214 as the potential SROUT. Next, as shown in FIG. 3, in the period t5, the potential of the clock signal CL1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a high level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a high level. Next, as shown in FIG. 3, in the period t5, the potential of the clock signal CL1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a high level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a high level. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU.

[0064] Next, as shown in FIG. 3, in the period t5, the potential of the clock signal CL1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a high level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a high level. Next, as shown in FIG. 3, in the period t5, the potential of the clock signal CL1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a high level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a high level. Next, as shown in FIG. 3, in the period t5, the potential of the clock signal CL1 applied to the wiring 210 is at a low level, the potential of the clock signal CL2 applied to the wiring 211 is at a high level, the potential of the clock signal CL3 applied to the wiring 212 is at a high level, the potential LIN applied to the wiring 208 is at a low level, and the potential RIN applied to the wiring 209 is at a high level. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. 。

[0065] Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. Therefore, in the period t5, in the pulse generation circuit 200, the transistors 202 to 204, 216 to 218, 220, and 222 are turned on. Also, the transistors 215, 219, 221, and 223 are turned off. Thus, the potential of the wiring 207 is output from the wiring 213 as the potential GOUT. Also, the potential of the wiring 206 is output as the potential SROU. T is output from the wiring 214.

[0066] In the above operation, the transistor 204 is turned off from the period t2 to the period t4. In particular, during periods t3 and t4, the clock signal CL1 applied to the wiring 210 When the transistor 204 is on because the potential is at a high level, the transistor 204 A current flows between the wiring 210 and the wiring 207 through the transistor 223. In one embodiment of the present invention, the gate and source terminals of the transistor 204 are electrically separated. Specifically, when the transistor 204 is turned off, the gate of the transistor 204 The potential of the wiring 206 is applied to the source terminal of the transistor 204, and the potential of the wiring 207 is applied to the source terminal of the transistor 205. Therefore, even if a current flows between the wiring 210 and the wiring 207, The electric potential of the wiring 207 increases due to the current, and the gate voltage Vgs of the transistor 204 exceeds the threshold As the voltage Vth approaches, transistor 204 can eventually be turned off.

[0067] FIG. 4 shows a shift register constructed by connecting the above-mentioned pulse generating circuit 200 in multiple stages. is shown as an example.

[0068] The shift register shown in FIG. 4 includes pulse generating circuits 200_1 to 200_y. The pulse generating circuits 200_1 to 200_y each have the same configuration as shown in FIG. 2. However, the wiring 210 shown in FIG. The wiring 212 is connected to any three of the clock signals CL1 to CL4. The potentials are given as follows:

[0069] Specifically, in the pulse generation circuit 200_4m+1, the clock signal CL1 is supplied to the wiring 210, the clock signal CL2 is supplied to the wiring 211, and the clock signal CL3 is supplied to the wiring 212. In the pulse generation circuit 200_4m+2, the clock signal CL2 is supplied to the wiring 210, the clock signal CL3 is supplied to the wiring 211, and the clock signal CL4 is supplied to the wiring 212. In the pulse generation circuit 200_ 4m+3, the clock signal CL3 is supplied to the wiring 210, the clock signal CL4 is supplied to the wiring 211, and the clock signal CL1 is supplied to the wiring 212. In the pulse generation circuit 200_4m+4, the clock signal CL4 is supplied to the wiring 210, the clock signal CL1 is supplied to the wiring 211, and the clock signal CL2 is supplied to the wiring 212. Here, m is an arbitrary integer that satisfies the condition that the total number of the pulse generation circuits 200 is y.

[0070] Also, in the shift register shown in FIG. 4, the positions of the wirings 208 to 214 of the pulse generation circuit 200_j (j is a natural number less than or equal to y) are schematically shown in FIG. 6. As can be seen from FIGS. 4 and 6, the potential SROUTj-1 output from the wiring 214 of the previous-stage pulse generation circuit 200_j-1 is supplied to the wiring 208 of the pulse generation circuit 200_j as the potential LIN. However, the potential of the start pulse signal SP is supplied to the wiring 208 of the first-stage pulse generation circuit 200_1.

[0071] Also, the potential SROUTj+2 output from the wiring 214 of the two-stage subsequent pulse generation circuit 200_ j+2 is supplied to the wiring 209 of the pulse generation circuit 200_j as the potential RIN. However, the potential RIN is supplied to the wiring 208 of the (y-1)-stage pulse generation circuit 200_y-1. _y-1 is provided, and the wiring 208 of the pulse generation circuit 200_y in the y-th stage is supplied with the potential RIN _y is configured to be supplied. The potential RIN_y-1 is assumed to be the potential SROUTy+1 that would be output from the pulse generation circuit 200_y+1 when assuming the existence of the pulse generation circuit 200_y+1 is assumed. Also, the potential RIN_y is assumed to be the potential SROUTy+2 that would be output from the pulse generation circuit 200_y+2 when assuming the existence of the pulse generation circuit 200_y+2 _y+2 is assumed.

[0072] The potential GOUTj is output from the wiring 213 of the pulse generation circuit 200_j

[0073] Fig. 5 shows the timing charts of the potentials of the clock signals CL1 to CL4, the start pulse signal SP and the potentials of the potentials GOUT1 to GOUT3. The clock signals CL1 to CL4 have waveforms in which the rising timing of the potential is shifted backward by one-fourth of a cycle each. The shift register shown in Fig. 4 operates according to the above signals. And the potential GOUT1 to the potential GOUTy having a pulse width of one-half of a cycle of the above clock signal and in which the pulses are shifted backward by one-fourth of a cycle of the above clock signal are output

[0074] For example, when supplying the potentials GOUT1 to GOUTy to a wiring called a bus line of a semiconductor display device, such as a scanning line or a signal line, using the shift register shown in Fig. 4 the output-side transistors 204 of the pulse generation circuits 200_1 to 200_y each require a large current supply capacity. Therefore, the transistor 204 ​​​​​​​The channel width W of the transistor 204 is designed to be larger than the channel widths W of the transistors other than the transistor 204 in many cases. Therefore, when the transistor 204 is in the normal-on state, the power consumption of the shift register increases, or phenomena such as the amplitudes of the output potentials GOUT1 to GOUTy becoming small are likely to occur significantly. However, in one embodiment of the present invention, even when the output-side transistor 204 included in each of the pulse generation circuits 200_1 to 200_y is in the normal-on state, the transistor 204 can be turned off when it should be turned off. Therefore, the shift register according to one embodiment of the present invention using the above shift register can suppress the power consumption to be low and prevent the amplitudes of the output potentials GOUT1 to GOUTy from becoming small. Further, a semiconductor display device according to one embodiment of the present invention using the above shift register can suppress the power consumption to be low and prevent the occurrence of display defects caused by the small amplitudes of the signals applied to the bus lines. As a comparative example, consider the case where the wiring 206 and the wiring 207 are electrically connected in the pulse generation circuit 200 shown in FIG. 2. FIG. 7(A) shows the connection relationships of the transistor 204, the transistor 222, the transistor 223, the capacitor element 225, the wiring 205, the wiring 207, and the wiring 210 included in the pulse generation circuit of the comparative example. In the pulse generation circuit of the comparative example, it is assumed that the wiring 207 is connected to the wiring 206 (not shown) and the potential VSS is applied.

[0075]

[0076]

[0077] In addition, in FIG. 7A, the wiring resistance of the wiring 207 is illustrated as a resistor 230. The wiring resistance of the wiring 210 is illustrated as a resistor 231.

[0078] As mentioned above, transistors using amorphous silicon or oxide semiconductors For example, if the channel length L of a transistor is 6 μm, When the width W is 10 μm, the current flowing when the gate voltage Vgs is 0 V is 0.5 μm. In order to increase the current supply capacity of the transistor, the channel width W is increased to 1 It is not uncommon to make the thickness of the transistor about 1000 μm, but the thickness of the transistor having the above current-voltage characteristics is about 1000 μm. If the channel width is increased from 10 μm to 1000 μm, when the gate voltage Vgs is 0 V, The current flowing through the resistor will be 100 times that, or 0.05 mA.

[0079] Assuming that each pulse generator consumes 0.05mA of current, the shift register If the number of stages of the pulse generation circuit in the shift register is 960, the total number of stages of the shift register is about 50. A current of mA will flow.

[0080] Assume that resistor 230 is 100 Ω and resistor 231 is 100 Ω. The transistor 204 is normally on, and as described above, when the gate voltage Vgs is 0 V, Assume that a current of .05 mA flows between the drain terminal of transistor 223 and wiring 210. The connection point is node A, and the connection point between the source terminal of the transistor 204 and the wiring 207 is node When the transistor 204 is turned on, a current flows through the transistor 204, and the potential of the node A falls. The potential of the wiring 207 increases due to the transistor 20 It corresponds to the product of the current flowing through 4, the resistance value of resistor 230, and the number of stages of the shift register. Also, The amount of potential drop in wiring 210 corresponds to the product of the current flowing through transistor 204, the resistance value of resistor 231, and the number of stages of the shift register. Therefore, the amount of potential drop and the amount of potential rise both become a maximum of 5V.

[0081] In FIG. 7(B), the ideal waveform of the potential GOUT output from wiring 213 is shown by solid line 232. The ideal potential GOUT has a potential difference of its pulse corresponding to the difference between potential VSS and potential VDD. Also, in FIG. 7(B), when the potential of wiring 207 rises and the potential in wiring 210 drops, the waveform of the potential GOUT output from wiring 213 is shown by solid line 233. The potential GOUT shown by solid line 233 has a potential difference of its pulse corresponding to the difference between potential VSS + ΔV1 and potential VDD - ΔV2. Since ΔV1 and ΔV2 are about 5V in the above example, it can be seen that the amplitude is significantly reduced from the original amplitude. However, in one aspect of the present invention, even if the output - side transistor 204 is normally - on,

[0082] the transistor 204 can be turned off. Therefore, it is possible to prevent the amplitude of the output potential GOUT from becoming small and to significantly suppress the power consumption.

[0083] (Embodiment 2) A configuration example of a pulse - generating circuit according to one aspect of the present invention will be described.

[0084] The pulse - generating circuit 300 shown in FIG. 8(A) includes a circuit 301 and transistors 302 to transistor 304. Circuit 301 corresponds to circuit 101 shown in FIG. 1(A). . Transistor 302 and transistor 303 correspond to transistor 102 shown in Fig. 1(A). Transistor 304 corresponds to transistor 103 shown in Fig. 1(A).

[0085] By connecting a plurality of stages of the pulse generation circuit 300, a shift register can be configured.

[0086] The gate of transistor 302 is connected to the gates of transistor 303 and transistor 304, its source terminal is connected to wiring 306, and its drain terminal is connected to circuit 301. The source terminal of transistor 303 is connected to wiring 306, and its drain terminal is connected to circuit 301 and wiring 314. The source terminal of transistor 304 is connected to wiring 307, and its drain terminal is connected to circuit 301 and wiring 313.

[0087] Also, circuit 301 has transistors 315 to 320. Specifically, the gate of transistor 315 is connected to wiring 308, its source terminal is connected to the drain terminal of transistor 302, and its drain terminal is connected to wiring 305. The gate of transistor 316 is connected to wiring 309, its source terminal is connected to the gates of transistor 302, transistor 303, and transistor 304, and its drain terminal is connected to wiring 305. The gate of transistor 317 is connected to wiring 310, its source terminal is connected to the gates of transistor 302, transistor 303, and transistor 304, and its drain terminal is connected to wiring 305. ​​​​​​​​​​​exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. When transistors 302 to 304 are n-channel type, specifically, a potential VDD is applied to wiring 305, a potential VSS is applied to wiring 306, and a potential VEE is applied to wiring 307. Also, in addition to the potential Vin in the semiconductor device 100 shown in FIG. 1(A), potentials of various signals such as a clock signal are applied to wirings 308 to 312. Then, a potential GOUT is output from wiring 313 and a potential SROUT is output from wiring 314. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312.

[0088] exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312. exists. The gate of transistor 318 is connected to wiring 308, its source terminal is connected to wiring 306, and its drain terminal is connected to the gates of transistors 302, 303, and 304. The gate of transistor 319 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 314, and its drain terminal is connected to wiring 311. The gate of transistor 320 is connected to the source terminal of transistor 315 and the drain terminal of transistor 302, its source terminal is connected to wiring 313, and its drain terminal is connected to wiring 312.

[0089] The pulse generation circuit 300 shown in FIG. 8(A) can electrically isolate the gate and the source terminal of the output-side transistor 304 with the above configuration. Therefore, even if transistor 304 is normally on and the potential of wiring 307 for supplying a potential to the source terminal of the transistor 304 increases, it can be turned off when it should be turned off. The pulse generation circuit 300 shown in FIG. 8(A) can electrically isolate the gate and the source terminal of the output-side transistor 304 with the above configuration. Therefore, even if transistor 304 is normally on and the potential of wiring 307 for supplying a potential to the source terminal of the transistor 304 increases, it can be turned off when it should be turned off. The pulse generation circuit 300 shown in FIG. 8(A) can electrically isolate the gate and the source terminal of the output-side transistor 304 with the above configuration. Therefore, even if transistor 304 is normally on and the potential of wiring 307 for supplying a potential to the source terminal of the transistor 304 increases, it can be turned off when it should be turned off. The pulse generation circuit 300 shown in FIG. 8(A) can electrically isolate the gate and the source terminal of the output-side transistor 304 with the above configuration. Therefore, even if transistor 304 is normally on and the potential of wiring 307 for supplying a potential to the source terminal of the transistor 304 increases, it can be turned off when it should be turned off. The pulse generation circuit 300 shown in FIG. 8(A) can electrically isolate the gate and the source terminal of the output-side transistor 304 with the above configuration. Therefore, even if transistor 304 is normally on and the potential of wiring 307 for supplying a potential to the source terminal of the transistor 304 increases, it can be turned off when it should be turned off.

[0090] The pulse generation circuit 330 shown in FIG. 8(B) includes a circuit 331 and transistors 332 to 334. The circuit 331 corresponds to the circuit 101 shown in FIG. 1(A). The transistors 332 and 333 correspond to the transistor 102 shown in FIG. 1(A). The transistor 334 corresponds to the transistor 103 shown in FIG. 1(A).

[0091] By connecting a plurality of stages of the above pulse generation circuit 330, a shift register can be configured.

[0092] The gate of the transistor 332 is connected to the gates of the transistors 333 and 334, its source terminal is connected to the wiring 336, and its drain terminal is connected to the circuit 331. The source terminal of the transistor 333 is connected to the wiring 336, and its drain terminal is connected to the circuit 331 and the wiring 345. The source terminal of the transistor 334 is connected to the wiring 337, and its drain terminal is connected to the circuit 331 and the wiring 344. The source terminal of the transistor 334 is connected to the wiring 337, and its drain terminal is connected to the circuit 331 and the wiring 344.

[0093] The circuit 331 also includes transistors 346 to 352. Specifically, the gate of the transistor 346 is connected to the wiring 338, its source terminal is connected to the drain terminal of the transistor 332, and its drain terminal is connected to the wiring 335. The gate of the transistor 347 is connected to the wiring 339, its source terminal is connected to the gates of the transistors 332, 333, and 334, and its drain terminal is connected to the wiring 335. The gate of the transistor 348 is connected to the wiring 335, and its drain terminal is connected to the wiring 335. ​​​​connected to wiring 340, with its source terminal connected to the gates of transistor 332, transistor 333, and transistor 334, and its drain terminal connected to wiring 335. Transistor 349 has its gate connected to wiring 338, its source terminal connected to wiring 336, and its drain terminal connected to the gates of transistor 332, transistor 333, and transistor 334. Transistor 350 has its gate connected to wiring 341, its source terminal connected to the gates of transistor 332, transistor 333, and transistor 334, and its drain terminal connected to wiring 335. Transistor 351 has its gate connected to the source terminal of transistor 346 and the drain terminal of transistor 332, its source terminal connected to wiring 345, and its drain terminal connected to wiring 342. Transistor 352 has its gate connected to the source terminal of transistor 346 and the drain terminal of transistor 332, its source terminal connected to wiring 344, and its drain terminal connected to wiring 343.

[0094] When transistors 332 to 334 are n-channel type, specifically, a potential VDD is applied to wiring 335, a potential VSS is applied to wiring 336, and a potential VEE is applied to wiring 337. Also, in addition to the potential Vin in the semiconductor device 100 shown in FIG. 1(A), potentials of various signals such as a clock signal are applied to wirings 338 to 343. Then, a potential GOUT is output from wiring 344, and a potential SROUT is output from wiring 345.

[0095] The pulse generation circuit 330 shown in FIG. 8(B) can electrically isolate the gate and the source terminal of the transistor 33 4. Therefore, even if the transistor 3 34 is in the normal-on state and the potential of the wiring 337 for supplying a potential to the source terminal of the transistor 334 rises, the transistor 334 can be turned off when it should be turned off.

[0096] The pulse generation circuit 360 shown in FIG. 9(A) includes a circuit 361 and transistors 362 to transistors 364. The circuit 361 corresponds to the circuit 101 shown in FIG. 1(A) . The transistors 362 and 363 correspond to the transistor 1 02 shown in FIG. 1(A). The transistor 364 corresponds to the transistor 103 shown in FIG. 1(A) .

[0097] By connecting a plurality of stages of the pulse generation circuit 360, a shift register can be configured .

[0098] The gate of the transistor 362 is connected to the gates of the transistors 363 and 364, its source terminal is connected to the wiring 366, and its drain terminal is connected to the circuit 361 . The source terminal of the transistor 363 is connected to the wiring 366, and its drain terminal is connected to the circuit 361 and the wiring 375. The source terminal of the transistor 364 is connected to the wiring 367, and its drain terminal is connected to the circuit 361 and the wiring 374 .

[0099] Further, the circuit 361 includes transistors 376 to 382. Specifically For transistor 376, its gate is connected to wiring 368, its source terminal is connected to the drain terminal of transistor 362, and its drain terminal is connected to wiring 365. For transistor 377, its gate is connected to wiring 365, and one of its source terminal and drain terminal is connected to the source terminal of transistor 376 and the drain terminal of transistor 362, and the other is connected to the gates of transistors 381 and 382. For transistor 378, its gate is connected to wiring 369, its source terminal is connected to the gates of transistors 362, 363, and 364, and its drain terminal is connected to wiring 365. For transistor 379, its gate is connected to wiring 368, its source terminal is connected to wiring 366, and its drain terminal is connected to the gates of transistors 362, 363, and 364. For transistor 380, its gate is connected to wiring 370, its source terminal is connected to the gates of transistors 362, 363, and 364, and its drain terminal is connected to wiring 365. For transistor 381, its source terminal is connected to wiring 375, and its drain terminal is connected to wiring 371. For transistor 382, its source terminal is connected to wiring 374, and its drain terminal is connected to wiring 372. When transistors 362 to 364 are n-channel type, specifically, a potential VDD is applied to wiring 365, a potential VSS is applied to wiring 366, and a potential VEE is applied to wiring 367. Also, to wirings 368 to 372, the half shown in Fig. 1(A) is applied. is applied. is applied. is applied. is applied. is applied. is applied.

[0100] When transistors 362 to 364 are n-channel type, specifically, a potential VDD is applied to wiring 365, a potential VSS is applied to wiring 366, and a potential VEE is applied to wiring 367. Also, to wirings 368 to 372, the half shown in Fig. 1(A) is applied. In addition to the potential Vin in the conductor device 100, potentials of various signals such as a clock signal are supplied. Then, the potential GOUT is output from the wiring 374, and the potential SROUT is output from the wiring 375.

[0101] The pulse generation circuit 360 shown in FIG. 9(A) can electrically isolate the gate and the source terminal of the output - side transistor 364 with the above - described configuration. Therefore, even if the transistor 364 is normally - on and the potential of the wiring 367 for supplying a potential to the source terminal of the transistor 364 rises, the transistor 364 can be turned off when it should be turned off.

[0102] The pulse generation circuit 400 shown in FIG. 9(B) includes a circuit 401 and transistors 402 to 404. The circuit 401 corresponds to the circuit 101 shown in FIG. 1(A). The transistors 402 and 403 correspond to the transistor 102 shown in FIG. 1(A). The transistor 404 corresponds to the transistor 103 shown in FIG. 1(A).

[0103] By connecting a plurality of stages of the above - described pulse generation circuit 400, a shift register can be configured.

[0104] The gate of the transistor 402 is connected to the gates of the transistors 403 and 404, its source terminal is connected to the wiring 406, and its drain terminal is connected to the circuit 401. The source terminal of the transistor 403 is connected to the wiring 406, and its drain terminal is connected to the circuit 401 and the wiring 415. The transistor 404 ​​​​​​​​​​​​​Its source terminal is connected to wiring 407, and its drain terminal is connected to circuit 401 and wiring 414 is connected.

[0105] Also, circuit 401 has transistors 416 to 423. Specifically transistor 416 has its gate connected to wiring 408, its source terminal connected to the drain terminal of transistor 402, and its drain terminal connected to wiring 405 is connected. Transistor 417 has its gate connected to wiring 405, one of its source and drain terminals connected to the source terminal of transistor 416 and the drain terminal of transistor 402, and the other connected to the gate of transistor 421. Transistor 418 has its gate connected to wiring 409, its source terminal connected to the gates of transistors 402, 403, and 404, and its drain terminal connected to wiring 405 is connected. Transistor 419 has its gate connected to wiring 408, its source terminal connected to wiring 406, and its drain terminal connected to the gates of transistors 402, 403, and 404. Transistor 420 has its gate connected to wiring 410, its source terminal connected to the gates of transistors 402, 403, and 404, and its drain terminal connected to wiring 405. Transistor 421 has its source terminal connected to wiring 415 and its drain terminal connected to wiring 411. Transistor 422 has its gate connected to wiring 405, one of its source and drain terminals connected to the gate of transistor 421, and the other connected to the gate of transistor 423 is connected. is connected. is connected. is connected. is connected. is connected. is connected. is connected. is connected. is connected. is connected. is connected. The source terminal of transistor 423 is connected to wiring 414, and its drain terminal is connected to wiring 412.

[0106] When transistors 402 to 404 are n-channel type, specifically, potential VDD is applied to wiring 405, potential VSS is applied to wiring 406, and potential VEE is applied to wiring 407. In addition to potential Vin in the semiconductor device 100 shown in FIG. 1(A), potentials of various signals such as a clock signal are applied to wirings 408 to 412. Then, potential GOUT is output from wiring 414, and potential SROUT is output from wiring 415.

[0107] The pulse generation circuit 400 shown in FIG. 9(B) can electrically isolate the gate and the source terminal of the output-side transistor 40 4 with the above configuration. Therefore, even if transistor 4 04 is normally on and the potential of wiring 407 for supplying potential to the source terminal of the transistor 404 increases accordingly, the transistor 404 can be turned off when it should be turned off.

[0108] The pulse generation circuit 430 shown in FIG. 10 includes a circuit 431 and transistors 432 to 43 4. The circuit 431 corresponds to the circuit 101 shown in FIG. 1(A). The transistors 432 and 433 correspond to the transistor 102 shown in FIG. 1(A). The transistor 434 corresponds to the transistor 103 shown in FIG. 1(A).

[0109] By connecting a plurality of stages of the above pulse generation circuit 430, a shift register can be configured. ​

[0110] Transistor 432 has its gate connected to the gates of transistor 433 and transistor 434, its source terminal connected to wiring 436, and its drain terminal connected to circuit 431. Transistor 433 has its source terminal connected to wiring 436, and its drain terminal connected to circuit 431 and wiring 445. Transistor 434 has its source terminal connected to wiring 437, and its drain terminal connected to circuit 431 and wiring 444.

[0111] Also, circuit 431 includes transistors 446 to 453. Specifically, transistor 446 has its gate connected to wiring 438, its source terminal connected to the drain terminal of transistor 432, and its drain terminal connected to wiring 435. Transistor 447 has its gate connected to wiring 439, its source terminal connected to the gates of transistor 432, transistor 433, and transistor 434, and its drain terminal connected to wiring 435. Transistor 448 has its gate connected to wiring 440, its source terminal connected to the gates of transistor 432, transistor 433, and transistor 434, and its drain terminal connected to wiring 435. Transistor 449 has its gate connected to wiring 438, its source terminal connected to wiring 436, and its drain terminal connected to the gates of transistor 432, transistor 433, and transistor 434. Transistor 450 has its gate connected to wiring 435, and either its source terminal or its drain terminal is connected to the source or drain terminal of transistor 446. is connected to the source terminal and the drain terminal of transistor 432, and the other is connected to the gate of transistor 451. The source terminal of transistor 451 is connected to wiring 445 , and its drain terminal is connected to wiring 441. The gate of transistor 452 is connected to wiring 435 , and one of its source terminal and drain terminal is connected to the source terminal of transistor 446 and the drain terminal of transistor 432, and the other is connected to the gate of transistor 453. The source terminal of transistor 453 is connected to wiring 444, and its drain terminal is connected to wiring 442.

[0112] When transistors 432 to 434 are of n-channel type, specifically, a potential VDD is applied to wiring 435, a potential VSS is applied to wiring 436, and a potential VEE is applied to wiring 437 . In addition, to the potential Vin in the semiconductor device 100 shown in FIG. 1(A), potentials of various signals such as a clock signal are applied to wirings 438 to 442 . Then, a potential GOUT is output from wiring 444, and a potential SROUT is output from wiring 445 .

[0113] The pulse generation circuit 430 shown in FIG. 10 can electrically isolate the gate and the source terminal of the output-side transistor 434 with the above configuration. Therefore, even if transistor 434 is in the normal-on state and, as a result, the potential of wiring 437 for supplying a potential to the source terminal of the transistor 434 increases, the transistor 434 can be turned off when it should be turned off.

[0114] This embodiment can be implemented in appropriate combination with other embodiments.

[0115] (Embodiment 3) A configuration example of an inverter, which is one of the semiconductor devices according to an aspect of the present invention, will be described.

[0116] FIG. 11 shows an example of an inverter according to an aspect of the present invention. The inverter 50 shown in FIG. 11 0 has a circuit 501, a transistor 502, and a transistor 503. The circuit 50 1 corresponds to the circuit 101 shown in FIG. 1(A). The transistor 502 is the same as the transistor 102 shown in FIG. 1(A) . The transistor 503 corresponds to the transistor 103 shown in FIG. 1(A).

[0117] The gate of the transistor 502 is connected to the wiring 509, its source terminal is connected to the wiring 50 5, and its drain terminal is connected to the circuit 501. The transistor 503 has its gate connected to the wiring 509, its source terminal connected to the wiring 506, and its drain terminal connected to the circuit 501 and the wiring 508.

[0118] Further, the circuit 501 has transistors 510 to 512 and a capacitive element 513 . Specifically, the gate of the transistor 510 is connected to the wiring 507, its source terminal is connected to the drain terminal of the transistor 502, and its drain terminal is connected to the wiring 504. The gate of the transistor 511 is connected to the wiring 504 , and one of its source terminal and drain terminal is connected to the source terminal of the transistor 510 and the drain terminal of the transistor 502, and the other is connected to the gate of the transistor 512 . is provided. The source terminal of transistor 512 is connected to the drain terminal of transistor 503 and wiring 508, and its drain terminal is connected to wiring 504. The capacitive element 513 has one of its electrodes connected to the gate of transistor 512 and the other electrode connected to wiring 508.

[0119] When transistors 502 and 503 are of the n-channel type, specifically, a potential VDD is applied to wiring 504, a potential VSS is applied to wiring 505, and a potential VEE is applied to wiring 506. Also, a clock signal potential is applied to wiring 507, and a potential Vin in the semiconductor device 100 shown in FIG. 1(A) is applied to wiring 509. In FIG. 1 1, the case where the potential Vin is the potential SROUT output from wiring 214 of the pulse generation circuit 200 shown in FIG. 2 is exemplified. And from wiring 508, a potential SROUTb obtained by inverting the polarity of the potential SROUT is output.

[0120] The inverter 500 shown in FIG. 11 can electrically isolate the gate of the output-side transistor 503 from its source terminal by the above configuration. Therefore, even if transistor 503 is a normally-on transistor and thereby the potential of wiring 506 for supplying a potential to the source terminal of the transistor 503 increases, it can be turned off when the transistor 503 should be turned off.

[0121] This embodiment can be implemented in appropriate combination with other embodiments.

[0122] (Embodiment 4) ​Taking an EL display device as an example, the pixel and driving circuit of the semiconductor display device according to one aspect of the present invention The cross-sectional structure will be described with reference to FIG. 12. FIG. 12 shows a cross-sectional view of a pixel 840 and a driving circuit 841 as an example.

[0123] In FIG. 12, the pixel 840 includes a light-emitting element 832 and a transistor 831 that controls the supply of current to the light-emitting element 832. In addition to the light-emitting element 832 and the transistor 831, the pixel 840 may have various semiconductor elements such as a transistor that controls the input of an image signal to the pixel 840 and a capacitive element that holds the potential of the image signal.

[0124] Also, in FIG. 12, the driving circuit 841 includes a transistor 830 and a capacitive element 833 for holding the gate voltage of the transistor 830. Specifically, the transistor 830 corresponds to the output-side transistor of a shift register that corresponds to a part of the driving circuit 841. In addition to the transistor 830 and the capacitive element 833, the driving circuit 841 may have various semiconductor elements such as transistors and capacitive elements.

[0125] The transistor 831 has a conductive film 816 that functions as a gate, a gate insulating film 802 on the conductive film 816, a semiconductor film 817 located on the gate insulating film 802 at a position overlapping the conductive film 816, and conductive films 815 and 818 that function as source terminals or drain terminals and are located on the semiconductor film 817. The conductive film 816 also functions as a scanning line.

[0126] The transistor 830 has a conductive film that functions as a gate on a substrate 800 having an insulating surface 812, a gate insulating film 802 on the conductive film 812, and at a position overlapping the conductive film 812 a semiconductor film 813 located on the gate insulating film 802, and a conductive film 814 and a conductive film 819 located on the semiconductor film 813, functioning as a source terminal or a drain terminal and having.

[0127] The capacitor element 833 includes a conductive film 812, a gate insulating film 802 on the conductive film 812, and a conductive film 819 located on the gate insulating film 802 at a position overlapping the conductive film 812 on a substrate 800 having an insulating surface. and having. On the conductive films 814, 815, 818, and 819, an insulating film 820 and an insulating film 821 are provided so as to be laminated in this order. And on the insulating film 821,

[0128] a conductive film 822 functioning as an anode is provided. The conductive film 822 is connected to the conductive film 818 through a contact hole 823 formed in the insulating film 820 and the insulating film 821. And. Also, an insulating film 824 having an opening through which a part of the conductive film 822 is exposed is provided on the insulating film 821. On a part of the conductive film 822 and the insulating film 824, an EL layer 825 and a conductive film 826 functioning as a cathode are provided so as to be laminated in this order. The region where the conductive film 822, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. And. are connected.

[0129] In addition, an insulating film 824 having an opening through which a part of the conductive film 822 is exposed is provided on the insulating film 821. On a part of the conductive film 822 and the insulating film 824, an EL layer 825 and a conductive film 826 functioning as a cathode are provided so as to be laminated in this order. The region where the conductive film 822, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. And. On a part of the conductive film 822 and the insulating film 824, an EL layer 825 and a conductive film 826 functioning as a cathode are provided so as to be laminated in this order. The region where the conductive film 822, the EL layer 825, and the conductive film 826 overlap corresponds to the light-emitting element 832. And. corresponds.

[0130] Note that in one aspect of the present invention, the transistors 830 and 831 may use a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, for the semiconductor film, or a wide-gap semiconductor such as an oxide semiconductor may be used for the semiconductor film. And. be used. It may be okay.

[0131] When a semiconductor such as silicon or germanium, which is amorphous, microcrystalline, polycrystalline or single-crystalline, is used for the semiconductor films of transistors 830 and 831, an impurity element that imparts one conductivity is added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. For example, by adding phosphorus or arsenic to the semiconductor film, an impurity region having n-type conductivity can be formed. Also, for example, by adding boron to the semiconductor film, an impurity region having p-type conductivity can be formed.

[0132] When an oxide semiconductor is used for the semiconductor films of transistors 830 and 831, a dopant may be added to the semiconductor film to form an impurity region that functions as a source terminal or a drain terminal. The addition of the dopant can use the ion implantation method. The dopant can be, for example, a noble gas such as helium, argon, or xenon, or a group 15 atom such as nitrogen, phosphorus, arsenic, or antimony. For example, when nitrogen is used as the dopant, the concentration of nitrogen atoms in the impurity region is 5×10 19 / cm 3 or more and 1× 10 22 / cm 3 or less, which is desirable.

[0133] Note that as the silicon semiconductor, amorphous silicon produced by a vapor growth method such as the plasma CVD method or sputtering method, polycrystalline silicon obtained by crystallizing amorphous silicon by treatment such as laser annealing, or hydrogen ions or the like are implanted into a single-crystalline silicon wafer to form a surface layer It is possible to use single-crystalline silicon from which a part has been peeled off, etc.

[0134] Note that as the oxide semiconductor, it is preferable to contain at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. Further, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to have gallium (Ga) in addition to them. Also, as a stabilizer, it is preferable to have tin (Sn). Further, as a stabilizer, it is preferable to have hafnium (Hf). Also, as a stabilizer, it is preferable to have aluminum (Al).

[0135] Also, as other stabilizers, it may contain any one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), which are lanthanoids.

[0136] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn-based oxide which is a binary metal oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide (also denoted as IGZO) which is a ternary metal oxide, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide Oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides , In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides , In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, I n-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In -Lu-Zn-based oxides, In-Sn-Ga-Zn-based oxides which are oxides of quaternary metals, I n-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al- Zn-based oxides, In-Sn-Hf-Zn-based oxides, In-Hf-Al-Zn-based oxides can be used. Further, the above oxide semiconductor may contain silicon.

[0137] Note that, for example, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Further, it may contain metal elements other than In, Ga, and Zn. The In-Ga-Zn-based oxide has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high mobility, so it is suitable as a semiconductor material used in semiconductor devices.

[0138] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) atomic ratio In-Ga-Zn-based oxides and oxides in the vicinity of its composition can be used. Alternatively, In:Sn:Zn = 1: 1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having a molecular ratio or an oxide having a composition close to that.

[0139] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0140] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and the acid The reduced electron vacancies result in a highly purified oxide semiconductor. A de semiconductor is an i-type (intrinsic semiconductor) or is very close to an i-type. Therefore, the off-state current of a transistor including the oxide semiconductor is extremely low. The band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. More preferably, the concentration of impurities such as moisture or hydrogen is sufficiently reduced. In addition, an oxide semiconductor film that has been highly purified by reducing oxygen vacancies is used. This allows the off-state current of the transistor to be reduced.

[0141] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor for a semiconductor film is low. For example, when the channel width is 1×10 6 μm Even with a device with a channel length of 10 μm, the voltage between the source and drain terminals (drain voltage When the applied voltage is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-state current normalized by the channel width of the transistor was found to be 100 zA / μm or less. In addition, the capacitance element and the transistor are connected to each other, so that current can flow into or out of the capacitance element. The off-state current was measured using a circuit that controls the outflow of charge using the transistor. In the measurement, a highly purified oxide semiconductor film was placed in a channel formation region of the transistor. The off-state current of the transistor is measured based on the change in the amount of charge per unit time of the capacitor. As a result, when the voltage between the source terminal and the drain terminal of the transistor is 3V, several It was found that an even lower off-current of 10 yA / μm could be obtained. In a transistor in which an oxide semiconductor film having a crystalline structure is used for a channel formation region, the off-state current is This is significantly lower than that of a silicon-based transistor having a low thermal conductivity.

[0142] Unless otherwise specified, in this specification, the off-state current is In this case, the drain terminal is set to a higher potential than the source terminal and gate. When the potential of the gate is 0 V or less with respect to the potential of the transistor, In this specification, the off-state current refers to the current that flows between the p-channel and p-channel terminals. In a diode-type transistor, the drain terminal is at a lower potential than the source terminal and gate. In this state, when the potential of the gate is 0V or higher with respect to the potential of the source terminal as the reference In other words, it refers to the current that flows between the source terminal and the drain terminal.

[0143] For example, the oxide semiconductor film may be formed using In (indium), Ga (gallium), and Zn ( It can be formed by sputtering using a target containing In-Ga- When forming a Zn-based oxide semiconductor film by sputtering, preferably, the atomic ratio is In :Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4, and a target of an In-Ga-Zn-based oxide is used. By using a target of an In-Ga-Zn-based oxide having the above atomic ratio to form an oxide semiconductor film, polycrystals or CAAC-OS described later are likely to be formed. Also, the filling rate of the target containing In, Ga, and Zn is 90% or more and 100% or less, preferably 95% or more and 10 0% less. By using a target with a high filling rate, the formed oxide semiconductor film becomes a dense film.

[0144] In addition, when using a material of an In-Zn-based oxide as the oxide semiconductor, the atomic ratio composition of the metal elements in the target used is, in terms of atomic ratio, In:Zn = 50:1 to 1:2 (in terms of molar ratio, In2O3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (in terms of molar ratio, In2O3:ZnO = 10:1 to 1:2), more preferably In:Zn = 1.5:1 to 15:1 (in terms of molar ratio, In2O3:ZnO = 3:4 to 15:2). For example, for the formation of an oxide semiconductor film that is an In-Zn-based oxide, the target used is such that when the atomic ratio is In:Zn:O = X:Y:Z, Z > 1.5X + Y . By keeping the ratio of Zn within the above range, an improvement in mobility can be achieved.

[0145] Specifically, for the oxide semiconductor film, a substrate is held in a processing chamber maintained in a reduced-pressure state, and while removing residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the above-mentioned ta ​​​It may be formed using a target. During film formation, the substrate temperature may be 100°C or higher and 600°C or lower, preferably it may also be 200°C or higher and 400°C or lower. By forming the film while heating the substrate, the impurity concentration in the formed oxide semiconductor film can be reduced. Also, damage due to sputtering is reduced. To remove residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as an exhaust means, a turbo pump with a cold trap added may be used. When evacuating the processing chamber using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. (more preferably compounds containing carbon atoms) are exhausted, so the concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced.

[0146] Note that in the oxide semiconductor film formed by sputtering or the like, there may be a large amount of moisture or hydrogen ( including hydroxyl groups) as impurities. Since moisture or hydrogen easily forms donor levels, it is an impurity for the oxide semiconductor. Therefore, in one aspect of the present invention, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film (dehydration or dehydrogenation), the oxide semiconductor film is subjected to heat treatment in a reduced-pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or an ultra-dry air (when measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy ) method, the moisture content is 20 ppm (dew point conversion of -55°C) or less , preferably 1 ppm or less, preferably 10 ppb or less of air) atmosphere.

[0147] ​​​​​By subjecting the oxide semiconductor film to a heat treatment, moisture or hydrogen in the oxide semiconductor film can be desorbed. Specifically, the heat treatment may be performed at a temperature of 250°C or higher and 750°C or lower, preferably 400°C or higher and lower than the distortion point of the substrate. For example, it may be performed at about 500°C for 3 minutes or more and 6 minutes or less. If the RTA method is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time, so that the treatment can be performed even at a temperature exceeding the distortion point of the glass substrate.

[0148] Note that oxygen may be desorbed from the oxide semiconductor film by the above heat treatment, and oxygen vacancies may be formed in the oxide semiconductor film. Therefore, in one aspect of the present invention, an oxygen-containing insulating film is used as an insulating film such as a gate insulating film in contact with the oxide semiconductor film. Then, after forming the oxygen-containing insulating film, by performing a heat treatment, oxygen is supplied from the insulating film to the oxide semiconductor film. With the above configuration, oxygen vacancies serving as donors can be reduced, and the stoichiometric composition of the oxide semiconductor contained in the oxide semiconductor film can be satisfied. It is preferable that the semiconductor film contains an amount of oxygen exceeding the stoichiometric composition. As a result, the oxide semiconductor film can be made closer to the i-type, the variation in the electrical characteristics of the transistor due to oxygen vacancies can be reduced, and the improvement in the electrical characteristics can be realized.

[0149] Note that the heat treatment for supplying oxygen to the oxide semiconductor film is preferably performed at 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower, in an atmosphere of nitrogen, ultra-dry air, or a rare gas (argon, helium, etc.). The above gas desirably has a water content of 20 ppm or less, preferably 1 ppm or less, and more preferably 10 ppb or less.

[0150] The oxide semiconductor may be amorphous or crystalline. In the latter case, it may be a single crystal, a polycrystal, or a structure partially having crystallinity. It may be composed of an amorphous structure, a structure containing a crystalline portion in an amorphous structure, or a non-amorphous structure. An example of a structure having a portion with crystallinity is a structure having a c-axis orientation and an ab-plane. It has a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the surface or interface, and has a perpendicular c-axis. When viewed from the perpendicular direction, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers, In the b-plane, the crystals have different a-axis or b-axis orientations (rotated around the c-axis). Things(CAAC-OS:C Axis Aligned Crystalline Oxi de Semiconductor.) may also be used.

[0151] In a broad sense, CAAC-OS is a non-single crystal that has three crystals perpendicular to the ab plane. The atomic arrangement is a square, hexagonal, equilateral triangle, or equilateral hexagon, and the direction is perpendicular to the c-axis. From the viewpoint of the structure, oxides that contain a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers, are called say.

[0152] CAAC-OS is not a single crystal, but it is not composed only of amorphous matter. Although CAAC-OS contains crystalline parts, the boundary between one crystalline part and another crystalline part cannot be clearly determined. Sometimes it’s impossible to tell.

[0153] A part of oxygen constituting CAAC-OS may be replaced by nitrogen. The c-axes of the individual crystal parts constituting the CAAC-OS are aligned in a certain direction (for example, The CAAC-OS surface may be aligned in a direction perpendicular to the plate surface. - The normal of the ab plane of each crystal part constituting the -OS may be oriented in a fixed direction (for example, a direction perpendicular to the substrate surface on which CAAC-OS is formed, the surface of CAAC-OS, etc.).

[0154] Depending on its composition and the like, CAAC-OS may or may not have translucency to visible light. not have it.

[0155] As an example of such CAAC-OS, when observed from a direction perpendicular to the film surface or the support substrate surface in the case of being formed in a film shape, a triangular or hexagonal atomic arrangement is recognized, and when observing the film cross-section a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized. crystals can also be cited.

[0156] Next, an example of a specific configuration of the transistor included in the semiconductor device of the present invention will be described .

[0157] The transistor shown in FIG. 13(A) is of a bottom gate type with a channel etch structure.

[0158] The transistor shown in FIG. 13(A) has a gate electrode (gate tr) 1602 formed on an insulating surface, a gate insulating film 1603 on the gate electrode 1602, and a semiconductor film 1604 overlapping the gate electrode 160 3, and a conductive film 1605 and a conductive film 1606 formed on the semiconductor film 1604. Further, the transistor has an insulating film 1607 formed on the semiconductor film 1604, the conductive film 1605, and the conductive film 1606 and may include it in its components.

[0159] Note that the transistor shown in FIG. 13(A) is insulated at a position overlapping the semiconductor film 1604 ​​It may further have a back gate electrode formed on the edge film 1607.

[0160] The transistor shown in Fig. 13(B) is of the bottom gate type with a channel protection structure.

[0161] And the transistor shown in Fig. 13(B) has a gate electrode 161 2 formed on the insulating surface, a gate insulating film 1613 on the gate electrode 1612, and a semiconductor film 1614 overlapping the gate electrode 1612 on the gate insulating film 1613. And a channel protection film 1618 formed on the semiconductor film 1614, and conductive films 1615 and 1616 formed on the semiconductor film 1614. Further, the transistor may include an insulating film 1617 formed on the channel protection film 1618, the conductive film 1615, and the conductive film 1616 as its components.

[0162]

[0163] Note that the transistor shown in Fig. 13(B) may further have a back gate electrode formed on the insulating film 1617 at a position overlapping the semiconductor film 1614.

[0163] By providing the channel protection film 1618, damage such as film reduction due to plasma or etching agent during etching in subsequent processes can be prevented for the portion that becomes the channel formation region of the semiconductor film 1614. Therefore, the reliability of the transistor can be improved.

[0164]

[0165] The transistor shown in Fig. 13(C) is of the bottom gate type with a bottom contact structure.

[0165] And the transistor shown in Fig. 13(C) has a gate electrode 162 formed on the insulating surface. ​​2, a gate insulating film 1623 on the gate electrode 1622, and a conductive film 1625, a conductive film 1626, and on the gate insulating film 1623, the gate electrode 1622 and overlap, and a semiconductor film 162 4 formed on the conductive films 1625 and 1626. Further, the transistor may include an insulating film 1627 formed on the conductive films 1625, 1626, and the semiconductor film 1624 in its components.

[0166] Note that the transistor shown in Fig. 13(C) may further have a back gate electrode formed on the insulating film 1627 at a position overlapping the semiconductor film 1624.

[0167] The transistor shown in Fig. 13(D) is a top gate type with a bottom contact structure.

[0168] And the transistor shown in Fig. 13(D) includes a conductive film 1645 formed on an insulating surface, a conductive film 1646, a semiconductor film 1644 on the conductive films 1645 and 1646, a gate insulating film 1643 formed on the semiconductor film 1644, and a gate electrode 1642 overlapping the semiconductor film 1644 on the gate insulating film 1643. Further, the transistor may include an insulating film 1647 formed on the gate electrode 1642 in its components.

[0169] This embodiment can be implemented in appropriate combination with other embodiments.

[0170] (Embodiment 5) FIG. 14 illustrates an example of a panel corresponding to one form of a semiconductor display device. FIG. 14 shows a panel including a substrate 700, a pixel portion 701 on the substrate 700, a signal line driving circuit 702, The display device includes a scanning line driver circuit 703 and a terminal 704 .

[0171] The pixel portion 701 has a plurality of pixels, and each pixel has a display element and a control circuit for controlling the operation of the display element. The scanning line driver circuit 703 is provided with one or more transistors for each pixel. The pixel portion 701 is provided with a pixel selector 702, and a pixel selector 703 is provided to select the pixel by controlling the supply of a potential to a scanning line connected to the pixel. The signal line driver circuit 702 outputs an image to the pixel selected by the scanning line driver circuit 703. Controls the signal supply.

[0172] In the panel shown in FIG. 14, the scanning line driver circuit 703 is provided with a shift register according to one embodiment of the present invention. In FIG. 14, a potential V This shows an example in which EE, potential VSS, and potential VDD are applied.

[0173] Since the scanning lines are connected to multiple pixels, they require a large current supply capacity. A potential is supplied to the scanning line by using a shift register according to one embodiment of the present invention. Therefore, the amplitude of the potential applied to the scanning line can be prevented from becoming small. The display defect in the pixel portion 701 caused by the small amplitude of the signal is reduced, and high image quality is achieved. It is possible to display images of.

[0174] In this embodiment, the scan line driver circuit 703 is provided with a shift register according to one embodiment of the present invention. However, the case where a transistor according to one embodiment of the present invention is used for the signal line driver circuit 702 is described. A soft register may also be used.

[0175] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0176] (Embodiment 6) A semiconductor device according to an aspect of the present invention includes a display device, a personal computer, and a recording medium equipped image playback device (typically a DVD: Digital Versatile Disc etc., which can play back a recording medium and has a display capable of displaying the image). In addition, electronic devices that can use the semiconductor device according to an aspect of the present invention include mobile phones, game machines including portable types, portable information terminals, electronic books, video cameras, digital still cameras such as cameras, goggle-type displays (head-mounted displays ), navigation systems, audio playback devices (car audio, digital audio players etc.), copiers, facsimiles, printers, printer copiers, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 15 .

[0177] FIG. 15(A) is a portable game machine, which has a housing 5001, a housing 5002, a display unit 5003, a display unit 5004, a microphone 5005, a speaker 5006, operation keys 5007, a start button 5008, etc. By using the semiconductor device according to an aspect of the present invention in the drive circuit of the portable game machine, it is possible to provide a portable game machine with low power consumption and stable operation. By using the semiconductor device according to an aspect of the present invention in the display unit 5003 or the display unit 5004, it is possible to provide a portable game machine with high image quality. Note that the portable game machine shown in FIG. 15(A) has two display units 5003 and 5004, but the number of display units of the portable game machine is not limited to this. game machine is not limited to this. The number of display units of the portable game machine is not limited to this.

[0178] FIG. 15(B) is a display device, which includes a housing 5201, a display unit 5202, a support base 5203, etc. By using the semiconductor device according to one aspect of the present invention in the drive circuit of the display device, a display device with low power consumption and stable operation can be provided. By using the semiconductor display device according to one aspect of the present invention in the display unit 5202, a display device with high image quality can be provided. Note that the display device includes all display devices for information display such as for personal computers, TV broadcast reception, and advertisement display.

[0179] FIG. 15(C) is a notebook personal computer, which includes a housing 5401, a display unit 5402, a keyboard 5403, a pointing device 5404, etc. By using the semiconductor device according to one aspect of the present invention in the drive circuit of the notebook personal computer, a notebook personal computer with low power consumption and stable operation can be provided. By using the semiconductor display device according to one aspect of the present invention in the display unit 5402, a notebook personal computer with high image quality can be provided.

[0180] FIG. 15(D) is a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit 5603, a second display unit 5604, a connection part 5605, operation keys 5606, etc. The first display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by the connection part 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection part 5605. The video on the first display unit 5603 can be It may also be configured to switch according to the angle between the first housing 5601 and the second housing 5602. In addition, at least one of the first display section 5603 and the second display section 5604 may be provided with a position input. A semiconductor display device with additional functions as a device may be used. The function of the input device can be added by providing a touch panel to the semiconductor display device. Alternatively, the function as a position input device can be realized by using a photoelectric conversion element also called a photosensor. The signal can also be added by providing it in a pixel portion of a semiconductor display device. By using a semiconductor device according to one embodiment of the present invention in a circuit, power consumption is low and operation is stable. A portable information terminal having the first display unit 5603 or the second display unit 5604 can be provided. By using a semiconductor display device according to one embodiment of the present invention, a portable information terminal with high image quality can be provided. It can be provided.

[0181] FIG. 15E shows a mobile phone. The mobile phone includes a housing 5801, a display unit 5802, an audio input unit 5803, The device has a voice output unit 5804, an operation key 5805, a light receiving unit 5806, etc. By converting the light received in the mobile phone into an electrical signal, it is possible to capture an image from the outside. By using a semiconductor device according to one embodiment of the present invention for a driver circuit of a mobile phone, power consumption can be reduced. In this way, a mobile phone with stable operation can be provided. By using such a semiconductor display device, a mobile phone with high image quality can be provided.

[0182] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0183] 100 Semiconductor device 101 Circuit 102 Transistor 103 Transistor 104 Wiring 105 Wiring 106 Wiring 107 Wiring 108 Wiring 109 Transistor 110 Capacitor Element 200 Pulse Generation Circuit 200_1 to 200_y Pulse Generation Circuit 201 Circuit 202 Transistor 203 Transistor 204 Transistor 205 Wiring 206 Wiring 207 Wiring 208 Wiring 209 Wiring 210 Wiring 211 Wiring 212 Wiring 213 Wiring 214 Wiring 215 Transistor 216 Transistor 217 Transistor 218 Transistor 219 Transistor 220 Transistor 221 Transistor 222 Transistor 223 Transistor 224 Capacitor Element 225 Capacitor Element 230 Resistor 231 Resistor 232 Solid Line 233 Solid Line 300 Pulse Generation Circuit 301 Circuit 302 Transistor 303 Transistor 304 Transistor 305 Wiring 306 Wiring 307 Wiring 308 Wiring 309 Wiring 310 Wiring 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Transistor 316 Transistor 317 Transistor 318 Transistor 319 Transistor 320 Transistor 330 Pulse Generation Circuit 331 Circuit 332 Transistor 333 Transistor 334 Transistor 335 Wiring 336 Wiring 337 Wiring 338 Wiring 339 Wiring 340 Wiring 341 Wiring 342 Wiring 343 Wiring 344 Wiring 345 Wiring 346 Transistor 347 Transistor 348 Transistor 349 Transistor 350 Transistor 351 Transistor 352 Transistor 360 Pulse Generation Circuit 361 Circuit 362 Transistor 363 Transistor 364 Transistor 365 Wiring 366 Wiring 367 Wiring 368 Wiring 369 Wiring 370 Wiring 371 Wiring 372 Wiring 374 Wiring 375 Wiring 376 Transistor 377 Transistor 378 Transistor 379 Transistor 380 Transistor 381 Transistor 382 Transistor 400 Pulse Generation Circuit 401 Circuit 402 Transistor 403 Transistor 404 Transistor 405 Wiring 406 Wiring 407 Wiring 408 Wiring 409 Wiring 410 Wiring 411 Wiring 412 Wiring 414 Wiring 415 Wiring 416 Transistor 417 Transistor 418 Transistor 419 Transistor 420 Transistor 421 Transistor 422 Transistor 423 Transistor 430 Pulse Generation Circuit 431 Circuit 432 Transistor 433 Transistor 434 Transistor 435 Wiring 436 Wiring 437 Wiring 438 Wiring 439 Wiring 440 Wiring 441 Wiring 442 Wiring 444 Wiring 445 Wiring 446 Transistor 447 Transistor 448 Transistor 449 Transistor 450 Transistor 451 Transistor 452 Transistor 453 Transistor 500 Inverter 501 Circuit 502 Transistor 503 Transistor 504 Wiring 505 Wiring 506 Wiring 507 Wiring 508 Wiring 509 Wiring 510 Transistor 511 Transistor 512 Transistor 513 Capacitor Element 700 Substrate 701 Pixel Section 702 Signal Line Driver Circuit 703 Scanning Line Driver Circuit 704 Terminal 800 Substrate 802 Gate Insulating Film 812 Conductive Film 813 Semiconductor Film 814 Conductive Film 815 Conductive Film 816 Conductive Film 817 Semiconductor Film 818 Conductive Film 819 Conductive Film 820 Insulating Film 821 Insulating Film 822 Conductive Film 823 Contact Hole 824 Insulating Film 825 EL Layer 826 Conductive Film 830 Transistor 831 Transistor 832 Light-emitting element 833 Capacitive element 840 Pixel 841 Driving circuit 1602 Gate electrode 1603 Gate insulating film 1604 Semiconductor film 1605 Conductive film 1606 Conductive film 1607 Insulating film 1612 Gate electrode 1613 Gate insulating film 1614 Semiconductor film 1615 Conductive film 1616 Conductive film 1617 Insulating film 1618 Channel protection film 1622 Gate electrode 1623 Gate insulating film 1624 Semiconductor film 1625 Conductive film 1626 Conductive film 1627 Insulating film 1642 Gate electrode 1643 Gate insulating film 1644 Semiconductor film 1645 Conductive film 1646 Conductive film 1647 Insulating film 5001 Housing 5002 Housing 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Housing 5202 Display unit 5203 Support stand 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 First housing 5602 Second housing 5603 First display unit 5604 Second display unit 5605 Connection part 5606 Operation key 5801 Housing 5802 Display unit 5803 Voice input unit 5804 Voice output unit 5805 Operation key 5806 Light receiving part

Claims

1. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; A second potential is supplied to the other of the source and the drain of the ninth transistor. Semiconductor device.

2. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; Semiconductor device.

3. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; a second potential is supplied to the other of the source and the drain of the ninth transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

4. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes a first transistor to a ninth transistor; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

5. In any one of claims 1 to 4, The first transistor to the ninth transistor have the same polarity. Semiconductor device.

6. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; a second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; Semiconductor device.

7. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; Semiconductor device.

8. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; a second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

9. A circuit comprising: The circuit has a function of controlling a supply of a potential to a first wiring electrically connected to a pixel, the circuit includes first to eleventh transistors; one of a source and a drain of the first transistor is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; a first potential is supplied to one of a source and a drain of the second transistor; the other of the source and the drain of the second transistor is electrically connected to the first wiring; one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; one of a source and a drain of the fourth transistor is electrically connected to the other of a source and a drain of the fifth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the first potential is supplied to one of the source and the drain of the fifth transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; a second potential is supplied to the gate of the sixth transistor; the first potential is supplied to one of the source and the drain of the eighth transistor; the other of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the ninth transistor is electrically connected to a gate of the fifth transistor; the second potential is supplied to the other of the source and the drain of the ninth transistor; one of a source and a drain of the tenth transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor; The first wiring has a function as a scanning line, A clock signal is supplied to the third wiring. Semiconductor device.

10. In any one of claims 6 to 9, The first transistor to the eleventh transistor have the same polarity. Semiconductor device.

11. In any one of claims 6 to 10, A gate of the tenth transistor and a gate of the eleventh transistor are input with mutually different signals. Semiconductor device.

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