Backup power supply device, control method, and control program

Abstract

To suppress the number of components and useless motions.SOLUTION: When an input voltage is equal to or more than a first set voltage, a control part performs a control in a first mode to operate a step-down circuit and charge an electric double layer capacitor, by allowing a first switching element to perform switching operation and by allowing a second switching element to perform switching operation, as a synchronous rectification element, and when the input voltage is less than the first set voltage, the control part performs a control in a second mode to operate a step-up circuit and discharge the electric double layer capacitor, by allowing the second switching element to perform switching operation and by allowing the first switching element to perform switching operation, as a synchronous rectification element. When the charging voltage of the electric double layer capacitor is less than a second set voltage in the first mode, the control part continues the first mode without switching to the second mode even if the input voltage becomes less than the first set voltage.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a backup power supply device, a control method, and a control program.

Background Art

[0002] Vehicles are equipped with various devices that operate using the power of a battery (e.g., an auxiliary battery). Patent Document 1 describes a backup power supply device for operating the above devices even when the battery cannot output power due to a traffic accident or the like.

[0003] The backup power supply device described in Patent Document 1 shares a coil between a boost circuit and a buck circuit. That is, the boost circuit and the buck circuit constitute a buck-boost circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The backup power supply device described in Patent Document 1 includes an output rectifying element connected in the forward direction from the boost circuit to the terminal portion as a current output path from the electric double layer capacitor to the terminal portion. However, it is desirable to suppress the number of components. Further, consider the case where the voltage of the electric double layer capacitor is less than the charging voltage threshold (insufficient voltage for backup output) in the charging mode of the electric double layer capacitor. And further, if the input voltage becomes less than the input voltage threshold, it will switch from the charging mode to the backup mode, and the necessary voltage cannot be output, resulting in a wasted operation (idle operation).

[0006] An object of the present invention is to provide a backup power supply device, a control method, and a control program that can suppress the number of components and suppress unnecessary operations.

Means for Solving the Problems

[0007] A backup power supply device according to an aspect of the present invention includes: a terminal unit having an input terminal, an output terminal, a connection point electrically connected to the output terminal, and an input rectifying element having an anode electrically connected to the input terminal and a cathode electrically connected to the connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil and the other end electrically connected to a reference potential; a control unit that performs control in a first mode of charging the electric double layer capacitor by operating the first switching element, the second switching element, and the coil as a step-down circuit by switching the first switching element based on the current flowing through the first switching element and the charging voltage of the electric double layer capacitor and switching the second switching element as a synchronous rectifying element when the input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, and performing control in a second mode of discharging the electric double layer capacitor by operating the first switching element, the second switching element, and the coil as a step-up circuit by switching the second switching element based on the current flowing through the second switching element and the output voltage output from the output terminal and switching the first switching element as a synchronous rectifying element when the input voltage is lower than the first set voltage; and the control unit In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, even if the input voltage is less than the first set voltage, the first mode is continued without switching to the second mode. It is characterized by this.

[0008] In the backup power supply device, The control unit, The time constant for determining whether the input voltage is equal to or greater than the first set voltage when switching from the second mode to the first mode is made longer than the time constant for determining whether the input voltage is less than the first set voltage when switching from the first mode to the second mode. It is characterized by this.

[0009] In the backup power supply device, The control unit, In the second mode, when the charging voltage of the electric double layer capacitor is less than the second set voltage and the output voltage has been at or below a predetermined third set voltage for a certain period of time, the second mode is switched to the first mode. It is characterized by this.

[0010] A control method according to an aspect of the present invention is A control method for a backup power supply device including an input terminal, an output terminal, a connection point electrically connected to the output terminal, and a terminal unit having an input rectifying element with an anode electrically connected to the input terminal and a cathode electrically connected to the connection point, an electric double layer capacitor with one end electrically connected to a reference potential, a first switching element with one end electrically connected to the connection point, a coil with one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor, and a second switching element with one end electrically connected to the other end of the first switching element and one end of the coil and the other end electrically connected to the reference potential, When the input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, based on the current flowing through the first switching element and the charging voltage of the electric double layer capacitor, the first switching element is switched, and the second switching element is switched as a synchronous rectifier element, so that the first switching element, the second switching element, and the coil operate as a step-down circuit to charge the electric double layer capacitor, and control in a first mode is performed. When the input voltage is lower than the first set voltage, based on the current flowing through the second switching element and the output voltage output from the output terminal, the second switching element is switched, and the first switching element is switched as a synchronous rectifier element, so that the first switching element, the second switching element, and the coil operate as a step-up circuit to discharge the electric double layer capacitor, and control in a second mode is performed. In the first mode, when the charging voltage of the electric double layer capacitor is lower than a predetermined second set voltage, even if the input voltage becomes lower than the first set voltage, the first mode is continued without switching to the second mode. It is characterized by the above.

[0011] The control program according to one aspect of the present invention is a control program for a backup power supply device including an input terminal, an output terminal, a first connection point electrically connected to the output terminal, and a terminal unit having an input rectifier element with an anode electrically connected to the input terminal and a cathode electrically connected to the first connection point, an electric double layer capacitor with one end electrically connected to a reference potential, a first switching element with one end electrically connected to the first connection point, a coil with one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor, and a second switching element with one end electrically connected to the other end of the first switching element and one end of the coil and the other end electrically connected to the reference potential. When the input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, the first switching element is switched based on the current flowing through the first switching element and the charging voltage of the electric double layer capacitor, and the second switching element is switched as a synchronous rectifier element. By operating, the first switching element, the second switching element, and the coil are operated as a step-down circuit to charge the electric double layer capacitor, and control in the first mode is performed. When the input voltage is less than the first set voltage, based on the current flowing through the second switching element and the output voltage output from the output terminal, the second switching element is switched, and the first switching element is switched as a synchronous rectifier element. By operating, the first switching element, the second switching element, and the coil are operated as a boost circuit to discharge the electric double layer capacitor, and control in the second mode is performed. In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, even if the input voltage becomes less than the first set voltage, the first mode is continued without switching to the second mode. Characterized by that.

Effect of the Invention

[0012] The backup power supply device, control method, and control program according to one aspect of the present invention have the effects of suppressing the number of components and suppressing wasteful operations.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

[0014] Embodiments of the backup power supply device, control method, and control program of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited by this embodiment.

[0015] <First Embodiment> FIG. 1 is a diagram showing a configuration of a backup power supply device according to the first embodiment.

[0016] The backup power supply device 1 has a voltage V of the battery 2 INWhen the voltage is equal to or higher than a predetermined input voltage threshold value, the electric double layer capacitor 3 is charged using the power supplied from the battery 2 via the input terminals 1a and 1b.

[0017] The input voltage threshold value corresponds to an example of the "first set voltage" of the present disclosure.

[0018] The backup power supply device 1 is the voltage V of the battery 2 IN When it is less than the input voltage threshold value, a DC voltage is output from the output terminal 1c using the power charged in the electric double layer capacitor 3. The power output from the output terminal 1c is supplied to an electronic device (not shown).

[0019] The battery 2 is exemplified by an auxiliary battery mounted on a vehicle, but the present disclosure is not limited thereto. The voltage V IN is exemplified by 12V or 24V, but the present disclosure is not limited thereto. The input voltage threshold value is exemplified by 9V, but the present disclosure is not limited thereto.

[0020] The backup power supply device 1 includes resistors R1 to R 12 up to, the capacitor C1, the electric double layer capacitor 3, the buck-boost circuit 4, the terminal portion 5, and the control portion 10. The buck-boost circuit 4 includes switching elements Q1 and Q2 and a coil L1. The terminal portion 5 includes input terminals 1a and 1b, an output terminal 1c, and a diode D1.

[0021] The input terminal 1a is electrically connected to the high potential side end of the battery 2. The input terminal 1b is electrically connected to the low potential side end of the battery 2. The low potential side end of the battery 2 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0022] One end of the resistor R1 is electrically connected to the input terminal 1a on the high potential side. The other end of the resistor R1 is electrically connected to one end of the resistor R2. The other end of the resistor R2 is electrically connected to the input terminal 1b on the low potential side. The resistors R1 and R2 are the voltage V INThe voltage V1 obtained by resistive voltage division is output to the control unit 10. That is, V1 = V IN ÷(R1 + R2) × R2.

[0023] The anode of the diode D1 is electrically connected to the input terminal 1a. The cathode of the diode D1 is electrically connected to the node N1.

[0024] The node N1 corresponds to an example of the "connection point" of the present disclosure.

[0025] The diode D1 allows the current flowing from the battery 2 to the node N1 to pass through when the voltage V IN is higher than the voltage V N1 of the node N1. The diode D1 blocks the current flowing from the node N1 to the battery 2 when the voltage V IN is lower than the voltage V N1 of the node N1.

[0026] One end of the capacitor C1 is electrically connected to the node N1. The other end of the capacitor C1 is electrically connected to the input terminal 1b. The capacitor C1 stabilizes and smoothes the voltage V N1 .

[0027] When the backup power supply device 1 charges the electric double layer capacitor 3, the voltage V N1 is the input voltage, that is, the voltage V IN . When the backup power supply device 1 discharges the electric double layer capacitor 3, the voltage V N1 is the output voltage.

[0028] One end of the resistor R3 is electrically connected to the node N1. The other end of the resistor R3 is electrically connected to one end of the resistor R4. The other end of the resistor R4 is electrically connected to the input terminal 1b. The resistors R3 and R4 output the voltage V2 obtained by resistive voltage division of the voltage V N1 to the control unit 10. That is, V2 = V N1 ÷(R3 + R4) × R4.

[0029] When the backup power supply device 1 charges the electric double layer capacitor 3, the voltage V2 is the input voltage, that is, the voltage V IN (= the voltage V N1 ). When the backup power supply device 1 discharges the electric double layer capacitor 3, the voltage V2 is the output voltage, that is, the voltage V N1 .

[0030] One end of the resistor R5 is electrically connected to the node N1. The other end of the resistor R5 is electrically connected to the drain of the switching element Q1. The voltage V6 at one end of the resistor R5 and the voltage V7 at the other end of the resistor R5 are input to the control unit 10.

[0031] The source of the switching element Q1 is electrically connected to one end of the coil L1. A switching control signal S1 is input from the control unit 10 to the gate of the switching element Q1 via the resistor R6.

[0032] The switching element Q1 corresponds to an example of the "first switching element" of the present disclosure.

[0033] In the present disclosure, each switching element is assumed to be a MOSFET, but it is not limited thereto. Each switching element may be a silicon power device, a GaN power device, a SiC power device, an IGBT (Insulated Gate Bipolar Transistor), or the like.

[0034] Each switching element has a parasitic diode (body diode). The parasitic diode is a pn junction between the back gate and the source and drain of the MOSFET. The parasitic diode can be used as a freewheel diode to discharge the transient reverse electromotive force when the transistor is off.

[0035] The control unit 10 can detect the current flowing between the drain and source of the switching element Q1 based on the voltage between both ends of the resistor R5, that is, the difference between the voltage V6 and the voltage V7.

[0036] In the embodiment, the backup power supply device 1 is provided with the resistor R5. However, the present disclosure is not limited to this. The control unit 10 may detect the current flowing between the drain and source of the switching element Q1 based on the voltage between the drain and source of the switching element Q1. In this case, the backup power supply device 1 may not be provided with the resistor R5. However, the on-resistance of the switching element Q1 has a greater temperature change compared to the resistor R5. Therefore, when high accuracy is required, the backup power supply device 1 should be provided with the resistor R5, and when high accuracy is not required, it is advisable to use the on-resistance of the switching element Q1.

[0037] The drain of the switching element Q2 is electrically connected to the source of the switching element Q1 and one end of the coil L1. The source of the switching element Q2 is electrically connected to one end of the resistor R8. The other end of the resistor R8 is electrically connected to the input terminal 1b. The switching control signal S2 is input from the control unit 10 to the gate of the switching element Q2 via the resistor R7.

[0038] The switching element Q2 corresponds to an example of the "second switching element" of the present disclosure.

[0039] One end of the resistor R9 is electrically connected to the source of the switching element Q2 and one end of the resistor R8. The voltage V4 at the source of the switching element Q2 and one end of the resistor R8 is input to the control unit 10 via the resistor R9.

[0040] Resistor R 10 One end of is electrically connected to the source of the switching element Q2 and one end of the resistor R8. The voltage V5 at the source of the switching element Q2 and one end of the resistor R8 is input to the control unit 10 via the resistor R 10 and.

[0041] The control unit 10 can detect the current flowing between the drain and source of the switching element Q2 based on the voltage across the resistor R8, that is, the voltage V4 or the voltage V5.

[0042] In the embodiment, the backup power supply device 1 is provided with the resistor R8, but the present disclosure is not limited thereto. The control unit 10 may detect the current flowing between the drain and source of the switching element Q2 based on the voltage between the drain and source of the switching element Q2. In this case, the backup power supply device 1 may not be provided with the resistor R8. However, the on-resistance of the switching element Q2 has a large temperature change compared with the resistor R8. Therefore, when high accuracy is required, the backup power supply device 1 may be provided with the resistor R8, and when high accuracy is not required, the on-resistance of the switching element Q2 may be used.

[0043] The other end of the coil L1 is electrically connected to one end (high potential side end) of the electric double layer capacitor 3. The other end (low potential side end) of the electric double layer capacitor 3 is electrically connected to the input terminal 1b.

[0044] One end of the resistor R 11 is electrically connected to one end of the electric double layer capacitor 3. One end of the resistor R 11 The other end is electrically connected to one end of the resistor R 12 The other end is electrically connected to one end of the resistor R 12 The other end is electrically connected to the other end of the electric double layer capacitor 3. One end of the resistor R 11 and the resistor R 12 output the voltage V3 obtained by resistively dividing the voltage V EDLC of the electric double layer capacitor 3 to the control unit 10. That is, V3 = V EDLC ÷(R 11 +R 12 )×R 12 is.

[0045] The control unit 10 controls the buck-boost circuit 4 based on the voltages from V1 to V7.

[0046] In the mode in which the control unit 10 charges the electric double layer capacitor 3 (hereinafter referred to as the "first mode"), the voltage V INControl the buck-boost circuit 4 so as to step down and output to the electric double layer capacitor 3. In the first mode, the input voltage of the buck-boost circuit 4 is the voltage V IN and the output voltage is the voltage V EDLC .

[0047] In the first mode, the control unit 10 operates the switching element Q1 and the coil L1 as a buck circuit. Also, in the first mode, the control unit 10 operates the switching element Q1 as the main switching element and the switching element Q2 as the synchronous rectification element.

[0048] In the mode in which the control unit 10 discharges the electric double layer capacitor 3 (hereinafter referred to as the "second mode"), the buck-boost circuit 4 is controlled so as to step up the voltage V EDLC and output it to the output terminal 1c. In the second mode, the input voltage of the buck-boost circuit 4 is the voltage V EDLC and the output voltage is the voltage V N1 .

[0049] In the second mode, the control unit 10 operates the switching element Q2 and the coil L1 as a boost circuit. Also, in the second mode, the control unit 10 operates the switching element Q2 as the main switching element and the switching element Q1 as the synchronous rectification element.

[0050] The control unit 10 includes a battery voltage drop monitoring unit 11, a mode switching timing adjustment unit 12, a switching frequency setting unit 13, a switching current detection unit 14, a current information detection unit 15, an overvoltage detection unit 16, an output voltage error detection unit 17, an on / off control unit 18, a drive selection unit 19, a first level shift unit 20, a second level shift unit 21, and gate drive circuits B1 and B2.

[0051] Based on the voltage V1, the battery voltage drop monitoring unit 11 monitors the voltage V INIt monitors whether the voltage has dropped below the input voltage threshold. Based on the output signal from the battery voltage drop monitoring unit 11, the mode switching timing adjustment unit 12 switches the mode signal S representing the first mode or the second mode MODE at the timing at the start of the switching period.

[0052] FIG. 2 is a diagram showing the circuit configuration of the battery voltage drop monitoring unit and the mode switching timing adjustment unit of the backup power supply device according to the embodiment.

[0053] The battery voltage drop monitoring unit 11 includes a comparator 31, a constant voltage source 32, a diode 151, a resistor 152, a capacitor 153, a comparator 154, a constant voltage source 155, an AND gate circuit 156, a NOT gate circuit 157, and an S-R flip-flop 158.

[0054] The voltage of the constant voltage source 32 is input to the non-inverting input terminal (+ terminal) of the comparator 31. The voltage of the constant voltage source 32 is a voltage corresponding to the input voltage threshold. Specifically, the voltage of the constant voltage source 32 is ((input voltage threshold)÷(R1 + R2)×R2). The voltage V1 is input to the inverting input terminal (- terminal) of the comparator 31.

[0055] When the voltage V1 is equal to or higher than the voltage of the constant voltage source 32, the comparator 31 outputs a low-level signal. That is, when the voltage V of the battery 2 IN is equal to or higher than the input voltage threshold, the comparator 31 outputs a low-level signal.

[0056] On the other hand, when the voltage V1 is lower than the voltage of the constant voltage source 32, the comparator 31 outputs a high-level signal. That is, when the voltage V of the battery 2 IN is lower than the input voltage threshold, the comparator 31 outputs a high-level signal.

[0057] The anode of diode 151 is electrically connected to the output terminal of comparator 31. The cathode of diode 151 is electrically connected to one input terminal of AND gate circuit 156.

[0058] One end of resistor 152 is electrically connected to the output terminal of comparator 31. The other end of resistor 152 is electrically connected to the cathode of diode 151 and one input terminal of AND gate circuit 156.

[0059] One end of the capacitor is electrically connected to the cathode of diode 151, the other end of resistor 152, and one input terminal of AND gate circuit 156. The other end of capacitor 153 is electrically connected to the reference potential.

[0060] When the signal S 100 output from comparator 31 IN is at a high level (when voltage V 100 is less than the input voltage threshold), the high-level signal S 100 is input to one input terminal of AND gate circuit 156 via diode 151.

[0061] When signal S 100 is at a low level (when voltage V IN is greater than or equal to the input voltage threshold), diode 151 is in an off state. Therefore, the low-level signal S 100 is input to one input terminal of AND gate circuit 156 via the RC filter composed of resistor 152 and capacitor 153.

[0062] That is, signal S 100 changes from low level to high level with a relatively short time constant when voltage V IN decreases from above the input threshold voltage to below the input voltage threshold.

[0063] On the other hand, signal S 100 changes from high level to low level with a relatively long time constant when voltage V IN increases from below the input threshold voltage to above the input voltage threshold.

[0064] The voltage of the constant voltage source 155 is input to the inverting input terminal (- terminal) of the comparator 154. The voltage of the constant voltage source 155 is a voltage corresponding to the charging voltage threshold (a voltage sufficient for the backup output). Specifically, the voltage of the constant voltage source 155 is ((charging voltage threshold) ÷ (R 11 +R 12 ) × R 12 ). The voltage V3 is input to the non-inverting input terminal (+ terminal) of the comparator 154.

[0065] The charging voltage threshold corresponds to an example of the "second set voltage" of the present disclosure.

[0066] The comparator 154 outputs a high-level signal when the voltage V3 is equal to or higher than the voltage of the constant voltage source 155. That is, the comparator 154 outputs a high-level signal when the voltage V of the electric double layer capacitor 3 EDLC is equal to or higher than the charging voltage threshold.

[0067] On the other hand, the comparator 154 outputs a low-level signal when the voltage V3 is lower than the voltage of the constant voltage source 155. That is, the comparator 154 outputs a low-level signal when the voltage V of the electric double layer capacitor 3 EDLC is lower than the charging voltage threshold.

[0068] The output signal of the comparator 154 is input to the other input terminal of the AND gate circuit 156.

[0069] The AND gate circuit 156 outputs a high-level signal when the voltage of the capacitor 153 is high level and the output signal of the comparator 154 is high level. That is, the AND gate circuit 156 outputs a high-level signal when the voltage V IN is lower than the input voltage threshold and the voltage V EDLC is equal to or higher than the charging voltage threshold.

[0070] However, the signal S 100 is the voltage V INWhen it drops from equal to or higher than the input threshold voltage to less than the input voltage threshold, it changes from a low level to a high level with a relatively short time constant.

[0071] On the other hand, signal S 100 is such that when voltage V IN rises from less than the input threshold voltage to equal to or higher than the input voltage threshold, it changes from a high level to a low level with a relatively long time constant.

[0072] Therefore, even if voltage V IN becomes equal to or higher than the input voltage threshold due to momentary noise or the like and then immediately settles to less than the input voltage threshold, the output signal of AND gate circuit 156 does not become a low level but is maintained at a high level.

[0073] The output signal of AND gate circuit 156 is input to the S terminal (set terminal) of S-R flip-flop 158.

[0074] NOT gate circuit 157 logically inverts signal S 100 and outputs it to the R terminal (reset terminal) of S-R flip-flop 158.

[0075] However, signal S 100 is such that when voltage V IN drops from equal to or higher than the input threshold voltage to less than the input voltage threshold, it changes from a low level to a high level with a relatively short time constant.

[0076] On the other hand, signal S 100 is such that when voltage V IN rises from less than the input threshold voltage to equal to or higher than the input voltage threshold, it changes from a high level to a low level with a relatively long time constant.

[0077] Therefore, even if voltage V IN becomes equal to or higher than the input voltage threshold due to momentary noise or the like and then immediately settles to less than the input voltage threshold, the output signal of NOT gate circuit 157 does not become a high level but is maintained at a low level.

[0078] The S-R flip-flop 158 is set and outputs a high-level signal when the signal S 100 is at a high level and the output signal of the comparator 154 is at a high level. That is, the S-R flip-flop 158 outputs a high-level signal when the voltage V IN is less than the input voltage threshold and the voltage V EDLC is greater than or equal to the charging voltage threshold.

[0079] Also, the S-R flip-flop 158 is reset and outputs a low-level signal when the signal S 100 is at a low level. That is, the S-R flip-flop 158 outputs a low-level signal when the voltage V IN is greater than or equal to the input voltage threshold.

[0080] As described above, even if the voltage V IN becomes greater than or equal to the input voltage threshold due to momentary noise or the like and then immediately settles below the input voltage threshold, the output signal of the AND gate circuit 156 does not become low level but is maintained at high level. Also, the output signal of the NOT gate circuit 157 does not become high level but is maintained at low level.

[0081] Therefore, even if the voltage V IN becomes greater than or equal to the input voltage threshold due to momentary noise or the like and then immediately settles below the input voltage threshold, the output signal of the S-R flip-flop 158 is maintained at high level.

[0082] The mode switching timing adjustment unit 12 includes a D flip-flop 41 and a one-shot circuit 42.

[0083] The output signal of the S-R flip-flop 158 is input to the D terminal (signal input terminal) of the D flip-flop 41.

[0084] The one-shot circuit 42 is a periodic pulse signal S representing the switching period OSCOutput a one-shot pulse to the T terminal (trigger input terminal) of the D flip-flop 41 at the timing when (described later) changes from low level to high level.

[0085] The D flip-flop 41 captures the output signal of the S-R flip-flop 158 at the timing when the one-shot pulse input from the one-shot circuit 42 changes from low level to high level. The D flip-flop 41 outputs a mode signal S representing the mode from the inverted output terminal (Q bar terminal). MODE Output it.

[0086] The mode signal S MODE represents the first mode (charging mode) when it is at high level and represents the second mode (discharging mode) when it is at low level.

[0087] Referring to FIG. 1 again, the switching frequency setting unit 13 outputs a periodic pulse signal S representing the switching frequency based on the mode signal S. MODE Based on OSC Output it.

[0088] FIG. 3 is a diagram showing the circuit configuration of the switching frequency setting unit of the backup power supply device according to the embodiment.

[0089] The switching frequency setting unit 13 includes NOT gate circuits (inverting circuits) 51 and 61, constant current sources 52, 53, 56 and 57, transfer gate circuits 54, 55, 58, 64 and 65, a capacitor 59, a comparator 60, and constant voltage sources 62 and 63.

[0090] The NOT gate circuit 51 inverts the mode signal S and outputs it to the transfer gate circuits 54 and 58. Therefore, the transfer gate circuits 54 and 58 are in the off state when the mode signal S is at high level (first mode) and are in the on state when the mode signal S is at low level (second mode). MODE Output it to the transfer gate circuits 54 and 58. Therefore, the transfer gate circuits 54 and 58 are in the off state when the mode signal S MODE is at high level (first mode) and are in the on state when the mode signal S MODE is at low level (second mode).

[0091] The low-potential side terminal of the capacitor 59 is electrically connected to the reference potential.

[0092] The constant current source 52 is electrically connected between the power supply potential VDD and the high-potential side terminal of the capacitor 59.

[0093] One end of the constant current source 53 is electrically connected to the power supply potential VDD. The other end of the constant current source 53 is electrically connected to the high-potential side terminal of the capacitor 59 via the transfer gate circuit 54.

[0094] Mode signal S MODE When is at the high level (first mode), the transfer gate circuit 54 is in the off state. Therefore, the capacitor 59 is charged only by the constant current source 52. Mode signal S MODE When is at the low level (second mode), the transfer gate circuit 54 is in the on state. Therefore, the capacitor 59 is charged by both the constant current sources 52 and 53. That is, since the charging current of the capacitor 59 changes according to the signal value of the mode signal S MODE the rising speed of the voltage changes.

[0095] The voltage at the high-potential side terminal of the capacitor 59 is the sawtooth wave signal S SAW is.

[0096] The inverting input terminal (- terminal) of the comparator 60 is electrically connected to the high-potential side terminal of the capacitor 59. The non-inverting input terminal (+ terminal) of the comparator 60 is electrically connected to the constant voltage source 62 via the transfer gate circuit 64 and is also electrically connected to the constant voltage source 63 via the transfer gate circuit 65.

[0097] The transfer gate circuit 64 is in the on state when the output signal of the comparator 60 is at the high level and is in the off state when the output signal of the comparator 60 is at the low level.

[0098] The NOT gate circuit 61 inverts the output signal of the comparator 60 and outputs it to the transfer gate circuits 55 and 65. Therefore, the transfer gate circuits 55 and 65 are in the OFF state when the output signal of the comparator 60 is at the high level, and are in the ON state when the output signal of the comparator 60 is at the low level.

[0099] The comparator 60 outputs a high-level signal when the voltage of the capacitor 59 is less than the reference voltage (the voltage of the constant voltage source 62 or 63). When the output signal of the comparator 60 is at the high level, the transfer gate circuit 64 is in the ON state, so the voltage of the constant voltage source 62 is input as the reference voltage to the non-inverting input terminal of the comparator 60.

[0100] The comparator 60 outputs a low-level signal when the voltage of the capacitor 59 is greater than or equal to the reference voltage (the voltage of the constant voltage source 62 or 63). When the output signal of the comparator 60 is at the low level, the transfer gate circuit 65 is in the ON state, so the voltage of the constant voltage source 63 is input as the reference voltage to the non-inverting input terminal of the comparator 60.

[0101] That is, the reference voltage of the comparator 60 is different when changing from the low level to the high level and when the output signal changes from the high level to the low level.

[0102] The output signal of the comparator 60 is the periodic pulse signal S OSC is.

[0103] One end of the transfer gate circuit 55 is electrically connected to the high-potential side end of the capacitor 59.

[0104] The constant current source 56 is electrically connected between the other end of the transfer gate circuit 55 and the reference potential.

[0105] One end of the transfer gate circuit 58 is electrically connected to the other end of the transfer gate circuit 55.

[0106] The constant current source 57 is electrically connected between the transfer gate circuit 58 and the reference potential.

[0107] Mode signal S MODE When it is at a high level (first mode), the capacitor 59 is discharged only by the constant current source 56. The mode signal S MODE When it is at a low level (second mode), the transfer gate circuit 58 is turned on. Therefore, the capacitor 59 is discharged by both the constant current sources 56 and 57. That is, since the discharge current of the capacitor 59 changes according to the signal value of the mode signal S MODE the voltage drop speed changes.

[0108] Overall, when the mode signal S MODE is at a high level (first mode), the capacitor 59 is charged and discharged at a relatively slow speed. Therefore, the frequencies of the sawtooth wave signal S SAW and the periodic pulse signal S OSC become relatively low.

[0109] On the other hand, when the mode signal S MODE is at a low level (second mode), the capacitor 59 is charged and discharged at a relatively fast speed. Therefore, the frequencies of the sawtooth wave signal S SAW and the periodic pulse signal S OSC become relatively high.

[0110] FIG. 4 is a diagram showing an example of the sawtooth wave signal and the periodic pulse signal of the backup power supply device according to the embodiment.

[0111] The sawtooth wave signal S SAW starts to rise from the timing t0. The rising speed of the sawtooth wave signal S SAW depends on the current values of the constant current sources 52 and 53. The periodic pulse signal S OSC becomes high level at the timing t0.

[0112] The periodic pulse signal S OSC is at a high level when the sawtooth wave signal S SAW reaches the voltage V100 Becomes low level at timing t1 when it reaches (the voltage of the constant voltage source 62). Periodic pulse signal S OSC When becomes low level, the reference voltage changes from voltage V 100 (the voltage of the constant voltage source 62) to voltage V 101 (the voltage of the constant voltage source 63). The sawtooth wave signal S SAW starts to fall from timing t1. The falling speed of the sawtooth wave signal S SAW depends on the current values of the constant current sources 56 and 57.

[0113] Periodic pulse signal S OSC becomes high level at timing t2 when the sawtooth wave signal S SAW reaches voltage V 101 . When the periodic pulse signal S OSC becomes high level, the reference voltage changes from voltage V 101 to voltage V 100 . The sawtooth wave signal S SAW starts to rise from timing t2.

[0114] Referring to FIG. 1 again, the first level shifter 20 level - shifts the voltages V6 and V7 to the voltage of the ground level and outputs them to the switching current detection unit 14.

[0115] The switching current detection unit 14 detects that the current flowing through the resistor R5, that is, the drain - source current of the switching element Q1 has reached zero or reversed based on the voltages after the voltages V6 and V7 are level - shifted.

[0116] Also, the switching current detection unit 14 detects that the current flowing through the resistor R8, that is, the drain - source current of the switching element Q2 has reached zero or reversed based on the voltage V4.

[0117] In the first mode, the switching current detection unit 14 outputs an inversion detection signal S REV to the on - off control unit 18 when the current flowing between the drain and source of the switching element Q2, which is a synchronous rectifier element, reaches zero or reverses.

[0118] Also, in the second mode, when the current flowing between the drain and source of the switching element Q1, which is a synchronous rectifier element, reaches zero or reverses, the switching current detection unit 14 outputs an inversion detection signal S REV to the on / off control unit 18.

[0119] FIG. 5 is a diagram showing the circuit configuration of the switching current detection unit of the backup power supply device according to the embodiment.

[0120] The switching current detection unit 14 includes comparators 121 and 122, transfer gate circuits 123 and 124, and a NOT gate circuit 125.

[0121] The inverting input terminal (- terminal) of the comparator 121 is electrically connected to the reference potential. The output signal of the first level shift unit 20 is input to the non-inverting input terminal (+ terminal) of the comparator 121. When the output signal of the first level shift unit 20 is greater than zero, the comparator 121 outputs a high-level signal, and when the output signal of the first level shift unit 20 is zero or less, it outputs a low-level signal.

[0122] The inverting input terminal (- terminal) of the comparator 122 is electrically connected to the reference potential. The voltage V4 is input to the non-inverting input terminal (+ terminal) of the comparator 122. When the voltage V4 is greater than zero, the comparator 122 outputs a high-level signal, and when the voltage V4 is zero or less, it outputs a low-level signal.

[0123] The NOT gate circuit 125 inverts the mode signal S MODE and outputs it to the transfer gate circuit 124.

[0124] When the mode signal S MODE is at a high level, the transfer gate circuit 123 outputs the output signal of the comparator 121 as the inversion detection signal S REV .

[0125] When the transfer gate circuit 124 has a low-level mode signal S MODE it outputs the output signal of the comparator 122 as the inversion detection signal S REV .

[0126] Referring to FIG. 1 again, the second level shifter 21 level-shifts the voltages V6 and V7 to the voltage of the ground level and outputs them to the current information detector 15.

[0127] In the first mode, the current information detector 15 detects the current information of the drain-source current of the switching element Q1 which is the main switching element.

[0128] In the second mode, the current information detector 15 detects the current information of the drain-source current of the switching element Q2 which is the main switching element.

[0129] FIG. 6 is a diagram showing the circuit configuration of the current information detector of the backup power supply device according to the embodiment.

[0130] The current information detector 15 includes a first voltage-current converter 71, diodes 72, 75, and 79, a resistor 73, a second voltage-current converter 74, a NOT gate circuit 77, transfer gate circuits 76 and 80, and a third voltage-current converter 78.

[0131] The first voltage-current converter 71 converts the voltage of the sawtooth wave signal S SAW into a current and outputs it.

[0132] The anode of the diode 72 is electrically connected to the first voltage-current converter 71. The cathode of the diode 72 is electrically connected to one end of the resistor 73. The connection point between the cathode of the diode 72 and one end of the resistor 73 is the node N2. The other end of the resistor 73 is electrically connected to the reference potential.

[0133] The voltage of the node N2 is the current information signal S CINFO .

[0134] The second voltage-current conversion unit 74 converts the voltages after the voltages V6 and V7 are level-shifted into currents and outputs them.

[0135] The anode of the diode 75 is electrically connected to the second voltage-current conversion unit 74. The cathode of the diode 75 is electrically connected to the node N2.

[0136] The transfer gate circuit 76 is electrically connected between the anode of the diode 75 and the reference potential.

[0137] The NOT gate circuit 77 inverts the mode signal S MODE and outputs it to the transfer gate circuit 76. Therefore, the transfer gate circuit 76 turns off when the mode signal S MODE is at a high level (first mode), and turns on when the mode signal S MODE is at a low level (second mode).

[0138] When the transfer gate circuit 76 is off, the output current of the second voltage-current conversion unit 74 flows to the node N2 via the diode 75. When the transfer gate circuit 76 is on, the output current of the second voltage-current conversion unit 74 flows to the reference potential.

[0139] The third voltage-current conversion unit 78 converts the voltage V5 into a current and outputs it.

[0140] The anode of the diode 79 is electrically connected to the third voltage-current conversion unit 78. The cathode of the diode 79 is electrically connected to the node N2.

[0141] The transfer gate circuit 80 is electrically connected between the anode of the diode 79 and the reference potential.

[0142] The transfer gate circuit 80 turns on when the mode signal S MODE is at a high level (first mode), and when the mode signal SMODE is turned off when it is at a low level (second mode).

[0143] When the transfer gate circuit 80 is in the on state, the output current of the third voltage-current conversion unit 78 flows to the reference potential. When the transfer gate circuit 80 is in the off state, the output current of the third voltage-current conversion unit 78 flows to the node N2 via the diode 79.

[0144] Summarizing the above, when the mode signal S MODE is at a high level (first mode), the sum of the output current of the first voltage-current conversion unit 71 and the output current of the second voltage-current conversion unit 74 flows to the node N2. That is, the current information signal S CINFO is a signal obtained by adding the information of the drain-source current of the switching element Q1, which is the main switching element, to the sawtooth wave signal S SAW .

[0145] On the other hand, when the mode signal S MODE is at a low level (second mode), the sum of the output current of the first voltage-current conversion unit 71 and the output current of the third voltage-current conversion unit 78 flows to the node N2. That is, the current information signal S CINFO is a signal obtained by adding the information of the drain-source current of the switching element Q2, which is the main switching element, to the sawtooth wave signal S SAW .

[0146] Referring to FIG. 1 again, the overvoltage detection unit 16 outputs an overvoltage detection signal S EDLC when it detects that the output voltage of the buck-boost circuit 4 (voltage V OVP ) is overvoltage in the first mode.

[0147] The overvoltage detection unit 16 outputs an overvoltage detection signal S N1 when it detects that the output voltage of the buck-boost circuit 4 (voltage V OVP ) is overvoltage in the second mode.

[0148] FIG. 7 is a diagram showing the circuit configuration of the overvoltage detection unit of the backup power supply device according to the embodiment.

[0149] The overvoltage detection unit 16 includes a comparator 101, constant voltage sources 102 and 103, transfer gate circuits 104, 105, 106 and 107, and a NOT gate circuit 108.

[0150] The inverting input terminal (the - terminal) of the comparator 101 is electrically connected to the constant voltage source 102 via the transfer gate circuit 104 and is also electrically connected to the constant voltage source 103 via the transfer gate circuit 105.

[0151] The voltage of the constant voltage source 102 is a voltage corresponding to a predetermined first overvoltage threshold, which is the overvoltage threshold of the output voltage of the buck - boost circuit 4 (voltage V EDLC ) in the first mode. Specifically, the voltage of the constant voltage source 102 is ((the first overvoltage threshold)÷(R 11 +R 12 )×R 12 ).

[0152] The voltage of the constant voltage source 103 is a voltage corresponding to a predetermined second overvoltage threshold, which is the overvoltage threshold of the output voltage of the buck - boost circuit 4 (voltage V N1 ) in the second mode. Specifically, the voltage of the constant voltage source 103 is ((the second overvoltage threshold)÷(R3 + R4)×R4).

[0153] The NOT gate circuit 108 inverts the mode signal S MODE and outputs it to the transfer gate circuits 105 and 107.

[0154] The transfer gate circuit 104 turns on when the mode signal S MODE is at a high level (the first mode) and turns off when the mode signal S MODE is at a low level (the second mode).

[0155] The transfer gate circuit 105 turns off when the mode signal S MODE is at a high level (the first mode) and turns off when the mode signal S MODEWhen is at low level (second mode), it is turned on.

[0156] A voltage V3 is input to a non-inverting input terminal (+ terminal) of the comparator 101 via a transfer gate circuit 106. In addition, a voltage V2 is input to a non-inverting input terminal of the comparator 101 via a transfer gate circuit 107.

[0157] The transfer gate circuit 106 receives the mode signal S MODE When the mode signal S is at a high level (first mode), it is turned on. MODE When is at low level (second mode), it is in the off state.

[0158] The transfer gate circuit 107 receives the mode signal S MODE is at a high level (first mode), the mode signal S MODE When is at low level (second mode), it is turned on.

[0159] In summary, in the first mode, when the voltage V3 is equal to or higher than the voltage of the constant voltage source 102, that is, when the voltage V EDLC is equal to or greater than the first overvoltage threshold, a high-level overvoltage detection signal S OVP In the second mode, when the voltage V2 is equal to or higher than the voltage of the constant voltage source 103, that is, when the voltage V N1 is equal to or greater than the second overvoltage threshold, a high-level overvoltage detection signal S OVP Output.

[0160] Referring again to FIG. 1, in the first mode, the output voltage error detection unit 17 detects the output voltage of the step-up / step-down circuit 4 (voltage V EDLC ) and the target voltage. ERR Output.

[0161] In the second mode, the output voltage error detection unit 17 detects the output voltage of the step-up / step-down circuit 4 (voltage V N1An error signal S representing the error between ERR is output.

[0162] FIG. 8 is a diagram showing the circuit configuration of the output voltage error detection unit of the backup power supply device according to the embodiment.

[0163] The output voltage error detection unit 17 includes error amplifiers (operational amplifiers) 81 and 85, constant voltage sources 82 and 86, resistors 83 and 87, capacitors 84 and 88, transfer gate circuits 89 and 90, and a NOT gate circuit 91.

[0164] The voltage of the constant voltage source 82 is input to the non-inverting input terminal (+ terminal) of the error amplifier 81. The voltage of the constant voltage source 82 is a voltage corresponding to the target voltage of the output voltage of the buck-boost circuit 4 in the second mode (voltage V N1 ). Specifically, the voltage of the constant voltage source 82 is ((the target voltage of the voltage V N1 )÷(R3 + R4)×R4).

[0165] The voltage V2 is input to the inverting input terminal (- terminal) of the error amplifier 81. Negative feedback is applied between the inverting input terminal and the output terminal of the error amplifier 81 by the resistor 83 and the capacitor 84. The error amplifier 81 outputs a voltage corresponding to the difference voltage between the voltage of the constant voltage source 82 and the voltage V2.

[0166] The voltage of the constant voltage source 86 is input to the non-inverting input terminal (+ terminal) of the error amplifier 85. The voltage of the constant voltage source 86 is a voltage corresponding to the target voltage of the output voltage of the buck-boost circuit 4 in the first mode (voltage V EDLC ). Specifically, the voltage of the constant voltage source 86 is ((the target voltage of the voltage V EDLC )÷(R 11 +R 12 )×R 12 ).

[0167] The voltage V3 is input to the inverting input terminal (- terminal) of the error amplifier 85. Negative feedback is applied between the inverting input terminal and the output terminal of the error amplifier 85 by a resistor 87 and a capacitor 88. The error amplifier 85 outputs a voltage corresponding to the difference voltage between the voltage of the constant voltage source 86 and the voltage V3.

[0168] The NOT gate circuit 91 inverts the mode signal S MODE and outputs it to the transfer gate circuit 89. Therefore, the transfer gate circuit 89 is in the off state when the mode signal S MODE is at the high level (first mode), and is in the on state when the mode signal S MODE is at the low level (second mode).

[0169] The transfer gate circuit 90 is in the on state when the mode signal S MODE is at the high level (first mode), and is in the off state when the mode signal S MODE is at the low level (second mode).

[0170] Summarizing the above, when the mode signal S MODE is at the high level (first mode), the output voltage error detection unit 17 outputs a voltage corresponding to the difference voltage between the voltage V3 and the voltage of the constant voltage source 86 as the error signal S ERR . That is, the output voltage error detection unit 17 outputs an error signal S EDLC corresponding to the difference voltage between the voltage V ERR which is the output voltage of the buck - boost circuit 4 and the target voltage (for example, 3V).

[0171] On the other hand, when the mode signal S MODE is at the low level (second mode), the output voltage error detection unit 17 outputs a voltage corresponding to the difference voltage between the voltage V2 and the voltage of the constant voltage source 82 as the error signal S ERR . That is, the output voltage error detection unit 17 outputs an error signal S N1 corresponding to the difference voltage between the voltage V ERR which is the output voltage of the buck - boost circuit 4 and the target voltage (for example, 12V).

[0172] Referring back to FIG. 1, the on-off control unit 18 controls the main switching element based on the periodic pulse signal S OSC , the inversion detection signal S REV , the current information signal S CINFO , the overvoltage detection signal S OVP and the error signal S ERR to generate the main switching control signal S SW1 for controlling the main switching element, and the synchronous rectification switching control signal S SW2 for controlling the synchronous rectification element, and outputs them to the drive selection unit 19.

[0173] In the first mode, the on-off control unit 18 controls the switching of the switching element Q1 and turns on the switching element Q2 during part of the period when the switching element Q1 is off. That is, the on-off control unit 18 operates the switching element Q1 as the main switching element and the switching element Q2 as the synchronous rectification element to perform synchronous rectification control.

[0174] In the second mode, the on-off control unit 18 controls the switching of the switching element Q2 and turns on the switching element Q1 during part of the period when the switching element Q2 is off. That is, the on-off control unit 18 operates the switching element Q2 as the main switching element and the switching element Q1 as the synchronous rectification element to perform synchronous rectification control.

[0175] The on-off control unit 18 adjusts the frequencies of the main switching control signal S SW1 and the synchronous rectification switching control signal S SW2 to match the frequency of the periodic pulse signal S OSC . The frequency of the periodic pulse signal S OSC is higher in the second mode than in the first mode. That is, the frequencies of the main switching control signal S SW1 and the synchronous rectification switching control signal S SW2 are higher in the second mode than in the first mode.

[0176] The on-off control unit 18 controls the main switching element and the synchronous rectification element so that the output voltage of the buck-boost circuit 4 approaches the target voltage. The error signal S ERR is, in the first mode, a signal corresponding to the voltage difference between the voltage V EDLC which is the output voltage of the buck-boost circuit 4 and the target voltage. The error signal S ERR is, in the second mode, a signal corresponding to the voltage difference between the voltage V N1 which is the output voltage of the buck-boost circuit 4 and the target voltage.

[0177] The on-off control unit 18 controls the synchronous rectification element to turn off at the timing when the inversion detection signal S REV becomes high level. That is, in the first mode, the on-off control unit 18 controls the switching element Q2 which is the synchronous rectification element to turn off at the timing when the inversion detection signal S REV becomes high level. Also, in the second mode, the on-off control unit 18 controls the switching element Q1 which is the synchronous rectification element to turn off at the timing when the inversion detection signal S REV becomes high level.

[0178] When the overvoltage detection signal S OVP becomes high level, the on-off control unit 18 stops the operation of the main switching element and the synchronous rectification element.

[0179] The on-off control unit 18 performs current-mode control of the main switching element and the synchronous rectification element based on the current information signal S SAW obtained by adding the drain-source current of the main switching element to the sawtooth wave signal S CINFO .

[0180] FIG. 9 is a diagram showing an example of the sawtooth wave signal, the current information signal, the error signal, and the main switching control signal of the backup power supply device according to the embodiment.

[0181] FIG. 9(a) is a diagram showing the main switching control signal S SAW in the case where the drain-source current of the main switching element is not added to the sawtooth wave signal S SW1 , that is, in the case of voltage-mode control.

[0182] The on-off control unit 18 sets the main switching control signal S SAW to a high level at the timing t 10 when the sawtooth wave signal S SW1 starts to rise.

[0183] The on-off control unit 18 sets the main switching control signal S SAW to a low level at the timing t ERR when the sawtooth wave signal S 11 reaches the error signal S SW1 .

[0184] FIG. 9(b) is a diagram showing the main switching control signal S SAW when the drain-source current of the main switching element is added to the sawtooth wave signal S SW1 , that is, in the case of current mode control.

[0185] Signal 111 indicates the drain-source current of the main switching element. The current information signal S CINFO is a signal obtained by adding signal 111 to the sawtooth wave signal S SAW .

[0186] The on-off control unit 18 sets the main switching control signal S CINFO to a high level at the timing t 20 when the current information signal S SW1 starts to rise.

[0187] The on-off control unit 18 sets the main switching control signal S CINFO to a low level at the timing t ERR when the current information signal S 21 reaches the error signal S SW1 . When the main switching control signal S SW1 becomes low, the main switching element turns off, so signal 111 becomes low.

[0188] Referring to FIG. 1 again, the drive selection unit 19 selects the mode signal S MODEWhen it is at a high level (first mode), the main switching control signal S SW1 is output to the gate drive circuit B1, and the synchronous rectification switching control signal S SW2 is output to the gate drive circuit B2.

[0189] When the drive selection unit 19 has a mode signal S MODE at a low level (second mode), the main switching control signal S SW1 is output to the gate drive circuit B2, and the synchronous rectification switching control signal S SW2 is output to the gate drive circuit B1.

[0190] FIG. 10 is a diagram showing the circuit configuration of the drive selection unit of the backup power supply device according to the embodiment.

[0191] The drive selection unit 19 includes AND gate circuits (logical product circuits) 131, 132, 134, and 135, OR gate circuits (logical sum circuits) 133 and 136, and a NOT gate circuit 137.

[0192] The NOT gate circuit 137 inverts the mode signal S MODE and outputs it to one input terminal of the AND gate circuit 132 and one input terminal of the AND gate circuit 134.

[0193] One input terminal of the AND gate circuit 131 receives the mode signal S MODE , and the other input terminal receives the main switching control signal S SW1 .

[0194] The other input terminal of the AND gate circuit 132 receives the synchronous rectification switching control signal S SW2 .

[0195] The other input terminal of the AND gate circuit 134 receives the main switching control signal S SW1 .

[0196] One input terminal of the AND gate circuit 135 receives the mode signal S MODEis input, and a synchronous rectification switching control signal S SW2 is input to the other input terminal.

[0197] One input terminal of the OR gate circuit 133 receives the output signal of the AND gate circuit 131, and the other input terminal receives the output signal of the AND gate circuit 132.

[0198] When the mode signal S MODE is at a high level (first mode), the OR gate circuit 133 outputs the main switching control signal S SW1 to the gate drive circuit B1.

[0199] When the mode signal S MODE is at a low level (second mode), the OR gate circuit 133 outputs the synchronous rectification switching control signal S SW2 to the gate drive circuit B1.

[0200] One input terminal of the OR gate circuit 136 receives the output signal of the AND gate circuit 134, and the other input terminal receives the output signal of the AND gate circuit 135.

[0201] When the mode signal S MODE is at a high level (first mode), the OR gate circuit 136 outputs the synchronous rectification switching control signal S SW2 to the gate drive circuit B2.

[0202] When the mode signal S MODE is at a low level (second mode), the OR gate circuit 136 outputs the main switching control signal S SW1 to the gate drive circuit B2.

[0203] Referring to FIG. 1 again, when the mode signal S MODE is at a high level (first mode), the gate drive circuit B1 outputs a switched control signal S1 obtained by amplifying the main switching control signal S SW1 to the gate of the switching element Q1.

[0204] When the gate drive circuit B1 has the mode signal S MODE at a low level (second mode), the switching control signal S1 obtained by amplifying the synchronous rectification switching control signal S SW2 is output to the gate of the switching element Q1.

[0205] When the gate drive circuit B2 has the mode signal S MODE at a high level (first mode), the switching control signal S2 obtained by amplifying the synchronous rectification switching control signal S SW2 is output to the gate of the switching element Q2.

[0206] When the gate drive circuit B2 has the mode signal S MODE at a low level (second mode), the switching control signal S2 obtained by amplifying the main switching control signal S SW1 is output to the gate of the switching element Q2.

[0207] (Modification of the first embodiment) The battery voltage drop monitoring unit 11 (see FIG. 2) is configured such that an RC filter composed of a resistor 152 and a capacitor 153 increases the time constant when the signal S 100 changes from a high level to a low level. However, instead of the RC filter, a timer circuit may be used to increase the time constant when the signal S 100 changes from a high level to a low level.

[0208] FIG. 11 is a diagram showing the circuit configuration of the battery voltage drop monitoring unit according to a modification of the first embodiment.

[0209] The battery voltage drop monitoring unit 11A does not include the diode 151, the resistor 152, and the capacitor 153 as compared with the battery voltage drop monitoring unit 11 (see FIG. 2). Further, the battery voltage drop monitoring unit 11A further includes a timer circuit 161 and an AND gate circuit 162 as compared with the battery voltage drop monitoring unit 11.

[0210] The timer circuit 161 includes a constant current source 171, a switching element 172, a capacitor 173, a constant voltage source 174, and a comparator 175.

[0211] The source of the switching element 172 is electrically connected to the reference potential. The signal S is input to the gate of the switching element 172. 100 When the signal S is at a high level, the switching element 172 turns on. When the signal S is at a low level, the switching element 172 turns off. 100 When the signal S is at a high level, the switching element 172 turns on. When the signal S is at a low level, the switching element 172 turns off. 100 When the signal S is at a high level, the switching element 172 turns on. When the signal S is at a low level, the switching element 172 turns off.

[0212] The low potential side end of the capacitor 173 is electrically connected to the reference potential. The high potential side end of the capacitor 173 is electrically connected to the drain of the switching element 172.

[0213] The constant current source 171 is electrically connected between the power supply potential VDD and the drain of the switching element 172 and the high potential side end of the capacitor 173.

[0214] When the signal S is at a high level, the switching element 172 turns on. Therefore, the capacitor 173 is discharged by the switching element 172. 100 When the signal S is at a high level, the switching element 172 turns on. Therefore, the capacitor 173 is discharged by the switching element 172.

[0215] When the signal S is at a low level, the switching element 172 turns off. Therefore, the capacitor 173 is charged by the constant current source 171. 100 When the signal S is at a low level, the switching element 172 turns off. Therefore, the capacitor 173 is charged by the constant current source 171.

[0216] The inverting input terminal (- terminal) of the comparator 175 is electrically connected to the constant voltage source 174. The non-inverting input terminal (+ terminal) of the comparator 175 is electrically connected to the high potential side end of the capacitor 173.

[0217] When the voltage of the capacitor 173 is less than the voltage of the constant voltage source 174, the comparator 175 outputs a low level signal.

[0218] When the voltage of the capacitor 173 is equal to or higher than the voltage of the constant voltage source 174, the comparator 175 outputs a high-level signal.

[0219] The timer circuit 161 starts charging the capacitor 173 at the timing when the signal S 100 changes from high level to low level, and outputs a high-level signal when the voltage of the capacitor 173 reaches the voltage of the constant voltage source 174. Also, the timer circuit 161 discharges the capacitor 173 at the timing when the signal S 100 changes from low level to high level, and outputs a low-level signal.

[0220] That is, the timer circuit 161 outputs a high-level signal at the timing when a predetermined time has elapsed after the voltage V IN changes from less than the input voltage threshold to equal to or higher than the input voltage threshold. Also, the timer circuit 161 outputs a low-level signal at the timing when the voltage V IN changes from equal to or higher than the input voltage threshold to less than the input voltage threshold.

[0221] Therefore, even if the voltage V IN becomes equal to or higher than the input voltage threshold due to momentary noise or the like and then immediately settles to less than the input voltage threshold, the output signal of the timer circuit 161 does not become high level and is maintained at low level.

[0222] The output signal of the NOT gate circuit 157 is input to one input terminal of the AND gate circuit 162. The output signal of the timer circuit 161 is input to the other input terminal of the AND gate circuit 162.

[0223] The AND gate circuit 162 outputs a high-level signal when the signal S 100 is low level and the output signal of the timer circuit 161 is high level. That is, the AND gate circuit 162 outputs a high-level signal when the voltage V IN is equal to or higher than the input voltage threshold and the voltage V INWhen a predetermined time has elapsed after the input voltage changes from below the input voltage threshold to above the input voltage threshold, a high-level signal is output to the R terminal (reset terminal) of the S-R flip-flop 158.

[0224] As described above, due to momentary noise or the like, even if the voltage V IN rises above the input voltage threshold but immediately returns below the input voltage threshold, the output signal of the timer circuit 161 does not become high level and remains low level.

[0225] Therefore, even if the voltage V IN rises above the input voltage threshold but immediately returns below the input voltage threshold due to momentary noise or the like, the output signal of the S-R flip-flop 158 remains high level.

[0226] (Effect) [1] The backup power supply device described in Patent Document 1 performs switching control only on the second switching element and does not control (operate) the first switching element during discharge. That is, the backup power supply device described in Patent Document 1 performs asynchronous rectification operation.

[0227] On the other hand, the backup power supply device 1 of the embodiment controls the switching element Q2 to perform switching control during discharge (in the second mode), and turns on the switching element Q1 during a part of the period when the switching element Q2 is off. That is, the backup power supply device 1 of the embodiment operates the switching element Q1 as a synchronous rectification element and performs synchronous rectification operation.

[0228] Thereby, the backup power supply device 1 of the embodiment can eliminate the need for an output rectifying element compared to the backup power supply device described in Patent Document 1, and can suppress the number of components.

[0229] The backup power supply device described in Patent Document 1 performs switching control only on the first switching element during charging, without controlling (operating) the second switching element, and causes the second switching element to function as a diode. That is, the backup power supply device described in Patent Document 1 performs asynchronous rectification operation.

[0230] On the other hand, the backup power supply device 1 according to the embodiment controls the switching element Q1 to perform switching control during charging (in the first mode), and turns on the switching element Q2 during a part of the period when the switching element Q1 is off. That is, the backup power supply device 1 according to the embodiment operates the switching element Q2 as a synchronous rectifier element and performs a synchronous rectification operation.

[0231] Thereby, the backup power supply device 1 according to the embodiment can suppress losses and improve efficiency as compared with the backup power supply device described in Patent Document 1.

[0232] [2] When the backup power supply device 1 according to the embodiment is in discontinuous current operation (light load), if the synchronous rectifier element remains on, a reverse current will flow, regenerating energy to the input side and reducing efficiency. Also, when the charging voltage of the electric double layer capacitor 3 increases in the backup power supply device 1 according to the embodiment, the regenerative energy becomes larger than the charging energy, and charging up to the target voltage becomes impossible. Therefore, the backup power supply device 1 according to the embodiment sweeps out the energy of the coil L1, and at the timing when the current between the drain and source of the synchronous rectifier element becomes zero or reverses, that is, when the reverse detection signal S REV becomes high level, controls the synchronous rectifier element to turn off. Thereby, the backup power supply device 1 according to the embodiment can suppress the reverse current and suppress the decrease in efficiency. Also, the backup power supply device 1 according to the embodiment can charge the charging voltage of the electric double layer capacitor 3 up to the target voltage.

[0233] [3] The backup power supply device 1 according to the embodiment can perform charging while restricting the charging current in the first mode. However, in the second mode, the backup power supply device 1 according to the embodiment must supply power while boosting the power required by the electronic device, so a large current can flow through the circuit.

[0234] Therefore, if the switching frequency of the backup power supply device 1 according to the embodiment is kept the same in the second mode, the size of the coil L1 must be increased. On the other hand, in the first mode, from the viewpoint of noise suppression, it is desirable not to increase the switching frequency too much for the backup power supply device 1 according to the embodiment.

[0235] Therefore, the switching frequency setting unit 13 sets the switching frequency in the second mode to be higher than the switching frequency in the first mode. Thereby, the backup power supply device 1 according to the embodiment can suppress the size of the coil L1 and can suppress noise.

[0236] [4] In the first mode, the backup power supply device 1 according to the embodiment performs control based on the difference voltage between the voltage V EDLC of the electric double layer capacitor 3, which is the output voltage of the buck-boost circuit 4, and the target voltage (specifically, based on the voltage V3). In the second mode, the backup power supply device 1 according to the embodiment performs control based on the difference voltage between the voltage V N1 that is the output voltage of the buck-boost circuit 4 and the target voltage (specifically, based on the voltage V2).

[0237] However, if the input side of one error amplifier is switched between the above two voltages during mode switching, problems may occur. That is, during mode switching, the input voltage of the error amplifier is switched to a completely different voltage level, so the output voltage of the error amplifier before mode switching and the output voltage of the error amplifier after mode switching will be completely different voltages. Therefore, response delay and unstable operation of the output voltage of the error amplifier may occur.

[0238] Therefore, the output voltage error detection unit 17 (see FIG. 8) includes two error amplifiers 81 and 85, and switches the output sides of the error amplifiers 81 and 85 when switching modes. As a result, the error amplifiers 81 and 85 always output output voltages corresponding to their respective input voltages (even when not used for control), and can suppress response delays and unstable operations during mode switching.

[0239] [5] Different from an error amplifier, a comparator can switch an input voltage to another voltage level. Therefore, the overvoltage detection unit 16 (see FIG. 7) includes one comparator 101, and switches the input voltage of the comparator 101 according to the mode. That is, in the first mode, the voltage V3 obtained by resistively dividing the voltage V of the electric double layer capacitor 3 is input to the comparator 101. In the second mode, the voltage obtained by resistively dividing the output voltage, i.e., the voltage V EDLC is switched at the input side of the comparator 101. N1

[0240] As a result, the backup power supply device 1 of the embodiment can detect overvoltage in both the first mode and the second mode with one comparator 101, and can suppress the circuit.

[0241] [6] Generally, current mode control is easier to perform phase compensation than voltage mode control, and it is possible to set a response increase (increase in frequency gain). Therefore, the on / off control unit 18 employs current mode control taking into account the current information signal S CINFO . However, the current detection points are different between the first mode and the second mode.

[0242] Therefore, the current information detection unit 15 (see FIG. 6) is a sawtooth wave signal S SAWThe current information to be added is switched according to the mode. That is, in the first mode, the current information detector 15 detects the current information of the current flowing between the drain and source of the switching element Q1, which is the main switching element. Also, in the second mode, the current information detector 15 detects the current information of the current flowing between the drain and source of the switching element Q2, which is the main switching element.

[0243] Thus, the backup power supply device 1 of the embodiment can achieve current mode control in either the first mode or the second mode.

[0244] [7] The first mode and the second mode are completely different controls. Therefore, if the mode is switched during the switching period, even if it is one switching period, it will result in an abnormal operation.

[0245] Therefore, the mode switching timing adjustment unit 12 (see FIG. 2) waits until the start of the next switching period, that is, the rising edge of the periodic pulse signal S, even if the magnitude relationship between the voltage V IN and the input voltage threshold value changes during the switching period, and then switches the mode signal S OSC . By doing so, the backup power supply device 1 of the embodiment can suppress the above abnormal operation. MODE

[0246] [8] Consider the case where in the first mode, the voltage V EDLC of the electric double layer capacitor 3 is less than the voltage threshold value (insufficient voltage for backup). And further, if the voltage V IN becomes less than the input voltage threshold value (for example, 9V), the backup power supply device 1 will switch from the first mode to the second mode and will not be able to output the required voltage V N1 , resulting in a wasteful operation (idle operation).

[0247] Therefore, in the first embodiment, the battery voltage drop monitoring unit 11 and the mode switching timing adjustment unit 12, in the first mode, when the voltage V EDLCIf it is less than the voltage threshold value, the first mode is continued without switching to the second mode.

[0248] As a result, the backup power supply device 1 can charge the electric double layer capacitor 3 when the battery has not been completely cut off but has dropped to about 6V to 9V due to deterioration or the like.

[0249] [9] In the second mode, consider the case where the voltage V of the electric double layer capacitor 3 EDLC drops below the voltage threshold value. And further, assuming that the voltage V IN becomes equal to or higher than the input voltage threshold value due to momentary noise or the like, it will switch from the second mode to the first mode. Then, even if the momentary noise or the like converges and the voltage V IN returns below the input voltage threshold value, as described in [8] above, the first mode will continue and it will not return to the second mode (the backup will be stopped).

[0250] If it is not momentary noise or the like but the voltage V IN is actually decreasing, there is a request to continue the backup until the lower limit limit of the backupable voltage V of the electric double layer capacitor 3 EDLC . This is because the lower limit of the backupable voltage V EDLC differs for each device of the load to be backed up.

[0251] Therefore, the battery voltage drop monitoring unit 11 determines whether the voltage V IN is equal to or higher than the input voltage threshold value with a relatively long time constant compared to the determination of whether the voltage V IN is less than the input voltage threshold value.

[0252] As a result, the backup power supply device 1 can continue the second mode when the voltage V IN becomes equal to or higher than the input voltage threshold value due to momentary noise or the like and then quickly settles below the input voltage threshold value.

[0253] <Second Embodiment> Among the components of the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0254] The second embodiment is a modification of the battery voltage drop monitoring unit 11A (see FIG. 11), which is a modification example of the first embodiment.

[0255] FIG. 12 is a diagram showing the circuit configuration of the battery voltage drop monitoring unit according to the second embodiment.

[0256] The battery voltage drop monitoring unit 11B further includes a comparator 181, a constant voltage source 182, a timer circuit 183, a NOT gate circuit 184, an AND gate circuit 185, and an OR gate circuit 186, as compared with the battery voltage drop monitoring unit 11A (see FIG. 11).

[0257] The voltage of the constant voltage source 182 is input to the inverting input terminal (- terminal) of the comparator 181. The voltage of the constant voltage source 182 is a voltage corresponding to the output voltage threshold. Specifically, the voltage of the constant voltage source 182 is ((output voltage threshold) ÷ (R3 + R4) × R4). The voltage V2 is input to the non-inverting input terminal (+ terminal) of the comparator 181.

[0258] The output voltage threshold corresponds to an example of the "third set voltage" of the present disclosure.

[0259] When the voltage V2 is equal to or higher than the voltage of the constant voltage source 182, the comparator 181 outputs a high-level signal. That is, when the voltage V N1 is equal to or higher than the output voltage threshold, the comparator 181 outputs a high-level signal.

[0260] On the other hand, when the voltage V2 is lower than the voltage of the constant voltage source 182, the comparator 181 outputs a low-level signal. That is, when the voltage V N1 is lower than the output voltage threshold, the comparator 181 outputs a low-level signal.

[0261] The timer circuit 183 includes a constant current source 191, a switching element 192, a capacitor 193, a constant voltage source 194, and a comparator 195. Since the connection relationships of the constant current source 191, the switching element 192, the capacitor 193, the constant voltage source 194, and the comparator 195 are the same as those of the constant current source 171, the switching element 172, the capacitor 173, the constant voltage source 174, and the comparator 175, the description thereof is omitted.

[0262] The timer circuit 183 starts charging the capacitor 193 at the timing when the output signal of the comparator 181 changes from a high level to a low level, and outputs a high-level signal when the voltage of the capacitor 193 reaches the voltage of the constant voltage source 194. Further, the timer circuit 183 discharges the capacitor 193 at the timing when the output signal of the comparator 181 changes from a low level to a high level, and outputs a low-level signal.

[0263] That is, the timer circuit 183 outputs a high-level signal at the timing when a predetermined time has elapsed after the voltage V N1 changes from equal to or higher than the output voltage threshold value to less than the output voltage threshold value. Further, the timer circuit 183 outputs a low-level signal at the timing when the voltage V N1 changes from less than the output voltage threshold value to equal to or higher than the output voltage threshold value.

[0264] The NOT gate circuit 184 inverts and outputs the output signal of the comparator 154.

[0265] The output signal of the NOT gate circuit 184 is input to the first input terminal of the AND gate circuit 185. The signal S 100 is input to the second input terminal of the AND gate circuit 185. The output signal of the timer circuit 183 is input to the third input terminal of the AND gate circuit 185.

[0266] The AND gate circuit 185 outputs a high-level signal when the voltage V3 is less than the voltage of the constant voltage source 155, the voltage V1 is less than the voltage of the constant voltage source 32, and a certain time has elapsed after the voltage V2 becomes less than the voltage of the constant voltage source 182.

[0267] That is, the AND gate circuit 185 outputs a high-level signal when the voltage V EDLC is less than the charging voltage threshold, the voltage V IN is less than the input voltage threshold, and a certain time has elapsed after the voltage V N1 becomes less than the output voltage threshold.

[0268] The output signal of the AND gate circuit 162 is input to one input terminal of the OR gate circuit 186. The output signal of the AND gate circuit 185 is input to the other input terminal of the OR gate circuit 186. The output signal of the OR gate circuit 186 is input to the R terminal (reset terminal) of the S-R flip-flop 158.

[0269] The S-R flip-flop 158 is set and outputs a high-level signal when the signal S 100 is at a high level and the output signal of the comparator 154 is at a high level. That is, the S-R flip-flop 158 outputs a high-level signal when the voltage V IN is less than the input voltage threshold and the voltage V EDLC is equal to or higher than the charging voltage threshold.

[0270] Also, the S-R flip-flop 158 is reset and outputs a low-level signal when the signal S 100 is at a low level and the output signal of the timer circuit 161 is at a high level. That is, the S-R flip-flop 158 outputs a low-level signal when a certain time has elapsed after the voltage V IN becomes equal to or higher than the input voltage threshold.

[0271] Also, the S-R flip-flop 158 is reset and outputs a low-level signal when the output signal of the comparator 154 is at a low level, the signal S 100 is at a high level, and the output signal of the timer circuit 183 is at a high level. That is, the S-R flip-flop 158 outputs a low-level signal when the voltage V EDLC is less than the charging voltage threshold, the voltage V INis less than the input threshold voltage, and when a certain time has elapsed after voltage V N1 becomes less than the output voltage threshold, it is reset and outputs a low-level signal.

[0272] (Effect) In the second embodiment, in the second mode, when a state where sufficient backup is not available (voltage V N1 is less than the output voltage threshold) continues for a certain period of time, it is switched from the second mode to the first mode.

[0273] As a result, in the backup power supply device 1, the battery 2 is not completely cut off, but for the case where the voltage V IN has become from 6V to about 9V due to deterioration or the like, the electric double layer capacitor 3 can be charged.

[0274] <Supplementary Note> In the embodiment, the control unit 10 is configured by a hardware circuit, but the present disclosure is not limited thereto. The control unit 10 may be configured by a processing device (such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor)) and a program.

[0275] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0276] 1 Backup power supply device 2 Battery 3 Electric double layer capacitor 4 Step-up / down circuit 5 Terminal section 10 Control Unit 11, 11A, 11B Battery Voltage Drop Monitoring Unit 12 Mode Switching Timing Adjustment Unit 13 Switching Frequency Setting Unit 14 Switching Current Detection Unit 15 Current Information Detection Unit 16 Overvoltage Detection Unit 17 Output Voltage Error Detection Unit 18 On / Off Control Unit 19 Drive Selection Unit 20 First Level Shift Unit 21 Second Level Shift Unit Q1, Q2 Switching Elements L1 Coil

Claims

1. A terminal unit having an input terminal, an output terminal, a connection point electrically connected to the output terminal, and an input rectifying element having an anode electrically connected to the input terminal and a cathode electrically connected to the connection point; An electric double layer capacitor having one end electrically connected to a reference potential; A first switching element having one end electrically connected to the connection point; A coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; A second switching element having one end electrically connected to the other end of the first switching element and one end of the coil and the other end electrically connected to a reference potential; When the input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, based on the current flowing through the first switching element and the charging voltage of the electric double layer capacitor, the first switching element is switched, and the second switching element is switched as a synchronous rectifying element, so that the first switching element, the second switching element, and the coil operate as a step-down circuit to charge the electric double layer capacitor, and perform control in a first mode. When the input voltage is less than the first set voltage, based on the current flowing through the second switching element and the output voltage output from the output terminal, the second switching element is switched, and the first switching element is switched as a synchronous rectifying element, so that the first switching element, the second switching element, and the coil operate as a boost circuit to discharge the electric double layer capacitor, and perform control in a second mode; a control unit; Comprising; The control unit is; In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, even if the input voltage becomes less than the first set voltage, the first mode is continued without switching to the second mode; A backup power supply device, characterized in that.

2. The control unit is; The time constant for determining whether the input voltage is equal to or higher than the first set voltage when switching from the second mode to the first mode is made longer than the time constant for determining whether the input voltage is less than the first set voltage when switching from the first mode to the second mode. The backup power supply device according to claim 1, characterized in that.

3. The control unit is In the second mode, when the charging voltage of the electric double layer capacitor is less than the second set voltage and the output voltage has been equal to or less than a predetermined third set voltage for a certain period of time, switch from the second mode to the first mode. The backup power supply device according to claim 1 or 2, characterized in that.

4. A terminal unit having an input terminal, an output terminal, a connection point electrically connected to the output terminal, and an input rectifying element having an anode electrically connected to the input terminal and a cathode electrically connected to the connection point; an electric double layer capacitor having one end electrically connected to a reference potential; a first switching element having one end electrically connected to the connection point; a coil having one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor; and a second switching element having one end electrically connected to the other end of the first switching element and one end of the coil and the other end electrically connected to the reference potential. A control method for a backup power supply device, comprising: When the input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, based on the current flowing through the first switching element and the charging voltage of the electric double layer capacitor, the first switching element is switched, and the second switching element is switched as a synchronous rectifying element, so that the first switching element, the second switching element, and the coil operate as a step-down circuit to charge the electric double layer capacitor, and perform control in the first mode. When the input voltage is less than the first set voltage, based on the current flowing through the second switching element and the output voltage output from the output terminal, the second switching element is switched, and the first switching element is switched as a synchronous rectifying element, so that the first switching element, the second switching element, and the coil operate as a boost circuit to discharge the electric double layer capacitor, and perform control in the second mode. In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, even if the input voltage becomes less than the first set voltage, the first mode is continued without switching to the second mode. A control method characterized by the above.

5. A control program for a backup power supply device including an input terminal, an output terminal, a connection point electrically connected to the output terminal, and a terminal portion having an input rectifying element with an anode electrically connected to the input terminal and a cathode electrically connected to the connection point, an electric double layer capacitor with one end electrically connected to a reference potential, a first switching element with one end electrically connected to the connection point, a coil with one end electrically connected to the other end of the first switching element and the other end electrically connected to the other end of the electric double layer capacitor, and a second switching element with one end electrically connected to the other end of the first switching element and the one end of the coil and the other end electrically connected to the reference potential, wherein: When the input voltage input to the input terminal is equal to or higher than a predetermined first set voltage, based on the current flowing through the first switching element and the charging voltage of the electric double layer capacitor, the first switching element is switched, and the second switching element is switched as a synchronous rectifying element, so that the first switching element, the second switching element, and the coil operate as a step-down circuit to charge the electric double layer capacitor, and control in the first mode is performed. When the input voltage is less than the first set voltage, based on the current flowing through the second switching element and the output voltage output from the output terminal, the second switching element is switched, and the first switching element is switched as a synchronous rectifying element, so that the first switching element, the second switching element, and the coil operate as a step-up circuit to discharge the electric double layer capacitor, and control in the second mode is performed. In the first mode, when the charging voltage of the electric double layer capacitor is less than a predetermined second set voltage, even if the input voltage becomes less than the first set voltage, the first mode is continued without switching to the second mode. A control program that causes a processing device to execute the above.

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