Drive method of semiconductor device

Abstract

Provided is a semiconductor device that can hold data for a long time. A semiconductor device that has a cell that is provided with a capacity, a first transistor, and a second transistor. The capacity has a first electrode, a second electrode, and a ferroelectric layer. The ferroelectric layer is provided between the first electrode and the second electrode and undergoes a polarization reversal as a result of the application of a first saturated polarization voltage or a second saturated polarization voltage that has a different polarity from the first saturated polarization voltage. The first electrode, the source or the drain of the first transistor, and the gate of the second transistor are electrically connected to each other. During a first period, the first saturated polarization voltage is applied to the ferroelectric layer. During a second period, a voltage of a value that is between the first saturated polarization voltage and the second saturated polarization voltage is applied to the ferroelectric layer as a data voltage.

Description

Technical Field

[0001] One aspect of the present invention relates to a method for driving a semiconductor device and the like.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a storage device, a display system, an electronic device, a lighting device, an input device, an input / output device, a method for driving them, or a method for manufacturing them.

Background Art

[0003] Metal oxides have attracted attention as semiconductors applicable to transistors. Indium-gallium-zinc oxide, referred to as "IGZO", "Igzo", etc., is a typical multi-component metal oxide. In research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as "oxide semiconductor transistor" or "OS transistor") has been reported to have an extremely small off-current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] In addition, a memory that utilizes the extremely small off-current of an OS transistor (sometimes referred to as an OS memory) has been proposed. For example, Patent Document 1 discloses the circuit configuration of a NOSRAM. Note that "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM". NOSRAM refers to a memory in which the cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell, and the access transistor is an OS transistor. The OS transistor has an extremely small current flowing between the source and the drain in the off state, that is, a leakage current. NOSRAM can be used as a non-volatile memory by holding charges corresponding to data in the cell using the characteristic of an extremely small leakage current.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0008] In a memory such as NOSRAM, charges corresponding to data are held in the capacitance of the cell. Therefore, if the amount of charge that can be held in the capacitance is small, a significant decrease in the data read accuracy due to the leakage of charges from the capacitance becomes prominent. Therefore, there are cases where data cannot be held in the cell for a long period of time.

[0009] One aspect of the present invention is to provide a semiconductor device capable of holding data for a long period of time and a driving method thereof. Or, one aspect of the present invention is to provide a low-power semiconductor device and a driving method thereof. Or, one aspect of the present invention is to provide a semiconductor device capable of applying a high voltage and a driving method thereof. Or, one aspect of the present invention is to provide a highly reliable semiconductor device and a driving method thereof. Or, one aspect of the present invention is to provide a novel semiconductor device and a driving method thereof.

[0010] Note that one aspect of the present invention does not necessarily need to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not prevent the existence of other problems. These other problems will become apparent from the description in the specification, claims, drawings, etc., and it is possible to extract these other problems from the description in the specification, claims, drawings, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a method for driving a semiconductor device having a cell provided with a capacitor, a first transistor, and a second transistor, the capacitor having a first electrode, a second electrode, and a ferroelectric layer, the ferroelectric layer being provided between the first electrode and the second electrode, the ferroelectric layer causing polarization reversal by applying a first saturation polarization voltage or a second saturation polarization voltage having a polarity different from that of the first saturation polarization voltage, and the first electrode, one of the source or drain of the first transistor, and the gate of the second transistor being electrically connected to each other, the method comprising: applying the first saturation polarization voltage to the ferroelectric layer in a first period; and applying, as a data voltage, a voltage having a value between the first saturation polarization voltage and the second saturation polarization voltage to the ferroelectric layer in a second period.

[0012] Alternatively, in the above aspect, the potential of the first electrode in the first period may be different from the potential of the first electrode in the second period, and the potential of the second electrode in the first period may be different from the potential of the second electrode in the second period.

[0013] Alternatively, in the above aspect, the first transistor may be turned on in the first period and the second period, and turned off in a third period.

[0014] Alternatively, in the above aspect, the cell may include a third transistor, one of the source or drain of the second transistor may be electrically connected to one of the source or drain of the third transistor, the third transistor may be turned off in the first to third periods, and the third transistor may be turned on in the fourth period.

[0015] Alternatively, in the above aspect, the potential of the second electrode may not vary in the second to fourth periods.

[0016] Alternatively, in the above aspect, a constant potential may be supplied to the other of the source or drain of the second transistor in the first to fourth periods.

[0017] Alternatively, in the above aspect, the polarity of the polarization amount of the ferroelectric layer in the first period and the polarity of the polarization amount of the ferroelectric layer in the second period may be the same.

[0018] Alternatively, in the above aspect, the data voltage may represent analog data.

[0019] Alternatively, in the above aspect, the first transistor may have a metal oxide in the channel formation region.

Advantages of the Invention

[0020] According to one aspect of the present invention, a semiconductor device capable of retaining data for a long period of time and a driving method thereof can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption and a driving method thereof can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device capable of applying a high voltage and a driving method thereof can be provided. Alternatively, according to one aspect of the present invention, a highly reliable semiconductor device and a driving method thereof can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device and a driving method thereof can be provided.

[0021] The description of multiple effects does not prevent the existence of other effects. Also, one embodiment of the present invention does not necessarily have all of the illustrated effects. Further, regarding one embodiment of the present invention, other problems, effects, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

[0022] FIG. 1A is a circuit diagram showing a configuration example of a cell. FIGS. 1B1 to 1B4 are diagrams showing a configuration example of a capacitor. FIG. 2 is a diagram showing the hysteresis characteristics of a ferroelectric. FIG. 3 is a timing chart showing an example of a cell driving method. FIGS. 4A and 4B are circuit diagrams showing an example of a cell driving method. FIGS. 5A and 5B are circuit diagrams showing an example of a cell driving method. FIG. 6 is a timing chart showing an example of a cell driving method. FIGS. 7A and 7B are circuit diagrams showing an example of a cell driving method. FIGS. 8A and 8B are circuit diagrams showing an example of a cell driving method. FIG. 9 is a timing chart showing an example of a cell driving method. FIGS. 10A and 10B are circuit diagrams showing a configuration example of a cell. FIGS. 11A and 11B are circuit diagrams showing a configuration example of a cell. FIGS. 12A and 12B are circuit diagrams showing a configuration example of a cell. FIG. 13 is a block diagram showing a configuration example of a semiconductor device. FIGS. 14A and 14B are diagrams for explaining a hierarchical neural network. FIG. 15A is a block diagram showing a configuration example of a semiconductor device. FIG. 15B is a circuit diagram showing a configuration example of a circuit included in the semiconductor device. FIGS. 16A to 16C are timing charts for explaining an operation example of a semiconductor device. FIGS. 17A to 17C are timing charts for explaining an operation example of a semiconductor device. Figures 18A to 18C are timing charts for explaining the operation example of the semiconductor device. Figure 19 is a diagram showing a structural example of the semiconductor device. Figures 20A to 20C are diagrams showing the configuration example of the transistor. Figure 21A is a diagram for explaining the classification of the crystal structure of IGZO. Figure 21B is a diagram for explaining the XRD spectrum of crystalline IGZO. Figure 21C is a diagram for explaining the selected area electron diffraction pattern of crystalline IGZO. Figure 22A is a perspective view showing an example of a semiconductor wafer. Figure 22B is a perspective view showing an example of a chip. Figures 22C and 22D are perspective views showing an example of an electronic component. Figures 23A to 23J are diagrams for explaining an example of an electronic device. Figures 24A to 24E are diagrams for explaining an example of an electronic device. Figures 25A to 25C are diagrams for explaining an example of an electronic device. Figure 26 is a circuit diagram for explaining the outline of the off-current measurement TEG of the embodiment. Figure 27A is a cross-sectional view for explaining the configuration of the capacitor of the embodiment. Figure 27B is a circuit diagram for explaining the outline of the capacitor leakage current measurement TEG of the embodiment. Figure 28 is a graph showing the temperature dependence of the leakage current of the embodiment.

Embodiments for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described. However, one embodiment of the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0024] In this specification and the like, ordinal numbers such as "first", "second", and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. For another example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0025] In the drawings, the same reference numerals may be given to the same elements, elements having similar functions, elements of the same material, or elements formed simultaneously, and repeated descriptions thereof may be omitted.

[0026] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Also, when described as an OS FET or an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0027] Also, in this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0028] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for driving the same will be described.

[0029] One aspect of the present invention relates to a semiconductor device having cells. The cells have a function of holding data. Specifically, the cells have capacitance, and by holding electric charges in the capacitance, the data written in the cells can be held. Therefore, the cells can be called memory cells, and the semiconductor device can be called a storage device.

[0030] In one aspect of the present invention, the capacitance is configured to include a first electrode, a second electrode, and a ferroelectric layer. The ferroelectric layer is provided between the first electrode and the second electrode. By configuring the capacitance in this way, the amount of electric charge that can be held in the capacitance can be made larger than that of a capacitance having a paraelectric layer provided between the first electrode and the second electrode. Therefore, the semiconductor device according to one aspect of the present invention can hold data for a long period of time. As a result, the frequency of refresh (rewriting of data to the cells) can be reduced, and thus the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0031] In this specification and the like, a ferroelectric substance refers to a substance that maintains the polarized state even after the application of voltage is stopped after being polarized by applying voltage. A paraelectric substance refers to a substance whose polarized state is not maintained and disappears when the application of voltage is stopped after being polarized by applying voltage.

[0032] <Example configuration of cell_1> FIG. 1A is a circuit diagram showing a configuration example of a cell 10 included in a semiconductor device according to one aspect of the present invention.

[0033] The cell 10 includes a capacitance 11, a transistor 21, a transistor 22, and a transistor 23. The capacitance 11 includes a ferroelectric layer 12, an electrode 13a, and an electrode 13b, and the ferroelectric layer 12 is provided between the electrode 13a and the electrode 13b.

[0034] Electrode 13a is electrically connected to one of the source or drain of transistor 21. One of the source or drain of transistor 21 is electrically connected to the gate of transistor 22. One of the source or drain of transistor 22 is electrically connected to one of the source or drain of transistor 23. Here, the node where electrode 13a, one of the source or drain of transistor 21, and the gate of transistor 22 are electrically connected is defined as node ND1.

[0035] The gate of transistor 21 is electrically connected to wiring 31. Electrode 13b is electrically connected to wiring 32. The gate of transistor 23 is electrically connected to wiring 33. The other of the source or drain of transistor 21 is electrically connected to wiring 41. The other of the source or drain of transistor 22 is electrically connected to wiring 42. The other of the source or drain of transistor 23 is electrically connected to wiring 43. Here, a fixed potential can be supplied to wiring 42.

[0036] Note that transistors 21 to 23 shown in Fig. 1A are not provided with a back gate, but a back gate may be provided. For example, a back gate may be provided for a part of transistors 21 to 23, or a back gate may be provided for all of them.

[0037] In cell 10 shown in Fig. 1A, the potential of wiring 31 can be set to the potential of the gate of transistor 21. Also, the potential of wiring 32 can be set to the potential of electrode 13b. Furthermore, the potential of wiring 33 can be set to the potential of the gate of transistor 23. For example, when transistor 21 is an n-channel transistor, when wiring 31 is at a high potential, transistor 21 can be turned on, and when wiring 31 is at a low potential, transistor 21 can be turned off. The relationship between transistor 23 and wiring 33 is the same.

[0038] When the transistor 21 is turned on, the node ND1 and the wiring 41 are electrically connected. Therefore, the potential of the wiring 41 can be written to the node ND1. Specifically, the charge corresponding to the potential of the wiring 41 can be accumulated in the node ND1. From the above, when the transistor 21 is turned on and a signal is supplied to the wiring 41, the data represented by the signal can be written into the cell 10. Therefore, the wiring 41 can be referred to as a write line.

[0039] After writing data into the cell 10, by turning off the transistor 21, the charge of the node ND1 is retained. Therefore, the data can be held in the cell 10.

[0040] The potential of the gate of the transistor 22 is the potential of the node ND1. Therefore, when the transistor 23 is turned on while the data is held in the cell 10, a current of a magnitude corresponding to the data flows through the transistors 22 and 23 to the wiring 43. Thereby, the data held in the cell 10 can be read out. Therefore, the wiring 43 can be referred to as a read line.

[0041] As described above, in the capacitor 11, the ferroelectric layer 12 is provided between the electrode 13a and the electrode 13b. Thereby, although details will be described later, when the ferroelectric layer 12 is not provided between the electrode 13a and the electrode 13b and a normal dielectric layer is provided, and assuming that the dielectric constant of the ferroelectric layer 12 and the normal dielectric layer is equal, the capacitance value of the capacitor 11 becomes larger. As a result, the amount of charge that can be stored in the capacitor 11 increases. Therefore, the fluctuation of the potential of the node ND1 due to the leakage of charge from the capacitor 11 is reduced. Therefore, the data can be held in the cell 10 for a long time. Thereby, since the frequency of refresh (rewriting of data to the cell 10) can be reduced, the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0042] Here, due to the small fluctuation in the potential of the node ND1 associated with the charge leakage from the capacitor 11, the data held by the cell 10 can be analog data. Also, the data held by the cell 10 can be multi-valued digital data, specifically digital data with three or more values. Of course, the cell 10 can also hold binary digital data.

[0043] As the ferroelectric layer 12, for example, barium titanate, lead zirconate titanate, strontium bismuth tantalate, etc. can be used.

[0044] The transistor 21 is preferably an OS transistor. The OS transistor has the characteristic that the off-current is extremely small. Therefore, by using the OS transistor as the transistor 21, it is possible to suppress the charge accumulated in the node ND1 from leaking through the transistor 21. As a result, the charge can be held in the node ND1 for a long time, so that the data of the cell 10 can be held for a long time. Thereby, the refresh frequency can be reduced, and the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0045] The transistors 22 and 23 can be transistors including silicon in the channel formation region (hereinafter referred to as Si transistors). As the silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used.

[0046] By using Si transistors as the transistors 22 and 23, the on-currents of the transistors 22 and 23 can be increased. As described above, a current of a magnitude corresponding to the potential of the node ND1 flows through the transistors 22 and 23 to the wiring 43, so that the data held in the cell 10 can be read out. From the above, by using Si transistors as the transistors 22 and 23, data can be read out at high speed.

[0047] Note that an Si transistor can be used as the transistor 21. Also, an OS transistor can be used as the transistors 22 and 23. Here, the OS transistor has the characteristic of high breakdown voltage. Therefore, by using the transistors 21 to 23 as OS transistors, a high voltage can be supplied to the node ND1. As a result, the difference between the minimum value and the maximum value of the potential of the signal that can be supplied to the wiring 41 can be increased.

[0048] FIGS. 1B1 to 1B4 are diagrams showing a configuration example of the capacitor 11. The capacitor 11 shown in FIGS. 1B1 to 1B4 is different from the capacitor 11 shown in FIG. 1A in that the layer provided between the electrodes 13a and 13b is different.

[0049] In the capacitor 11 shown in FIG. 1B1 and the capacitor 11 shown in FIG. 1B2, in addition to the ferroelectric layer 12, a paraelectric layer 14 is provided. FIG. 1B1 shows a configuration in which the ferroelectric layer 12 has a region in contact with the electrode 13a and the paraelectric layer 14 has a region in contact with the electrode 13b. On the other hand, FIG. 1B2 shows a configuration in which the paraelectric layer 14 has a region in contact with the electrode 13a and the ferroelectric layer 12 has a region in contact with the electrode 13b.

[0050] In the capacitor 11 shown in FIG. 1B3, a ferroelectric layer 12a, a ferroelectric layer 12b, and a paraelectric layer 14 are provided. The ferroelectric layer 12a has a region in contact with the electrode 13a, and the ferroelectric layer 12b has a region in contact with the electrode 13b. The paraelectric layer 14 is provided between the ferroelectric layer 12a and the ferroelectric layer 12b. The ferroelectric layer 12a and the ferroelectric layer 12b can use the same material as the ferroelectric layer 12.

[0051] In the capacitor 11 shown in FIG. 1B4, a ferroelectric layer 12, a paraelectric layer 14a, and a paraelectric layer 14b are provided. The paraelectric layer 14a has a region in contact with the electrode 13a, and the paraelectric layer 14b has a region in contact with the electrode 13b. The ferroelectric layer 12 is provided between the paraelectric layer 14a and the paraelectric layer 14b.

[0052] As the paraelectric layer 14, the paraelectric layer 14a, and the paraelectric layer 14b, for example, high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc. can be used. Thereby, the capacitance value of the capacitor 11 can be made large.

[0053] As shown in FIGS. 1B1 to 1B4, by configuring the capacitor 11 such that a plurality of dielectric layers are stacked, leakage of the charge stored in the capacitor 11 can be suppressed. Thereby, since the charge can be held in the node ND1 for a long time, the data of the cell 10 can be held for a long time. Thereby, since the refresh frequency can be reduced, the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0054] <Characteristics of the ferroelectric layer 12> The ferroelectric layer 12 has hysteresis characteristics. FIG. 2 is a graph showing the hysteresis characteristics of the ferroelectric layer 12. In FIG. 2, the horizontal axis represents the voltage applied to the ferroelectric layer 12, specifically, the value obtained by subtracting the potential of the electrode 13b from the potential of the electrode 13a. Also, the vertical axis represents the polarization amount of the ferroelectric layer 12. When the value is positive, it indicates that positive charges are biased toward the electrode 13b side and negative charges are biased toward the electrode 13a side. On the other hand, when the polarization amount is negative, it indicates that positive charges are biased toward the electrode 13a side and negative charges are biased toward the electrode 13b side. Note that the voltage shown on the horizontal axis of the graph in FIG. 2 may be the value obtained by subtracting the potential of the electrode 13a from the potential of the electrode 13b. Also, the polarization amount shown on the vertical axis of the graph in FIG. 2 may be set to a positive value when positive charges are biased toward the electrode 13a side and negative charges are biased toward the electrode 13b side, and a negative value when positive charges are biased toward the electrode 13b side and negative charges are biased toward the electrode 13a side.

[0055] As shown in FIG. 2, the hysteresis characteristics of the ferroelectric layer 12 can be represented by a curve 51 and a curve 52. Let the voltages at the intersection of the curve 51 and the curve 52 be the voltage VSP1 and the voltage VSP2. In FIG. 2, it is assumed that the value of the voltage VSP1 is negative and the value of the voltage VSP2 is positive. It can be said that the voltage VSP1 and the voltage VSP2 have different polarities.

[0056] After applying the voltage VSP1 to the ferroelectric layer 12 and then increasing the voltage applied to the ferroelectric layer 12, the polarization amount of the ferroelectric layer 12 increases according to the curve 51. On the other hand, after applying the voltage VSP2 to the ferroelectric layer 12 and then decreasing the voltage applied to the ferroelectric layer 12, the polarization amount of the ferroelectric layer 12 decreases according to the curve 52. Therefore, the voltage VSP1 and the voltage VSP2 can be referred to as saturation polarization voltages.

[0057] Here, when the polarization amount of the ferroelectric layer 12 changes according to the curve 51, the voltage applied to the ferroelectric layer 12 when the polarization amount of the ferroelectric layer 12 is 0 is defined as voltage V1. Also, when the polarization amount of the ferroelectric layer 12 changes according to the curve 52, the voltage applied to the ferroelectric layer 12 when the polarization amount of the ferroelectric layer 12 is 0 is defined as voltage V2. As shown in FIG. 2, the voltage V1 can be a positive value, and the voltage V2 can be a negative value. The value of the voltage V1 and the value of the voltage V2 can be values between the voltage VSP1 and the voltage VSP2.

[0058] <Example of a cell driving method_1> FIG. 3 is a timing chart showing an example of a driving method of the cell 10. In the timing chart shown in FIG. 3, "H" represents a high potential and "L" represents a low potential. Note that in the timing chart shown in FIG. 3, potential changes due to wiring resistance, resistance between the drain and source of a transistor, etc., and signal delays are not considered. The same applies to other timing charts.

[0059] During the period T1, the potential of the wiring 31 is set to a high potential, the potential of the wiring 32 is set to the potential PCH, and the potential of the wiring 33 is set to a low potential. By setting the potential of the wiring 31 to a high potential, the transistor 21 is turned on, and by setting the potential of the wiring 33 to a low potential, the transistor 23 is turned off. In this state, the potential of the wiring 41 is set to the potential PRES. Since the transistor 21 is turned on, the potential of the node ND1 becomes the potential PRES. As described above, the voltage applied to the ferroelectric layer 12, specifically, the difference between the potential of the electrode 13a and the potential of the electrode 13b becomes the voltage "PRES - PCH". In the following description as well, the voltage applied to the ferroelectric layer 12 refers to the difference between the potential of the electrode 13a and the potential of the electrode 13b.

[0060] FIG. 4A is a circuit diagram showing the state of the cell 10 during the period T1. In FIG. 4A, a transistor in the off state is shown with an × mark. The same description may be made in other figures.

[0061] As shown in FIG. 4A, in period T1, a voltage VSP1 is applied to the ferroelectric layer 12. Specifically, the values of the potential PRES and the potential PCH are set such that the value of the voltage “PRES - PCH” is equal to the value of the voltage VSP1. For example, when the voltage VSP1 is -3.3V, the potential PRES is set to 0V and the potential PCH is set to 3.3V.

[0062] Note that in FIG. 4A, the voltage applied to the ferroelectric layer 12 is shown surrounded by a dashed - dotted line. Similar descriptions may be made in other drawings.

[0063] In period T1, by applying a voltage VSP1, which is the saturation polarization voltage, to the ferroelectric layer 12, the polarization state of the ferroelectric layer 12 can be reset. Therefore, the potential PRES supplied to the node ND1 in period T1 can be referred to as the reset potential. Also, the operation performed in period T1 can be referred to as the reset operation.

[0064] In period T2, the potential of the wiring 32 is set to the potential PCL. In this state, a data signal is supplied to the wiring 41. Specifically, the potential of the wiring 41 is set to the potential PSIG. Since the transistor 21 is in the on - state, the potential of the node ND1 becomes the potential PSIG. As a result, the voltage applied to the ferroelectric layer 12 becomes the voltage “PSIG - PCL”. Here, the potential PCL can be set to a potential lower than the potential PCH.

[0065] FIG. 4B is a circuit diagram showing the state of the cell 10 in period T2. Note that in FIG. 4B, the potentials and voltages changed from period T1 are shown surrounded by a double - dashed line. Similar descriptions may be made in other drawings.

[0066] As shown in FIG. 4B, let the voltage applied to the ferroelectric layer 12 in period T2 be voltage VSIG. Since the potential PSIG supplied to node ND1 in period T2 corresponds to the potential of the data signal, voltage VSIG can be referred to as the data voltage. Since voltage VSP1 is applied to the ferroelectric layer 12 in period T1, in period T2, the polarization amount of the ferroelectric layer 12 becomes as shown by curve 51 in FIG. 2.

[0067] Here, set the values of potential PSIG and potential PCL such that the value of voltage VSIG is higher than voltage VSP1 and lower than voltage VSP2. In particular, since the capacitance value of capacitor 11 corresponds to the slope of curve 51, specifically, for example, the slope of the tangent line of curve 51, it is preferable to set the value of voltage VSIG such that the slope of curve 51 is greater than or equal to a certain value. Thereby, the capacitance value of capacitor 11 can be increased. Specifically, as described above, when a paraelectric layer is provided instead of the ferroelectric layer 12 between electrode 13a and electrode 13b, assuming that the dielectric constant of the ferroelectric layer 12 is equal to that of the paraelectric layer, the capacitance value of capacitor 11 increases.

[0068] Specifically, for example, it is preferable that the value of voltage VSIG is equal to or higher than the voltage at which the slope of curve 51 is a certain value or more and equal to or lower than the voltage at the inflection point of curve 51. Also, it is preferable that the value of voltage VSIG is such that the polarity of the polarization amount of the ferroelectric layer 12 in period T1 is the same as the polarity of the polarization amount of the ferroelectric layer 12 in period T2. That is, when the polarity of the ferroelectric layer 12 in period T1 is negative, specifically, when positive charges are biased toward electrode 13a and negative charges are biased toward electrode 13b, it is preferable that the polarity of the ferroelectric layer 12 in period T2 is also negative. Therefore, it is preferable that voltage VSIG is equal to or lower than voltage V1 shown in FIG. 2. In FIG. 4B and the like, voltage VSIG is assumed to be equal to or lower than voltage V1.

[0069] From the above, it is preferable that the value of the voltage VSIG is, for example, equal to or higher than the voltage at which the slope of the curve 51 becomes equal to or greater than a certain value and equal to or lower than the voltage V1. For example, when the voltage V1 is 1.2V and the potential PCL is 0V, it is preferable that the potential PSIG is equal to or higher than 0V and equal to or lower than 1.2V. In this case, the voltage VSIG becomes equal to or higher than 0V and equal to or lower than 1.2V.

[0070] As described above, data can be written into the cell 10 during the period T2.

[0071] During the period T3, the potential of the wiring 31 is set to a low potential. As a result, since the transistor 21 is turned off, the charge accumulated in the node ND1 is retained. Therefore, the potential of the node ND1 is retained at the potential PSIG.

[0072] FIG. 5A is a circuit diagram showing the state of the cell 10 during the period T3. As shown in FIG. 5A, during the period T3, the voltage applied to the ferroelectric layer 12 is retained at the voltage VSIG.

[0073] By writing data into the cell 10 by the method shown in the periods T1 and T2, as described above, the capacitance value of the capacitor 11 can be increased. As a result, the amount of charge that can be stored in the capacitor 11 can be increased. Therefore, during the period T3, the fluctuation of the potential of the node ND1 due to the leakage of charge from the capacitor 11 can be reduced. Accordingly, data can be retained in the cell 10 for a long period of time. As a result, the refresh frequency can be reduced, and thus the power consumption of the semiconductor device according to one aspect of the present invention can be reduced. Further, as described above, the data held by the cell 10 can be analog data. Also, the data held by the cell 10 can be multi-valued digital data, specifically digital data of three values or more. Of course, the cell 10 can also hold binary digital data.

[0074] During period T4, set the potential of wiring 33 to a high potential. As a result, since transistor 23 turns on, a current of a magnitude corresponding to the potential PSIG of node ND1 flows through wiring 43 via transistor 22 and transistor 23. Thereby, the data held in cell 10 can be read out.

[0075] Figure 5B is a circuit diagram showing the state of cell 10 during period T4. Transistor 23 turns on, and the data held in cell 10 is read out from wiring 43.

[0076] During period T5, set the potential of wiring 33 to a low potential. As a result, transistor 23 turns off, and the reading of the data held in cell 10 ends. Since the potential of node ND1 does not change due to the reading of the data, the reading is a non-destructive read.

[0077] The above is an example of a method for driving cell 10.

[0078] <An example of a method for driving a cell_2> In the driving method shown in FIGS. 3 to 5, voltage VSP1 was applied to ferroelectric layer 12 during period T1. However, during period T1, a voltage VSP2, which is a saturation polarization voltage having a polarity different from that of voltage VSP1, may be applied to ferroelectric layer 12. FIG. 6 is a timing chart showing an example of a method for driving cell 10 when voltage VSP2 is applied to ferroelectric layer 12 during period T1. FIGS. 7A, 7B, 8A, and 8B are circuit diagrams showing the state of cell 10 during periods T1 to T4 shown in FIG. 6, respectively.

[0079] As shown in FIG. 6, the potential of wiring 32 can be set to potential PCL during period T1 and can be set to potential PCH during periods T2 to T5. Also, in the driving method shown in FIG. 3, for example, potential PRES was lower than potential PSIG, but in the driving method shown in FIG. 6, potential PRES can be made higher than potential PSIG.

[0080] When driving the cell 10 by the method shown in FIG. 6, the values of the potential PRES and the potential PCL are set so that the value of the voltage "PRES-PCL" becomes equal to the value of the voltage VSP2. For example, when the voltage VSP2 is 3.3V, the potential PRES is set to 3.3V and the potential PCL is set to 0V.

[0081] When driving the cell 10 by the method shown in FIG. 6, the voltage applied to the ferroelectric layer 12 in the period T2 becomes the voltage "PSIG-PCH". Since the voltage VSP2 is applied to the ferroelectric layer 12 in the period T1, in the period T2, the polarization amount of the ferroelectric layer 12 becomes as shown by the curve 52 shown in FIG. 2.

[0082] When driving the cell 10 by the method shown in FIG. 6, the value of the voltage VSIG is preferably, for example, not less than the voltage V2 shown in FIG. 2 and not more than the voltage at which the slope of the curve 52, specifically, for example, the slope of the tangent line of the curve 52 becomes a certain value or more. For example, when the voltage V2 is -1.2V and the potential PCH is 3.3V, the potential PSIG is preferably not less than 2.1V and not more than 3.3V. In this case, the voltage VSIG is not less than -1.2V and not more than 0V. In FIG. 7B etc., the voltage VSIG is assumed to be not less than the voltage V2.

[0083] <An example of the cell driving method_3> In the driving methods shown in FIGS. 3 to 5, the potential of the wiring 32 is varied, but the potential of the wiring 32 may be a fixed potential. FIG. 9 is a timing chart showing an example of a driving method of the cell 10 when the potential PCL is supplied as a fixed potential to the wiring 32 in the periods T1 to T5.

[0084] When driving the cell 10 by the method shown in FIG. 9, the potential of the node ND1 in the period T1 is set as the potential PRESa. The potential PRESa can be a potential lower than the potential PRES shown in FIG. 3 or the like. For example, when the voltage VSP1 is -3.3V and the potential PCL is 0V, the potential PRESa can be -3.3V. As described above, for example, when the voltage VSP1 is -3.3V, the potential PRES can be 0V. Therefore, if the voltage VSP1 is the same, the potential PRESa can be made lower than the potential PRES.

[0085] When driving the cell 10 by the method shown in FIG. 9, it is preferable to use an OS transistor as the transistor 21. As described above, the OS transistor has the characteristic of high breakdown voltage. Therefore, when using an OS transistor as the transistor 21, the potential PRESa can be made lower. Similarly, it is preferable to use an OS transistor also for the transistor 22. Furthermore, an OS transistor may also be used for the transistor 23.

[0086] <Example configuration of cell_2> In the cell 10 shown in FIG. 1A, all of the transistors 21 to 23 are assumed to be n-channel transistors, but one aspect of the present invention is not limited to this. FIG. 10A is a circuit diagram showing a configuration example of the cell 10 when the transistors 22 and 23 are p-channel transistors. In the cell 10 shown in FIG. 10A, the transistor 21 can be, for example, an OS transistor or an Si transistor. Also, the transistors 22 and 23 can be Si transistors.

[0087] FIG. 10B is a circuit diagram showing a configuration example of the cell 10 when all of the transistors 21 to 23 are p-channel transistors. In the cell 10 shown in FIG. 10B, the transistors 21 to 23 can be, for example, Si transistors.

[0088] The driving method shown in FIGS. 3 to 9 can be applied even when the cell 10 has the configuration shown in FIG. 10A or FIG. 10B by appropriately changing the magnitude relationship of the potentials or the like.

[0089] The cell 10 shown in FIG. 1A has the transistor 23, but it does not necessarily have the transistor 23. FIG. 11A is a circuit diagram showing a configuration example of the cell 10 in which the transistor 23 is omitted. In the cell 10 having the configuration shown in FIG. 11A, one of the source or drain of the transistor 22 is electrically connected to the wiring 43. When driving the cell 10 shown in FIG. 11A, the data held in the cell 10 can be read from the wiring 43 without performing the operation in the period T4 shown in FIG. 3 or the like.

[0090] In the cell 10 shown in FIG. 11A or the like, the wiring having the function as the write line is the wiring 41, and the wiring having the function as the read line is the wiring 43, but the write line and the read line may be shared. The cell 10 shown in FIG. 11B is different from the cell 10 shown in FIG. 11A in that the wiring having the function as the write line and the wiring having the function as the read line are shared as the wiring 44.

[0091] In the cell 10 shown in FIG. 11B, the other of the source or drain of the transistor 21 and one of the source or drain of the transistor 22 are electrically connected to the wiring 44. In this way, by sharing the write line and the read line, the number of wirings provided in the semiconductor device having the cell 10 can be reduced. Thereby, the semiconductor device can be miniaturized.

[0092] FIG. 12A is a modified example of the cell 10 shown in FIG. 1A, and is different from the cell 10 shown in FIG. 1A in that the wiring having the function as the write line and the wiring having the function as the read line are shared as the wiring 44. In the cell 10 having the configuration shown in FIG. 12A, the other of the source or drain of the transistor 21 and the other of the source or drain of the transistor 23 are electrically connected to the wiring 44.

[0093] FIG. 12B is a modified example of the cell 10 shown in FIG. 12A, and is different from the cell 10 shown in FIG. 12A in that the other of the source or drain of the transistor 21 is electrically connected to one of the source or drain of the transistor 22 and one of the source or drain of the transistor 23.

[0094] When driving the cell 10 shown in FIG. 12B in the manner shown in FIG. 3 or the like, a high potential is supplied to the wiring 33 together with the wiring 31 in the periods T1 and T2. As a result, the transistor 23 is turned on together with the transistor 21. Therefore, the wiring 44 and the node ND1 are in a conductive state, and the potential PRES, the potential PSIG, etc. can be supplied to the node ND1.

[0095] By configuring the cell 10 as shown in FIG. 12B, it is possible to suppress the generation of parasitic capacitance between the gate of the transistor 21 and the wiring 44. Therefore, it is possible to suppress the generation of noise in the data written in the cell 10.

[0096] <Configuration Example of Semiconductor Device_1> FIG. 13 is a block diagram showing a configuration example of a semiconductor device 60 having the cell 10. In the semiconductor device 60, a cell array 61 is constituted by m rows and n columns (m and n are integers of 2 or more) of cells 10. The semiconductor device 60 also has a circuit 62 and a circuit 63.

[0097] In FIG. 13, [1,1], [i,1], [m,1], [1,j], [i,j], [m,j], [1,n], [i,n], [m,n] (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) are addresses of the cell 10. For example, the cell 10 denoted as [i,j] is the cell 10 at the i-th row and j-th column. Hereinafter, for example, the cell 10 with the address [i,j] is denoted as cell 10[i,j].

[0098] Cell 10 is electrically connected to circuit 62 via wiring 31, wiring 32, and wiring 33, and is electrically connected to circuit 63 via wiring 41 and wiring 43. For example, cell 10[i,j] is electrically connected to circuit 62 via wiring 31(i), wiring 32(i), and wiring 33(i), and is electrically connected to circuit 63 via wiring 41(j) and wiring 43(j).

[0099] Circuit 62 has a function of generating a potential necessary for driving cell 10 and supplying it to wiring 31, wiring 32, or wiring 33. By circuit 62, writing data to cell 10 and reading data held in cell 10 can be sequentially performed from the cell 10 in the first row to the cell 10 in the m-th row. As shown in FIG. 9, when supplying a fixed potential to wiring 32, it is not necessary to electrically connect wiring 32 to circuit 62.

[0100] Here, the reset operation, which is an operation performed during period T1, can be performed, for example, simultaneously for all cells 10. For example, when driving cell 10 in the method shown in FIG. 9, the potential PRESa, which is the potential of wiring 41 during period T1, becomes low. For example, the potential PRESa becomes a negative value. Therefore, when turning off transistor 21, if the potential of the gate of transistor 21 is not lowered, the difference between the potential of the gate of transistor 21 and the source potential PRESa may be equal to or greater than the threshold voltage of transistor 21, and it may not be possible to turn it off. For example, when the potential PRESa is -3.3V, even if a potential of 0V is supplied as a low potential to the gate of transistor 21, it may not be possible to turn off the transistor. When the reset operation, which is an operation performed during period T1, is sequentially performed for each row of cell 10, the cell 10 for which the reset operation has not been performed may be performing a data read operation. If transistor 21 included in cell 10 performing the data read operation is not in the off state, the potential of node ND1 becomes the potential PRESa, and data may not be read correctly. From the above, when driving cell 10 in the method shown in FIG. 9, it is preferable to perform the reset operation, which is an operation performed during period T1, simultaneously for all cells 10, for example.

[0101] Circuit 63 has the function of writing data into cell 10 and the function of reading data from cell 10. For example, circuit 63 has the function of generating potentials such as potential PRES and potential PSIG and supplying them to cell 10 via wiring 41. Further, circuit 63 has the function of reading data from cell 10 based on the potential of wiring 43. When cell 10 has the configuration shown in FIG. 11B, FIG. 12A, or FIG. 12B, circuit 63 is electrically connected to cell 10 via wiring 44. For example, cell 10[i,j] can be electrically connected to circuit 63 via wiring 44(j).

[0102] In the semiconductor device 60 shown in FIG. 13, it is assumed that circuit 62 generates all of the potential supplied to wiring 31, the potential supplied to wiring 32, and the potential supplied to wiring 33, but different circuits may generate the respective potentials. For example, the circuit that generates the potential supplied to wiring 32 may be different from the circuits that generate the potential supplied to wiring 31 and the potential supplied to wiring 33. Further, although circuit 63 has both the function of writing data into cell 10 and the function of reading data from cell 10, the circuit having the function of writing data into cell 10 and the circuit having the function of reading data from cell 10 may be different.

[0103] The configurations, methods, etc. shown in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments, examples, etc. described in this specification.

[0104] (Embodiment 2) In this embodiment, a semiconductor device according to an aspect of the present invention and a driving method thereof will be described. Specifically, a semiconductor device having a function of performing neural network operations will be described.

[0105] <Hierarchical neural network> First, a hierarchical neural network will be described. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 100 shown in FIG. 14A is an example thereof, and the neural network 100 has layers from the first layer to the R-th layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the R-th layer corresponds to the output layer, and the other layers correspond to the intermediate layers. Note that in FIG. 14A, the (k - 1)-th layer and the k-th layer (where k is an integer of 3 or more and R - 1 or less) are illustrated as intermediate layers, and the illustration of the other intermediate layers is omitted.

[0106] Each layer of the neural network 100 has one or more neurons. In FIG. 14A, the first layer has neurons N1 (1) through neuron N p (1) (where p is an integer of 1 or more), the (k - 1)-th layer has neurons N1 (k-1) through neuron N m (k-1) (where m is an integer of 1 or more), the k-th layer has neurons N1 (k) through neuron N n (k) (where n is an integer of 1 or more), and the R-th layer has neurons N1 (R) through neuron N q (R) (where q is an integer of 1 or more).

[0107] Note that in FIG. 14A, neurons N1 (1) , neuron N p (1) , neurons N1 (k-1) , neuron N m (k-1) , neurons N1 (k) , neuron N n (k) , neurons N1 (R) , neuron N q (R)In addition, neuron N of the (k - 1)-th layer i (k-1) (where i is an integer from 1 to m), neuron N of the k-th layer j (k) (where j is an integer from 1 to n) is also shown, and the illustration of other neurons is omitted.

[0108] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output in each neuron will be described. In this description, neuron N of the k-th layer j (k) is focused on.

[0109] FIG. 14B shows neuron N of the k-th layer j (k) and the signal input to neuron N j (k) and the signal output from neuron N j (k) .

[0110] Specifically, the output signals z1 (k-1) to z m (k-1) of each of neurons N1 (k-1) to N m (k-1) of the (k - 1)-th layer are output towards neuron N j (k) . And neuron N j (k) generates z (k-1) to z m (k-1) in response to z1 j (k) and outputs z j (k) as an output signal towards each neuron of the (k + 1)-th layer (not shown).

[0111] The signal input from the neurons in the previous layer to the neurons in the next layer has the degree of signal transmission determined by the connection strength of the synapses connecting those neurons (hereinafter referred to as the weight coefficient). In the neural network 100, the signal output from the neurons in the previous layer is multiplied by the corresponding weight coefficient and input to the neurons in the next layer. Let i be an integer from 1 to m, and for the neuron N in the (k - 1)-th layer i (k-1) and the neuron N in the k-th layer j (k) when the weight coefficient of the synapse between them is w i (k-1) j (k) the signal input to the neuron N in the k-th layer j (k) can be expressed by Equation (1).

[0112]

Equation

[0113] That is, when signals are transmitted from each of the neurons N1 in the (k - 1)-th layer (k-1) to neuron N m (k-1) to the neuron N in the k-th layer j (k) the signals z1 (k-1) to z m (k-1) are multiplied by the weight coefficients (w1 (k-1) j (k) to w m (k-1) j (k) ) corresponding to those signals respectively. And for the neuron N in the k-th layer j (k) there are w1 (k-1) j (k) ·z1 (k-1) to w m (k-1) j (k) ·z m (k-1)is input. At this time, the sum u of the signals input to the neuron N in the k-th layer j (k) is given by Equation (2). j (k) is as follows.

[0114]

Equation

[0115] Also, a bias may be given as a bias to the result of the sum of products of the weight coefficients w1 (k-1) j (k) to w m (k-1) j (k) and the signals z1 (k-1) to z m (k-1) of the neuron. When the bias is b, Equation (2) can be rewritten as the following equation.

[0116]

Equation

[0117] The neuron N j (k) generates an output signal z j (k) in response to u j (k) Here, the output signal z j (k) from the neuron N j (k) is defined by the following equation.

[0118]

Equation

[0119] The function f(u j (k)) is an activation function in a hierarchical neural network, and functions such as a step function, a linear ramp function, and a sigmoid function can be used. Note that the activation function may be the same for all neurons or may be different. In addition, the activation function of neurons may be the same or different for each layer.

[0120] By the way, the signal output by the neurons in each layer, the weight coefficient w, or the bias b may be an analog value or a digital value. As a digital value, for example, it may be a binary value or a ternary value. Values with even larger bit numbers are also possible. As an example, in the case of an analog value, functions such as a linear ramp function and a sigmoid function may be used as the activation function. In the case of a binary digital value, for example, a step function that outputs -1 or 1, or 0 or 1, may be used. Also, the signal output by the neurons in each layer may be three or more values. In this case, the activation function may be a step function with three or more values, for example, the output is -1, 0, or 1, or a step function with 0, 1, or 2, etc. Also, for example, as an activation function that outputs five or more values, a step function that outputs -2, -1, 0, 1, or 2 may be used. By using a digital value for at least one of the signal output by the neurons in each layer, the weight coefficient w, or the bias b, the circuit scale can be reduced, the power consumption can be reduced, or the operation speed can be increased, etc. Also, by using an analog value for at least one of the signal output by the neurons in each layer, the weight coefficient w, or the bias b, the accuracy of the operation can be improved.

[0121] When an input signal is input to the first layer (input layer) of the neural network 100, in each layer from the first layer (input layer) to the last layer (output layer) in sequence, based on the signal input from the previous layer, the output signal is generated using Equation (1), Equation (2) (or Equation (3)), and Equation (4), and the operation of outputting the output signal to the next layer is performed. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network 100.

[0122] <Configuration Example of Arithmetic Circuit> Here, in the neural network 100 described above, an example of an arithmetic circuit capable of performing the operations of Expression (2) (or Expression (3)) and Expression (4) will be described. In this arithmetic circuit, as an example, the weight coefficients of the synaptic circuits of the neural network 100 are binary values (a combination of “-1” and “+1”, or a combination of “0” and “+1”, etc.), ternary values (a combination of “-1”, “0”, and “1”, etc.), or multi-valued values of four or more values (in the case of five values, a combination of “-2”, “-1”, “0”, “1”, and “2”, etc.), and the activation function of the neuron is a function that outputs binary values (a combination of “-1” and “+1”, or a combination of “0” and “+1”, etc.), ternary values (a combination of “-1”, “0”, and “1”, etc.), or multi-valued values of four or more values (in the case of four values, a combination of “0”, “1”, “2”, and “3”, etc.). Also, in this specification and the like, the weight coefficient is referred to as the first data, and the value of the signal (which may be referred to as the arithmetic value) input from the neuron in the previous layer to the neuron in the next layer is sometimes referred to as the second data. Note that the weight coefficients of the synaptic circuits of the neural network 100 and the arithmetic values are not limited to digital values, and it is also possible to use analog values for at least one of them.

[0123] The arithmetic circuit 110 shown in FIG. 15A is, as an example, a semiconductor device having an array unit ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 110 processes the signals z1 (k) to n (k) input to the neurons N1 (k-1) to m (k-1) in the k-th layer in FIGS. 14A and 14B, and generates the signals z1 (k) to n (k) output from each of the neurons N1 (k) to n (k) and is a circuit that generates z.

[0124] Note that the entire arithmetic circuit 110 or a part thereof may be used for applications other than neural networks or AI. For example, when performing a multiplication-accumulation operation or a matrix operation in graphic calculations or scientific calculations, the entire arithmetic circuit 110 or a part thereof may be used for processing. That is, not only for AI calculations, but also for general calculations, the entire arithmetic circuit 110 or a part thereof may be used.

[0125] The circuit ILD is electrically connected to the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n] as an example. The circuit WLD is electrically connected to the wirings WLS[1] to WLS[m] as an example. The circuit XLD is electrically connected to the wirings XLS[1] to XLS[m] as an example. The circuit AFP is electrically connected to the wirings OL[1] to OL[n] and the wirings OLB[1] to OLB[n] as an example.

[0126] <<Array section ALP>> The array section ALP has m×n circuits MP as an example. The circuits MP are arranged in a matrix of m rows and n columns within the array section ALP as an example. In FIG. 15A, the circuit MP located at the i-th row and j-th column (where i is an integer from 1 to m and j is an integer from 1 to n) is denoted as circuit MP[i,j]. However, in FIG. 15A, only the circuits MP[1,1], MP[m,1], MP[i,j], MP[1,n], and MP[m,n] are illustrated, and the illustration of the other circuits MP is omitted.

[0127] The circuit MP[i,j] is electrically connected to the wiring IL[j], the wiring ILB[j], the wiring WLS[i], the wiring XLS[i], the wiring OL[j], and the wiring OLB[j] as an example.

[0128] The circuit MP[i,j] is a neuron N as an example i (k-1) and neuron N j (k)It has a function of holding the weight coefficient (first data) between them. Specifically, the circuit MP[i, j] holds information (such as potential, resistance value, current value, etc.) corresponding to the first data (weight coefficient) input from the wiring IL[j] and the wiring ILB[j]. Also, the circuit MP[i, j] i (k-1) has a function of outputting the product of the signal z i (k-1) (second data) output from the neuron N and the first data. As a specific example, the circuit MP[i, j] inputs information (such as potential, resistance value, current value, etc.) corresponding to the second data z i (k-1) from the wiring XLS[i], and outputs information (such as potential, resistance value, current value, etc.) corresponding to the product of the first data and the second data to the wirings OL[j] and OLB[j]. Although an example where both the wiring IL[j] and the wiring ILB[j] are arranged is shown, one aspect of the present invention is not limited to this. Only one of the wirings IL[j] and ILB[j] may be arranged.

[0129] <<Circuit ILD>> As an example, the circuit ILD has a function of inputting information (such as potential, resistance value, current value, etc.) corresponding to the first data w1 (k-1) 1 (k) to w m (k-1) n (k) which are weight coefficients, to each of the circuits MP[1, 1] to MP[m, n] via the wirings IL[1] to IL[n] and the wirings ILB[1] to ILB[n]. As a specific example, the circuit ILD supplies information (such as potential, resistance value, or current value, etc.) corresponding to the first data w i (k-1) j (k) to the circuit MP[i, j] via the wirings IL[j] and ILB[j].

[0130] <<Circuit XLD>> As an example, the circuit XLD is the neuron N1 (k-1)up to neuron N m (k-1) The second data z1 corresponding to the calculated value output from (k-1) up to z m (k-1) has a function of supplying, via wirings XLS[1] to XLS[m], to each of circuits MP[1,1] to MP[m,n]. Specifically, circuit XLD supplies, via wiring XLS[i], the information (e.g., potential, current value, etc.) corresponding to the second data z output from neuron N i (k-1) The second data z output from i (k-1) to each of circuits MP[i,1] to MP[i,n].

[0131] <<Circuit WLD>> Circuit WLD has, as an example, a function of selecting a circuit MP that is a writing destination for information (e.g., potential, resistance value, current value, etc.) corresponding to the first data input from circuit ILD. For example, when writing information (e.g., potential, resistance value, current value, etc.) to circuits MP[i,1] to MP[i,n] located in the i-th row of array section ALP, circuit WLD may supply, to wiring WLS[i], a signal for turning on or off the writing switching elements included in circuits MP[i,1] to MP[i,n], and supply, to wiring WLS, a potential for turning off the writing switching elements included in circuits MP other than the i-th row. In addition, for example, in addition to wiring WLS[i], a wiring for transmitting an inverted signal of the signal input to wiring WLS[i] may be separately arranged.

[0132] <<Circuit AFP>> The circuit AFP has, for example, circuits ACTF[1] to ACTF[n]. The circuit ACTF[j] is electrically connected to each of, for example, the wiring OL[j] and the wiring OLB[j]. The circuit ACTF[j] generates a signal according to each piece of information (for example, potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j]. For example, it compares each piece of information (for example, potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j], and generates a signal according to the comparison result. The signal corresponds to the signal z output from the neuron N j (k) from which it is output j (k) That is, the circuits ACTF[1] to ACTF[n] function as circuits that perform the operation of the activation function of the neural network described above, for example. However, one aspect of the present invention is not limited to this. For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Or, for example, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting an output impedance. Or, for example, the circuits ACTF[1] to ACTF[n] may have a function of converting current or charge into voltage. Or, for example, the circuits ACTF[1] to ACTF[n] may have a function of initializing the potential of the wiring OL[j] or the wiring OLB[j].

[0133] <<Circuit MP>> FIG. 15B shows an example of the configuration of the circuit MP. The circuit MP has a circuit MC and a circuit MCr. The circuit MC has, for example, transistors M1 to M4 and a capacitor C1. The circuit MCr has, for example, transistors M1r to M4r and a capacitor C1r. The capacitor C1 and the capacitor C1r can have the same configuration as the capacitor 11 shown in Embodiment 1. Note that, for example, the holding unit HC is constituted by the transistor M2 and the capacitor C1. Also, for example, the holding unit HCr is constituted by the transistor M2r and the capacitor C1r.

[0134] The transistors M1 to M4 and the transistors M1r to M4r shown in FIG. 15B are, as an example, n-channel transistors of a multi-gate structure having gates above and below the channel. Each of the transistors M1 to M4 and the transistors M1r to M4r has a first gate and a second gate. In particular, as an example, it is preferable that the size of the transistor M3 is equal to the size of the transistor M4, and it is preferable that the size of the transistor M3r is equal to the size of the transistor M4r.

[0135] In the circuit MP of FIG. 15B, one of the source or drain of the transistor M1 is electrically connected to the wiring VE. The other of the source or drain of the transistor M1 is electrically connected to one of the source or drain of the transistor M3 and one of the source or drain of the transistor M4. The gate of the transistor M1 is electrically connected to the first electrode of the capacitor C1 and one of the source or drain of the transistor M2. The second electrode of the capacitor C1 is electrically connected to the wiring VE. The other of the source or drain of the transistor M2 is electrically connected to the wiring OL. The gate of the transistor M2 is electrically connected to the wiring WL. The other of the source or drain of the transistor M3 is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring WX1L. The other of the source or drain of the transistor M4 is electrically connected to the wiring OLB, and the gate of the transistor M4 is electrically connected to the wiring X2L.

[0136] In the circuit MCr, a connection configuration different from that of the circuit MC will be described. The other of the source or drain of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and the other of the source or drain of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. One of the source or drain of the transistor M1r and the second electrode of the capacitor C1r are electrically connected to the wiring VEr.

[0137] In the holding section HC shown in FIG. 15B, the electrical connection point of the gate of the transistor M1, the first electrode of the capacitor C1, and one of the source or drain of the transistor M2 is defined as the node n1. Also, in the holding section HCr shown in FIG. 15B, the electrical connection point of the gate of the transistor M1r, the first electrode of the capacitor C1r, and one of the source or drain of the transistor M2r is defined as the node n1r.

[0138] The holding section HC, as an example, has a function of holding a potential corresponding to the first data. The holding of the potential in the holding section HC included in the circuit MC in FIG. 15B is performed by inputting the potential from the wiring OL when the transistors M2 and M3 are in the on state, writing the potential to the capacitor C1, and then turning off the transistor M2. Thereby, the potential of the node n1 can be held as the potential corresponding to the first data. At this time, a current can be input from the wiring OL, and a potential having a magnitude corresponding to the magnitude of the current can be held in the capacitor C1. Therefore, the influence of the variation in the current characteristics of the transistor M1 can be reduced.

[0139] Also, for the transistor M1, in order to hold the potential of the node n1 for a long time, it is preferable to apply a transistor with a small off-current, such as an OS transistor. Further, as the transistor M1, a transistor having a back gate may be applied, and a low potential may be applied to the back gate to shift the threshold voltage to the positive side to reduce the off-current.

[0140] In order to simply explain the current flowing in and out of the circuit MP in the operation example described later, both ends of the wiring OL shown in FIG. 15B are defined as the nodes ina and outa, and both ends of the wiring OLB are defined as the nodes inb and outb.

[0141] The wirings VE and VEr function as wirings for supplying a fixed potential as an example. When the transistors M3, M3r, M4, or M4r are n-channel transistors, the fixed potential can be, for example, VSS (low potential), ground potential, or other low potentials.

[0142] <<Operation Example>> Next, the operation example of the circuit MP shown in FIG. 15B will be described. FIGS. 16A to 16C, FIGS. 17A to 17C, and FIGS. 18A to 18C are timing charts showing the operation example of the circuit MP, and show the potential fluctuations of the wirings WL, WX1L, X2L, nodes n1, and n1r, respectively. Note that “H” described in FIGS. 16A to 18C indicates a high potential, and “L” indicates a low potential. Also, in this operation example, the current amount output from the wiring OL to the node outa (or from the node outa to the wiring OL) is I OL is set. Also, the current amount output from the wiring OLB to the node outb (or from the node outb to the wiring OLB) is I OLB is set. In the timing charts shown in FIGS. 16A to 18C, the change amounts of the currents I OL , I OLB are also shown.

[0143] Note that in this operation example, it is assumed that VSS (low potential) is supplied as the fixed potential to the wirings VE and VEr.

[0144] In the circuit MP shown in FIG. 15B, when transistors M2 and M3 are in the on state, transistor M1 has a diode-connected configuration. Therefore, when current flows from wiring OL to circuit MC, the potentials of the other of the source or drain of transistor M1 and the gate of transistor M1 become substantially equal. The said potential is determined by the amount of current flowing from wiring OL to circuit MC and the potential of one of the source or drain of transistor M1 (here VSS), etc. Here, by holding the potential of the gate of transistor M1 in capacitor C1 and then turning transistor M2 off, transistor M1 functions as a current source that flows a current corresponding to the potential of the gate of transistor M1. Therefore, the influence of variations in the current characteristics of transistor M1 can be reduced.

[0145] For example, when transistors M2 and M3 are in the on state and a current of amount I1 flows from wiring OL through circuit MC to wiring VE, let the potential of the gate (node n1) of transistor M1 be V1. Here, by turning transistor M2 off, V1 is held by the holding unit HC. As a result, transistor M1 can cause a current I1, which is a current corresponding to the potential VSS of one of the source or drain of transistor M1 and the potential V1 of the gate of transistor M1, to flow between the source and drain of transistor M1. In this specification, etc., such an operation is described as "transistor M1 is programmed to have an amount of current flowing between the source and drain of transistor M1 as I1", etc.

[0146] In this operation example, the amount of current flowing from the wiring OL to the circuit MC is set to three types: 0, I1, and I2. Therefore, the amount of current programmed into the transistor M1 is three types: 0, I1, and I2. For example, when the potential of the gate of the transistor M1 held in the holding unit HC is VSS, since the potential of each of one of the source or drain of the transistor M1 and the other of the source or drain is also VSS, if the threshold voltage of the transistor M1 is higher than 0, the transistor M1 is in the off state. Therefore, no current flows between the source and drain of the transistor M1. Thus, it can be said that the amount of current flowing between the source and drain of the transistor M1 is programmed to 0. Also, for example, when the potential of the gate of the transistor M1 held in the holding unit HC is V1, if the threshold voltage of the transistor M1 is lower than V1 - VSS, the transistor M1 is in the on state. At this time, let the amount of current flowing through the transistor M1 be I1. Therefore, when the potential of the gate of the transistor M1 is V1, it can be said that the amount of current flowing between the source and drain of the transistor M1 is programmed to I1. Also, for example, when the potential of the gate of the transistor M1 held in the holding unit HC is V2, if the threshold voltage of the transistor M1 is lower than V2 - VSS, the transistor M1 is in the on state. At this time, let the amount of current flowing through the transistor M1 be I2. Therefore, when the potential of the gate of the transistor M1 is V2, it can be said that the amount of current flowing between the source and drain of the transistor M1 is programmed to I2.

[0147] Note that the amount of current I1 is set to be greater than 0 and less than I2. Also, the potential V1 is set to be higher than VSS and lower than V2. Also, the threshold voltage of the transistor M1 is set to be higher than 0 and lower than V1 - VSS.

[0148] Before explaining the operation examples, the first data (e.g., weight coefficients here) held by circuit MP is defined as follows. When VSS is held at node n1 of holding section HC and VSS is held at node n1r of holding section HCr, circuit MP is assumed to hold "0" as the first data (weight coefficient). When V1 is held at node n1 of holding section HC and VSS is held at node n1r of holding section HCr, circuit MP is assumed to hold "+1" as the first data (weight coefficient). When V2 is held at node n1 of holding section HC and VSS is held at node n1r of holding section HCr, circuit MP is assumed to hold "+2" as the first data (weight coefficient). When VSS is held at node n1 of holding section HC and V1 is held at node n1r of holding section HCr, circuit MP is assumed to hold "-1" as the first data (weight coefficient). When VSS is held at node n1 of holding section HC and V2 is held at node n1r of holding section HCr, circuit MP is assumed to hold "-2" as the first data (weight coefficient).

[0149] Also, as an example, the second data (e.g., the value (computed value) of the neuron signal here) input to circuit MP is defined as follows. When a high potential is applied to wiring WX1L and a low potential is applied to wiring X2L, "+1" is input to circuit MP as the second data (the value of the neuron signal). When a low potential is applied to wiring WX1L and a high potential is applied to wiring X2L, "-1" is input to circuit MP as the second data (the value of the neuron signal). When a low potential is applied to wiring WX1L and a low potential is applied to wiring X2L, "0" is assumed to be input to circuit MP as the second data (the value of the neuron signal). Note that, as an example, the high potential is VDD, or a potential 10% or more, or 20% or more higher than VDD.

[0150] Hereinafter, the operation examples of circuit MP will be described for each combination of values that the first data (e.g., weight coefficients hereinafter) and the second data (e.g., the value (computed value) of the neuron signal, etc.) can take.

[0151] 〔Condition 1〕 First, as an example, consider a case where the first data (weight coefficient) is "0" and the second data (value of the neuron signal (computed value)) input to the circuit MP is "+1". FIG. 16A is a timing chart of the circuit MP in that case.

[0152] During period T11, the holding units HC and HCr hold the initial potential. In FIG. 16A, for example, it is assumed that nodes n1 and n1r hold a potential higher than the potential VSS as the initial potential.

[0153] Also, a low potential is applied to the wirings WL, WX1L, and X2L. As a result, a low potential is input to the gates of the transistors M2, M2r, M3, M3r, M4, and M4r, respectively, so that each of the transistors M2, M2r, M3, M3r, M4, and M4r is in an off state.

[0154] During period T12, a high potential is applied to the wiring WL and the wiring WX1L. As a result, a high potential is input to the gates of the transistors M2, M2r, M3, and M3r, respectively, so that each of the transistors M2, M2r, M3, and M3r is in an on state.

[0155] Although not shown in FIG. 16A, an initialization potential V ini is applied to each of the wirings OL and OLB. Since each of the transistors M2, M2r, M3, and M3r is in an on state, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr each become V ini That is, during period T12, the potentials of the node n1 of the holding unit HC and the node n1r of the holding unit HCr are initialized.

[0156] Note that as the initialization potential V ini it is preferably the ground potential, for example. Also, as the initialization potential V iniIt may be VSS, a potential higher than the ground potential, or a potential lower than the ground potential. Also, the initialization potential V supplied to each of the wirings OL and OLB ini may be different from each other. Note that the initialization potential V need not be input to each of the wirings OL and OLB ini It is not necessarily required to provide the period T12. Or, it is not necessarily required to perform initialization during the period T12.

[0157] During the period T13, the potential VSS is input from the wiring OL to the circuit MC, and the potential VSS is input from the wiring OLB to the circuit MCr. As a result, the potential of the node n1 of the holding unit HC becomes VSS, and the potential of the node n1r of the holding unit HCr becomes VSS. Thereby, in the circuit MC, since the transistor M1 is programmed to flow 0 as the current amount, no current flows from the wiring OL through the circuit MC to the wiring VE. Also, in the circuit MCr, since the transistor M1r is programmed to flow 0 as the current amount, no current flows from the wiring OLB through the circuit MCr to the wiring VEr. In other words, during the period T13, since the transistors M1 and M1r are in the off state, the state between the wiring OL and the wiring VE becomes non-conductive, and the state between the wiring OLB and the wiring VEr becomes non-conductive.

[0158] During the period T14, a low potential is applied to the wiring WL and the wiring WX1L. As a result, a low potential is input to the gates of the transistors M2, M2r, M3, and M3r, respectively, so that each of the transistors M2, M2r, M3, and M3r is in the off state. When the transistors M2 and M2r are in the off state, the potential VSS of the node n1 of the holding unit HC is held, and the potential VSS of the node n1r of the holding unit HCr is held. Also, when the transistor M3 is in the off state, no current flows from the wiring OL through the circuit MC to the wiring VE. Similarly, when the transistor M3r is in the off state, no current flows from the wiring OLB through the circuit MCr to the wiring VEr.

[0159] By the operations in periods T11 to T14, “0” is set as the first data (weight coefficient) of circuit MP.

[0160] In period T15, as an input of the signal (computed value) “+1” of the neuron to circuit MP, a high potential is input to wiring WX1L and a low potential is input to wiring X2L. At this time, a high potential is input to the gates of transistors M3 and M3r respectively, and a low potential is input to the gates of transistors M4 and M4r respectively. Therefore, each of transistors M3 and M3r becomes an on state, and each of M4 and M4r becomes an off state. That is, by this operation, the connection between circuit MC and wiring OL, and between circuit MCr and wiring OLB becomes a conductive state, and the connection between circuit MC and wiring OLB, and between circuit MCr and wiring OL becomes a non-conductive state.

[0161] Note that since transistor M1 is in an off state (programmed to pass a current of 0), no current flows between wiring OL and OLB to wiring VE in circuit MC. Similarly, since transistor M1r is in an off state (programmed to pass a current of 0), no current flows between wiring OL and OLB to wiring VEr in circuit MCr. From the above, the current I OL output from node outa of wiring OL, and the current I OLB output from node outb of wiring OLB do not change between period T14 and period T15.

[0162] Incidentally, in this condition, since the first data (weight coefficient) is “0” and the second data (value of the neuron signal (computed value)) input to circuit MP is “+1”, using Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) is “0”. The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) is “0” corresponds to the case where currents I OL and I OLB do not change in period T15 in the operation of circuit MP.

[0163] Note that once the first data (e.g., weight coefficient, etc.) is input, multiple multiplication and addition operations may be performed by changing only the second data (value of neuron signal, calculation value, etc.) without updating its value. In this case, since it is not necessary to update the first data (weight coefficient), power consumption can be reduced. Note that in order to reduce the update of the first data (weight coefficient), it is necessary to hold the first data (weight coefficient) for a long time. At this time, for example, when using an OS transistor, it is possible to hold the first data (weight coefficient) for a long time by taking advantage of the low off-current.

[0164] 〔Condition 2〕 Next, as an example, consider the case where the first data (weight coefficient) is “+1” and the second data (value of neuron signal (calculation value)) input to circuit MP is “+1”. FIG. 16B is a timing chart of circuit MP in that case.

[0165] Regarding the operations in period T11 and period T12, since they are the same as the operations in period T11 and period T12 of condition 1, refer to the description of the operations in period T11 and period T12 of condition 1.

[0166] In period T13, a current amount I1 is input from wiring OL to circuit MC, and a potential VSS is input from wiring OLB to circuit MCr. As a result, the potential of node n1 of holding part HC becomes V1, and the potential of node n1r of holding part HCr becomes VSS. Thereby, in circuit MC, transistor M1 is programmed to conduct a current amount I1, so a current amount I1 flows from wiring OL through circuit MC to wiring VE. Also, in circuit MCr, since transistor M1r is programmed to conduct a current amount of 0, no current flows from wiring OLB through circuit MCr to wiring VEr.

[0167] During period T14, a low potential is applied to wiring WL and wiring WX1L. As a result, a low potential is input to the gates of transistors M2, M2r, M3, and M3r respectively, so that transistors M2, M2r, M3, and M3r are all in the off state. When transistors M2 and M2r are in the off state, the potential V1 of node n1 of the holding unit HC is held, and the potential VSS of node n1r of the holding unit HCr is held. Also, when transistor M3 is in the off state, no current flows from wiring OL to wiring VE through circuit MC. Similarly, when transistor M3r is in the off state, no current flows from wiring OLB to wiring VEr through circuit MCr.

[0168] By the operations during periods T11 to T14, “+1” is set as the first data (weight coefficient) of circuit MP.

[0169] During period T15, as the input of the second data (“+1”, the value (computed value) of the neuron signal) to circuit MP, a high potential is input to wiring WX1L and a low potential is input to wiring X2L. At this time, a high potential is input to the gates of transistors M3 and M3r respectively, and a low potential is input to the gates of transistors M4 and M4r respectively. Therefore, transistors M3 and M3r are in the on state, and M4 and M4r are in the off state. That is, by this operation, the connection between circuit MC and wiring OL and the connection between circuit MCr and wiring OLB become conductive, and the connection between circuit MC and wiring OLB and the connection between circuit MCr and wiring OL become non-conductive.

[0170] At this time, in circuit MC, since transistor M3 is in the on state and transistor M1r is in the on state (because it is programmed to flow current I1 as the current amount), a current flows between wiring OL and wiring VE. Also, in circuit MC, since transistor M4 is in the off state, no current flows between wiring OLB and wiring VE. On the other hand, in circuit MCr, although transistor M3r is in the on state, since transistor M1 is in the off state (because it is programmed to flow 0 as the current amount), no current flows between wiring OLB and wiring VEr. Also, in circuit MCr, since transistor M4r is in the off state, no current flows between wiring OL and wiring VEr. From the above, the current I OL output from the node outa of wiring OL increases by I1 during period T15, and the current I OLB output from the node outb of wiring OLB does not change between period T14 and period T15.

[0171] Incidentally, in this condition, since the first data (weight coefficient) is set to "+1" and the second data (value of the neuron signal) input to circuit MP is set to "+1", using Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) is "+1". The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) is "+1" corresponds to the case where the current I OL increases by I1 during period T15 and the current I OLB does not change in the operation of circuit MP.

[0172] During the period T13 of these conditions, for example, by programming the current flowing from the wiring OL to the circuit MC to be I2 instead of I1, V2 can be held in the holding unit HC. As a result, “+2” is set as the first data (weight coefficient) of the circuit MP. By setting the first data (weight coefficient) to “+2” and the signal of the neuron input to the circuit MP to “+1”, from Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) is “+2”. The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) is “+2” corresponds to the case where the current I OL increases by I2 during the period T15 and the current I OLB does not change. In this way, by holding VSS in the holding unit HCr in the circuit MCr and programming a current other than I1 in the circuit MC, a positive value other than “+1” can be set as the first data (weight coefficient) of the circuit MP.

[0173] 〔Condition 3〕 Next, as an example, consider the case where the first data (weight coefficient) is “-1” and the second data (value of the neuron signal (computed value)) input to the circuit MP is “+1”. FIG. 16C is a timing chart of the circuit MP in that case.

[0174] Regarding the operations in the periods T11 and T12, since they are the same as the operations in the periods T11 and T12 of Condition 1, refer to the description of the operations in the periods T11 and T12 of Condition 1.

[0175] During period T13, a potential VSS is input from wiring OL to circuit MC, and a current amount I1 is input from wiring OLB to circuit MCr as a current amount. As a result, the potential of node n1 of holding section HC becomes VSS, and the potential of node n1r of holding section HCr becomes V1. Thereby, in circuit MCr, transistor M1 is programmed to conduct a current of 0 as a current amount, so no current flows from wiring OL through circuit MC to wiring VE. Also, in circuit MCr, since transistor M1r is programmed to conduct a current of I1 as a current amount, a current amount I1 flows from wiring OLB through circuit MCr to wiring VEr as a current amount.

[0176] During period T14, a low potential is applied to wiring WL and wiring WX1L. As a result, a low potential is input to the gates of transistors M2, M2r, M3, and M3r respectively, so each of transistors M2, M2r, M3, and M3r is turned off. When transistors M2 and M2r are turned off, the potential VSS of node n1 of holding section HC is held, and the potential V1 of node n1r of holding section HCr is held. Also, when transistor M3 is turned off, no current flows from wiring OL through circuit MC to wiring VE. Similarly, when transistor M3r is turned off, no current flows from wiring OLB through circuit MCr to wiring VEr.

[0177] By the operations during periods T11 to T14, “-1” is set as the first data (weight coefficient) of circuit MP.

[0178] During period T15, as the second data (“+1”, the signal (computed value) of the neuron) is input to circuit MP, a high potential is input to wiring WX1L and a low potential is input to wiring X2L. At this time, a high potential is input to the gates of transistors M3 and M3r respectively, and a low potential is input to the gates of transistors M4 and M4r respectively. Therefore, each of transistors M3 and M3r is turned on, and each of M4 and M4r is turned off. That is, by this operation, conduction is established between circuit MC and wiring OL, and between circuit MCr and wiring OLB, and non-conduction is established between circuit MC and wiring OLB, and between circuit MCr and wiring OL.

[0179] At this time, in circuit MC, although transistor M3 is turned on, transistor M1 is turned off (because it is programmed to allow a current of 0 to flow), so no current flows from wiring OL to wiring VE. Also, in circuit MC, since transistor M4 is turned off, no current flows from wiring OLB to wiring VE. On the other hand, in circuit MCr, since transistor M3r is turned on and transistor M1r is turned on (because it is programmed to allow a current of I1 to flow), current flows from wiring OLB to wiring VEr. Also, in circuit MCr, since transistor M4r is turned off, no current flows from wiring OL to wiring VEr. From the above, the current I OL output from node outa of wiring OL does not change between period T14 and period T15, and the current I OLB output from node outb of wiring OLB increases by I1 in period T15.

[0180] Incidentally, in this condition, since the first data (weight coefficient) is set to "-1" and the second data (value of neuron signal (computed value)) input to circuit MP is set to "+1", when using Equation (1), the product of the first data (weight coefficient) and the second data (value of neuron signal) is "-1". The result that the product of the first data (weight coefficient) and the second data (value of neuron signal) is "-1" corresponds to the case where the current I OL does not change during period T15 and the current I OLB increases by I1.

[0181] Note that during period T13 of this condition, for example, by programming the current flowing from wiring OLB to circuit MCr to be I2 instead of I1, V2 can be held in holding unit HCr. As a result, "-2" is set as the first data (weight coefficient) of circuit MP. By setting the first data (weight coefficient) to "-2" and the second data (value of neuron signal) input to circuit MP to "+1", from Equation (1), the product of the first data (weight coefficient) and the second data (value of neuron signal) is "-2". The result that the product of the first data (weight coefficient) and the second data (value of neuron signal) is "-2" corresponds to the case where the current I OL does not change during period T15 and the current I OLB increases by I2. In this way, by holding VSS in holding unit HC in circuit MC and programming a current amount other than I1 in circuit MCr, a positive value other than "+1" can be set as the weight coefficient of circuit MP.

[0182] 〔Condition 4〕 In this condition, as an example, consider the operation of circuit MP when the first data (weight coefficient) is "0" and the second data (value of neuron signal (computed value)) input to circuit MP is "-1". FIG. 17A is a timing chart of circuit MP in that case.

[0183] Regarding the operations during Periods T11 to T14, since they are the same as the operations during Periods T11 to T14 under Condition 1, refer to the description of the operations during Periods T11 to T14 under Condition 1.

[0184] During Period T15, as the second data (“-1”, the value (computed value) of the neuron signal) is input to circuit MP, a low potential is input to wiring WX1L and a high potential is input to wiring X2L. At this time, a low potential is input to the gates of transistors M3 and M3r respectively, and a high potential is input to the gates of transistors M4 and M4r respectively. For this reason, each of transistors M3 and M3r becomes an off state, and each of M4 and M4r becomes an on state. That is, by this operation, the connection between circuit MC and wiring OL, and between circuit MCr and wiring OLB becomes a non-conductive state, and the connection between circuit MC and wiring OLB, and between circuit MCr and wiring OL becomes a conductive state.

[0185] Since transistor M1 is in an off state (because it is programmed to pass a current of 0), no current flows between wiring OL and OLB to wiring VE in circuit MC. That is, the current I OL output from node outa of wiring OL OLB and the current I OL output from node outb of wiring OLB OLB do not change between Period T14 and Period T15. Similarly, since transistor M1r is in an off state (because it is programmed to pass a current of 0), no current flows between wiring OL and OLB to wiring VEr in circuit MCr. That is, the current I

[0186] Incidentally, in this condition, since the first data (weight coefficient) is set to "0" and the second data (value of neuron signal (computed value)) input to circuit MP is set to "-1", when using Equation (1), the product of the first data (weight coefficient) and the second data (value of neuron signal) becomes "0". The result that the product of the first data (weight coefficient) and the second data (value of neuron signal) becomes "0" corresponds to the case where neither current I OL nor current I OLB changes, which is consistent with the result of the circuit operation of Condition 1.

[0187] 〔Condition 5〕 In this condition, as an example, consider the operation of circuit MP when the first data (weight coefficient) is set to "+1" and the second data (value of neuron signal (computed value)) input to circuit MP is set to "-1". FIG. 17B is the timing chart of circuit MP in that case.

[0188] Regarding the operation in Periods T11 to T14, since it is the same as the operation in Periods T11 to T14 of Condition 2, refer to the explanation of the operation in Periods T11 to T14 of Condition 2.

[0189] In Period T15, as the input of the second data (value of neuron signal (computed value)) "-1" to circuit MP, a low potential is input to wiring WX1L and a high potential is input to wiring X2L. At this time, a low potential is input to the gates of transistors M3 and M3r respectively, and a high potential is input to the gates of transistors M4 and M4r respectively. Therefore, each of transistors M3 and M3r becomes an off state, and each of M4 and M4r becomes an on state. That is, by this operation, the connection between circuit MC and wiring OL, and the connection between circuit MCr and wiring OLB become non-conductive states, and the connection between circuit MC and wiring OLB, and the connection between circuit MCr and wiring OL become conductive states.

[0190] At this time, in circuit MC, since transistor M3 is in the off state, no current flows between wiring OL and wiring VE. Also, in circuit MC, since transistor M4 is in the on state and transistor M1r is in the on state (because it is programmed to flow current I1 as the current amount), current flows between wiring OLB and wiring VE. On the other hand, in circuit MCr, since transistor M3r is in the off state, no current flows between wiring OLB and wiring VEr. Also, in circuit MCr, although transistor M4r is in the on state, since transistor M1 is in the off state (because it is programmed to flow 0 as the current amount), no current flows between wiring OL and wiring VEr. From the above, the current I OL output from the node outa of wiring OL does not change between period T14 and period T15, and the current I OLB output from the node outb of wiring OLB increases by I1 in period T15.

[0191] Incidentally, since this condition sets the first data (weight coefficient) to "+1" and the second data (value of the neuron signal (computed value)) input to circuit MP to "-1", using Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) is "-1". The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) is "-1" means that in the operation of circuit MP, the current I OL does not change, and the current I OLB corresponds to the case where it increases by I1, which is consistent with the result of the circuit operation of condition 3.

[0192] Note that, as described in Condition 2, during the period T13 of this condition, for example, the current flowing from the wiring OL to the circuit MC may be programmed to I2 instead of I1, and V2 may be held in the holding unit HC. As a result, “+2” is set as the first data (weight coefficient) of the circuit MP. By setting the first data (weight coefficient) to “+2” and the signal of the neuron input to the circuit MP to “-1”, from Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) is “-2”. The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) is “-2” corresponds to the case where the current I OL does not change during the period T15 and the current I OLB increases by I2. Thus, by holding VSS in the holding unit HCr in the circuit MCr and programming a current other than I1 in the circuit MC, a positive value other than “+1” can be set as the weight coefficient of the circuit MP.

[0193] 〔Condition 6〕 In this condition, as an example, consider the operation of the circuit MP when the first data (weight coefficient) is “-1” and the second data (value of the neuron signal (computed value)) input to the circuit MP is “-1”. FIG. 17C is a timing chart of the circuit MP in that case.

[0194] Regarding the operation during the period T11 to the period T14, since it is the same as the operation during the period T11 to the period T14 of Condition 3, refer to the description of the operation during the period T11 to the period T14 of Condition 3.

[0195] During period T15, as the second data (“-1”, which is the value of the neuron signal (computed value)) is input to circuit MP, a low potential is input to wiring WX1L and a high potential is input to wiring X2L. At this time, a low potential is input to the gates of transistors M3 and M3r respectively, and a high potential is input to the gates of transistors M4 and M4r respectively. Therefore, each of transistors M3 and M3r is turned off, and each of M4 and M4r is turned on. That is, by this operation, the connection between circuit MC and wiring OL, and the connection between circuit MCr and wiring OLB become non-conductive states, while the connection between circuit MC and wiring OLB, and the connection between circuit MCr and wiring OL become conductive states.

[0196] At this time, in circuit MC, since transistor M3 is in the off state, no current flows between wiring OL and wiring VE. Also, in circuit MC, although transistor M4 is in the on state, since transistor M1 is in the off state (programmed to pass 0 as the current amount), no current flows between wiring OLB and wiring VE. On the other hand, in circuit MCr, since transistor M3r is in the off state, no current flows between wiring OLB and wiring VEr. Also, in circuit MCr, since transistor M4r is in the on state and transistor M1 is in the on state (programmed to pass I1 as the current amount), current flows between wiring OL and wiring VEr. From the above, the current I OL output from node outa of wiring OL increases by I1 during period T15, and the current I OLB output from node outb of wiring OLB does not change between period T14 and period T15.

[0197] Incidentally, in this condition, since the first data (weight coefficient) is set to "-1" and the second data (value of the neuron signal (computed value)) input to circuit MP is set to "-1", when using Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) becomes "+1". The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) becomes "+1" corresponds to the change of current I during period T14 and period T15 in the operation of circuit MP, and the non-change of current I OL which corresponds to the case where current I OLB does not change, and this is consistent with the result of the circuit operation of Condition 2.

[0198] As described in Condition 3 as well, in period T13 of this condition, for example, the current flowing from wiring OLB to circuit MCr may be programmed to I2 instead of I1, and V2 may be held in holding unit HC. As a result, "-2" is set as the first data (weight coefficient) of circuit MP. By setting the first data (weight coefficient) to "-2" and the second data (value of the neuron signal) input to circuit MP to "-1", from Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) becomes "+2". The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) becomes "+2" corresponds to the case where current I OL does not change and current I OLB increases by I2 in the operation of circuit MP. In this way, by holding VSS in holding unit HC in circuit MC and programming a current other than I1 in circuit MCr, a positive value other than "+1" can be set as the weight coefficient of circuit MP.

[0199] 〔Condition 7〕 In this condition, as an example, consider the operation of circuit MP under Condition 7 where the first data (weight coefficient) is "0" and the second data (value of the neuron signal (computed value)) input to circuit MP is "0". Figure 18A is the timing chart of circuit MP in that case.

[0200] Regarding the operations in periods T11 to T14, since they are the same as the operations in periods T11 to T14 under condition 1, refer to the description of the operations in periods T11 to T14 under condition 1.

[0201] In period T15, as the second data (the value of the neuron signal (computed value)) “0” is input to circuit MP, a low potential is input to wiring WX1L and a low potential is input to wiring X2L. At this time, a low potential is input to the gates of transistors M3, M3r, M4, and M4r respectively. Therefore, each of transistors M3, M3r, M4, and M4r is in an off state. That is, by this operation, between circuit MC and wiring OL, between circuit MCr and wiring OLB, between circuit MC and wiring OLB, and between circuit MCr and wiring OL become non-conductive states.

[0202] Therefore, in circuit MC, regardless of the amount of the programmed current flowing through transistor M1, no current flows between wiring OL and one of wiring VE or wiring VEr. Similarly, in circuit MCr, regardless of the amount of the programmed current flowing through transistor M1r, no current flows between wiring OLB and the other of wiring VE or wiring VEr. That is, the current I OL output from the node outa of wiring OL, and OLB the current I

[0203] output from the node outb of wiring OLB do not change between period T14 and period T15.

[0203] Incidentally, since this condition sets the first data (weight coefficient) to “0” and the second data (the value of the neuron signal (computed value)) input to circuit MP to “0”, using Equation (1), the product of the first data (weight coefficient) and the second data (the value of the neuron signal) is “0”. The result that the product of the first data (weight coefficient) and the second data (the value of the neuron signal) is “0” corresponds to the case where the currents I OL and I OLB do not change in period T15 in the operation of circuit MP, and this is consistent with the results of the circuit operations of conditions 1 and 4.

[0204] 〔Condition 8〕 In this condition, as an example, consider the operation of circuit MP under Condition 8 where the first data (weight coefficient) is “+1” and the second data (value of neuron signal (computed value)) input to circuit MP is “0”. FIG. 18B is a timing chart of circuit MP in that case.

[0205] Regarding the operations in periods T11 to T14, since they are the same as the operations in periods T11 to T14 of Condition 2, refer to the description of the operations in periods T11 to T14 of Condition 2.

[0206] In period T15, as the input of the second data (value of neuron signal (computed value)) “0” to circuit MP, a low potential is input to wiring WX1L and a low potential is input to wiring X2L. At this time, a low potential is input to the gates of transistors M3, M3r, M4, and M4r respectively. Therefore, each of transistors M3, M3r, M4, and M4r is turned off. That is, similar to Condition 7, by this operation, regardless of the amount of programmed current flowing through each of transistors M1 and M1r, the circuits between circuit MC and wiring OL, between circuit MCr and wiring OLB, between circuit MC and wiring OLB, and between circuit MCr and wiring OL become non-conductive states. For this reason, no current flows between wiring OL and one of wiring VE or VEr, and no current flows between wiring OLB and the other of wiring VE or VEr either. From the above, the current I OL output from node outa of wiring OL, and the current I OLB output from node outb of wiring OLB do not change between period T14 and period T15.

[0207] Incidentally, since this condition sets the first data (weight coefficient) to "+1" and the second data (neuron signal (computed value)) input to circuit MP to "0", using Equation (1), the product of the first data (weight coefficient) and the second data (value of the neuron signal) is "0". The result that the product of the first data (weight coefficient) and the second data (value of the neuron signal) is "0" corresponds to the case where neither current I OL nor current I OLB changes, which is consistent with the circuit operation results of Conditions 1, 4, and 7.

[0208] 〔Condition 9〕 In this condition, as an example, consider the operation of circuit MP with Condition 9 being the case where the first data (weight coefficient) is "-1" and the second data (value of the neuron signal (computed value)) input to circuit MP is "0". Figure 18C is the timing chart of circuit MP in that case.

[0209] Regarding the operation in Periods T11 to T14, since it is the same as the operation in Periods T11 to T14 of Condition 3, refer to the explanation of the operation in Periods T11 to T14 of Condition 3.

[0210] During period T15, as the second data (the value of the neuron signal (computed value)) "0" is input to circuit MP, a low potential is input to wiring WX1L and a low potential is input to wiring X2L. At this time, a low potential is input to the gates of transistors M3, M3r, M4, and M4r respectively. Therefore, each of transistors M3, M3r, M4, and M4r is in an off state. That is, similar to condition 7, by this operation, regardless of the amount of programmed current flowing through each of transistors M1 and M1r, the circuit between circuit MC and wiring OL, between circuit MCr and wiring OLB, between circuit MC and wiring OLB, and between circuit MCr and wiring OL becomes non-conductive. For this reason, no current flows between wiring OL and one of wiring VE or VEr, and no current flows between wiring OLB and the other of wiring VE or VEr either. From the above, the current I OL output from the node outa of wiring OL, and the current I OLB output from the node outb of wiring OLB do not change between period T14 and period T15.

[0211] Incidentally, in this condition, since the first data (weight coefficient) is "-1" and the second data (the value of the neuron signal (computed value)) input to circuit MP is "0", using Equation (1), the product of the first data (weight coefficient) and the second data (the value of the neuron signal) is "0". The result that the product of the first data (weight coefficient) and the second data (the value of the neuron signal) is "0" corresponds to the case where the currents I OL and I OLB do not change between period T14 and period T15 in the operation of circuit MP, and this is consistent with the results of the circuit operations of conditions 1, 4, 7, and 8.

[0212] The results of the operation examples of conditions 1 to 9 described above are summarized in the following table. In the following table, a high potential is described as "H" and a low potential is described as "L".

[0213]

Table 1

[0214] Here, as an example, the case where one circuit MC and one circuit MCr are connected to the wirings OL and OLB respectively is shown. Regarding this, as shown in FIG. 15A etc., when a plurality of circuits MC and MCr are connected to the wirings OL and OLB respectively, the currents output from each circuit MC and MCr are added together based on Kirchhoff's current law. As a result, a sum operation is performed. That is, in the circuits MC and MCr, a product operation is performed, and a sum operation is performed by adding the currents from the plurality of circuits MC and MCr. As a result of the above, a product-sum operation process is performed.

[0215] By the way, in the operation of the circuit MP, by performing a calculation where the first data (weight coefficient) is only the two values of "+1" and "-1", and the second data (value of the neuron signal) is only the two values of "+1" and "-1", the circuit MP can perform the same operation as an exclusive NOR circuit (coincidence circuit).

[0216] Also, in the operation of the circuit MP, by performing a calculation where the first data (weight coefficient) is only the two values of "+1" and "0", and the second data (value of the neuron signal) is only the two values of "+1" and "0", the circuit MP can perform the same operation as a logical product circuit.

[0217] By the way, in this operation example, the potentials held in the holding parts HC and HCr of the circuits MC and MCr of the circuit MP are multi-valued like VSS, V1, V2, etc., but the holding parts HC and HCr may hold a potential indicating a binary value or an analog value. For example, when the first data (weight coefficient) is a "positive analog value", a high-level analog potential is held at the node n1 of the holding part HC, and a low potential is held at the node n1r of the holding part HCr. When the first data (weight coefficient) is a "negative analog value", for example, a low potential is held at the node n1 of the holding part HC, and a high-level analog potential is held at the node n1r of the holding part HCr. And the current I OL and the current I OLB have magnitudes corresponding to the analog potential.

[0218] The configurations, methods, etc. shown in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments, examples, etc. described in this specification.

[0219] (Embodiment 3) In this embodiment, a configuration example of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked and provided will be described. By adopting such a configuration, the degree of freedom in designing the semiconductor device can be increased. Further, by stacking and providing transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0220] A part of the cross-sectional structure of the semiconductor device is shown in FIG. 19. The semiconductor device shown in FIG. 19 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 20A is a top view of the transistor 500. FIG. 20B is a cross-sectional view taken along the portion L1 - L2 indicated by the dashed-dotted line in FIG. 20A, and is a cross-sectional view of the transistor 500 in the channel length direction. FIG. 20C is a cross-sectional view taken along the portion W1 - W2 indicated by the dashed-dotted line in FIG. 20A, and is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to the OS transistor included in the semiconductor device shown in the above embodiment, for example, the transistor 21. Further, the transistor 550 corresponds to the Si transistor included in the semiconductor device shown in the above embodiment, for example, the transistor 22.

[0221] As described above, the transistor 500 is an OS transistor. The OS transistor has an extremely small off-current. Therefore, it is possible to hold the data potential or charge written to the memory node via the transistor 500 for a long period of time. That is, since the refresh operation frequency of the memory node is reduced or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

[0222] In FIG. 19, the transistor 500 is provided above the transistor 550, and the capacitor 600 is provided above the transistor 550 and the transistor 500.

[0223] The transistor 550 is provided on the substrate 371. The substrate 371 is, for example, a p-type silicon substrate. The substrate 371 may also be an n-type silicon substrate. The oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed by buried oxide in the substrate 371, for example, silicon oxide. The transistor 550 is provided on a single-crystal silicon, so-called SOI (Silicon On Insulator) substrate provided on the substrate 371 with the oxide layer 374 interposed therebetween.

[0224] In the SOI substrate, an insulator 373 that functions as an element isolation layer is provided on the substrate 371. The substrate 371 also has a well region 372. The well region 372 is a region to which n-type or p-type conductivity is imparted according to the conductivity type of the transistor 550. In the single-crystal silicon in the SOI substrate, a semiconductor region 375, low-resistance regions 376a and 376b that function as a source region or a drain region are provided. A low-resistance region 376c is provided on the well region 372.

[0225] The transistor 550 can be provided so as to overlap with the well region 372 doped with an impurity element that imparts conductivity. The well region 372 can function as the bottom gate electrode of the transistor 550 by independently changing the potential through the low-resistance region 376c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 372, the threshold voltage of the transistor 550 can be made larger and the off-current can be reduced. Therefore, by applying a negative potential to the well region 372, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be made smaller. As a result, the power consumption based on the through-current or the like in the arithmetic circuit having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0226] The transistor 550 is preferably a so-called Fin type in which the upper surface of the semiconductor layer and the side surfaces in the channel width direction are covered with the conductor 378 via the insulator 377. By forming the transistor 550 into the Fin type, the effective channel width is increased, thereby improving the on characteristics of the transistor 550. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 550 can be improved.

[0227] Note that the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.

[0228] The conductor 378 may function as a first gate (also referred to as a top gate) electrode. In addition, the well region 372 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the potential applied to the well region 372 can be controlled via the low resistance region 376c.

[0229] In the region where the channel of the semiconductor region 375 is formed, the region in the vicinity thereof, the source region, or the drain region, the low resistance region 376a, the low resistance region 376b, and the low resistance region 376c etc. connected to the electrode for controlling the potential of the well region 372, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice interval may also be used. Alternatively, by using GaAs and GaAlAs etc., the transistor 550 may be a HEMT.

[0230] The well region 372, the low-resistance regions 376a, 376b, and 376c contain, in addition to the semiconductor material applied to the semiconductor region 375, elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron.

[0231] The conductor 378 that functions as a gate electrode can be made of a conductive material such as a semiconductor material like silicon, a metal material, an alloy material, or a metal oxide material, which contains elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron. Also, the conductor 378 may use a silicide such as nickel silicide.

[0232] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0233] The low-resistance regions 376a, 376b, and 376c may be configured by laminating another conductor, for example, a silicide such as nickel silicide. By adopting such a configuration, the conductivity of the region that functions as an electrode can be increased. Also, at this time, an insulator that functions as a sidewall spacer (also referred to as a sidewall insulating layer) may be provided on the side surfaces of the conductor 378 that functions as a gate electrode and the insulator that functions as a gate insulating film. By adopting such a configuration, it is possible to prevent the conductor 378 and the low-resistance regions 376a and 376b from being in a conductive state.

[0234] An insulator 379, an insulator 381, an insulator 383, and an insulator 385 are sequentially laminated and provided covering the transistor 550.

[0235] As the insulators 379, 381, 383, and 385, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0236] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0237] The insulator 381 may have a function as a planarization film that planarizes a step formed by a transistor 550 or the like provided therebelow. For example, the upper surface of the insulator 381 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0238] Also, for the insulator 383, it is preferable to use a film having a barrier property such that hydrogen or impurities do not diffuse from the substrate 371 or the transistor 550 or the like into the region where the transistor 500 is provided.

[0239] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0240] The amount of hydrogen desorption can be analyzed using, for example, temperature programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 383 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 383, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less.

[0241] Note that the insulator 385 preferably has a lower dielectric constant than the insulator 383. For example, the relative dielectric constant of the insulator 385 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 385 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 383. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0242] In addition, conductors 328, 330, etc. that are connected to the capacitor 600 or the transistor 500 are embedded in the insulators 379, 381, 383, and 385. Note that the conductors 328 and 330 have the function of a plug or a wiring. Also, conductors having the function of a plug or a wiring may be given the same reference numeral when a plurality of configurations are grouped together. Also, in this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0243] As the material of each plug and wiring (conductors 328, 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used singly or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form it with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0244] A wiring layer may be provided on the insulator 385 and the conductor 330. For example, in FIG. 19, the insulator 350, the insulator 352, and the insulator 354 are provided in a stacked manner in sequence. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug connected to the transistor 550 or a wiring. Note that the conductor 356 can be provided using the same material as the conductor 328 and the conductor 330.

[0245] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350 as in the case of the insulator 383. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0246] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0247] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 19, the insulator 360, the insulator 362, and the insulator 364 are provided in a stacked manner in sequence. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

[0248] Incidentally, for example, as with insulator 383, it is preferable to use an insulator having a barrier property against hydrogen for insulator 360. Further, conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 360 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0249] A wiring layer may be provided on insulator 364 and conductor 366. For example, in FIG. 19, insulators 370, 369, and 368 are sequentially stacked and provided. Further, conductor 376 is formed in insulators 370, 369, and 368. Conductor 376 has a function as a plug or wiring. Note that conductor 376 can be provided using the same material as conductors 328 and 330.

[0250] Incidentally, for example, as with insulator 383, it is preferable to use an insulator having a barrier property against hydrogen for insulator 370. Further, conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 370 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0251] A wiring layer may be provided on insulator 368 and conductor 376. For example, in FIG. 19, insulators 380, 382, and 384 are sequentially stacked and provided. Further, conductor 386 is formed in insulators 380, 382, and 384. Conductor 386 has a function as a plug or wiring. Note that conductor 386 can be provided using the same material as conductors 328 and 330.

[0252] Note that, for example, as with insulator 383, it is preferable to use an insulator having a barrier property against hydrogen for insulator 380. Further, conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 380 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0253] In the above, the wiring layer including conductor 356, the wiring layer including conductor 366, the wiring layer including conductor 376, and the wiring layer including conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited to this. The number of wiring layers similar to the wiring layer including conductor 356 may be three or less, or may be five or more.

[0254] On insulator 384, insulators 510, 512, 514, and 516 are sequentially stacked and provided. Any of insulators 510, 512, 514, and 516 preferably uses a material having a barrier property against oxygen and hydrogen.

[0255] For example, for insulators 510 and 514, it is preferable to use a film having a barrier property against hydrogen or impurities from, for example, substrate 371 or the region where transistor 550 is provided to the region where transistor 500 is provided. Therefore, a material similar to that of insulator 383 can be used.

[0256] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 550.

[0257] Also, as the film having barrier properties against hydrogen, for example, for the insulator 510 and the insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0258] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable to be used as a protective film for the transistor 500.

[0259] Also, for example, for the insulator 512 and the insulator 516, the same materials as those of the insulator 379 can be used. Also, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0260] Also, the conductor 518 and the conductor (for example, the conductor 503) constituting the transistor 500 are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 has a function as a capacitor 600, or a plug connected to the transistor 550, or a wiring. The conductor 518 can be provided using the same materials as those of the conductor 328 and the conductor 330.

[0261] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0262] Above the insulator 516, a transistor 500 is provided.

[0263] As shown in FIGS. 20A and 20B, the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 disposed on the bottom surface and the side surface of the opening, and a conductor 560 disposed on the formation surface of the insulator 545.

[0264] Also, as shown in FIGS. 20A and 20B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. Also, as shown in FIGS. 20A and 20B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 20A and 20B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.

[0265] In this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0266] In the transistor 500, a configuration in which two layers of the oxide 530a and the oxide 530b are laminated in a region where a channel is formed and in its vicinity is shown, but the present invention is not limited to this. For example, a single layer of the oxide 530b or a laminated configuration of three or more layers may be provided.

[0267] In addition, in the transistor 500, the conductor 560 is shown in a two-layer stacked configuration, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer configuration or a stacked configuration of three or more layers. Further, the transistor 500 shown in FIGS. 19, 20A, and 20B is an example and is not limited to its configuration, and an appropriate transistor may be used according to the circuit configuration, driving method, or the like.

[0268] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode and the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing an alignment margin, the occupied area of the transistor 500 can be reduced. As a result, miniaturization and high integration of the semiconductor device can be achieved.

[0269] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0270] Conductor 560 may function as a first gate (also referred to as a gate or a top gate) electrode. Further, conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In that case, by changing the potential applied to conductor 503 independently without linking it to the potential applied to conductor 560, the threshold voltage of transistor 500 can be controlled. In particular, by applying a negative potential to conductor 503, the threshold voltage of transistor 500 can be increased and the off-current can be reduced. Therefore, applying a negative potential to conductor 503 can make the drain current smaller when the potential applied to conductor 560 is 0 V than when no potential is applied.

[0271] Conductor 503 is arranged so as to overlap with oxide 530 and conductor 560. Thereby, when a potential is applied to conductor 560 and conductor 503, the electric field generated from conductor 560 and the electric field generated from conductor 503 are connected and can cover the channel formation region formed in oxide 530.

[0272] In this specification and the like, a configuration of a transistor in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (S-channel) configuration. Further, the S-channel configuration disclosed in this specification and the like is different from the Fin type configuration and the planar type configuration. By adopting the S-channel configuration, it is possible to enhance the resistance to the short-channel effect, in other words, to make a transistor in which the short-channel effect hardly occurs.

[0273] Further, conductor 503 has the same configuration as conductor 518, conductor 503a is formed in contact with the inner walls of the openings of insulator 514 and insulator 516, and conductor 503b is further formed inside. Note that in transistor 500, a configuration in which conductor 503a and conductor 503b are laminated is shown, but the present invention is not limited to this. For example, conductor 503 may be provided in a single layer or a laminated configuration of three or more layers.

[0274] Here, the conductor 503a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (it is difficult for the above impurities to permeate). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (it is difficult for the above oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0275] For example, since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0276] Further, when the conductor 503 also serves as a wiring, the conductor 503b preferably uses a highly conductive material mainly composed of tungsten, copper, or aluminum. In this embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer structure.

[0277] The insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.

[0278] Here, the insulator 524 in contact with the oxide 530 preferably uses an insulator containing more oxygen than stoichiometric oxygen. The oxygen is likely to be released from the film by heating. In this specification and the like, the oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. When hydrogen enters the oxygen vacancies in the oxide 530, the defect (hereinafter, V OIn some cases, it may be H. ) functions as a donor, and electrons that are carriers may be generated. Also, a part of hydrogen may combine with oxygen that binds to metal atoms to generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor rich in hydrogen tends to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, V in the oxide 530 O H is preferably reduced as much as possible to high-purity intrinsic or substantially high-purity intrinsic. Thus, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygen addition treatment"). V O By using an oxide semiconductor in which V

[0279] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen desorbs by heating. An oxide that desorbs oxygen by heating means that, by TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0280] In addition, the insulator having the excess oxygen region and the oxide 530 may be subjected to one or more of heat treatment, microwave treatment, or RF treatment while being in contact with each other. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the bond of VoH is broken, in other words, a reaction of "V O H → Vo + H" occurs, and dehydrogenation can be achieved. A part of the hydrogen generated at this time may combine with oxygen to be removed as H2O from the oxide 530 or the insulator near the oxide 530. Also, a part of the hydrogen may be gettered by the conductors 542a and 542b.

[0281] In addition, the microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Also, the microwave treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa or more, more preferably 400 Pa or more. Further, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2 + Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0282] In addition, during the manufacturing process of the transistor 500, it is preferable to perform heat treatment with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 530 to create oxygen vacancies (V OIt is possible to reduce . Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. Or, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0283] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired with the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with the oxygen deficiency to form V O H.

[0284] In addition, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0285] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen or impurities, so that the oxygen possessed by the oxide 530 does not diffuse to the insulator 520 side. In addition, it is possible to suppress the conductor 503 from reacting with the oxygen possessed by the insulator 524 or the oxide 530.

[0286] The insulator 522 is preferably a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0287] In particular, it is preferable to use an insulator containing one or both of aluminum and hafnium oxides, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (oxygen is difficult to permeate). As the insulator containing one or both of aluminum and hafnium oxides, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 or the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0288] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. The above insulators may be laminated with silicon oxide, silicon oxynitride, or silicon nitride and used.

[0289] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Also, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity can be obtained.

[0290] Note that in the transistor 500 of FIGS. 20A and 20B, although the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a three-layer stacked structure, the second gate insulating film may have a single-layer, two-layer, or four-layer or more stacked structure. In that case, it is not limited to a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0291] The transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0292] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0293] In addition, as the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use a metal oxide having a band gap of preferably 2 eV or more, more preferably 2.5 eV or more. Thus, by using a metal oxide having a large band gap, the off-current of the transistor can be reduced.

[0294] The oxide 530 has the oxide 530a under the oxide 530b, so that the diffusion of impurities from the component formed below the oxide 530a to the oxide 530b can be suppressed.

[0295] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0296] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0297] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0298] Specifically, by having a common element (as the main component) other than oxygen in the oxide 530a and the oxide 530b, a mixed layer with a low density of defect energy levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is advisable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0299] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0300] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements is preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0301] In addition, in FIG. 20B, although the conductors 542a and 542b are shown as a single-layer structure, they may also be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may also be used.

[0302] In addition, there are a three-layer structure in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or a molybdenum nitride film is provided, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0303] As shown in FIG. 20B, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0304] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0305] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided to cover the side surface of the oxide 530 and contact the insulator 524.

[0306] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, as the insulator 544, silicon oxynitride, silicon nitride, etc. can also be used.

[0307] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate), etc., which are insulators containing one or both of aluminum or hafnium oxides. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in a later process. When the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0308] By having the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 542a and the conductor 542b by the excess oxygen possessed by the insulator 580.

[0309] The insulator 545 functions as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excessive amount of oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0310] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0311] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Further, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less. Further, the above-described microwave treatment may be performed before and / or after the formation of insulator 545.

[0312] Further, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from insulator 545 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Further, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0313] Note that insulator 545 may have a stacked structure, similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Further, a stacked structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0314] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 20B and 20C, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0315] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 545 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Further, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0316] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0317] Insulator 580 is provided on conductor 542a and conductor 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, as insulator 580, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, or resin, etc. preferably can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide with pores are preferable because an excess oxygen region can be easily formed in a later process.

[0318] Insulator 580 preferably has an excess oxygen region. By providing insulator 580 that releases oxygen upon heating, oxygen in insulator 580 can be efficiently supplied to oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in insulator 580 is reduced.

[0319] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b. Thereby, conductor 560 is formed to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0320] When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of conductor 560 from decreasing. For that purpose, if the film thickness of conductor 560 is increased, conductor 560 can have a high aspect ratio shape. In the present embodiment, since conductor 560 is provided to be embedded in the opening of insulator 580, even if conductor 560 has a high aspect ratio shape, it can be formed without collapsing conductor 560 during the process.

[0321] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0322] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used.

[0323] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0324] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 etc., it is preferable that the concentration of impurities such as water or hydrogen in the insulator 581 is reduced.

[0325] Also, conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided facing each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductors 546 and 548 described later.

[0326] An insulator 582 is provided on the insulator 581. It is preferable to use a material that is barrier against oxygen or hydrogen for the insulator 582. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0327] In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the intrusion of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0328] Also, an insulator 586 is provided on the insulator 582. The insulator 586 can use the same material as the insulator 379. Further, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0329] Also, conductors 546, 548, etc. are embedded in the insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0330] The conductors 546 and 548 function as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 550. The conductors 546 and 548 can be provided using the same materials as the conductors 328 and 330.

[0331] After the formation of the transistor 500, an opening may be formed so as to surround the transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 500 with the above-described insulator having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively wrapped with an insulator having high barrier properties against hydrogen or water. When forming an opening so as to surround the transistor 500, for example, when forming an opening reaching the insulator 522 or the insulator 514 and forming the above-described insulator having high barrier properties so as to be in contact with the insulator 522 or the insulator 514, a part of the manufacturing process of the transistor 500 can be also served, which is preferable. As the insulator having high barrier properties against hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 may be used.

[0332] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0333] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0334] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0335] In this embodiment, the conductors 612 and 610 are shown in a single-layer configuration, but the configuration is not limited thereto, and a stacked configuration of two or more layers may be used. For example, between a conductor having barrier properties and a conductor having high conductivity, a conductor having barrier properties and a conductor having high adhesiveness to the conductor having high conductivity may be formed.

[0336] A ferroelectric can be used for the insulator 630. For the insulator 630, for example, the same materials as those used for the ferroelectric layer 12 shown in the above embodiment can be used. Further, the insulator 630 may have a stacked configuration of a ferroelectric layer and a paraelectric layer as shown in FIGS. 1B1 to 1B4.

[0337] The conductor 620 is provided so as to overlap the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when forming simultaneously with other components such as a conductor, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0338] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be formed using the same material as the insulator 379. Further, the insulator 640 may function as a planarization film covering the uneven shape thereunder.

[0339] By using this configuration, miniaturization or high integration can be achieved in a semiconductor device using a transistor having an oxide semiconductor.

[0340] The configurations, methods, etc. shown in this embodiment can be implemented in appropriate combination with at least a part thereof and other embodiments, examples, etc. described in this specification.

[0341] (Embodiment 4) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0342] The metal oxide preferably contains at least one of indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, it may contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0343] <Classification of crystal structures> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 21A. FIG. 21A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0344] As shown in FIG. 21A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, "CAAC (c-axis-aligned crystalline)", "nc (nanocrystalline)", and "CAC (Cloud-Aligned Composite)" are included in "Crystalline". Note that "single crystal", "poly crystal", and "completely amorphous" are excluded from the classification of "Crystalline". Further, "single crystal" and "poly crystal" are included in "Crystal".

[0345] Note that the structure within the thick frame shown in FIG. 21A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0346] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 21B. Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 21B will be simply referred to as the XRD spectrum. The vertical axis of FIG. 21B is Intensity, and the horizontal axis is 2θ. Note that the composition of the CAAC-IGZO film shown in FIG. 21B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 21B is 500 nm.

[0347] As shown in FIG. 21B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected at around 2θ = 31°. Note that, as shown in FIG. 21B, the peak at around 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0348] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 21C. FIG. 21C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 21C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0349] As shown in FIG. 21C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0350] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 21A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0351] Here, details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0352] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the direction of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0353] Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0354] Also, in an In-M-Zn oxide (the element M is one or a plurality of elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0355] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type, composition, etc. of the metal elements constituting CAAC-OS.

[0356] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam (also referred to as the direct spot) transmitted through the sample as the center of symmetry.

[0357] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even near the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or the interatomic bond distance changes due to the substitution of metal atoms, etc.

[0358] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and there is a high possibility of causing a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carriers being trapped. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for constituting CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0359] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct crystal grain boundaries. Therefore, it can be said that CAAC-OS is less likely to have a reduction in electron mobility due to crystal grain boundaries. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0360] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0361] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0362] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0363] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0364] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is a configuration distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0365] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0366] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0367] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0368] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0369] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily to endow CAC-OS with a switching function (on / off function). That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be realized.

[0370] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0371] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0372] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0373] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less than, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0374] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0375] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0376] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0377] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0378] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry (SIMS)) near the interface between the oxide semiconductor and the oxide semiconductor are 2×10 18 atoms / cm 3 or less, preferably 2×1017 atoms / cm 3 Shall be as follows.

[0379] In addition, when an alkali metal or alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0380] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0381] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, carriers, i.e., electrons, may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate carriers, i.e., electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0382] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0383] The configurations, methods, etc. shown in this embodiment can be implemented in appropriate combination with at least a part of other embodiments, examples, etc. described in this specification.

[0384] (Embodiment 5) In this embodiment, an example of a semiconductor wafer on which a semiconductor device or the like shown in the above embodiment is formed, and an example of an electronic component in which the semiconductor device is incorporated are shown.

[0385] <Semiconductor Wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 22A.

[0386] The semiconductor wafer 4800 shown in Fig. 22A has a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion without the circuit portions 4802 is the spacing 4803, which is a dicing area.

[0387] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the side opposite to the side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warpage and the like of the wafer 4801 can be reduced, and miniaturization as a component can be achieved.

[0388] As the next process, a dicing process is performed. Dicing is performed along the scribe lines SCL1 and SCL2 (which may be referred to as dicing lines or cutting lines) indicated by the dashed line. Note that, in order to facilitate the dicing process, the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular.

[0389] By performing the dicing process, a chip 4800a as shown in Fig. 22B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately the same length as the kerf of the scribe line SCL1 or the kerf of the scribe line SCL2.

[0390] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 22A. For example, it may be a semiconductor wafer having a rectangular shape. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0391] <Electronic component> FIG. 22C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 22C has a chip 4800a in a mold 4711. As the chip 4800a, a storage device or the like according to one aspect of the present invention can be used.

[0392] FIG. 22C omits a part to show the inside of the electronic component 4700. The electronic component 4700 has lands 4712 outside the mold 4711. The lands 4712 are electrically connected to electrode pads 4713, and the electrode pads 4713 are electrically connected to the chip 4800a by wires 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0393] FIG. 22D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 4730, an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

[0394] As the semiconductor device 4710, for example, a chip 4800a, the semiconductor device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device can be used.

[0395] The package substrate 4732 can use a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 4731 can use a silicon interposer, a resin interposer, or the like.

[0396] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Further, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be referred to as a "rewiring substrate" or an "intermediate substrate". In addition, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. Also, in the case of a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0397] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult for a resin interposer.

[0398] In HBM, it is necessary to connect many wirings in order to realize a wide memory bandwidth. For this reason, fine and high-density wiring formation is required for the interposer on which HBM is mounted. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0399] In addition, in a SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer is less likely to occur. Also, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0400] Further, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0401] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 22D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix pattern at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0402] The electronic component 4730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0403] The configurations, methods, etc. shown in this embodiment can be implemented by appropriately combining at least a part thereof with other embodiments, examples, etc. described in this specification.

[0404] (Embodiment 6) In this embodiment, an application example of a semiconductor device according to an aspect of the present invention will be described.

[0405] A semiconductor device according to an aspect of the present invention can be applied to, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game machines, etc.). It can also be used for image sensors, IoT (Internet of Things), healthcare, etc. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large-scale computers such as server systems.

[0406] An example of an electronic device having a semiconductor device according to an aspect of the present invention will be described. Note that FIGS. 23A to 23J and FIGS. 24A to 24E illustrate how the electronic component 4700 or the electronic component 4730 having the semiconductor device is included in each electronic device.

[0407] [Mobile phone] The information terminal 5500 shown in FIG. 23A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0408] By applying a semiconductor device according to an aspect of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser, etc.) generated during the execution of an application.

[0409] [Wearable terminal] Further, FIG. 23B shows an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.

[0410] Similar to the aforementioned information terminal 5500, the wearable terminal can hold temporary files generated during the execution of an application by applying the semiconductor device according to one aspect of the present invention.

[0411] [Information Terminal] Further, FIG. 23C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0412] Similar to the aforementioned information terminal 5500, the desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the semiconductor device according to one aspect of the present invention.

[0413] In the above description, smartphones, wearable terminals, and desktop information terminals are illustrated in FIGS. 23A to 23C as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0414] [Household Appliance] Further, FIG. 23D shows an electric refrigerator-freezer 5800 as an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0415] The semiconductor device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can transmit and receive information such as food stored in the electric refrigerator 5800 and expiration dates of the food to and from an information terminal or the like through the Internet or the like. The electric refrigerator 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.

[0416] In this example, an electric refrigerator has been described as an electric appliance. Other electric appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, etc.

[0417] [Game console] In addition, FIG. 23E shows a portable game console 5200 which is an example of a game console. The portable game console 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0418] Furthermore, FIG. 23F shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 either wirelessly or by wire. Although not shown in FIG. 23F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, or a slide knob, etc. Also, the controller 7522 is not limited to the shape shown in FIG. 23F, and the shape of the controller 7522 can be variously changed according to the genre of the game. For example, in a shooting game such as a FPS (First Person Shooter), a controller in the shape of a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller in the shape of a musical instrument or a music device can be used. Furthermore, the stationary game machine may be configured to operate by a game player's gesture and / or voice, instead of using a controller, and instead be equipped with a camera, a depth sensor, a microphone, etc.

[0419] In addition, the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.

[0420] By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, a portable game machine 5200 with low power consumption or a stationary game machine 7500 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence of the heat on the circuit itself, the peripheral circuit, and the module can be minimized.

[0421] Furthermore, by applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, it is possible to hold a temporary file or the like necessary for the operations occurring during the execution of the game.

[0422] As an example of a game machine, a portable game machine is shown in FIG. 23E. Further, a home stationary game machine is shown in FIG. 23F. Note that the electronic device according to one aspect of the present invention is not limited to this. Examples of the electronic device according to one aspect of the present invention include, for example, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), a pitching machine for batting practice installed in a sports facility, and the like.

[0423] [Mobile body] The semiconductor device described in the above embodiment can be applied to an automobile, which is a mobile body, and the periphery of the driver's seat of the automobile.

[0424] An automobile 5700, which is an example of a mobile body, is illustrated in FIG. 23G.

[0425] Around the driver's seat of the automobile 5700, there is provided an instrument panel that provides various information by displaying a speedometer or a tachometer, and the running distance, fuel gauge, gear state, air conditioner settings, and the like. Further, a display device for indicating such information may be provided around the driver's seat.

[0426] In particular, the display device can supplement a field of view blocked by a pillar or the like, a blind spot of the driver's seat, etc. by projecting an image from an imaging device (not shown) provided in the automobile 5700, and can improve safety. That is, by displaying an image from an imaging device provided outside the automobile 5700, the blind spot can be supplemented and safety can be improved.

[0427] The semiconductor device described in the above embodiment can temporarily hold information. Therefore, the semiconductor device can be used for holding necessary temporary information in an automatic driving system of the automobile 5700 or a system that performs road guidance, danger prediction, etc. The display device may be configured to display temporary information such as road guidance and danger prediction. Further, it may be configured to hold an image of a driving recorder provided in the automobile 5700.

[0428] In the above description, an automobile has been described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc.

[0429] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0430] FIG. 23H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0431] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be minimized.

[0432] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0433] FIG. 23I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, etc. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0434] When recording the video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can hold temporary files generated during encoding.

[0435] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter-defibrillator (ICD).

[0436] FIG. 23J is a schematic cross-sectional view showing an example of an ICD. The ICD body 5400 has at least a battery 5401, an electronic component 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0437] The ICD body 5400 is implanted into the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0438] The ICD main body 5400 has the function as a pacemaker and performs pacing on the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing and ventricular tachycardia, ventricular fibrillation, etc. remain, treatment by electric shock is performed.

[0439] In order to appropriately perform pacing and electric shock, the ICD main body 5400 needs to constantly monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store data on the heart rate acquired by the sensor etc., the number of times of treatment by pacing, time, etc. in the electronic component 4700.

[0440] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, by having a plurality of batteries in the ICD main body 5400, the safety can be enhanced. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0441] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activity may be configured such that physiological signals such as pulse, respiratory rate, heart rate, body temperature, etc. can be confirmed by an external monitoring device.

[0442] [Expansion Device for PC] The semiconductor device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0443] FIG. 24A shows an example of the expansion device, an expansion device 6100 that can be carried and is externally attached to a PC and is equipped with a chip capable of storing information. The expansion device 6100 can store information by the chip by connecting to the PC, for example, via a USB (Universal Serial Bus) or the like. Note that FIG. 24A illustrates the expansion device 6100 in a portable form, but the expansion device according to an aspect of the present invention is not limited thereto, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0444] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. A circuit for driving the semiconductor device and the like described in the above embodiment is provided on the substrate 6104. For example, an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0445] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to an information terminal or an electronic device such as a digital camera.

[0446] FIG. 24B is a schematic diagram of the appearance of an SD card, and FIG. 24C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a writing circuit, a load driver, a reading circuit, etc. provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0447] By providing the electronic component 4700 also on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data of the electronic component 4700 can be read and written.

[0448] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0449] FIG. 24D is a schematic diagram of the appearance of the SSD, and FIG. 24E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, etc. are incorporated in the controller chip 5156. Note that the circuit configurations of each of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a memory that functions as a work memory may also be provided in the controller chip 5156.

[0450] [Computer] The computer 5600 shown in FIG. 25A is an example of a large computer. A plurality of rack-mounted computers 5620 are stored in a rack 5610 in the computer 5600.

[0451] The computer 5620 can have, for example, the configuration of the perspective view shown in FIG. 25B. In FIG. 25B, the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are respectively connected to the motherboard 5630.

[0452] The PC card 5621 shown in FIG. 25C is an example of a processing board equipped with a CPU, GPU, semiconductor devices, etc. The PC card 5621 has a board 5622. The board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Although FIG. 25C shows semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, for those semiconductor devices, the descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below may be referred to.

[0453] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe, etc.

[0454] The connection terminals 5623, 5624, and 5625 can be used as interfaces for, for example, supplying power to and inputting signals to the PC card 5621. Also, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Also, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark), etc.

[0455] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminals into sockets (not shown) provided on the board 5622.

[0456] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, a CPU, and the like. As the semiconductor device 5627, for example, the electronic component 4730 can be used.

[0457] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of the semiconductor device 5628 include a storage device and the like. As the semiconductor device 5628, for example, the electronic component 4700 can be used.

[0458] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0459] By using the semiconductor device according to one aspect of the present invention in the above-described various electronic devices and the like, the power consumption of the electronic device can be reduced.

[0460] The configurations, methods, etc. shown in the present embodiment can be implemented by appropriately combining at least a part thereof with other embodiments, examples, etc. described in this specification.

Example

[0461] In this example, an off-current measurement TEG (Test Element Group) sample and a capacitance leakage current measurement TEG sample having the transistor 500 shown in FIGS. 20A to 20C were fabricated, and the temperature dependence was evaluated.

[0462] [Off-Current Measurement] First, the configuration of the off-current measurement TEG sample having the transistor 500 will be described. As shown in FIGS. 20A to 20C, the sample includes an insulator 512 disposed on a substrate (not shown), an insulator 514 on the insulator 512, an insulator 516 disposed on the insulator 514, a conductor 503 disposed so as to be embedded in the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, regions 543a and 543b provided spaced apart from each other in the oxide 530b, a conductor 542a disposed on the region 543a, a conductor 542b disposed on the region 543b, an insulator 544 disposed on the conductor 542a, the conductor 524b, and the insulator 524, an insulator 580 disposed on the insulator 544, an insulator 545 disposed on the oxide 530b, a conductor 560 disposed on the insulator 545, an insulator 574 disposed on the insulator 580 and the conductor 560, and an insulator 581 disposed on the insulator 574.

[0463] As the oxide 530a, an In-Ga-Zn oxide having a film thickness of 10 nm formed by DC sputtering was used. Note that, for forming the oxide 530a, a target with an In:Ga:Zn = 1:3:4 [atomic ratio] was used.

[0464] As the oxide 530b, an In-Ga-Zn oxide having a film thickness of 15 nm formed by DC sputtering was used. Note that, for forming the oxide 530b, a target with an In:Ga:Zn = 1:1:2 [atomic ratio] was used.

[0465] The insulator 545 had a four-layer laminated structure. The first layer of the insulator 545 was aluminum oxide formed by ALD method with a film thickness of 1 nm. The second layer of the insulator 545 was silicon oxynitride formed by CVD method with a film thickness of 5 nm. The third layer of the insulator 545 was hafnium oxide formed by ALD method with a film thickness of 1.5 nm. The fourth layer of the insulator 545 was silicon nitride formed by ALD method with a film thickness of 1 nm. After the formation of the second layer of the insulator 545 and after the formation of the third layer of the insulator 545, microwave treatment was performed respectively. For the microwave treatment, argon gas and oxygen gas were used as the treatment gas, the treatment temperature was set to 400 °C, and the treatment time was set to 600 seconds.

[0466] In addition to the above configuration, the sample further had a conductor 540. Also, after the sample was fabricated, heat treatment was performed in a nitrogen atmosphere at a temperature of 400 °C for 8 hours. Thus, an off-current measurement TEG sample having a transistor 500 was fabricated.

[0467] Next, Fig. 26 shows a circuit diagram outlining the off-current measurement TEG. The off-current TEG has terminals A to E, a transistor 901, a transistor 902, a reading circuit 903, and a node ND2. The transistor 901 is a write transistor for supplying a potential to the node ND2. Also, the transistor 902 is the transistor to be measured for off-current. As the transistor 902, 20,000 transistors with a designed channel length of 60 nm and a designed channel width of 60 nm are connected in parallel. That is, the transistor 902 has a designed channel length of 60 nm and a designed channel width of (60 nm × 20000 = 1.2 mm).

[0468] One of the source or drain of transistor 901 is electrically connected to terminal A. The other of the source or drain of transistor 901 is electrically connected to node ND2. Also, the gate of transistor 901 is electrically connected to terminal B. One of the source or drain of transistor 902 is electrically connected to node ND2. The other of the source or drain of transistor 902 is electrically connected to terminal D. Also, the gate of transistor 902 is electrically connected to terminal C. Also, the bottom gate of transistor 902 is electrically connected to terminal E. Further, the reading circuit 903 is electrically connected to node ND2. The reading circuit 903 can always read the potential of node ND2.

[0469] Next, a method for measuring the off-current will be described. First, a potential V11 at which transistor 901 turns on is supplied to terminal B to turn on transistor 901. Next, a potential V12 is supplied to terminal A until the potential of node ND2 becomes V12. In this embodiment, V12 is set to 1.2V. Next, a potential V13 at which transistor 901 turns off is supplied to terminal B to turn off transistor 901. Note that transistor 902 is always turned off by supplying a potential of -2V to terminal C, a potential of -3V to terminal E, and a potential of 0V to terminal D, respectively.

[0470] By reading, with the reading circuit 903, the change in the potential of node ND2 over time after transistor 901 is turned off in this way, the leakage current of transistor 902, that is, the off-current, can be calculated. Specifically, if the off-current of transistor 902 is I off , the capacitance of node ND2 is C ND , the potential change of node ND2 is ΔV ND , and the elapsed time is t, then I off = C ND × ΔV NDIt is obtained by / t. Note that the channel length of transistor 901 is a designed value of 500 nm, and the channel width is 60 nm. Since the channel width of transistor 901 is 1 / 20000 of the channel width of transistor 902, the off-current of transistor 901 can be ignored.

[0471] In the measurement environment at a temperature of 150 °C, the potential change ΔV of node ND2 over an elapsed time of 1 hour ND is read, and in the measurement environment at a temperature of 125 °C, the potential change ΔV of node ND2 over an elapsed time of 1 hour ND is read, and in the measurement environment at a temperature of 100 °C, the potential change ΔV of node ND2 over an elapsed time of 2 hours ND is read, and in the measurement environment at a temperature of 85 °C, the potential change ΔV of node ND2 over an elapsed time of 4 hours ND is read.

[0472] Fig. 28 shows a graph of the temperature dependence of the off-current of transistor 902. The horizontal axis in Fig. 28 indicates 1000 times the reciprocal of the absolute temperature T [K], and the vertical axis indicates the leakage current (off-current). The off-current of transistor 902 at each temperature is shown by a diamond-shaped plot in Fig. 28. At a temperature of 150 °C, the off-current is 1.4×10 -20 (A), at a temperature of 125 °C, the off-current is 2.9×10 -21 (A), at a temperature of 100 °C, the off-current is 6.9×10 -22 (A), and at a temperature of 85 °C, the off-current is 2.9×10 -22 (A) are obtained respectively. Also, the approximate straight line is shown by a solid line. When the approximate straight line is extrapolated to room temperature (RT), at room temperature, an off-current of approximately 2×10 -24 (A) and a very small off-current are estimated. From the above, the temperature dependence of the off-current is confirmed.

[0473] [Measurement of capacitance leakage current] Next, the configuration of the capacitance leakage current measurement TEG sample having transistor 500 will be described. The capacitance leakage current measurement TEG sample has a capacitance configuration in addition to the configuration of the off-current measurement TEG sample described in the above [Off-current measurement].

[0474] FIG. 27A shows a cross-sectional view of the capacitor structure. The capacitor includes a conductor 910a on a transistor 500 (not shown), a conductor 910b on the conductor 910a, a dielectric 930a covering the conductor 910a and the conductor 910b, a dielectric 930b on the dielectric 930a, conductors 920a on the dielectric 930b and a conductor 920b on the conductor 920a, an insulator 983a covering the conductors 920a and 920b, and an insulator 983b on the insulator 983a.

[0475] As the conductor 910a, tungsten with a film thickness of 30 nm formed by sputtering was used. As the conductor 910b, titanium nitride with a film thickness of 5 nm formed by CVD was used. The conductors 910a and 910b function as the lower electrode of the capacitor.

[0476] As the dielectric 930a, aluminum oxide with a film thickness of 14 nm formed by ALD was used. As the dielectric 930b, silicon oxynitride with a film thickness of 7 nm formed by CVD was used. The dielectrics 930a and 930b function as the dielectric of the capacitor.

[0477] As the conductor 920a, titanium nitride with a film thickness of 10 nm formed by CVD was used. As the conductor 920b, tungsten with a film thickness of 20 nm formed by sputtering was used. The conductors 920a and 920b function as the upper electrode of the capacitor.

[0478] As the insulator 983a, aluminum oxide with a film thickness of 5 nm formed by ALD was used. As the insulator 983b, aluminum oxide with a film thickness of 35 nm formed by sputtering was used. The insulators 983a and 983b function as the passivation film. After forming the capacitor, heat treatment was performed at a temperature of 400 °C for 8 hours in a nitrogen atmosphere. Thus, a capacitor leakage current measurement TEG sample was fabricated.

[0479] Next, a circuit diagram outlining the capacitance leakage current measurement TEG is shown in FIG. 27B. The capacitance leakage current measurement TEG includes terminal A, terminal B, terminal D, transistor 901, capacitor 904, read circuit 903, and node ND2. Transistor 901 is a write transistor for supplying a potential to node ND2. Also, capacitor 904 is the capacitor whose capacitance leakage current is to be measured. As capacitor 904, 60,000 capacitors having the configuration shown in FIG. 27A with a capacitance of 4.26 fF are connected in parallel.

[0480] One of the source or drain of transistor 901 is electrically connected to terminal A. Also, the other of the source or drain of transistor 901 is electrically connected to node ND2. Also, the gate of transistor 901 is electrically connected to terminal B. Also, one electrode of capacitor 904 is electrically connected to node ND2. Also, the other electrode of capacitor 904 is electrically connected to terminal D. Also, read circuit 903 is electrically connected to node ND2. Read circuit 903 can always read the potential of node ND2.

[0481] Next, a method for measuring capacitance leakage will be described. First, a potential V11 at which transistor 901 is turned on is supplied to terminal B to turn on transistor 901. Next, a potential V12 is supplied to terminal A until the potential of node ND2 becomes V12. In this embodiment, V12 is set to 1.2 V. Also, 0 V is supplied to terminal D.

[0482] By reading, with read circuit 903, the change in the potential of node ND2 over time after transistor 901 is turned off in this way, the leakage current of capacitor 904 can be calculated. Specifically, if the capacitance leakage current is I CS , the capacitance of capacitor 904 is C CS , the potential change of node ND2 is ΔV ND , and the elapsed time is t, then I CS = C CS × ΔV ND / t. Note that the variation in the potential of node ND2 due to the off-current of transistor 901 is negligibly small.

[0483] In the measurement environment at a temperature of 150°C, the potential change ΔV of node ND2 over an elapsed time of 1 hour was read. ND In the measurement environment at a temperature of 125°C, the potential change ΔV of node ND2 over an elapsed time of 4 hours was read. ND In the measurement environment at a temperature of 100°C, the potential change ΔV of node ND2 over an elapsed time of 8 hours was read. ND was read.

[0484] Fig. 28 shows a graph of the temperature dependence of the leakage current of capacitor 904. As described above, the horizontal axis in Fig. 28 indicates 1000 times the reciprocal of the absolute temperature T [K], and the vertical axis indicates the leakage current. The leakage current of capacitor 904 at each temperature is shown by white circle plots in Fig. 28. At a temperature of 150°C, the leakage current of 2.2×10 -20 (A), at a temperature of 125°C, the leakage current of 1.2×10 -21 (A), and at a temperature of 100°C, the leakage current of 3.3×10 -22 (A) were obtained respectively. Also, an approximate straight line is shown by a broken line. It was confirmed from the approximate straight line that the capacitor leakage current decreases as the temperature gets lower. At room temperature, a very small capacitor leakage current was estimated. From the above, the temperature dependence of the capacitor leakage current was confirmed.

[0485] The configurations, methods, etc. shown in this embodiment can be implemented by appropriately combining at least a part of them with other embodiments described in this specification.

Description of Reference Numerals

[0486] 10: Cell, 11: Capacity, 12: Ferroelectric layer, 12a: Ferroelectric layer, 12b: Ferroelectric layer, 13a: Electrode, 13b: Electrode, 14: Paraelectric layer, 14a: Paraelectric layer, 14b: Paraelectric layer, 21: Transistor, 22: Transistor, 23: Transistor, 31: Wiring, 32: Wiring, 33: Wiring, 41: Wiring, 42: Wiring, 43: Wiring, 44: Wiring, 51: Curve, 52: Curve, 60: Semiconductor device, 61: Cell array, 62: Circuit, 63: Circuit, 100: Neural network, 110: Arithmetic circuit, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 368: Insulator, 369: Insulator, 370: Insulator, 371: Substrate, 372: Well region, 373: Insulator, 374: Oxide layer, 375: Semiconductor region, 376: Conductor, 376a: Low-resistance region, 376b: Low-resistance region, 376c: Low-resistance region, 377: Insulator, 378: Conductor, 379: Insulator, 380: Insulator, 381: Insulator, 382: Insulator, 383: Insulator, 384: Insulator, 385: Insulator, 386: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 524b: Conductor, 530: Oxide, 530a: Oxide, 530b: Oxide, 540: Conductor, 540a: Conductor, 540b: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 548: Conductor, 550: Transistor, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacity, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 640: Insulator, 901: Transistor, 902: Transistor, 903: Read circuit, 904: Capacity, 910a: Conductor, 910b: Conductor, 920a: Conductor, 920b: Conductor, 930a: Dielectric, 930b: Dielectric, 983a: Insulator, 983b: Insulator, 4700: Electronic component, 4702: Printed circuit board, 4704: Mounting substrate, 4710: Semiconductor device4711: Mold, 4712: Land, 4713: Electrode Pad, 4714: Wire, 4730: Electronic Component, 4731: Interposer, 4732: Package Substrate, 4733: Electrode, 4735: Semiconductor Device, 4800: Semiconductor Wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit Section, 4803: Spacing, 4803a: Spacing, 5110: SD Card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller Chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory Chip, 5156: Controller Chip, 5200: Portable Game Machine, 5201: Housing, 5202: Display Unit, 5203: Button, 5300: Desktop Information Terminal, 5301: Main Body, 5302: Display Unit, 5303: Keyboard, 5400: ICD Main Body, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian Vein, 5406: Superior Vena Cava, 5500: Information Terminal, 5510: Housing, 5511: Display Unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC Card, 5622: Board, 5623: Connection Terminal, 5624: Connection Terminal, 5625: Connection Terminal, 5626: Semiconductor Device, 5627: Semiconductor Device, 5628: Semiconductor Device, 5629: Connection Terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric Refrigerator-Freezer, 5801: Housing, 5802: Refrigerator Door, 5803: Freezer Door, 5900: Information Terminal, 5901: Housing, 5902: Display Unit, 5903: Operation Switch, 5904: Operation Switch, 5905: Band, 6100: Expansion Device, 6101: Housing, 6102: Cap, 6103: USB Connector, 6104: Substrate, 6106: Controller Chip, 6240: Digital Camera, 6241: Housing, 6242: Display Unit, 6243: Operation Switch, 6244: Shutter Button, 6246: Lens, 6300: Video Camera, 6301: Housing, 6302: Housing, 6303: Display Unit, 6304: Operation Switch, 6305: Lens, 6306: Connection Section, 7500: Console Game Machine, 7520: Main Body, 7522: Controller

Claims

1. A cell having a capacitance, a first transistor, a second transistor, and a third transistor, wherein the capacitance has a first electrode, a second electrode, and a ferroelectric layer, the ferroelectric layer is provided between the first electrode and the second electrode, the ferroelectric layer generates polarization inversion by applying a first saturation polarization voltage or a second saturation polarization voltage having a polarity different from that of the first saturation polarization voltage, the first electrode, one of the source or drain of the first transistor, and the gate of the second transistor are electrically connected to each other, a driving method of a semiconductor device, wherein one of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor, in a first period, applying the first saturation polarization voltage to the ferroelectric layer, in a second period, applying a voltage having a value between the first saturation polarization voltage and the second saturation polarization voltage to the ferroelectric layer as a data voltage, turning on the first transistor in the first period and the second period, turning off the first transistor in a third period, turning off the third transistor in the first to third periods, a driving method of a semiconductor device, turning on the third transistor in a fourth period.

2. In Claim 1, the potential of the first electrode in the first period is different from the potential of the first electrode in the second period, a driving method of a semiconductor device, wherein the potential of the second electrode in the first period is different from the potential of the second electrode in the second period.

3. In Claim 1 or Claim 2, a driving method of a semiconductor device, supplying a constant potential to the other of the source or drain of the second transistor in the first to fourth periods.

4. In any one of Claims 1 to 3, a driving method of a semiconductor device, wherein the polarity of the polarization amount of the ferroelectric layer in the first period is the same as the polarity of the polarization amount of the ferroelectric layer in the second period.

5. In any one of Claims 1 to 4, a driving method of a semiconductor device, wherein the data voltage represents analog data.

6. In any one of Claims 1 to 5, A method for driving a semiconductor device in which the first transistor has a metal oxide in a channel formation region. **Claim 7**: In accordance with Claim 6, A method for driving a semiconductor device, wherein the metal oxide is a metal oxide containing indium.

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