Semiconductor device

Abstract

To provide a new semiconductor device.SOLUTION: A semiconductor device includes a drive circuit and first to third transistor layers. The first transistor layer includes a first memory cell with a first transistor and a first capacitor. The second transistor layer includes a second memory cell with a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting to the amplifier circuit. The first to third transistor layers are provided on a silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification describes semiconductor devices and the like.

[0002] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device, etc. are semiconductor devices themselves and may have a semiconductor device.

Background Art

[0003] Metal oxides have attracted attention as semiconductors applicable to transistors. Indium-Gallium-Zinc oxide, called "IGZO", "Igzo", etc., is a typical multi-component metal oxide. In research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been found (for example, Non-Patent Document 1).

[0004] A transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as "oxide semiconductor transistor" or "OS transistor") has been reported to have an extremely small off-current (for example, Non-Patent Documents 1 and 2). Various semiconductor devices using OS transistors have been fabricated (for example, Non-Patent Documents 3 and 4).

[0005] The manufacturing process of OS transistors can be incorporated into the CMOS process for conventional Si transistors, and OS transistors can be stacked on Si transistors. For example, Patent Document 1 discloses a configuration in which a plurality of layers of a memory cell array having OS transistors are stacked on a substrate provided with Si transistors.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device or the like having a novel configuration as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration capable of reducing manufacturing costs in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration capable of miniaturizing the device in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems. Or one aspect of the present invention is to provide a semiconductor device or the like having a novel configuration with small variations in the electrical characteristics of transistors and excellent reliability in a semiconductor device that functions as a memory device using an extremely small off-current as one of the problems.

[0009] The description of a plurality of problems does not prevent the existence of each other's problems. One aspect of the present invention does not need to solve all the exemplified problems. Also, problems other than those listed will naturally become apparent from the description of this specification, and such problems can also be the problems of one aspect of the present invention.

Means for Solving the Problems

[0010] One aspect of the present invention has a drive circuit having a plurality of transistors using a silicon substrate as a channel, and first to third transistor layers each having a plurality of transistors using a metal oxide as a channel. The first transistor layer has a first memory cell having a first transistor and a first capacitor. The second transistor layer has a second memory cell having a second transistor and a second capacitor. The third transistor layer has a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line, and the second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting it to the amplifier circuit. The first to third transistor layers are provided on a silicon substrate, and the third transistor layer is provided between the first transistor layer and the second transistor layer. It is a semiconductor device.

[0011] In one aspect of the present invention, it is preferable that the semiconductor device has a first local bit line and a second local bit line provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0012] In one aspect of the present invention, it is preferable that the semiconductor device has a global bit line, and the global bit line has a function of electrically connecting the amplifier circuit and the drive circuit.

[0013] In one aspect of the present invention, it is preferable that the semiconductor device has a global bit line provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0014] In one aspect of the present invention, it is preferable that the semiconductor device has a metal oxide containing In, Ga, and Zn.

[0015] One aspect of the present invention includes a drive circuit having a plurality of transistors using a silicon substrate as a channel, and an element layer provided with a plurality of transistor layers stacked thereon. The element layer includes first to third transistor layers each having a plurality of transistors using a metal oxide as a channel. The first transistor layer has a first memory cell having a first transistor and a first capacitor. The second transistor layer has a second memory cell having a second transistor and a second capacitor. The third transistor layer has a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line, and the second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting it to the amplifier circuit. The element layer is provided stacked on the silicon substrate, and the third transistor layer is provided between the first transistor layer and the second transistor layer. It is a semiconductor device.

[0016] In one aspect of the present invention, it is preferable that the semiconductor device is such that the first local bit line and the second local bit line are provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0017] In one aspect of the present invention, it is preferable that the semiconductor device has a global bit line, and the global bit line has a function of electrically connecting the amplifier circuit and the drive circuit.

[0018] In one aspect of the present invention, it is preferable that the semiconductor device is such that the global bit line is provided in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0019] In one aspect of the present invention, it is preferable that the semiconductor device is such that the metal oxide contains In, Ga, and Zn.

[0020] One aspect of the present invention is an electronic device having at least one of the semiconductor device described above, an antenna, a battery, an operation switch, a microphone, or a speaker.

[0021] For other aspects of the present invention, they are described in the embodiments described below and in the drawings.

Advantages of the Invention

[0022] One aspect of the present invention can provide a semiconductor device or the like with a novel configuration. Or one aspect of the present invention can provide a semiconductor device or the like with a novel configuration that can reduce manufacturing costs in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention can provide a semiconductor device or the like with a novel configuration that is excellent in low power consumption in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention can provide a semiconductor device or the like with a novel configuration that can miniaturize the device in a semiconductor device that functions as a memory device using an extremely small off-current. Or one aspect of the present invention can provide a semiconductor device or the like with a novel configuration in which fluctuations in the electrical characteristics of transistors are small and the reliability is excellent in a semiconductor device that functions as a memory device using an extremely small off-current.

[0023] The description of multiple effects does not prevent the existence of other effects. Also, one aspect of the present invention does not necessarily have to have all of the exemplified effects. Also, regarding one aspect of the present invention, other problems, effects, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

[0024]

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Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments of the present invention will be described. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be construed as being limited to the description of the embodiments shown below.

[0026] In this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0027] In the drawings, the same reference numerals may be given to the same elements, elements having the same or similar functions, elements of the same material, or elements formed simultaneously, and repeated explanations may be omitted.

[0028] In this specification, for example, the power supply potential VDD may be described by omitting it as the potential VDD, VDD, etc. The same applies to other components (for example, signals, voltages, circuits, elements, electrodes, wirings, etc.).

[0029] When the same reference numerals are used for a plurality of elements, particularly when it is necessary to distinguish them, a distinguishing reference numeral such as “_1”, “_2”, “[n]”, “[m,n]”, etc. may be appended to the reference numeral for description. For example, the second wiring GL is described as wiring GL[2].

[0030] (Embodiment 1) A configuration example of a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 1 to 12.

[0031] Note that a semiconductor device is a device that utilizes semiconductor characteristics, and is a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.) and a device having the circuit. The semiconductor device described in the present embodiment can function as a storage device using a transistor with an extremely small off-current.

[0032] FIG. 1 shows a block diagram for explaining the cross-sectional structure of the semiconductor device 10.

[0033] The semiconductor device 10 has a plurality of element layers 50_1 to 50_M (M is a natural number) on a silicon substrate 60. The element layers 50_1 to 50_M each have a transistor layer 20, a transistor layer 30, and a transistor layer 40. The transistor layer 30 is composed of a plurality of transistor layers 31_1 to 31_k (k is a natural number of 2 or more). The transistor layer 40 is composed of a plurality of transistor layers 32_1 to 31_k.

[0034] The block diagram shown in FIG. 1 corresponds to a schematic diagram defining the z-axis direction in order to explain the arrangement of each component. The z-axis direction means a direction perpendicular or substantially perpendicular to the surface of the silicon substrate 60. Note that “substantially perpendicular” means a state where the angle is 85 degrees or more and 95 degrees or less. For ease of understanding, the z-axis direction may be referred to as the perpendicular direction. Note that the surface of the silicon substrate 60 corresponds to a surface formed by the x-axis and the y-axis defined in a direction perpendicular or substantially perpendicular to the z-axis direction. For ease of understanding, the x-axis direction may be referred to as the depth direction and the y-axis direction may be referred to as the horizontal direction.

[0035] The transistor layer 30 composed of a plurality of transistor layers 31_1 to 31_k has a plurality of memory cells (not shown) in each transistor layer. Each memory cell has a transistor and a capacitor. Note that the capacitor may be referred to as a capacitive element. Note that the element layer refers to a layer in which elements such as capacitors and transistors are provided, and is a layer having members such as conductors, semiconductors, and insulators.

[0036] Similarly, the transistor layer 40 composed of a plurality of transistor layers 32_1 to 32_k has a plurality of memory cells in each transistor layer. Each memory cell has a transistor and a capacitor.

[0037] Note that the memory cells included in each of the transistor layers 31_1 to 31_k and 32_1 to 32_k can be called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) that uses a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an OS transistor) as a memory. Since it can be composed of one transistor and one capacitor, high density of the memory can be realized. Further, by using the OS transistor, the data retention period can be lengthened.

[0038] In the configuration of one aspect of the present invention, by adopting a configuration using a memory cell having an OS transistor, charge corresponding to a desired voltage can be held in a capacitor located on the other side of the source or drain by utilizing the characteristic that the leakage current (hereinafter referred to as off-current) flowing between the source and the drain during the off state is extremely low. That is, in the memory cell, the data once written can be held for a long time. Therefore, the frequency of data refresh can be reduced and low power consumption can be achieved.

[0039] In addition, in a memory cell using an OS transistor, since data can be rewritten and read by charging or discharging electric charges, substantially unlimited rewrites and reads of data are possible. A memory cell using an OS transistor does not involve a structural change at the atomic level like a magnetic memory or a resistive change memory, and thus has excellent rewrite resistance. Also, different from a flash memory, a memory cell using an OS transistor does not show instability due to an increase in electron trapping centers even when repeatedly rewritten.

[0040] In addition, a memory cell using an OS transistor can be freely arranged on a silicon substrate having a transistor (hereinafter referred to as an Si transistor) containing silicon in a channel formation region, etc., so that integration can be easily performed. Also, since an OS transistor can be fabricated using the same manufacturing equipment as an Si transistor, it can be fabricated at low cost.

[0041] In addition, an OS transistor can be a four-terminal semiconductor device when it includes a back gate electrode in addition to a gate electrode, a source electrode, and a drain electrode. An OS transistor can be configured with an electric circuit network in which the input and output of a signal flowing between the source and the drain can be independently controlled according to the voltage applied to the gate electrode or the back gate electrode. Therefore, circuit design can be performed with the same concept as that of an LSI. In addition, an OS transistor has better electrical characteristics than an Si transistor in a high-temperature environment. Specifically, since the ratio of the on-current to the off-current is large even at a high temperature of 125°C or higher and 150°C or lower, a good switching operation can be performed.

[0042] The transistor layer 20 has a function of selecting one of the plurality of memory cells included in the transistor layer 30 and the transistor layer 40 to perform data writing and reading.

[0043] The transistor layer 20 has a plurality of switching circuits and amplification circuits. The switching circuit has a function of selecting a local bit line connected to one of the plurality of memory cells. With this configuration, at the time of reading, a slight potential difference of the local bit line is amplified and output to the global bit line GBL, and data can be read by further amplifying it with a sense amplifier provided on the silicon substrate. The amplification circuit has a function of amplifying and outputting the signal of the local bit line to the global bit line GBL.

[0044] Note that the local bit line is a bit line directly connected to the memory cell. The global bit line GBL is a bit line that is electrically connected to the memory cell by selecting any one of the plurality of local bit lines. The data signal applied to the global bit line or the local bit line corresponds to the signal written to the memory cell or the signal read from the memory cell. The data signal is described as a binary signal having a high-level or low-level potential corresponding to data 1 or data 0. Note that the data signal may be a multi-value of three values or more. In the drawings, the global bit line GBL may be illustrated with a thick line or a thick dotted line or the like in order to enhance visibility.

[0045] As illustrated in FIG. 1, the transistor layer 20 is provided between the transistor layer 30 and the transistor layer 40 in the z-axis direction. The transistor layer 20 included in each element layer 50_1 to 50_M has a function of outputting the data signal selected by the switching circuit and amplified by the amplification circuit to the drive circuit included in the silicon substrate 60 via the global bit line GBL. Further, the transistor layer 20 has a function of applying the data signal output from the drive circuit included in the silicon substrate 60 to the local bit line selected by the switching circuit.

[0046] The silicon substrate 60 has a drive circuit for writing or reading data to / from the memory cell selected by the transistor layer 20 via the global bit line GBL and the local bit line. The drive circuit has a plurality of Si transistors using the silicon substrate 60 as a channel.

[0047] In one embodiment of the present invention, as a transistor provided in each element layer, an OS transistor with an extremely low off-current is used. Therefore, the refresh frequency of the data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be achieved. The OS transistors can be stacked and manufactured by repeatedly using the same manufacturing process in the vertical direction, thereby reducing the manufacturing cost. Further, in one embodiment of the present invention, the transistors constituting the memory cell are arranged in the vertical direction instead of the planar direction, so that the memory density can be improved and the device can be miniaturized. Also, since the OS transistor has less variation in electrical characteristics compared to the Si transistor even in a high-temperature environment, it can function as a semiconductor device that is a storage device with less variation in the electrical characteristics of the transistors when stacked and integrated and excellent reliability.

[0048] Next, FIG. 2A shows a block diagram of an element layer 50 corresponding to any one of the element layers 50_1 to 50_M in FIG. 1.

[0049] As shown in FIG. 1, in the element layer 50 in one aspect of the present invention, a plurality of transistor layers 30 and 40 having memory cells are provided in the layers above and below the transistor layer 20 in the z-axis direction. By adopting such a configuration, the distance between the transistor layer 20 and the transistor layer 30 or the transistor layer 40 can be made close. By shortening the local bit line, the parasitic capacitance can be reduced. By repeatedly manufacturing the plurality of transistor layers 30 and 40 in the vertical direction using the same manufacturing process, the manufacturing cost can be reduced.

[0050] FIG. 2B is a diagram showing each configuration in the element layer 50 shown in FIG. 2A using circuit symbols.

[0051] The transistor layer 20 includes a switching circuit 21 and an amplifying circuit 22. The transistor layers 31_1, 31_2, 32_1, and 32_2 each have a plurality of memory cells 33. The memory cell 33 has a transistor 34 and a capacitor 35. The transistor 34 functions as a switch that switches between a conductive state and a non-conductive state in response to the control of a word line WL connected to the gate. The local bit lines LBL_A1 and LBL_A2 correspond to the local bit lines connected to the memory cells 33 located on the lower layer side of the switching circuit 21. The local bit lines LBL_B1 and LBL_B2 correspond to the local bit lines connected to the memory cells 33 located on the upper layer side of the switching circuit 21.

[0052] As shown in FIG. 2B, the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 are each connected to one of the source or drain of the transistor 34 included in different memory cells. The capacitor 35 is connected to the other of the source or drain of the transistor 34.

[0053] The transistor 34 is the OS transistor described above. The capacitor 35 has a structure in which an insulator is sandwiched between conductors serving as electrodes. As the conductor constituting the electrode, in addition to metal, a semiconductor layer provided with conductivity can be used. Although details will be described later, in addition to the configuration in which the capacitor 35 is disposed at an overlapping position above or below the transistor 34, a part of the semiconductor layer or electrode constituting the transistor 34 can be used as one electrode of the capacitor 35.

[0054] The switching circuit 21 has a function of supplying the potential of a selected one of a plurality of local bit lines such as the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 to the amplifying circuit 22 in response to a signal for selecting any one of the local bit lines. The switching circuit 21 has a circuit that functions as a multiplexer.

[0055] The amplifying circuit 22 has a function of amplifying the potential of the local bit line selected by the switching circuit 21 and outputting it to the global bit line GBL. Alternatively, it has a function of transmitting the potential of the global bit line GBL to the local bit line selected by the switching circuit 21. The amplifying circuit 22 has a function as a reading circuit that can amplify the potential of the local bit line and output it to the global bit line GBL according to a signal for controlling the reading of the data signal. Also, the amplifying circuit 22 has a function as a writing circuit that can transmit the potential of the global bit line GBL to the local bit line selected by the switching circuit 21 according to a signal for controlling the writing of the data signal.

[0056] The transistors constituting the switching circuit 21 and the amplifying circuit 22 included in the transistor layer 20 are also preferably composed of OS transistors, similar to the transistor 34. Since the transistor layers 20, 30, and 40 constituting the element layer 50 using OS transistors can be stacked and arranged on a silicon substrate having Si transistors, integration can be easily performed.

[0057] In FIG. 2B, in the switching circuit 21, a configuration is illustrated in which the local bit lines LBL_A1, local bit line LBL_A2, local bit line LBL_B1, and local bit line LBL_B2 connected to the memory cells in the upper and lower layers of the transistor layer 20 are selected, but other configurations may also be possible.

[0058] In FIGS. 3A and 3B, configurations different from the connection with the local bit lines LBL_A1, local bit line LBL_A2, local bit line LBL_B1, and local bit line LBL_B2 described in FIG. 2B are shown.

[0059] It is also possible to adopt a configuration in which a switching circuit is provided for each pair of local bit lines provided in the upper and lower layers of the transistor layer having the switching circuit. For example, as shown in FIG. 3A, the switching circuit 21_A switches the local bit line LBL_A1 and the local bit line LBL_B1 and outputs the result to the global bit line GBL via the amplifier circuit 22_A and the switch 27A. The switching circuit 21_B switches the local bit line LBL_A2 and the local bit line LBL_B2 and outputs the result to the global bit line GBL via the amplifier circuit 22_B and the switch 27B. Note that the switches 27A and 27B can be configured using the OS transistors described above.

[0060] Alternatively, it is also possible to adopt a configuration in which a switching circuit is provided for each local bit line provided in the upper layer or the lower layer of the transistor layer having the switching circuit. For example, as shown in FIG. 3B, the switching circuit 21_A switches the local bit line LBL_A1 and the local bit line LBL_A2 and outputs the result to the global bit line GBL via the amplifier circuit 22_A and the switch 27C. The switching circuit 21_B switches the local bit line LBL_B1 and the local bit line LBL_B2 and outputs the result to the global bit line GBL via the amplifier circuit 22_B and the switch 27D. Note that the switches 27C and 27D can be configured using the OS transistors described above.

[0061] FIG. 4A shows a perspective view of the semiconductor device 10 in which the element layers 50_1 to 50_M shown in FIG. 1 are arranged on the silicon substrate 60. In FIG. 4A, in addition to the vertical direction (z-axis direction), the depth direction (x-axis direction) and the horizontal direction (y-axis direction) are represented.

[0062] In FIG. 4A, the memory cells 33 included in the transistor layers 31_1, 31_2, 32_1, and 32_2 are illustrated by dotted lines. The switching circuit 21 and the amplifier circuit 22 included in the transistor layer 20 are also illustrated by dotted lines.

[0063] As shown in FIG. 4A, a semiconductor device 10 according to an aspect of the present invention includes transistor layers 20, 30, and 40 having OS transistors, which are stacked. Therefore, the same manufacturing process can be repeatedly used in the vertical direction, and the manufacturing cost can be reduced. Further, in the semiconductor device 10 according to an aspect of the present invention, the transistor layers 30 and 40 having memory cells 33 are stacked and arranged in the vertical direction instead of the planar direction, so that the memory density can be improved and the device can be miniaturized.

[0064] FIG. 4B is a diagram showing each circuit provided on a silicon substrate 60, with the configurations of the element layers 50_1 to 50_M shown in FIG. 4A omitted. In FIG. 4B, a control logic circuit 61, a row drive circuit 62, a column drive circuit 63, and an output circuit 64, which are composed of Si transistors on the silicon substrate 60, are shown. The control logic circuit 61, the row drive circuit 62, the column drive circuit 63, and the output circuit 64 will be described in detail in Embodiment 4.

[0065] FIG. 5 corresponds to a diagram showing the transistor layers 20, 31_1, 31_2, 32_1, and 32_2 of the semiconductor device 10 shown in FIG. 4A extracted. In FIG. 5, a switching circuit 21 and an amplifier circuit 22 in the transistor layer 20 are shown. Also in FIG. 5, transistors 34, capacitors 35, local bit lines LBL, and word lines WL included in the memory cells in the transistor layers 31_1, 31_2, 32_1, and 32_2 are shown. In FIG. 5, the local bit lines LBL are shown by broken lines for enhanced visibility. Also in FIG. 5, a global bit line GBL provided penetrating each transistor layer in the z-axis direction is shown. As described above, the global bit line GBL is shown by a thick line compared to other lines for enhanced visibility.

[0066] In the semiconductor device 10, as shown in FIG. 5, a local bit line LBL connected to a transistor 34 included in a memory cell, an amplification circuit 22 in a transistor layer 20, and a global bit line GBL connected to a silicon substrate 60 are provided in the z-axis direction, that is, in a direction perpendicular to the silicon substrate 60. With this configuration, the local bit line LBL between each memory cell and the switching circuit can be shortened. Therefore, since the parasitic capacitance of the local bit line LBL can be significantly reduced, even if the data signal held in the memory cell is multi-valued, the potential can be read out. Further, in one aspect of the present invention, since the data held in the memory cell can be read out as a current, even if it is multi-valued, the data can be easily read out.

[0067] FIG. 6 is a diagram showing a circuit configuration of an example of a switching circuit 21 and an amplification circuit 22 included in the transistor layer 20. In FIG. 6, transistors 21_1 to 21_4 that function as a multiplexer or a demultiplexer for selecting any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 described in FIG. 2B, and transistors 22_1 to 22_3 that constitute the amplification circuit 22 are shown.

[0068] The transistor 21_1 controls the conduction state between the local bit line LBL_A1 and the gate of the transistor 22_1. A signal SEL1 for controlling the conduction state of the transistor 21_1 is applied to the gate of the transistor 21_1. Similarly, the transistors 21_2 to 21_4 control the conduction state between the local bit lines LBL_A2, LBL_B1, or LBL_B2 and the gate of the transistor 22_1. Signals SEL2 to SEL4 are applied to the gates of the transistors 21_2 to 21_4.

[0069] Transistors 22_1 and 22_3 are transistors that constitute a read circuit for the data signal held in memory cell 33. The gate of transistor 22_1 is connected to one of the sources or drains of transistors 21_1 to 21_4. The source of transistor 22_1 is connected to wiring SL to which a fixed potential is applied. The drain of transistor 22_1 is connected to the source of transistor 22_3. The drain of transistor 22_3 is connected to global bit line GBL. The potential of the gate of transistor 22_1 is amplified by transistor 22_1 and read out to global bit line GBL in accordance with the control of signal RE applied to the gate of transistor 22_3.

[0070] Transistor 22_2 is a transistor that constitutes a write circuit for the data signal held in memory cell 33. One of the source or drain of transistor 22_2 is connected to one of the sources or drains of transistors 21_1 to 21_4. For transistor 22_2, the other of the source or drain is connected to global bit line GBL. Transistor 22_2 can write the potential of global bit line GBL to memory cell 33 in accordance with the control of signal WE applied to the gate and the control of the signal applied to word line WL.

[0071] In FIGS. 7A to 7C, circuit diagrams for explaining modified examples of switching circuit 21 and amplifier circuit 22 illustrated in FIG. 6 are shown.

[0072] FIG. 7A is a circuit diagram showing the configuration of the switching circuit 21 and the amplifier circuit 22 described in FIG. 6. As shown in FIG. 7A, the transistors 21_1 to 21_4 constituting the switching circuit 21 select any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2, and control the conduction state between the gate of the transistor 22_1. Further, the transistors 21_1 to 21_4 constituting the switching circuit 21 control to apply the potential of the global bit line GBL to any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 via the transistor 22_2. The amplifier circuit 22 controls to convert the potential of the gate of the transistor 22_1 into a current and transmit it to the global bit line GBL.

[0073] FIG. 7B corresponds to a circuit diagram in which the connection of one of the source or drain terminals of the transistor 22_2 in FIG. 7A is changed. Further, FIG. 7C corresponds to a circuit diagram in which the connection of the transistor 22_3 in FIG. 7A to the wiring SL side is changed. As described above, the switching circuit 21 and the amplifier circuit 22 according to one aspect of the present invention can have various circuit configurations.

[0074] In FIGS. 7A to 7C, each transistor is illustrated as a transistor having a top gate structure or a bottom gate structure without a back gate electrode, but the structure of the transistor is not limited thereto. For example, as shown in FIG. 8A, the transistors 23_1 to 23_4 and 24_1 to 24_3 having back gate electrodes connected to the back gate electrode line BGL may be used. By adopting the configuration of FIG. 8A, it is possible to easily control electrical characteristics such as the threshold voltage of the transistors 23_1 to 23_4 and 24_1 to 24_3 from the outside.

[0075] Alternatively, as shown in FIG. 8B, the transistors 25_1 to 25_4 and 26_1 to 26_3 having back gate electrodes connected to the gate electrodes may be used. By adopting the configuration of FIG. 8B, the amount of current flowing through the transistors 25_1 to 25_4 and 26_1 to 26_3 can be increased.

[0076] Although the semiconductor device 10 in FIG. 1 has been described as having one type of memory cell, it may have two or more types of memory cells. FIG. 9A shows a block diagram of a semiconductor device 10A corresponding to a modified example of the semiconductor device 10.

[0077] The semiconductor device 10A is different from the semiconductor device 10 in that transistor layers 41A and 41B having memory cells with different circuit configurations are provided between the transistor layer 20 and the transistor layer 30, and between the transistor layer 20 and the transistor layer 40.

[0078] FIG. 9B is a circuit diagram showing a configuration example of the memory cells included in the transistor layers 41A and 41B. The memory cell 41 includes a transistor 42, a transistor 43, and a capacitor 44.

[0079] One of the source or drain of the transistor 42 is connected to the gate of the transistor 43. The gate of the transistor 43 is connected to one electrode of the capacitor 44. The other of the source or drain of the transistor 42 and one of the source or drain of the transistor 43 are connected to the wiring BL2. The other of the source or drain of the transistor 43 is connected to the wiring SL2. The other electrode of the capacitor 44 is electrically connected to the wiring CAL. Here, a node where one of the source or drain of the transistor 42, the gate of the transistor 43, and one electrode of the capacitor 44 are connected is defined as node N.

[0080] The wiring CAL functions as a wiring for applying a predetermined potential to the other electrode of the capacitor 44. When reading data from the memory cell 41, the potential of the wiring CAL is made different from the potential of the wiring CAL when writing data to the memory cell 41 and when the memory cell 41 is holding data. Thereby, the apparent threshold voltage of the transistor 43 when reading data from the memory cell 41 can be made different from the apparent threshold voltage of the transistor 43 when writing data to the memory cell 41 and when the memory cell 41 is holding data.

[0081] When the memory cell 41 has the configuration shown in FIG. 9B, when writing data to the memory cell 41 and while the memory cell 41 is holding data, no current flows between the wiring SL2 and the wiring BL2 regardless of the data written to the memory cell 41. On the other hand, when reading data from the memory cell 41, a current corresponding to the data held in the memory cell 41 flows between the wiring SL2 and the wiring BL2.

[0082] The transistors 42 and 43 are preferably OS transistors. As described above, the OS transistor has an extremely low off-current. Therefore, the charge corresponding to the data written to the memory cell 41 can be held in the node N for a long time. That is, in the memory cell 41, the once-written data can be held for a long time. Therefore, the frequency of data refresh can be reduced, and the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0083] The memory cell 41 having the configuration shown in FIG. 9B can be called a NOSRAM (Nonvolatile Oxide Semiconductor RAM) using an OS transistor as a memory. The NOSRAM has the feature that it can perform non-destructive readout. On the other hand, the above-described DOSRAM performs destructive readout when reading the held data.

[0084] The semiconductor device 10A can transfer data with a high read frequency from the DOSRAM to the NOSRAM by having the memory cell 41. As described above, since the NOSRAM can perform non-destructive readout, the frequency of data refresh can be reduced. Therefore, the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0085] In FIGS. 10A and 10B, circuit diagrams for explaining a modified example of the semiconductor device 10 illustrated in FIG. 1 are shown.

[0086] FIG. 10A shows a semiconductor device 10B in which the transistor layer 40 is omitted in the element layers 50_1 to 50_M of the semiconductor device 10 illustrated in FIG. 1. The semiconductor device 10B illustrated in FIG. 10A has a transistor layer 30 having transistors 31_1 to 31_k below the transistor layer 20 having a switching circuit and an amplification circuit. Also in this configuration, the operation of controlling the memory cell by the switching circuit and the amplification circuit is possible.

[0087] FIG. 10B shows a semiconductor device 10C in which the transistor layer 30 is omitted in the element layers 50_1 to 50_M of the semiconductor device 10 illustrated in FIG. 1. The semiconductor device 10C illustrated in FIG. 10B has a transistor layer 40 having transistors 32_1 to 32_k above the transistor layer 20 having a switching circuit and an amplification circuit. Also in this configuration, the operation of controlling the memory cell by the switching circuit and the amplification circuit is possible.

[0088] FIG. 11 shows, in addition to the memory cell 33, switching circuit, and amplification circuit described with reference to FIGS. 6 and 7A, the OS transistors 21_1 to 21_4 and 22_1 to 22_3, a precharge circuit 62_A, a precharge circuit 62_B, a sense amplifier 62_C, a switch circuit 62_D, a switch circuit 62_E, and a write / read circuit 69, which are composed of Si transistors on a silicon substrate 60.

[0089] Also, the transistors 22_2 and 22_3 included in the transistor layer 20 are connected to the global bit lines GBL_A and GBL_B as shown in FIG. 11. The global bit lines GBL_A and GBL_B are provided in a direction perpendicular to the surface of the silicon substrate 60, similar to the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2, and are connected to the Si transistors.

[0090] The precharge circuit 62_A is composed of n-channel transistors 65_1 to 65_3. The precharge circuit 62_A is a circuit for precharging the global bit lines GBL_A and GBL_B and the selected local bit lines to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL1 and the signal WE.

[0091] The precharge circuit 62_B is composed of n-channel transistors 65_4 to 65_6. The precharge circuit 62_B is a circuit for precharging the global bit lines GBL_A and GBL_B and the selected local bit lines to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL2 and the signal WE.

[0092] Sense amplifier 62_C is composed of p-channel transistors 67_1 and 67_2 and n-channel transistors 67_3 and 67_4 connected to wiring VHH or wiring VLL. Wiring VHH or wiring VLL is wiring having a function of supplying VDD or VSS. Transistors 67_1 to 67_4 are transistors that constitute an inverter loop. By setting the word line WL to a high level, the potential of the selected local bit line LBL changes, and the current flowing through transistor 22_1 changes accordingly. Global bit lines GBL_A and GBL_B become the high power supply potential VDD or the low power supply potential VSS according to the current flowing through transistor 22_1. The potentials of global bit lines GBL_A and GBL_B can be output to the outside via switch circuits 62_D and 62_E and via write / read circuit 69. Write / read circuit 69 controls the writing of data signals according to signal EN_data.

[0093] Switch circuit 62_D is a circuit for controlling the conduction state between sense amplifier 62_C, global bit line GBL_A, and global bit line GBL_B. Switch circuit 62_D is switched on or off under the control of switching signal CSEL1. For switches 66_A and 66_B, in the case of n-channel transistors, they are on when switching signal CSEL1 is at a high level and off when at a low level. Switch circuit 62_E is a circuit for controlling the conduction state between write / read circuit 69 and the bit line pair connected to sense amplifier 62_C. Switch circuit 62_E is switched on or off under the control of switching signal CSEL2. The configuration of switches 68_C and 68_D may be the same as that of switches 66_A and 66_B.

[0094] Also, FIG. 12 shows a timing chart for explaining the operation of the circuit diagram shown in FIG. 11. In the timing chart shown in FIG. 12, period T11 corresponds to the period for explaining the write operation, period T12 corresponds to the precharge operation of bit line BL, period T13 corresponds to the precharge operation of global bit line GBL, period T14 corresponds to the charge sharing operation, period T15 corresponds to the read standby operation, and period T16 corresponds to the read operation. In the explanation of the operation, the local bit line connected to the memory cell to which the data signal is to be written is defined as local bit line LBL, and the signal applied to the gate of the transistor connected to the local bit line LBL is defined as signal SEL. Signal SEL corresponds to any one of signals SEL_1 to SEL_4 for making the local bit line to which the selected memory cell is connected and the gate of transistor 22_1 in a conductive state.

[0095] In period T11, word line WL connected to the gate of the transistor of the memory cell to which the data signal is to be written is set to a high level. In period T11, signal SEL, signal WE, and signal EN_data are set to a high level, and the data signal is written into the memory cell via global bit line GBL and bit line BL.

[0096] In period T12, in order to precharge local bit line LBL, precharge line PCL1 is set to a high level with signal SEL and signal WE set to a high level. Local bit line LBL is precharged to the precharge potential. In period T12, it is preferable that both wiring VHH and wiring VLL for supplying the power supply voltage to sense amplifier 62_C are set to VDD / 2 to suppress the power consumption due to the through current.

[0097] In period T13, in order to precharge global bit line GBL, precharge line PCL2 is set to a high level. Global bit line GBL is precharged to the precharge potential. In period T13, by setting both wiring VHH and wiring VLL to VDD, global bit line GBL with a large load can be precharged in a short time.

[0098] During period T14, in order to perform charge sharing for equalizing the charge held in the memory cell 33 and the charge pre-charged in the local bit line LBL, the word line WL and the signal SEL are set to high level. The local bit line LBL and the gate of the transistor 22_1 become equipotential. During period T14, it is preferable that both the wiring VHH and the wiring VLL for supplying the power supply voltage to the sense amplifier 62_C are set to VDD / 2 to suppress the power consumption due to the through current.

[0099] During period T15, the word line WL and the signal RE are set to high level. This is a period in which a current flows through the transistor 22_1 according to the potential of the gate of the transistor 22_1, and the potential of the global bit line GBL varies according to the amount of the current. The switching signal CSEL1 is set to low level so that the variation in the potential of the global bit line GBL is not affected by the sense amplifier 62_C. The wiring VHH or the wiring VLL is the same as in period T14.

[0100] During period T16, the switching signal CSEL1 is set to high level, and the data signal written in the memory cell is read out by amplifying the variation in the potential of the global bit line GBL with the bit line pair connected to the sense amplifier 62_C.

[0101] In one embodiment of the present invention, as a transistor provided in each element layer, an OS transistor with an extremely low off-current is used. Therefore, the refresh frequency of the data held in the memory cell can be reduced, and a semiconductor device with low power consumption can be achieved. The OS transistors can be stacked and manufactured by repeatedly using the same manufacturing process in the vertical direction, thereby reducing the manufacturing cost. Further, in one embodiment of the present invention, the transistors constituting the memory cell are arranged not in the planar direction but in the vertical direction, so that the memory density can be improved and the device can be miniaturized. Also, since the OS transistor has less variation in electrical characteristics than the Si transistor even in a high-temperature environment, it can be a semiconductor device that functions as a storage device with small variation in electrical characteristics of the transistors and excellent reliability when stacked and integrated.

[0102] In the element layer according to one aspect of the present invention, a transistor layer having a memory cell is provided above and below a transistor layer including a switching circuit and an amplification circuit in the z-axis direction. By adopting such a configuration, the distance between the memory cell and the switching circuit and the amplification circuit can be reduced. By shortening the local bit line, the parasitic capacitance can be reduced. By repeatedly manufacturing a plurality of transistor layers 30 and 40 in the vertical direction using the same manufacturing process, the manufacturing cost can be reduced.

[0103] (Embodiment 2) Hereinafter, an example of a semiconductor device that functions as a storage device according to one aspect of the present invention will be described.

[0104] FIG. 13 is a diagram showing an example of a semiconductor device in which memory units 470 (memory units 470_1 to 470_m: m is a natural number of 2 or more) are stacked on an element layer 411 having a circuit provided on a semiconductor substrate 311. In FIG. 13, a plurality of memory units 470 are stacked on the element layer 411, and each of the plurality of memory units 470 has a corresponding transistor layer 413 (transistor layers 413_1 to 413_m) and a plurality of memory device layers 415 (memory device layers 415_1 to 415_n: n is a natural number of 2 or more) on each transistor layer 413. An example is shown. In each memory unit 470, an example in which a memory device layer 415 is provided on the transistor layer 413 is shown, but the present embodiment is not limited to this. A transistor layer 413 may be provided on the plurality of memory device layers 415, or memory device layers 415 may be provided above and below the transistor layer 413.

[0105] The element layer 411 has a transistor 300 provided on the semiconductor substrate 311 and can function as a circuit (sometimes referred to as a peripheral circuit) of the semiconductor device. Examples of the circuit include a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, an amplifier circuit, a word line driver circuit, an output circuit, a control logic circuit, and the like.

[0106] The transistor layer 413 has a transistor 200T and can function as a circuit for controlling each memory unit 470. The memory device layer 415 has a memory device 420. The memory device 420 shown in the present embodiment has a transistor 200M and a capacitor element 292.

[0107] Incidentally, the value of m above is not particularly limited, but it is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. Also, the value of n above is not particularly limited, but it is 2 or more and 100 or less, preferably 2 or more and 50 or less, and more preferably 2 or more and 10 or less. Further, the product of m and n above is 4 or more and 256 or less, preferably 4 or more and 128 or less, and more preferably 4 or more and 64 or less.

[0108] Further, FIG. 13 shows a cross-sectional view in the channel length direction of the transistor 200T and the transistor 200M included in the memory unit.

[0109] As shown in FIG. 13, a transistor 300 is provided on a semiconductor substrate 311, and a transistor layer 413 and a memory device layer 415 included in the memory unit 470 are provided on the transistor 300. In one memory unit 470, the transistor 200T included in the transistor layer 413 and the memory device 420 included in the memory device layer 415 are electrically connected by a plurality of conductors 424, and the transistor 300 and the transistor 200T included in the transistor layer 413 in each memory unit 470 are electrically connected by a conductor 426. Further, the conductor 426 is preferably electrically connected to the transistor 200T via a conductor 428 that electrically connects to any one of the source, drain, and gate of the transistor 200T. The conductor 424 is preferably provided in each layer of the memory device layer 415. Also, the conductor 426 is preferably provided in each layer of the transistor layer 413 and the memory device layer 415.

[0110] Also, although details will be described later, it is preferable to provide an insulator that suppresses the permeation of impurities such as water or hydrogen and oxygen on the side surfaces of the conductor 424 and the conductor 426. As such an insulator, for example, silicon nitride, aluminum oxide, or silicon oxynitride may be used.

[0111] The memory device 420 has the transistor 200M and the capacitance element 292, and the transistor 200M can have the same structure as the transistor 200T included in the transistor layer 413. Further, the transistors 200T and 200M may be collectively referred to as the transistor 200.

[0112] Here, for the transistor 200, it is preferable to use, for a semiconductor including a region where a channel is formed (hereinafter, also referred to as a channel formation region), a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor.

[0113] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Further, as the oxide semiconductor, indium oxide, In-Ga oxide, or In-Zn oxide may be used. Note that by using an oxide semiconductor having a high ratio of indium, the on-current or field-effect mobility of the transistor can be increased.

[0114] The transistor 200 using an oxide semiconductor in the channel formation region has an extremely small leakage current in the non-conducting state, so that a semiconductor device with low power consumption can be provided. Further, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, it can be used for the transistor 200 that constitutes a highly integrated semiconductor device.

[0115] On the other hand, in a transistor using an oxide semiconductor, its electrical characteristics fluctuate due to impurities and oxygen vacancies (also referred to as V O : oxygen vacancy) in the oxide semiconductor, and it tends to have a normally-on characteristic (a characteristic in which a channel exists even when no voltage is applied to the gate electrode and a current flows through the transistor).

[0116] Therefore, it is preferable to use an oxide semiconductor with a reduced impurity concentration and defect level density. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0117] Therefore, it is preferable that the impurity concentration in the oxide semiconductor is reduced as much as possible. Examples of impurities in the oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0118] In particular, hydrogen as an impurity contained in the oxide semiconductor may form oxygen vacancies in the oxide semiconductor. Further, a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) may generate electrons serving as carriers. Furthermore, a part of hydrogen may react with oxygen bonded to a metal atom to generate electrons serving as carriers.

[0119] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. In addition, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate.

[0120] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor with reduced impurities such as hydrogen and oxygen vacancies for the oxide semiconductor used in the transistor 200.

[0121] <Sealing structure> Therefore, in order to suppress the mixing of impurities from the outside, the transistor 200 may be sealed using a material that suppresses the diffusion of impurities (hereinafter also referred to as a barrier material for impurities).

[0122] In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability). Or, it refers to a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0123] For example, as materials having a function of suppressing diffusion with respect to hydrogen and oxygen, there are aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride, etc. In particular, since silicon nitride or silicon oxynitride has a high barrier property against hydrogen, it is preferably used as a material for sealing.

[0124] Also, for example, as materials having a function of capturing and fixing hydrogen, there are metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, etc.

[0125] Between the transistor 300 and the transistor 200, it is preferable that an insulator 211, an insulator 212, and an insulator 214 are provided as a layer having a barrier property. By using a material that suppresses the diffusion and permeation of impurities such as hydrogen in at least one of the insulator 211, the insulator 212, and the insulator 214, it is possible to suppress the diffusion of impurities such as hydrogen and water contained in the semiconductor substrate 311, the transistor 300, etc. into the transistor 200. Also, by using a material that suppresses the permeation of oxygen in at least one of the insulator 211, the insulator 212, and the insulator 214, it is possible to suppress the diffusion of oxygen contained in the channel of the transistor 200 or the transistor layer 413 into the element layer 411. For example, it is preferable to use a material that suppresses the permeation of impurities such as hydrogen and water as the insulator 211 and the insulator 212, and use a material that suppresses the permeation of oxygen as the insulator 214. Further, it is more preferable to use a material having a property of absorbing and occluding hydrogen as the insulator 214. As the insulator 211 and the insulator 212, nitrides such as silicon nitride and silicon oxynitride can be used, for example. As the insulator 214, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, etc. can be used, for example. In particular, it is preferable to use aluminum oxide as the insulator 214.

[0126] Further, it is preferable that an insulator 287 is provided on the side surfaces of the transistor layer 413 and the memory device layer 415, that is, on the side surfaces of the memory unit 470, and it is preferable that an insulator 282 is provided on the upper surface of the memory unit 470. At this time, the insulator 282 preferably contacts the insulator 287, and the insulator 287 preferably contacts at least one of the insulator 211, the insulator 212, and the insulator 214. As the insulator 287 and the insulator 282, it is preferable to use a material that can be used for the insulator 214.

[0127] Further, it is preferable that an insulator 283 and an insulator 284 are provided so as to cover the insulator 282 and the insulator 287, and the insulator 283 preferably contacts at least one of the insulator 211, the insulator 212, and the insulator 214. FIG. 13 shows an example in which the insulator 287 contacts the side surface of the insulator 214, the side surface of the insulator 212, and the upper surface and side surface of the insulator 211, and the insulator 283 contacts the upper surface and side surface of the insulator 287 and the upper surface of the insulator 211, but the present embodiment is not limited thereto. The insulator 287 may contact the side surface of the insulator 214 and the upper surface and side surface of the insulator 212, and the insulator 283 may contact the upper surface and side surface of the insulator 287 and the upper surface of the insulator 212. As the insulator 282 and the insulator 287, it is preferable to use a material that can be used for the insulator 211 and the insulator 212.

[0128] In the above structure, it is preferable to use a material that suppresses oxygen permeation as the insulator 287 and the insulator 282. Further, it is more preferable to use a material having the property of capturing and fixing hydrogen as the insulator 287 and the insulator 282. By using a material having a function of capturing and fixing hydrogen on the side closer to the transistor 200, hydrogen in the transistor 200 or in the memory unit 470 is captured and fixed by the insulator 214, the insulator 287, and the insulator 282, so that the hydrogen concentration in the transistor 200 can be reduced. Further, as the insulator 283 and the insulator 284, it is preferable to use a material that suppresses the permeation of impurities such as hydrogen and water.

[0129] With the above structure, the memory unit 470 is surrounded by the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284. More specifically, the memory unit 470 is surrounded by the insulator 214, the insulator 287, and the insulator 282 (which may be referred to as the first structure), and the memory unit 470 and the first structure are surrounded by the insulator 211, the insulator 212, the insulator 283, and the insulator 284 (which may be referred to as the second structure). Also, the structure in which the memory unit 470 is surrounded by a plurality of structures of two or more layers is sometimes called a nested structure. Here, the fact that the memory unit 470 is surrounded by a plurality of structures may be expressed as the memory unit 470 being sealed by a plurality of insulators.

[0130] Also, the second structure seals the transistor 200 via the first structure. Therefore, the hydrogen existing outside the second structure is suppressed from diffusing into the inside (the transistor 200 side) of the second structure by the second structure. That is, the first structure can efficiently capture and fix the hydrogen existing in the internal structure of the second structure.

[0131] As the above structure, specifically, a metal oxide such as aluminum oxide can be used for the first structure, and a nitride such as silicon nitride can be used for the second structure. More specifically, an aluminum oxide film may be disposed between the transistor 200 and the silicon nitride film.

[0132] Furthermore, the hydrogen concentration in the film can be reduced by appropriately setting the film formation conditions for the material used for the structure.

[0133] Generally, a film formed by using the CVD method has higher coating properties than a film formed by using the sputtering method. On the other hand, the compound gas used in the CVD method often contains hydrogen, and a film formed by using the CVD method has a higher hydrogen content than a film formed by using the sputtering method.

[0134] Therefore, for example, a film with a reduced hydrogen concentration in the film (specifically, a film formed by a sputtering method) may be used for the film adjacent to the transistor 200. On the other hand, when using a film with high film-forming property and relatively high hydrogen concentration in the film (specifically, a film formed by a CVD method) as a film for suppressing the diffusion of impurities, a film having a function of capturing and fixing hydrogen and with a reduced hydrogen concentration may be disposed between the transistor 200 and the film with relatively high hydrogen concentration and high film-forming property.

[0135] That is, a film with a relatively low hydrogen concentration in the film may be used for the film disposed adjacent to the transistor 200. On the other hand, a film with a relatively high hydrogen concentration in the film may be disposed remotely from the transistor 200.

[0136] Specifically, as the above structure, when the transistor 200 is sealed using silicon nitride formed by a CVD method, an aluminum oxide film formed by a sputtering method may be disposed between the transistor 200 and the silicon nitride film formed by a CVD method. More preferably, a silicon nitride film formed by a sputtering method may be disposed between the silicon nitride film formed by a CVD method and the aluminum oxide film formed by a sputtering method.

[0137] In addition, when forming a film using a CVD method, the hydrogen concentration in the formed film may be reduced by forming the film using a compound gas that does not contain hydrogen atoms or has a low content of hydrogen atoms.

[0138] Also, it is preferable that an insulator 282 and an insulator 214 are provided between each transistor layer 413 and the memory device layer 415, or between each memory device layer 415. Further, it is preferable that an insulator 296 is provided between the insulator 282 and the insulator 214. The insulator 296 can be made of the same material as the insulator 283 and the insulator 284. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material may be used. Here, the insulator 282, the insulator 296, and the insulator 214 may be elements constituting the transistor 200. It is preferable that the insulator 282, the insulator 296, and the insulator 214 also serve as components of the transistor 200 because the number of manufacturing steps for the semiconductor device can be reduced.

[0139] Also, it is preferable that the side surfaces of the insulator 282, the insulator 296, and the insulator 214 provided between each transistor layer 413 and the memory device layer 415, or between each memory device layer 415, are in contact with the insulator 287. With such a structure, the transistor layer 413 and the memory device layer 415 are each surrounded and sealed by the insulator 282, the insulator 296, the insulator 214, the insulator 287, the insulator 283, and the insulator 284.

[0140] Also, an insulator 274 may be provided around the insulator 284. Further, a conductor 430 may be provided so as to be embedded in the insulator 274, the insulator 284, the insulator 283, and the insulator 211. The conductor 430 is electrically connected to the circuit included in the transistor 300, i.e., the element layer 411.

[0141] Also, in the memory device layer 415, since the capacitor element 292 is formed in the same layer as the transistor 200M, the height of the memory device 420 can be made approximately the same as that of the transistor 200M, and an excessive increase in the height of each memory device layer 415 can be suppressed. Thereby, the number of memory device layers 415 can be increased relatively easily. For example, a stack including the transistor layer 413 and the memory device layer 415 may be about 100 layers.

[0142] <Transistor 200> Using FIG. 14A, the transistor 200 that can be used for the transistor 200T included in the transistor layer 413 and the transistor 200M included in the memory device 420 will be described.

[0143] As shown in FIG. 14A, the transistor 200 includes an insulator 216, conductors 205 (conductor 205a and conductor 205b), an insulator 222, an insulator 224, oxides 230 (oxide 230a, oxide 230b, and oxide 230c), conductors 242 (conductor 242a and conductor 242b), oxides 243 (oxide 243a and oxide 243b), an insulator 272, an insulator 273, an insulator 250, and conductors 260 (conductor 260a and conductor 260b).

[0144] Also, the insulator 216 and the conductor 205 are provided on the insulator 214, and an insulator 280 and an insulator 282 are provided on the insulator 273. The insulator 214, the insulator 280, and the insulator 282 can be regarded as constituting a part of the transistor 200.

[0145] Also, a semiconductor device according to an aspect of the present invention includes conductors 240 (conductor 240a and conductor 240b) that are electrically connected to the transistor 200 and function as plugs. Note that insulators 241 (insulator 241a and insulator 241b) may be provided in contact with side surfaces of the conductors 240 that function as plugs. Also, conductors 246 (conductor 246a and conductor 246b) that are electrically connected to the conductor 240 and function as wirings are provided on the insulator 282 and on the conductor 240.

[0146] Also, it is preferable that the conductors 240a and 240b use a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductors 240a and 240b may have a laminated structure.

[0147] When the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Further, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen may be used singly or in a laminate. By using the conductive material, it is possible to further reduce the mixing of impurities such as water or hydrogen diffused from the insulator 280 into the oxide 230 through the conductor 240a and the conductor 240b. Further, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0148] Further, as the insulator 241 provided in contact with the side surface of the conductor 240, for example, silicon nitride, aluminum oxide, or silicon oxynitride may be used. Since the insulator 241 is provided in contact with the insulator 272, the insulator 273, the insulator 280, and the insulator 282, it is possible to suppress the mixing of impurities such as water or hydrogen from the insulator 280 into the oxide 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0149] For the conductor 246, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

[0150] In the transistor 200, the conductor 260 functions as the first gate of the transistor, and the conductor 205 functions as the second gate of the transistor. Further, the conductor 242a and the conductor 242b function as a source electrode or a drain electrode.

[0151] The oxide 230 functions as a semiconductor having a channel formation region.

[0152] The insulator 250 functions as a first gate insulator, and the insulators 222 and 224 function as second gate insulators.

[0153] Here, in the transistor 200 shown in FIG. 14A, the conductor 260 is self-alignedly formed via the oxide 230c and the insulator 250 in the opening provided in the insulator 280, the insulator 273, the insulator 272, the conductor 242, etc.

[0154] That is, since the conductor 260 is formed so as to fill the opening provided in the insulator 280 etc. via the oxide 230c and the insulator 250, alignment of the conductor 260 is not required in the region between the conductor 242a and the conductor 242b.

[0155] Here, it is preferable to provide the oxide 230c in the opening provided in the insulator 280 etc. Therefore, the insulator 250 and the conductor 260 have a region that overlaps with the laminated structure of the oxide 230b and the oxide 230a via the oxide 230c. By adopting such a structure, since the oxide 230c and the insulator 250 can be formed by continuous film formation, the interface between the oxide 230 and the insulator 250 can be kept clean. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 200 can obtain a high on-current and high frequency characteristics.

[0156] Also, in the transistor 200 shown in FIG. 14A, the bottom surface and the side surface of the conductor 260 are in contact with the insulator 250. Also, the bottom surface and the side surface of the insulator 250 are in contact with the oxide 230c.

[0157] Also, as shown in FIG. 14A, the transistor 200 has a structure in which the insulator 282 and the oxide 230c are in direct contact. By adopting such a structure, diffusion of oxygen contained in the insulator 280 into the conductor 260 can be suppressed.

[0158] Therefore, the oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b through the oxide 230c, so that the oxygen deficiencies in the oxide 230a and the oxide 230b can be reduced, and the electrical characteristics and reliability of the transistor 200 can be improved.

[0159] Hereinafter, a detailed configuration of a semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

[0160] It is preferable to use, as the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region, a metal oxide (hereinafter, also referred to as an oxide semiconductor) that functions as an oxide semiconductor.

[0161] For example, as the metal oxide that functions as an oxide semiconductor, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a large energy gap, the leakage current (off-current) in the non-conducting state of the transistor 200 can be made extremely small. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0162] Specifically, as the oxide 230, a metal oxide such as an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. Further, as the oxide 230, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used.

[0163] As shown in FIG. 14A, the oxide 230 preferably has an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least partially in contact with the upper surface of the oxide 230b. Here, the side surface of the oxide 230c is preferably provided in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272, the insulator 273, and the insulator 280.

[0164] That is, the oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a under the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed. Also, by having the oxide 230c on the oxide 230b, diffusion of impurities from a structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0165] Note that in the transistor 200, a configuration in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are laminated in the channel formation region and its vicinity is shown, but the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. For example, the oxide 230c may have a two-layer structure to provide a four-layer stacked structure.

[0166] In addition, the oxide 230 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. Further, the oxide 230c can use a metal oxide that can be used for the oxide 230a or the oxide 230b.

[0167] Specifically, as the oxide 230a, a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used.

[0168] In addition, as the oxide 230b, a metal oxide having a composition of In:Ga:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, or a composition of 1:1:1 [atomic ratio] or in the vicinity thereof may be used. Also, as the oxide 230b, a metal oxide having a composition of In:Ga:Zn = 5:1:3 [atomic ratio] or in the vicinity thereof, or a composition of In:Ga:Zn = 10:1:3 [atomic ratio] or in the vicinity thereof may be used. Further, as the oxide 230b, an In-Zn oxide (for example, a composition of In:Zn = 2:1 [atomic ratio] or in the vicinity thereof, a composition of In:Zn = 5:1 [atomic ratio] or in the vicinity thereof, or a composition of In:Zn = 10:1 [atomic ratio] or in the vicinity thereof) may be used. Also, as the oxide 230b, an In oxide may be used.

[0169] In addition, as the oxide 230c, a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio or a composition in the vicinity thereof], Ga:Zn = 2:1 [atomic ratio] or a composition in the vicinity thereof, or Ga:Zn = 2:5 [atomic ratio] or a composition in the vicinity thereof may be used. Further, materials that can be used for the oxide 230b may be applied to the oxide 230c, and it may be provided in a single layer or a laminate. For example, specific examples of the case where the oxide 230c has a laminated structure include a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof and In:Ga:Zn = 1:3:4 [atomic ratio] or a composition in the vicinity thereof, a laminated structure of Ga:Zn = 2:1 [atomic ratio] or a composition in the vicinity thereof and In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof, a laminated structure of Ga:Zn = 2:5 [atomic ratio] or a composition in the vicinity thereof and In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof, a laminated structure of gallium oxide and In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof, and the like.

[0170] Note that the configuration of the OS transistor included in the memory cell 33 shown in Embodiment 1 and the configuration of the OS transistor included in the element layer 50 may be different. For example, for the oxide 230c included in the OS transistor provided in the memory cell 33, a metal oxide having a composition of In:Ga:Zn = 4:2:3 [atomic ratio] or a composition in the vicinity thereof is used, and for the oxide 230c included in the OS transistor provided in the element layer 50, In:Ga:Zn = 5:1:3 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn = 10:1:3 [atomic ratio] or a composition in the vicinity thereof, In:Zn = 10:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn = 5:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn = 2:1 [atomic ratio] or a composition in the vicinity thereof may be used.

[0171] In addition, in the oxide 230b and the oxide 230c, it is preferable to increase the ratio of indium in the film because the on-current or field-effect mobility of the transistor can be increased. The above-mentioned composition in the vicinity includes a range of ±30% of the desired atomic ratio.

[0172] Further, the oxide 230b may have crystallinity. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later. Oxides having crystallinity such as CAAC-OS have a dense structure with less impurities and defects (such as oxygen deficiency) and high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Further, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0173] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Further, the conductor 205 is preferably provided embedded in the insulator 216.

[0174] When the conductor 205 functions as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0175] Note that, as shown in FIG. 14A, the conductor 205 may be provided to be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. Although not shown here, it is preferable that the conductor 205 extends to a region outside the oxide 230a and the oxide 230b in the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap via an insulator outside the side surface of the oxide 230 in the channel width direction. By providing the conductor 205 to be large, local charging (referred to as charge-up) may be alleviated in the process using plasma in the manufacturing process after the formation of the conductor 205. However, one aspect of the present invention is not limited to this. The conductor 205 may overlap at least the oxide 230 located between the conductor 242a and the conductor 242b.

[0176] Also, with reference to the bottom surface of the insulator 224, the height of the bottom surface of the conductor 260 in the region where the oxide 230a, the oxide 230b, and the conductor 260 do not overlap is preferably arranged at a position lower than the height of the bottom surface of the oxide 230b.

[0177] Although not shown, in the channel width direction, the conductor 260 functioning as a gate has a structure that covers the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, so that the electric field generated from the conductor 260 can easily act on the entire channel formation region generated in the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. In this specification, the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the conductor 260 and the conductor 205 is called a surrounded channel (S-channel) structure.

[0178] In addition, the conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Further, for the conductor 205b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a two-layer structure, it may have a multilayer structure of three or more layers.

[0179] Here, by continuously forming different film types of an oxide semiconductor, an insulator or a conductor located under the oxide semiconductor, and an insulator or a conductor located above the oxide semiconductor without exposing them to the atmosphere, it is possible to form an oxide semiconductor film with a reduced concentration of impurities (particularly, hydrogen and water) and substantially high-purity intrinsic properties, which is preferable.

[0180] At least one of the insulator 222, the insulator 272, and the insulator 273 preferably functions as a barrier insulating film that suppresses the entry of impurities such as water or hydrogen into the transistor 200 from the substrate side or from above. Therefore, at least one of the insulator 222, the insulator 272, and the insulator 273 preferably uses an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate).

[0181] For example, it is preferable to use silicon nitride or silicon oxynitride as the insulator 273, and aluminum oxide or hafnium oxide as the insulator 222 and the insulator 272.

[0182] Thereby, it is possible to suppress the diffusion of impurities such as water or hydrogen to the transistor 200 side through the insulator 222. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 222.

[0183] In addition, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 280 disposed via the insulators 272 and 273 toward the transistor 200. Thus, it is preferable that the transistor 200 has a structure surrounded by the insulators 272 and 273 having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0184] Here, the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. In this specification, oxygen desorbed by heating may be referred to as excess oxygen. For example, the insulator 224 may be appropriately silicon oxide or silicon oxynitride. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0185] Specifically, as the insulator 224, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. The oxide that desorbs oxygen by heating means that the desorption amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more in a temperature programmed desorption gas analysis (TDS (Thermal Desorption Spectroscopy) analysis). Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0186] The insulator 222 preferably functions as a barrier insulating film that suppresses the intrusion of impurities such as water or hydrogen from the substrate side into the transistor 200. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, etc. with the insulator 222 and the insulator 283, it is possible to suppress the intrusion of impurities such as water or hydrogen from the outside into the transistor 200.

[0187] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, it is possible to reduce the diffusion of the oxygen contained in the oxide 230 to the lower side of the insulator 222, which is preferable. In addition, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0188] As the insulator 222, an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulator containing one or both of oxides of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the intrusion of impurities such as hydrogen from the peripheral portion of the transistor 200 into the oxide 230.

[0189] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators and used.

[0190] In addition, the insulator 222 may be a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). For example, when the insulator 222 is a laminate, a three-layer laminate in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order, or a four-layer laminate in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed in this order may be used. Further, as the insulator 222, a compound containing hafnium and zirconium may be used. As the miniaturization and high integration of semiconductor devices progress, problems such as leakage current in transistors and capacitor elements may occur due to the thinning of the gate insulator and the dielectric used in capacitor elements. By using a high-k material as the insulator functioning as the gate insulator and the dielectric used in capacitor elements, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor element while maintaining the physical film thickness.

[0191] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0192] In addition, an oxide 243 (oxide 243a and oxide 243b) may be disposed between the oxide 230b and the conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode or a drain electrode. Since the conductor 242 and the oxide 230b are not in contact, it is possible to suppress the conductor 242 from absorbing the oxygen of the oxide 230b. That is, by preventing the oxidation of the conductor 242, it is possible to suppress a decrease in the conductivity of the conductor 242. Therefore, the oxide 243 preferably has a function of suppressing the oxidation of the conductor 242.

[0193] By disposing an oxide 243 having a function of suppressing oxygen permeation between a conductor 242 that functions as a source electrode or a drain electrode and an oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. With such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved.

[0194] As the oxide 243, a metal oxide having an element M selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be used. In particular, it is preferable to use aluminum, gallium, yttrium, or tin as the element M. The concentration of the element M in the oxide 243 is preferably higher than that in the oxide 230b. Further, gallium oxide may be used as the oxide 243. Further, a metal oxide such as an In-M-Zn oxide may be used as the oxide 243. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, the film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be preferably suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal, the release of oxygen in the oxide 230 may be suppressed.

[0195] Note that the oxide 243 is not necessarily provided. In that case, when the conductor 242 (conductor 242a and conductor 242b) comes into contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242, and the conductor 242 may be oxidized. When the conductor 242 is oxidized, the probability of a decrease in the conductivity of the conductor 242 is high. Note that the diffusion of oxygen in the oxide 230 into the conductor 242 can be rephrased as the conductor 242 absorbing oxygen in the oxide 230.

[0196] In addition, when oxygen in the oxide 230 diffuses into the conductor 242 (conductor 242a and conductor 242b), a different layer may be formed between the conductor 242a and the oxide 230b, and between the conductor 242b and the oxide 230b. Since the different layer contains more oxygen than the conductor 242, it is presumed that the different layer has insulating properties. At this time, the three-layer structure of the conductor 242, the different layer, and the oxide 230b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure, or a diode junction structure mainly composed of a MIS structure.

[0197] Note that the above different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, the different layer may be formed between the conductor 242 and the oxide 230c, or may be formed between the conductor 242 and the oxide 230b and between the conductor 242 and the oxide 230c.

[0198] On the oxide 243, conductors 242 (conductor 242a and conductor 242b) that function as a source electrode and a drain electrode are provided. The film thickness of the conductor 242 may be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0199] As the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Also, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0200] The insulator 272 is provided in contact with the upper surface of the conductor 242 and preferably functions as a barrier layer. With this configuration, it is possible to suppress the absorption of excess oxygen in the insulator 280 by the conductor 242. Also, by suppressing the oxidation of the conductor 242, it is possible to suppress an increase in the contact resistance between the transistor 200 and the wiring. Therefore, good electrical characteristics and reliability can be given to the transistor 200.

[0201] Therefore, the insulator 272 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 272, for example, it is advisable to form an insulator containing one or both oxides of aluminum and hafnium. Also, as the insulator 272, for example, an insulator containing aluminum nitride may be used.

[0202] As shown in FIG. 14A, the insulator 272 contacts a part of the upper surface of the conductor 242b and the side surface of the conductor 242b. Although not shown, the insulator 272 also contacts a part of the upper surface of the conductor 242a and the side surface of the conductor 242a. Further, an insulator 273 is disposed on the insulator 272. By doing so, for example, it is possible to suppress oxygen added to the insulator 280 from being absorbed by the conductor 242.

[0203] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0204] Similar to the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b. Also, similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0205] Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses oxygen diffusion, oxygen diffusion from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Also, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0206] In addition, the metal oxide may function as part of the gate insulator. Therefore, when using silicon oxide, silicon oxynitride, etc. for the insulator 250, it is preferable to use a metal oxide which is a high-k material with a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it becomes possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0207] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, it is preferable to use an insulator containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate).

[0208] Alternatively, the metal oxide may function as part of the gate. In this case, it is advisable to provide a conductive material containing oxygen on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

[0209] In particular, as the conductor functioning as a gate, it is preferable to use a conductive material containing a metal element and oxygen included in the metal oxide in which a channel is formed. Also, a conductive material containing the aforementioned metal element and nitrogen may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which a channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0210] Conductor 260 is shown as a two-layer structure in Fig. 14A, but it may be a single-layer structure or a laminated structure of three or more layers.

[0211] For conductor 260a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0212] Also, since conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of conductor 260b by oxygen contained in insulator 250 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0213] In addition, the conductor 260b preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Further, the conductor 260b may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above conductive material.

[0214] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxides applicable to the oxide 230 according to the present invention will be described.

[0215] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that gallium, yttrium, tin, etc. are contained. Also, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

[0216] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.). In particular, as element M, aluminum, gallium, yttrium, or tin may be used.

[0217] In this specification, etc., a metal oxide having nitrogen may also be generically called a metal oxide. Also, a metal oxide having nitrogen may be called a metal oxynitride.

[0218] <Transistor 300> The transistor 300 will be described with reference to FIG. 14B. The transistor 300 is provided on a semiconductor substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the semiconductor substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0219] Here, in the transistor 300 shown in FIG. 14B, the semiconductor region 313 (a part of the semiconductor substrate 311) where a channel is formed has a convex shape. The side surface and the upper surface of the semiconductor region 313 can be provided to be covered with the conductor 316 via the insulator 315. Note that the conductor 316 may be made of a material for adjusting the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate 311, it is also called a FIN-type transistor. Note that an insulator that functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Here, the case where a part of the semiconductor substrate 311 is processed to form a convex portion is shown, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0220] Note that the transistor 300 shown in FIG. 14B is merely an example and is not limited to its structure. An appropriate transistor may be used according to the circuit configuration and the driving method.

[0221] <Memory device 420> Next, the memory device 420 shown in FIG. 13 will be described. Regarding the transistor 200M included in the memory device 420, descriptions overlapping with those of the transistor 200 will be omitted.

[0222] In the memory device 420, the conductor 242a of the transistor 200M functions as one of the electrodes of the capacitor element 292, and the insulators 272 and 273 function as dielectrics. The conductor 290 is provided so as to sandwich the insulators 272 and 273 therebetween and overlap with the conductor 242a, and functions as the other electrode of the capacitor element 292. The conductor 290 may be used as the other electrode of the capacitor element 292 of the adjacent memory device 420. Alternatively, the conductor 290 may be electrically connected to the conductor 290 of the adjacent memory device 420.

[0223] The conductor 290 sandwiches the insulators 272 and 273 therebetween and is also disposed on the upper surface and the side surface of the conductor 242a. At this time, the capacitor element 292 is preferable because a capacitance larger than the capacitance obtained by the area where the conductor 242a and the conductor 290 overlap is obtained.

[0224] The conductor 424 is electrically connected to the conductor 242b and is also electrically connected to the conductor 424 located in the lower layer via the conductor 205.

[0225] As the dielectric of the capacitor element 292, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. can be used. Also, these materials can be laminated and used. When the dielectric of the capacitor element 292 has a laminated structure, a laminate of aluminum oxide and silicon nitride or a laminate of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the lamination are not limited. For example, silicon nitride may be laminated on aluminum oxide, or aluminum oxide may be laminated on silicon nitride.

[0226] Alternatively, zirconium oxide having a dielectric constant higher than that of the above material may be used as the dielectric of the capacitor element 292. As the dielectric of the capacitor element 292, zirconium oxide may be used as a single layer or as part of a laminate. For example, a laminate of zirconium oxide and aluminum oxide can be used. Also, the dielectric of the capacitor element 292 may be a three-layer laminate, and zirconium oxide may be used for the first layer and the third layer, and aluminum oxide may be used for the second layer between the first layer and the third layer.

[0227] By using zirconium oxide having a high dielectric constant as the dielectric of the capacitor element 292, the area occupied by the capacitor element 292 in the memory device 420 can be reduced. Therefore, it is preferable that the area required for the memory device 420 can be reduced and the bit cost can be improved.

[0228] Also, as the conductor 290, a material that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, etc. can be used.

[0229] In the present embodiment, an example is shown in which the transistor 200M and the capacitor element 292 are symmetrically arranged with the conductor 424 sandwiched therebetween. By arranging the pair of transistor 200M and capacitor element 292 in this way, the number of conductors 424 electrically connected to the transistor 200M can be reduced. Therefore, it is preferable that the area required for the memory device 420 can be reduced and the bit cost can be improved.

[0230] When the insulator 241 is provided on the side surface of the conductor 424, the conductor 424 is connected to at least a part of the upper surface of the conductor 242b.

[0231] By using the conductor 424 and the conductor 205, the transistor 200T in the memory unit 470 and the memory device 420 can be electrically connected.

[0232] <Modification Example 1 of Memory Device 420> Next, with reference to FIG. 15B, as a modification of the memory device 420, a memory device 420A will be described. The memory device 420A includes a transistor 200M and a capacitive element 292A electrically connected to the transistor 200M. The capacitive element 292A is provided below the transistor 200M.

[0233] In the memory device 420A, the conductor 242a is disposed in an opening provided in the oxide 243a, the oxide 230b, the oxide 230a, the insulator 224, and the insulator 222, and is electrically connected to the conductor 205 at the bottom of the opening. The conductor 205 is electrically connected to the capacitive element 292A.

[0234] The capacitive element 292A includes a conductor 294 that functions as one of the electrodes, an insulator 295 that functions as a dielectric, and a conductor 297 that functions as the other of the electrodes. The conductor 297 sandwiches the insulator 295 therebetween and overlaps the conductor 294. Also, the conductor 297 is electrically connected to the conductor 205.

[0235] The conductor 294 is provided on the bottom and side surfaces of an opening formed in an insulator 298 provided on the insulator 296, and the insulator 295 is provided so as to cover the insulator 298 and the conductor 294. Also, the conductor 297 is provided so as to be embedded in a recess of the insulator 295.

[0236] Also, a conductor 299 is provided so as to be embedded in the insulator 296, and the conductor 299 is electrically connected to the conductor 294. The conductor 299 may be electrically connected to the conductor 294 of an adjacent memory device 420A.

[0237] The conductor 297 sandwiches the insulator 295 therebetween and is also disposed on the upper surface and the side surface of the conductor 294. At this time, the capacitive element 292A is preferable because a capacitance larger than the capacitance obtained by the area where the conductor 294 and the conductor 297 overlap is obtained.

[0238] As the insulator 295 that functions as the dielectric of the capacitive element 292A, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. can be used. Also, these materials can be used in a stacked manner. When the insulator 295 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack are not limited. For example, silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.

[0239] Further, as the insulator 295, zirconium oxide having a higher dielectric constant than the above materials may be used. As the insulator 295, zirconium oxide may be used as a single layer, or may be used as part of a stack. For example, a stack of zirconium oxide and aluminum oxide can be used. Also, the insulator 295 may be a three-layer stack, with zirconium oxide used for the first and third layers, and aluminum oxide used for the second layer between the first and third layers.

[0240] By using zirconium oxide having a high dielectric constant as the insulator 295, the area occupied by the capacitive element 292A in the memory device 420A can be reduced. Therefore, the area required for the memory device 420A can be reduced, and the bit cost can be improved, which is preferable.

[0241] Also, as the conductor 297, conductor 294, and conductor 299, materials that can be used for the conductor 205, conductor 242, conductor 260, conductor 424, etc. can be used.

[0242] Also, as the insulator 298, materials that can be used for the insulator 214, insulator 216, insulator 224, and insulator 280, etc. can be used.

[0243] <Modified Example 2 of Memory Device 420> Next, using FIG. 15C, a modified example of the memory device 420, i.e., the memory device 420B, will be described. The memory device 420B includes a transistor 200M and a capacitive element 292B electrically connected to the transistor 200M. The capacitive element 292B is provided above the transistor 200M.

[0244] The capacitive element 292B includes a conductor 276 that functions as one of the electrodes, an insulator 277 that functions as a dielectric, and a conductor 278 that functions as the other of the electrodes. The conductor 278 sandwiches the insulator 277 therebetween and overlaps with the conductor 276.

[0245] An insulator 275 is provided on the insulator 282, and the conductor 276 is provided at the bottom and on the side surfaces of the openings formed in the insulators 275, 282, 280, 273, and 272. The insulator 277 is provided so as to cover the insulator 282 and the conductor 276. Further, the conductor 278 is provided so as to overlap with the conductor 276 within the recess of the insulator 277, and at least a part thereof is provided on the insulator 275 via the insulator 277. The conductor 278 may be used as the other of the electrodes of the capacitive element 292B of an adjacent memory device 420B. Alternatively, the conductor 278 may be electrically connected to the conductor 278 of an adjacent memory device 420B.

[0246] The conductor 278 sandwiches the insulator 277 therebetween and is also disposed on the upper surface and the side surface of the conductor 276. At this time, the capacitive element 292B is preferable because a capacitance larger than the capacitance obtained by the area where the conductor 276 and the conductor 278 overlap is obtained.

[0247] Also, an insulator 279 may be provided so as to fill the recess of the conductor 278.

[0248] As the insulator 277 that functions as the dielectric of the capacitive element 292B, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. can be used. Also, these materials can be used in a stacked manner. When the insulator 277 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide can be used. Here, the top and bottom of the stack are not limited. For example, silicon nitride may be stacked on aluminum oxide, or aluminum oxide may be stacked on silicon nitride.

[0249] Further, as the insulator 277, zirconium oxide having a higher dielectric constant than the above materials may be used. As the insulator 277, zirconium oxide may be used as a single layer, or may be used as a part of the stack. For example, a stack of zirconium oxide and aluminum oxide can be used. Also, the insulator 277 may be a three-layer stack, and zirconium oxide may be used for the first layer and the third layer, and aluminum oxide may be used for the second layer between the first layer and the third layer.

[0250] By using zirconium oxide having a high dielectric constant as the insulator 277, the area occupied by the capacitive element 292B in the memory device 420B can be reduced. Therefore, the area required for the memory device 420B can be reduced, and the bit cost can be improved, which is preferable.

[0251] Also, as the conductor 276 and the conductor 278, materials that can be used for the conductor 205, the conductor 242, the conductor 260, the conductor 424, etc. can be used.

[0252] Also, as the insulator 275 and the insulator 279, materials that can be used for the insulator 214, the insulator 216, the insulator 224, the insulator 280, etc. can be used.

[0253] <Connection between the memory device 420 and the transistor 200T> In the region 422 surrounded by the dashed-dotted line in FIG. 13, the memory device 420 is electrically connected to the gate of the transistor 200T via a conductor 424 or the like, but the present embodiment is not limited to this.

[0254] FIG. 16 shows an example in which the memory device 420 is electrically connected to a conductor 242b that functions as one of the source and drain of the transistor 200T via a conductor 424, a conductor 205, a conductor 246b, and a conductor 240b.

[0255] In this way, the connection method between the memory device 420 and the transistor 200T can be determined according to the function of the circuit included in the transistor layer 413.

[0256] FIG. 17 shows an example in which the memory unit 470 includes a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0257] The memory device layers 415_1 to 415_4 each include a plurality of memory devices 420.

[0258] The memory device 420 is electrically connected to the memory devices 420 included in different memory device layers 415 and the transistor 200T included in the transistor layer 413 via a conductor 424 and a conductor 205.

[0259] The memory unit 470 is sealed by insulators 211, 212, 214, 287, 282, 283, and 284. An insulator 274 is provided around the insulator 284. A conductor 430 is provided on the insulators 274, 284, 283, and 211 and is electrically connected to the element layer 411.

[0260] In addition, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen by heating. Or, the insulator 280 has an excess oxygen region.

[0261] Note that the insulator 211, the insulator 283, and the insulator 284 are preferably made of a material having a high blocking property against hydrogen. Also, the insulator 214, the insulator 282, and the insulator 287 are preferably made of a material having a function of capturing or fixing hydrogen.

[0262] For example, examples of the material having a high blocking property against hydrogen include silicon nitride or silicon oxynitride. Also, examples of the material having a function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0263] In this specification, the barrier property means a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Or, it means a function of capturing and fixing the corresponding substance (also referred to as gettering).

[0264] Note that there is no particular limitation on the crystal structure of the materials used for the insulator 211, the insulator 212, the insulator 214, the insulator 287, the insulator 282, the insulator 283, and the insulator 284, but it may have an amorphous or crystalline structure. For example, it is preferable to use an amorphous aluminum oxide film as the material having a function of capturing or fixing hydrogen. Amorphous aluminum oxide may capture and fix a larger amount of hydrogen than highly crystalline aluminum oxide.

[0265] Here, the following model can be considered for the excess oxygen in the insulator 280 with respect to the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

[0266] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. In the diffusion of the hydrogen, excess oxygen in the insulator 280 reacts with the hydrogen in the oxide semiconductor to form an OH bond and diffuses through the insulator 280. When a hydrogen atom having an OH bond reaches a material (typically, the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom, etc.) in the insulator 282 and is captured or fixed in the insulator 282. On the other hand, it is presumed that the oxygen atom of the excess oxygen having an OH bond remains in the insulator 280 as excess oxygen. That is, in the diffusion of the hydrogen, it is highly probable that the excess oxygen in the insulator 280 plays a bridging role.

[0267] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important elements.

[0268] As an example, an insulator 280 having excess oxygen is formed on the oxide semiconductor, and then the insulator 282 is formed. After that, it is preferable to perform a heat treatment. Specifically, the heat treatment is performed at a temperature of 350 °C or higher, preferably 400 °C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen. The time of the heat treatment is 1 hour or longer, preferably 4 hours or longer, more preferably 8 hours or longer.

[0269] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280, the insulator 282, and the insulator 287. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0270] After the above heat treatment, the insulator 283 and the insulator 284 are formed. Since the insulator 283 and the insulator 284 are materials having a high hydrogen blocking function, it is possible to suppress the hydrogen diffused outward or the hydrogen existing outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0271] In addition, regarding the above heat treatment, although the configuration in which it is performed after forming the insulator 282 has been exemplified, it is not limited thereto. For example, after forming the transistor layer 413, or after forming the memory device layers 415_1 to 415_3, the above heat treatment may be performed respectively. Further, when hydrogen is diffused outward by the above heat treatment, hydrogen is diffused above or in the lateral direction of the transistor layer 413. Similarly, when heat treatment is performed after forming the memory device layers 415_1 to 415_3, hydrogen is diffused above or in the lateral direction.

[0272] In the above manufacturing process, the above-described sealing structure is formed by the adhesion of the insulator 211 and the insulator 283.

[0273] As described above, by adopting the above structure and the above manufacturing process, a semiconductor device using an oxide semiconductor with a reduced hydrogen concentration can be provided. Therefore, a semiconductor device with good reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided.

[0274] FIGS. 18A to 18C are diagrams showing an example in which the arrangement of the conductor 424 is different from that in FIG. 17. FIG. 18A shows a layout view when the memory device 420 is viewed from above, FIG. 18B is a cross-sectional view of the portion indicated by the alternate long and short dash line A1 - A2 in FIG. 18A, and FIG. 18C is a cross-sectional view of the portion indicated by the alternate long and short dash line B1 - B2 in FIG. 18A. In FIG. 18A, for ease of understanding of the figure, the illustration of the conductor 205 is omitted. When the conductor 205 is provided, the conductor 205 has a region overlapping with the conductor 260 and the conductor 424.

[0275] As shown in FIG. 18A, the opening where the conductor 424 is provided, that is, the conductor 424 is provided not only in the region overlapping with the oxide 230a and the oxide 230b, but also outside the oxide 230a and the oxide 230b. In FIG. 18A, an example is shown where the conductor 424 is provided so as to protrude to the B2 side of the oxide 230a and the oxide 230b, but the present embodiment is not limited to this. The conductor 424 may be provided so as to protrude to the B1 side of the oxide 230a and the oxide 230b, or may be provided so as to protrude to both the B1 side and the B2 side.

[0276] FIGS. 18B and 18C show an example in which the memory device layer 415_p is stacked on the memory device layer 415_p-1 (p is a natural number from 2 to n). The memory device 420 included in the memory device layer 415_p-1 is electrically connected to the memory device 420 included in the memory device layer 415_p via the conductor 424 and the conductor 205.

[0277] In FIG. 18B, an example is shown in which, in the memory device layer 415_p-1, the conductor 424 is connected to the conductor 242 of the memory device layer 415_p-1 and the conductor 205 of the memory device layer 415_p. Here, the conductor 424 is also connected to the conductor 205 of the memory device layer 415_p-1 outside the B2 side of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a.

[0278] In FIG. 18C, it can be seen that the conductor 424 is formed along the side surfaces on the B2 side of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a, and is electrically connected to the conductor 205 through openings formed in the insulator 280, the insulator 273, the insulator 272, the insulator 224, and the insulator 222. Here, an example in which the conductor 424 is provided along the side surfaces on the B2 side of the conductor 242, the oxide 243, the oxide 230b, and the oxide 230a is shown by a dotted line in FIG. 18B. Also, an insulator 241 may be formed between the side surfaces on the B2 side of the conductor 242, the oxide 243, the oxide 230b, the oxide 230a, the insulator 224, and the insulator 222 and the conductor 424.

[0279] By providing the conductor 424 also in a region that does not overlap with the conductor 242 or the like, the memory device 420 can be electrically connected to memory devices 420 provided in different memory device layers 415. Also, the memory device 420 can be electrically connected to the transistor 200T provided in the transistor layer 413.

[0280] Also, when the conductor 424 is used as a bit line, by providing the conductor 424 also in a region that does not overlap with the conductor 242 or the like, the distance between the bit lines of the memory devices 420 adjacent in the B1 - B2 direction can be increased. As shown in FIG. 18A, the distance between the conductors 424 on the conductor 242 is d1, but the distance between the conductors 424 located in the lower layer than the oxide 230a, that is, within the openings formed in the insulator 224 and the insulator 222 is d2, and d2 is larger than d1. By making some of the distances d2 compared to the case where the distance between the conductors 424 adjacent in the B1 - B2 direction is d1, the parasitic capacitance of the conductor 424 can be reduced. Reducing the parasitic capacitance of the conductor 424 is preferable because the capacitance required for the capacitive element 292 can be reduced.

[0281] In the memory device 420, a conductor 424 that functions as a common bit line for two memory cells is provided. By appropriately adjusting the dielectric constant of the dielectric used for the capacitance and the parasitic capacitance between the bit lines, the cell size of each memory cell can be reduced. Here, an estimate of the cell size of the memory cell, an estimate of the bit density, and an estimate of the bit cost when the channel length is 30 nm (also referred to as the 30 nm node) will be described. In FIGS. 19A to 19D described below, for ease of understanding of the drawings, the illustration of the conductor 205 is omitted. When the conductor 205 is provided, the conductor 205 has a region that overlaps with the conductor 260 and the conductor 424.

[0282] FIG. 19A shows an example in which hafnium oxide with a thickness of 10 nm and silicon oxide with a thickness of 1 nm are sequentially stacked as the dielectric of the capacitance, a slit is provided between the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b of each memory cell included in the memory device 420, and a conductor 424 that functions as a bit line is provided so as to overlap with the conductor 242 and the slit. The memory cell 432 thus obtained is referred to as cell A.

[0283] The cell size in cell A is 45.25F 2 is.

[0284] FIG. 19B shows an example in which first zirconium oxide, aluminum oxide thereon, and second zirconium oxide are sequentially stacked as the dielectric of the capacitance, a slit is provided between the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b of each memory cell included in the memory device 420, and a conductor 424 that functions as a bit line is provided so as to overlap with the conductor 242 and the slit. The memory cell 433 thus obtained is referred to as cell B.

[0285] Since cell B has a higher dielectric constant of the dielectric used for the capacitance compared to cell A, the area of the capacitance can be reduced. Therefore, in cell B, the cell size can be reduced compared to cell A. The cell size in cell B is 25.53F 2It is.

[0286] Cell A and cell B correspond to the memory cells included in the memory device 420, the memory device 420A, or the memory device 420B shown in FIGS. 13, 15A to 15C, and 16.

[0287] FIG. 19C shows an example in which, as a dielectric of a capacitor, a first zirconium oxide, an aluminum oxide thereon, and a second zirconium oxide thereon are laminated, and a conductor 242, an oxide 243, an oxide 230a, and an oxide 230b included in the memory device 420 are shared by each memory cell, and a conductor 424 functioning as a bit line is provided so as to overlap a part that overlaps the conductor 242 and a part outside the conductor 242. The memory cell 434 thus obtained is referred to as cell C.

[0288] The interval between the conductors 424 in cell C becomes wider in the lower layer than the oxide 230a compared with above the conductor 242. Therefore, the parasitic capacitance of the conductor 424 can be reduced, and the area of the capacitor can be reduced. Further, no slit is provided in the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b. From the above, in cell C, the cell size can be reduced compared with cell A and cell B. The cell size in cell C is 17.20F 2 It is.

[0289] FIG. 19D shows an example in which the conductor 205 and the insulator 216 are not provided in cell C. Such a memory cell 435 is referred to as cell D.

[0290] By not providing the conductor 205 and the insulator 216 in cell D, the memory device 420 can be made thinner. Therefore, the memory device layer 415 having the memory device 420 can be made thinner, and the height of the memory unit 470 in which a plurality of memory device layers 415 are stacked can be reduced. When the conductor 424 and the conductor 205 are regarded as bit lines, the bit lines can be shortened within the memory unit 470. Since the bit lines can be shortened, the parasitic load of the bit lines is reduced, the parasitic capacitance of the conductor 424 can be further reduced, and the area of the capacitance can be reduced. Also, no slits are provided in the conductor 242, the oxide 243, the oxide 230a, and the oxide 230b. As described above, in cell D, the cell size can be reduced as compared with cells A, B, and C. The cell size in cell D is 15.12F 2 is.

[0291] Cells C and D correspond to the memory cells included in the memory device 420 shown in FIGS. 18A to 18C.

[0292] Here, the bit density and the bit cost C b were estimated for cells A to D and cell E in which multi-valuing was performed in cell D. Also, the obtained estimates were compared with the predicted values of the bit density and the bit cost in currently commercially available DRAMs.

[0293] The bit cost C in the semiconductor device according to one aspect of the present invention b was estimated using Equation 1.

[0294]

Equation

[0295] Here, n is the number of stacked memory device layers, P c is mainly the number of patterning times of the element layer 411 as a common part, P s is the number of patterning times per layer of the memory device layer 415 and the transistor layer 413, D dis the bit density of the DRAM, D 3d is the bit density of one layer of the memory device layer 415, P d indicates the number of patterning times of the DRAM. However, P d includes the increase due to scaling.

[0296] Table 1 shows the predicted values of the bit density of commercially available DRAMs and the estimated bit density of the semiconductor device of one aspect of the present invention. Note that the commercially available DRAMs are of two types with process nodes of 18 nm and 1X nm. Also, the process node of the semiconductor device of one aspect of the present invention is assumed to be 30 nm, and the bit density was estimated with the number of stacked layers of the memory device layer in cells A to E being 5 layers, 10 layers, and 20 layers.

[0297] [Table 1]

[0298] Table 2 shows the results of estimating the relative bit cost of the semiconductor device of one aspect of the present invention from the bit cost of commercially available DRAMs. Note that for the comparison of bit costs, a DRAM with a process node of 1X nm was used. Also, the process node of the semiconductor device of one aspect of the present invention is assumed to be 30 nm, and the relative bit cost was estimated with the number of stacked layers of the memory device layer in cells A to D being 5 layers, 10 layers, and 20 layers.

[0299] [Table 2]

[0300] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0301] (Embodiment 3) In this embodiment, the configurations of CAC-OS (Cloud-Aligned Composite Oxide Semiconductor), which is a metal oxide that can be used for the OS transistor described in the above embodiment, and CAAC-OS (c-axis Aligned Crystal Oxide Semiconductor) will be described.

[0302] <Configuration of Metal Oxide> CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) serving as carriers, and the insulating function is the function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be maximally enhanced.

[0303] Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0304] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0305] In addition, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide bandgap due to an insulating region and a component having a narrow bandgap due to a conductive region. In such a configuration, when carriers flow, carriers mainly flow in the component having a narrow bandgap. Further, the component having a narrow bandgap acts complementarily to the component having a wide bandgap, and carriers also flow in the component having a wide bandgap in conjunction with the component having a narrow bandgap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0306] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0307] <Structure of Metal Oxide> Oxide semiconductors can be divided into single-crystalline oxide semiconductors and other non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0308] In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from the above. Here, the classification of the crystal structure in oxide semiconductors will be described with reference to FIG. 20A. FIG. 20A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

[0309] As shown in FIG. 20A, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. In addition, completely amorphous is included in Amorphous. In addition, CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) are included in Crystalline. In addition, single crystal and poly crystal are included in Crystal.

[0310] Note that the structure within the thick frame shown in FIG. 20A belongs to the New crystalline phase. This structure is in the boundary region between Amorphous and Crystal. That is, it can be said that it has a completely different structure from the energetically unstable Amorphous and Crystalline.

[0311] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) image. Here, the XRD spectra of quartz glass and IGZO having a crystal structure classified as Crystalline (also referred to as crystalline IGZO) are shown in FIGS. 20B and 20C. FIG. 20B shows the XRD spectrum of quartz glass, and FIG. 20C shows the XRD spectrum of crystalline IGZO. Note that the crystalline IGZO shown in FIG. 20C has a composition of In:Ga:Zn = 4:2:3 [atomic ratio]. In addition, the crystalline IGZO shown in FIG. 20C has a thickness of 500 nm.

[0312] As shown by the arrow in FIG. 20B, the quartz glass has substantially symmetric peaks in the XRD spectrum. On the other hand, as shown by the arrow in FIG. 20C, the crystalline IGZO has asymmetric peaks in the XRD spectrum. The asymmetry of the peaks in the XRD spectrum indicates the presence of crystals. In other words, if the peaks in the XRD spectrum are not symmetric, it cannot be said to be amorphous.

[0313] CAAC-OS has a c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction, resulting in a crystal structure with strain. Note that the strain refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

[0314] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons. Note that in CAAC-OS, even in the vicinity of the strain, a clear grain boundary (also called a grain boundary) cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements. Note that a crystal structure in which a clear grain boundary (grain boundary) is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of the transistor or a decrease in the field-effect mobility due to carrier capture. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. Note that to form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0315] In addition, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable, and when element M in the (M,Zn) layer is substituted with indium, it can also be expressed as an (In,M,Zn) layer. Further, when indium in the In layer is substituted with element M, it can also be expressed as an (In,M) layer.

[0316] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, since distinct grain boundaries cannot be confirmed in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiency). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Further, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0317] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Accordingly, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0318] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0319] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0320] <Transistor having an oxide semiconductor> Subsequently, the case where the above oxide semiconductor is used for a transistor will be described.

[0321] By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0322] Also, for a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered and the density of defect levels may be lowered. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0323] Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density because the density of defect levels is low.

[0324] Also, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0325] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Also, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0326] <Impurities> Here, the effects of various impurities in the oxide semiconductor will be described.

[0327] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Hereinafter, preferably 2×10 17 atoms / cm 3 or less.

[0328] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0329] In addition, when nitrogen is contained in the oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 19 atoms / cm 3 in SIMS, preferably less than 5×10 18 atoms / cm 3Hereinafter, more preferably 1×10 18 atoms / cm 3 Hereinafter, even more preferably 5×10 17 atoms / cm 3 or less.

[0330] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less, preferably less than 1×10 19 atoms / cm 3 less, more preferably less than 5×10 18 atoms / cm 3 less, even more preferably less than 1×10 18 atoms / cm 3 or less.

[0331] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0332] Note that this embodiment can be combined with other embodiments shown in this specification as appropriate.

[0333] (Embodiment 4) In this embodiment, the control logic circuit 61, the row driving circuit 62, the column driving circuit 63, and the output circuit 64 provided on the silicon substrate 60 in the semiconductor device 10 described in Embodiment 1 will be described.

[0334] FIG. 21 is a block diagram showing a configuration example of a semiconductor device that functions as a memory device. The semiconductor device 10E has a peripheral circuit 80 and a memory cell array 70. The peripheral circuit 80 has a control logic circuit 61, a row drive circuit 62, a column drive circuit 63, and an output circuit 64.

[0335] The memory cell array 70 has a plurality of memory cells 33. The row drive circuit 62 has a row decoder 71 and a word line driver circuit 72. The column drive circuit 63 has a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84. The precharge circuit 82 has a function of precharging global bit lines GBL or local bit lines LBL or the like. The amplifier circuit 83 has a function of amplifying a data signal read from the global bit line GBL or the local bit line LBL. The amplified data signal is output to the outside of the semiconductor device 10E as a digital data signal RDATA via the output circuit 64.

[0336] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 80, and a high power supply voltage (VIL) for the memory cell array 70 are supplied to the semiconductor device 10E from the outside.

[0337] In addition, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the semiconductor device 10E from the outside. The address signal ADDR is input to the row decoder 71 and the column decoder 81, and the WDATA is input to the write circuit 84.

[0338] The control logic circuit 61 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 71 and the column decoder 81. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 61 are not limited to these, and other control signals may be input as necessary. For example, a control signal for determining defective bits may be input, and a data signal read from the address of a specific memory cell may be specified as a defective bit.

[0339] Note that each of the above circuits or signals can be appropriately selected or discarded as necessary.

[0340] Generally, in semiconductor devices such as computers, various storage devices (memories) are used according to the application. Fig. 22 shows various storage devices by layer. The storage devices located in the upper layer are required to have a faster access speed, and the storage devices located in the lower layer are required to have a larger storage capacity and a higher recording density. In Fig. 22, from the top layer in order, it shows the memory mounted as a register in an arithmetic processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0341] The memory mounted as a register in an arithmetic processing unit such as a CPU is used for temporarily storing arithmetic results, etc., so the access frequency from the arithmetic processing unit is high. Therefore, a faster operating speed is required rather than a large storage capacity. Also, the register has a function of holding setting information of the arithmetic processing unit, etc.

[0342] SRAM is used, for example, in a cache. The cache has a function of replicating and holding a part of the information held in the main memory. By replicating frequently used data in the cache, the access speed to the data can be increased.

[0343] DRAM is used, for example, as main memory. Main memory has a function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0344] 3D NAND memory is used, for example, as storage. Storage has a function of holding data that requires long-term storage, various programs used in an arithmetic processing unit, and the like. Therefore, storage is required to have a storage capacity larger than the operating speed and a high recording density. The recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0345] The semiconductor device functioning as a storage device according to one aspect of the present invention has a high operating speed and can hold data for a long period of time. The semiconductor device according to one aspect of the present invention can be suitably used as a semiconductor device located in a boundary region 901 including both the layer where the cache is located and the layer where the main memory is located. Further, the semiconductor device according to one aspect of the present invention can be suitably used as a semiconductor device located in a boundary region 902 including both the layer where the main memory is located and the layer where the storage is located.

[0346] (Embodiment 5) This embodiment shows an example of an electronic component and an electronic device in which the semiconductor device and the like shown in the above embodiment are incorporated.

[0347] <Electronic component> First, an example of an electronic component in which the semiconductor device 10 and the like are incorporated will be described with reference to FIGS. 23A and 23B.

[0348] Fig. 23A shows a perspective view of the electronic component 700 and the substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Fig. 23A has a semiconductor device 10 in which an element layer 50 is laminated on a silicon substrate 60 within a mold 711. Fig. 23A does not show a part of the electronic component 700 in order to show the inside thereof. The electronic component 700 has lands 712 outside the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 10 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0349] Fig. 23B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 10 are provided on the interposer 731.

[0350] In the electronic component 730, an example is shown in which the semiconductor device 10 is used as a high bandwidth memory (HBM). Also, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

[0351] As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.

[0352] The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Further, the interposer 731 has a function of electrically connecting an integrated circuit provided on the interposer 731 to an electrode provided on the package substrate 732. For these reasons, the interposer may be referred to as a "rewiring substrate" or an "intermediate substrate". In addition, a through electrode may be provided on the interposer 731, and the integrated circuit and the package substrate 732 may be electrically connected using the through electrode. Also, in a silicon interposer, a TSV (Through Silicon Via) can be used as the through electrode.

[0353] It is preferable to use a silicon interposer as the interposer 731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult in a resin interposer.

[0354] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, fine and high-density wiring formation is required for the interposer on which HBM is mounted. Therefore, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0355] Also, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer hardly occurs. Further, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0356] Further, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 730. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in the present embodiment, it is preferable to align the heights of the semiconductor device 10 and the semiconductor device 735.

[0357] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. FIG. 23B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix pattern at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Further, the electrodes 733 may be formed of conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0358] The electronic component 730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0359] <Electronic device> Next, an example of an electronic device including the above-described electronic component will be described with reference to FIG. 24.

[0360] The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezo sensor, optical sensor, gyro sensor, etc.), and a moving mechanism. The electronic component 730 has a processor or the like and has a function of controlling these peripheral devices. For example, the electronic component 700 has a function of storing data acquired by the sensor.

[0361] The microphone has a function of detecting acoustic signals such as the user's voice and environmental sound. Also, the speaker has a function of emitting audio signals such as voice and warning sound. The robot 7100 can analyze the audio signal input via the microphone and emit the necessary audio signal from the speaker. The robot 7100 can communicate with the user using the microphone and the speaker.

[0362] The camera has a function of imaging the surroundings of the robot 7100. Also, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can image the surrounding images using the camera and analyze the images to detect the presence or absence of obstacles when moving.

[0363] The flying object 7120 has a propeller, a camera, a battery, etc., and has a function of flying autonomously. The electronic component 730 has a function of controlling these peripheral devices.

[0364] For example, the image data captured by the camera is stored in the electronic component 700. The electronic component 730 can analyze the image data and detect the presence or absence of obstacles when moving. Also, the remaining battery level can be estimated from the change in the battery's charge capacity by the electronic component 730.

[0365] The cleaning robot 7140 has a display disposed on the upper surface, a plurality of cameras disposed on the side surface, a brush, operation buttons, various sensors, etc. Although not shown, the cleaning robot 7300 is provided with tires, a suction port, etc. The cleaning robot 7300 can move automatically, detect dust, and suck dust from the suction port provided on the lower surface.

[0366] For example, the electronic component 730 can analyze the image captured by the camera and determine the presence or absence of obstacles such as walls, furniture, or steps. Also, when an object that is likely to get caught in the brush, such as wiring, is detected by image analysis, the rotation of the brush can be stopped.

[0367] Automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. For example, based on data such as navigation information, speed, engine state, gear selection state, and brake usage frequency, electronic component 730 performs control to optimize the driving state of automobile 7160. For example, the image data captured by the camera is stored in electronic component 700.

[0368] Electronic component 700 and / or electronic component 730 can be incorporated into a TV device 7200 (television receiver), smartphone 7210, PC (personal computer) 7220, 7230, game console 7240, game console 7260, etc.

[0369] For example, the electronic component 730 incorporated in the TV device 7200 can function as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

[0370] Smartphone 7210 is an example of a mobile information terminal. Smartphone 7210 has a microphone, a camera, a speaker, various sensors, and a display unit. These peripheral devices are controlled by electronic component 730.

[0371] PCs 7220 and 7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to PC 7230 wirelessly or by wire. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a desktop game console. A controller 7262 is connected to game console 7260 wirelessly or by wire. Electronic component 700 and / or electronic component 730 can also be incorporated into controller 7262.

[0372] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0373] (Supplementary Note Regarding the Description in this Specification, etc.) Regarding the above embodiments and the description of each configuration in the embodiments, the following supplementary notes are provided.

[0374] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples to form an aspect of the present invention. Also, when multiple configuration examples are shown within one embodiment, it is possible to appropriately combine the configuration examples.

[0375] Note that the content described in one embodiment (even a part of the content) can be applied, combined, or replaced with respect to the content described in another part of the same embodiment (even a part of the content) and / or the content described in one or more other embodiments (even a part of the content).

[0376] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0377] Note that the figure (even a part of it) described in one embodiment can be combined with another part of the figure, another figure (even a part of it) described in the same embodiment, and / or the figure (even a part of it) described in one or more other embodiments to form even more figures.

[0378] Also, in this specification and the like, in the block diagram, the components are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate the components by function, and there may be cases where a single circuit is involved in multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0379] In the drawings, the size, layer thickness, or area is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. The drawings are schematically shown for clarity and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0380] Also, in the drawings and the like, the positional relationship of the components shown is relative. Therefore, when explaining the components with reference to the drawings, terms such as "above" and "below" indicating the positional relationship may be used for convenience. The positional relationship of the components is not limited to the description in this specification and can be appropriately rephrased according to the situation.

[0381] In this specification and the like, when explaining the connection relationship of a transistor, the notations "one of the source or drain" (or the first electrode, or the first terminal) and "the other of the source or drain" (or the second electrode, or the second terminal) are used. This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Regarding the names of the source and drain of a transistor, they can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode.

[0382] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0383] In addition, in this specification and the like, voltage and potential can be appropriately rephrased. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground voltage (earthing voltage), the voltage can be rephrased as potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to wiring or the like may change.

[0384] In this specification and the like, a node can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. according to the circuit configuration, device structure, etc. Also, it is possible to rephrase a terminal, wiring, etc. as a node.

[0385] In this specification and the like, "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection where electrical signal transmission between A and B is possible when an object (such as a switch, transistor element, or diode, or a circuit including the element and wiring) exists between A and B. Note that when A and B are electrically connected, it includes the case where A and B are directly connected. Here, "A and B are directly connected" means a connection where electrical signal transmission between A and B is possible via wiring (or an electrode) etc. without passing through the above object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0386] In this specification and the like, a switch is something that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether current flows or not. Or, a switch is something that has a function of selecting and switching the path through which current flows.

[0387] In this specification and the like, the channel length refers to, for example, in the top view of a transistor, the distance between the source and the drain in the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate overlap, or in the region where the channel is formed.

[0388] In this specification and the like, the channel width refers to, for example, the length of the portion where the source and the drain face each other in the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or in the region where the channel is formed.

[0389] Note that in this specification and the like, terms such as "film" and "layer" can be interchanged with each other depending on the case or the situation. For example, the term "conductive layer" may be changed to the term "conductive film" in some cases. Or, for example, the term "insulating film" may be changed to the term "insulating layer" in some cases.

Description of Reference Numerals

[0390] 10: Semiconductor device, 10A: Semiconductor device, 10B: Semiconductor device, 10C: Semiconductor device, 10E: Semiconductor device, 20: Transistor layer, 21: Switching circuit, 21_A: Switching circuit, 21_B: Switching circuit, 21_1: Transistor, 21_2: Transistor, 21_4: Transistor, 22: Amplification circuit, 22_A: Amplification circuit, 22_B: Amplification circuit, 22_1: Transistor, 22_2: Transistor, 22_3: Transistor, 22_4: Transistor, 23_1: Transistor, 23_4: Transistor, 24_1: Transistor, 24_3: Transistor, 25_1: Transistor, 25_4: Transistor, 26_1: Transistor, 26_3: Transistor, 27A: Switch, 27B: Switch, 27C: Switch, 27D: Switch, 30: Transistor layer, 31_k: Transistor layer, 31_1: Transistor layer, 31_2: Transistor layer, 32: Transistor layer, 32_k: Transistor layer, 32_1: Transistor layer, 32_2: Transistor layer, 33: Memory cell, 34: Transistor, 35: Capacitor, 40: Transistor layer, 41: Memory cell, 41A: Transistor layer, 41B: Transistor layer, 42: Transistor, 43: Transistor, 44: Capacitor, 50: Element layer, 50_M: Element layer, 50_1: Element layer, 60: Silicon substrate, 61: Control logic circuit, 62: Row drive circuit, 62_A: Precharge circuit, 62_B: Precharge circuit, 62_C: Sense amplifier, 62_D: Switching circuit, 62_E: Switching circuit, 63: Column drive circuit, 64: Output circuit, 65_1: Transistor, 65_3: Transistor, 65_4: Transistor, 65_6: Transistor, 66_A: Switch, 67_1: Transistor, 67_2: Transistor, 67_3: Transistor, 67_4: Transistor, 68_C: Switch, 69: Circuit, 70: Memory cell array, 71: Row decoder, 72: Word line driver circuit, 80: Peripheral circuit, 81: Column decoder, 82: Precharge circuit, 83: Amplification circuit, 84: Circuit, 200: Transistor, 200M: Transistor, 200T: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 211: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide,230a: Oxide, 230b: Oxide, 230c: Oxide, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor, 243: Oxide, 243a: Oxide, 243b: Oxide, 246: Conductor, 246a: Conductor, 246b: Conductor, 250: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 272: Insulator, 273: Insulator, 274: Insulator, 275: Insulator, 276: Conductor, 277: Insulator, 278: Conductor, 279: Insulator, 280: Insulator, 282: Insulator, 283: Insulator, 284: Insulator, 287: Insulator, 290: Conductor, 292: Capacitor element, 292A: Capacitor element, 292B: Capacitor element, 294: Conductor, 295: Insulator, 296: Insulator, 297: Conductor, 298: Insulator, 299: Conductor, 300: Transistor, 311: Semiconductor substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 411: Element layer, 413: Transistor layer, 413_m: Transistor layer, 413_1: Transistor layer, 415: Memory device layer, 415_n: Memory device layer, 415_p: Memory device layer, 415_p-1: Memory device layer, 415_1: Memory device layer, 415_3: Memory device layer, 415_4: Memory device layer, 420: Memory device, 420A: Memory device, 420B: Memory device, 422: Region, 424: Conductor, 426: Conductor, 428: Conductor, 430: Conductor, 432: Memory cell, 433: Memory cell, 434: Memory cell, 435: Memory cell, 470: Memory unit, 470_m: Memory unit, 470_1: Memory unit, 700: Electronic component, 702: Printed circuit board, 704: Mounting substrate, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 901: Boundary region, 902: Boundary region, 7100: Robot, 7120: Aircraft, 7140: Cleaning robot, 7160: Automobile, 7200: TV device, 7210: Smartphone, 7220: PC, 7230: PC, 7232: Keyboard, 7233: Monitor device,7240: Game console, 7260: Game console, 7262: Controller, 7300: Cleaning robot,

Claims

1. A semiconductor device having a first transistor layer, a second transistor layer having a region located above the first transistor layer, and a third transistor layer having a region located above the second transistor layer, wherein the first transistor layer has a first memory cell and a second memory cell, the second transistor layer has a switching circuit and an amplification circuit, the third transistor layer has a third memory cell and a fourth memory cell, the first memory cell is always electrically connected to the switching circuit via a first local bit line, the second memory cell is always electrically connected to the switching circuit via a second local bit line, the third memory cell is always electrically connected to the switching circuit via a third local bit line, the fourth memory cell is always electrically connected to the switching circuit via a fourth local bit line, the switching circuit is always electrically connected to the amplification circuit, the amplification circuit is always electrically connected to a global bit line, and the switching circuit has a function of selecting the first local bit line, the second local bit line, the third local bit line, and the fourth local bit line.

2. A semiconductor device having a first transistor layer, a second transistor layer having a region located above the first transistor layer, and a third transistor layer having a region located above the second transistor layer, wherein the first transistor layer has a first memory cell and a second memory cell, the second transistor layer has a switching circuit and an amplification circuit, the third transistor layer has a third memory cell and a fourth memory cell, the first memory cell is always electrically connected to the switching circuit via a first local bit line, the second memory cell is always electrically connected to the switching circuit via a second local bit line, the third memory cell is always electrically connected to the switching circuit via a third local bit line, the fourth memory cell is always electrically connected to the switching circuit via a fourth local bit line, the switching circuit is always electrically connected to the amplification circuit, the amplification circuit is always electrically connected to a global bit line, and the switching circuit has a function of selecting the first local bit line, the second local bit line, the third local bit line, and the fourth local bit line. At least one of the first to fourth memory cells has a transistor having an oxide semiconductor in a channel formation region. The oxide semiconductor is an indium oxide semiconductor device.

3. A semiconductor device having a first transistor layer, a second transistor layer having a region located above the first transistor layer, and a third transistor layer having a region located above the second transistor layer. The first transistor layer has a first memory cell and a second memory cell. The second transistor layer has a switching circuit and an amplifying circuit. The third transistor layer has a third memory cell and a fourth memory cell. The first memory cell is always in conduction with the switching circuit via a first local bit line. The second memory cell is always in conduction with the switching circuit via a second local bit line. The third memory cell is always in conduction with the switching circuit via a third local bit line. The fourth memory cell is always in conduction with the switching circuit via a fourth local bit line. The switching circuit is always in conduction with the amplifying circuit. The amplifying circuit is always in conduction with a global bit line. The switching circuit has a function of selecting the first local bit line, the second local bit line, the third local bit line, and the fourth local bit line. At least one of the first to fourth memory cells has a transistor having an oxide semiconductor in a channel formation region.

4. In claim 2, The oxide semiconductor is an In-Zn oxide semiconductor device.

5. In any one of claims 1 to 4, Having a drive circuit, The drive circuit is always in conduction with the global bit line.

Images