Semiconductor device

Abstract

To provide a semiconductor device having a large storage capacity.SOLUTION: A semiconductor device includes first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. An opening is provided collectively for a structure in which the first insulator, the first conductor, the second insulator, the second conductor and the third insulator are stacked in the order. Further, the second conductor is selectively removed by etching in the opening. Then, the fourth insulator is formed on a side face of the opening, and the third conductor is formed in a region where the second conductor is removed. The first semiconductor, the fifth insulator and the second semiconductor are formed in order in the remaining opening to form a semiconductor device having a three-dimensional structure. A material containing a metal oxide may be applied for the first semiconductor, and a material containing a metal oxide or silicon may be applied for the second semiconductor.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an object, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the present invention relates to a technique according to one embodiment of the present invention disclosed in the present specification. Fields of application include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, processor, electronic device, driving method thereof, manufacturing method thereof, and inspection method thereof One example is a method or a system comprising at least one of them. [Background technology]

[0003] In recent years, various electronic devices such as personal computers, smartphones, and digital cameras have become The device has a central processing unit (CPU), a graphics processing unit, Electronic components such as LEDs, memory devices, and sensors are used in these devices. Improvements are being made in various areas, including reducing power consumption.

[0004] In particular, the amount of data handled by the electronic devices mentioned above has been increasing in recent years. There is a demand for storage devices with large storage capacities. This paper discloses a semiconductor device that enables writing and reading of large amounts of data. To realize a memory device with a large memory capacity, technology is required to miniaturize the circuits of the memory device. It is being done.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide a storage device having a novel semiconductor device. Or, one aspect of the present invention aims to provide an electronic device using a storage device having a novel semiconductor device. Or, one aspect of the present invention aims to provide a storage device with a large data capacity. Or, one aspect of the present invention aims to provide a highly reliable storage device. It should be noted that the problems of one aspect of the present invention are not limited to the above-listed problems. The above-listed problems do not prevent the existence of other problems. Other problems are those not mentioned in this section as described below. Problems not mentioned in this section can be derived by those skilled in the art from the descriptions in the specification or the drawings, etc., and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not necessarily solve all of the above-listed problems and other problems.

Means for Solving the Problems

[0007] ​​​​​​​​​​

[0008] (1) One aspect of the present invention is a semiconductor device having first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. The first conductor is provided on the upper surface of the first insulator, and the second insulator is provided on the upper surface of the first conductor. The second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided on the first lower surface of the third insulator. The fourth insulator is provided so as to be continuous with a region including the side surface of the first insulator, the side surface of the first conductor, the side surface of the second insulator, the second upper surface of the second insulator, the side surface of the second conductor, the second lower surface of the third insulator, and the side surface of the third insulator. The third conductor is provided in a region overlapping the side surface of the second conductor among the region where the fourth insulator is formed. The first semiconductor is provided on the formation surface of the third conductor and in regions overlapping the side surface of the first insulator, the side surface of the second conductor, the side surface of the second insulator, and the side surface of the third insulator among the region where the fourth insulator is formed. The fifth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is provided on the formation surface of the fifth insulator. It is a semiconductor device characterized by this.

[0009] (2) Alternatively, one aspect of the present invention is a semiconductor device having first to fifth insulators, first to third conductors, and first to third semiconductors. The first conductor is provided on the first upper surface of the first insulator, and the first conductor is provided on the first lower surface of the second insulator. The second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided on the first lower surface of the third insulator. The third semiconductor is provided in a region including the second upper surface of the first insulator, the side surface of the first conductor, and the second lower surface of the second insulator. The fourth insulator is provided on the side surface of the first insulator, the formation surface of the first semiconductor, the side surface of the second insulator, and the second upper surface of the second insulator.​​​​ A region including a surface, a side surface of a second conductor, a second lower surface of a third insulator, and a side surface of the third insulator is provided so as to be continuous. The third conductor is provided in a region where the second conductor is superimposed on the side surface of the second conductor. The first semiconductor is provided in a region where the formation surface of the third conductor is superimposed on the side surface of the first insulator, the formation surface of the third semiconductor, the side surface of the second insulator, and the third insulator in a region where the second insulator is superimposed. The fifth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is provided on the formation surface of the fifth insulator in a semiconductor device characterized by this.

[0010] (3) Alternatively, one aspect of the present invention is a semiconductor device having first to fourth insulators, first to fourth conductors, a first semiconductor and a second semiconductor. The first insulator is provided on the first upper surface of the first conductor, the second conductor is provided on the first upper surface of the first insulator, the second insulator is provided on the first lower surface of the third conductor, the second conductor is provided on the first lower surface of the second insulator, the third insulator is provided on the side surface of the first conductor, the second upper surface of the first conductor, the side surface of the first insulator, the second upper surface of the first insulator, the side surface of the second conductor, the second lower surface of the second insulator, the side surface of the second insulator, the second lower surface of the third conductor and the side surface of the third conductor so as to be continuous. The fourth conductor is provided in a region where the third insulator is formed and is superimposed on the side surface of the first insulator, the side surface of the second conductor, and the side surface of the second insulator. The first semiconductor is provided in a region where the formation surface of the fourth conductor is superimposed on the first conductor and the third conductor in a region where the third insulator is formed. The fourth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is provided on the fourth insulator. The fourth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is provided on the fourth insulator. The fourth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is provided on the fourth ​A semiconductor device characterized by having a formation surface of an insulator.

[0011] (4) Or, one aspect of the present invention is, in the above (1) to (3), a sixth insulator and a fifth conductor and the sixth insulator has a formation surface of the second semiconductor, and the fourth conductor has a formation surface of the sixth insulator. A semiconductor device characterized by having a formation surface. A semiconductor device characterized by having a formation surface of an insulator.

[0012] (5) Or, one aspect of the present invention is, in the above (1) to (4), the first semiconductor is a metal oxide A semiconductor device characterized by having a semiconductor device.

[0013] (6) Or, one aspect of the present invention is, in the above (1) to (5), the second semiconductor is a metal oxide A semiconductor device characterized by having a semiconductor device.

[0014] (7) Or, one aspect of the present invention is, in the above (1) to (5), the second semiconductor is silicon A semiconductor device characterized by having a semiconductor device.

[0015] (8) Or, one aspect of the present invention is a storage device having the semiconductor device described in the above (1) to (7) and a peripheral circuit And a storage device having the same.

[0016] (9) Or, one aspect of the present invention is an electronic device having the storage device described in the above (8) and a housing Is.

Advantages of the Invention

[0017] According to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to one aspect of the present invention, a storage device having a novel semiconductor device can be provided. Or, this According to one aspect, a storage device having a novel semiconductor device can be provided. Or, this According to one aspect of the invention, an electronic device using a memory device having a novel semiconductor device can be provided. Alternatively, according to one aspect of the invention, a memory device with a large data capacity can be provided. Alternatively, according to one aspect of the invention, a highly reliable memory device can be provided.

[0018] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are those effects not mentioned in this item described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or the drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above.

Brief Description of the Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. The metal oxide is an oxide insulator, an oxide conductor (including a transparent oxide conductor). ) Oxide Semiconductor (also simply referred to as OS) It is classified into etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplification action, a rectification action , and a switching action and can form a channel formation region of a transistor, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide sem iconductor), abbreviated as OS. Also, when described as an OS FET , it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor .

[0021] Also, in this specification etc., a transistor having silicon in the channel formation region may be described as a Si transistor.

[0022] Also, in this specification etc., a metal oxide having nitrogen may also be generically referred to as a metal oxide (metal ox ide). Also, a metal oxide having nitrogen may be referred to as a metal oxynitride (me tal oxynitride).

[0023] (Embodiment 1) In this embodiment, the circuit configuration, operation method, and fabrication method of a semiconductor device according to an aspect of the disclosed invention will be described. In the following description, for example, "[x,y]" means the element in the x-th row and y-th column, and "[z]" means the element in the z-th row or z-th column. When it is not necessary to specify a row or a column in particular, these notations are omitted.

[0024] <Example of Circuit Configuration> First, the circuit configuration of the semiconductor device will be described with reference to FIG. 1(A). FIG. 1(A ) shows a circuit diagram of n memory cells (n is an integer of 1 or more). That is, memory cells of memory cells MC[1] to MC[n], and wirings WWL[1] to WWL[n] for controlling them, wirings RWL[1] to RWL[n , wiring WBL, and wiring RBL. Note that the wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0025] Each memory cell MC has a transistor WTr, a transistor RTr, and a capacitor element C S. The transistor RTr shown in FIG. 1(A) is a transistor having a back gate, and by applying a potential to the back gate, the threshold voltage of the transistor RTr can be varied. Note that the wiring BGL shown in FIG. 1(A) is electrically connected to the back gates of the transistors RTr each owned by the memory cells MC[1] to MC[n]. Further, the semiconductor device shown in FIG. 1 may not be configured to be electrically connected to each of the back gates of the transistors RTr owned by the memory cells MC[1] to MC[n], but may be configured to be electrically connected independently to each of the back gates to supply different potentials to each other. It may be configured to supply different potentials to each other.

[0026] The channel formation region of the transistor WTr preferably has a metal oxide described in Embodiment 3. In particular, in the case of a metal oxide selected from one or more of indium, element M (as element M, for example, aluminum, gallium, yttrium, tin, etc.), and zinc , since the metal oxide functions as a wide-gap semiconductor, the transistor included in the channel formation region has the characteristic of a very low off-current. By applying a transistor having this characteristic as the transistor WTr for holding data, data can be held in the memory cell MC for a long time. As a result, since the number of refresh times of the held data can be reduced, the power consumption of the semiconductor device can be reduced.

[0027] Also, as the channel formation region of the transistor RTr, it is preferable to use a material with a high field-effect mobility of the transistor. By using such a transistor, the semiconductor device can operate faster. For example, as the material included in the channel formation region of the transistor RTr, it can have a semiconductor material such as the metal oxide and silicon described in Embodiment 3.

[0028] The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. The switching between the on state and the off state of the transistor WTr is performed by the potential applied to the wiring WWL. The potential of one electrode of the capacitor element CS is controlled by the wiring RWL. The other electrode of the capacitor element CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitor element CS can be referred to as a memory node. The memory node of each memory cell MC is electrically connected to the first terminal of the transistor WTr

[0029] included in the memory cell MC. Also, the second terminal of the transistor WTr is, The first terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr. The first terminal of the transistor RTr of the adjacent memory cell is connected in series with the second terminal of the transistor RTr of the adjacent memory cell. The second transistor WTr of the memory cell MC[n] is electrically connected to the The terminal is electrically connected to the wiring WBL, and the transistor R The second terminal of the transistor is electrically connected to the wiring RBL. The connection point between the second terminal of the transistor RTr in the memory cell MC[n] and the wiring RBL is The first terminal of the transistor RTr in the memory cell MC[1] is called node N1. In order to control the conduction state between the node N1 and the wiring RBL, A selection transistor may be connected in series with the transistor RTr. Similarly, the node N 2 and the node N2. A selection transistor may be connected in series with Tr.

[0030] Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. In some cases, depending on the circumstances, or as required, the semiconductor device shown in FIG. For example, one embodiment of the present invention is a circuit configuration in which the As shown in the figure, if necessary, the transistor WTr may also be provided with a back gate. The semiconductor device shown in FIG. In addition to the configuration of the semiconductor device, the transistors of the memory cells MC[1] to MC[n] are A back gate is provided for the transistor WTr, and each back gate is connected to the wiring BGL and the It is configured to be connected pneumatically. Also, for example, one aspect of the present invention is as shown in FIG. 1(C). As shown, it may be a semiconductor device without providing a back gate to the transistor RTr and the transistor WTr.

[0031] By the way, when it is desired to further increase the storage capacity of the semiconductor device shown in FIGS. 1(A), (B), and (C), the semiconductor devices shown in FIGS. 1(A), (B), and (C) may be arranged side by side in a matrix. For example, when the semiconductor devices shown in FIG. 1(B) are arranged side by side in a matrix, the circuit configuration becomes the configuration shown in FIG. 2.

[0032] The semiconductor device shown in FIG. 2 is obtained by arranging the semiconductor devices shown in FIG. 2(B) in m columns (m is an integer of 1 or more) as one column, and is configured to be electrically connected so as to share the wiring RWL and the wiring WWL with the memory cells MC in the same row. That is, the semiconductor device shown in FIG. 2 is a matrix semiconductor device of n rows and m columns, and has memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in FIG. 2 is electrically connected by the wiring RWL[1] to the wiring RWL[n], the wiring WWL[1] to the wiring WWL[n], the wiring RBL[1] to the wiring RBL[m], the wiring WBL[1] to WBL[m], and the wiring BGL[1] to the wiring BGL[m]. Specifically, one electrode of the capacitive element CS of the memory cell MC[j,i] (j is an integer of 1 or more and n or less, and i is an integer of 1 or more and m or less) is electrically connected to the wiring RWL[j], and the gate of the transistor WTr of the memory cell MC[j,i] is electrically connected to the wiring WWL[j]. The wiring WBL[i] is connected to the second terminal of the transistor WTr of the memory cell MC[n,i].[[]] ​​​​​​​​​​​​ are electrically connected, and the wiring RBL[i] is connected to the transistor RT of the memory cell MC[n,i] is electrically connected to the second terminal of r.

[0033] Note that FIG. 2 shows the memory cell MC[1,1], the memory cell MC[1,i], the memory cell M C[1,m], the memory cell MC[j,1], the memory cell MC[j,i], the memory cell MC [j,m], the memory cell MC[n,1], the memory cell MC[n,i], the memory cell MC n,m], the wiring RWL[1], the wiring RWL[j], the wiring RWL[n], the wiring WWL[1] , the wiring WWL[j], the wiring WWL[n], the wiring RBL[1], the wiring RBL[i], the wiring R BL[m], the wiring WBL[1], the wiring WBL[i], the wiring WBL[m], the wiring BGL[1 , the wiring BGL[i], the wiring BGL[m], the capacitor element CS, the transistor WTr, the tran sistor RTr, the nodes N1 and N2 are only shown, and other wirings, elements, symbols , and codes are omitted.

[0034] Also, the semiconductor device shown in FIG. 2(C) is arranged in m columns (m is an integer of 1 or more). arranged side by side is shown in FIG. 3. Note that the semiconductor device shown in FIG. 3 has a configuration in which no back gate is provided for each transistor of all the memory cells , and therefore, the semiconductor device shown in FIG. 3 does not have the wiring BGL. Note that for the semiconductor device of FIG. 3, refer to the description of the semiconductor device shown in FIG. 2.

[0035] <Example of Operating Method> Next, an example of the operating method of the semiconductor device shown in FIGS. 1(A) to 1(C) will be described . Note that the low-level potential and the high-level potential used in the following description mean specific potentials Rather, if the wiring is different, the specific potential may also be different. For example, for wiring WW Each of the low-level potential and the high-level potential applied to L may be a potential different from the low-level potential and the high-level potential applied to wiring RWL.

[0036] Also, in this example of the operation method, for the wiring BGL shown in FIGS. 1(A) and (B) and the BGW[1] to BGW[n] shown in FIG. 1(B), it is assumed that potentials within the normal operating range of the transistor RTr and the transistor WTr are applied in advance. Therefore, the operations of the semiconductor devices shown in FIGS. 1(A) to (C) can be considered similarly to each other.

[0037] FIG. 4(A) is a timing chart showing an example of an operation of writing data into a semiconductor device, and FIG. 4(B) is a timing chart showing an example of an operation of reading data from a semiconductor device. Each of the timing charts in FIGS. 4(A) and (B) shows changes in the magnitudes of the potentials of the wirings WWL[1], the wiring WWL[2], the wiring WWL[n], the wiring RWL[1], the wiring RWL[2], the wiring RWL [n], the node N1, and the node N2. Also, the wiring W BL shows the data supplied to the wiring WBL.

[0038] FIG. 4(A) shows an example of writing each of the data D[1] to the data D[n] into the memory cells MC[1] to the memory cells MC[n]. Note that the data D[1] to the data D[n] can be binary or multi-valued. And the data D[1] to the data D [n] are assumed to be supplied from the wiring WBL. That is, in the circuit configuration of the semiconductor device shown in FIGS. 1(A) to (C), the writing of data is from the memory cell MC[1] to the memory ​​​​​It is sequentially performed on the cell MC[n].

[0039] Conversely, after writing data to the memory cell MC[2], when attempting to write data to the memory cell MC[1], the data written in the memory cell MC[2] must be read out and saved in another location; otherwise, the data held in the memory cell MC[2] will be lost at the stage of writing data to the memory cell MC[1].

[0040] In the circuit configuration of the semiconductor device shown in FIGS. 1(A) to (C), when writing data to the memory cell MC[i] ( where i is an integer greater than or equal to 2 and less than or equal to n), in order to prevent rewriting of the data held in the memory cells MC[1] to MC[i - 1], a low-level potential is supplied to the wirings WWL[1] to WWL[i - 1] to turn off each transistor WTr included in the memory cells MC[1] to MC[i - 1]. Thereby, the respective data held in the memory cells MC[1] to MC[i - 1] can be protected.

[0041] Also, when writing data to the memory cell MC[i], since the data is supplied from the wiring WBL, a high-level potential is supplied to the wirings WWL[i] to WWL[n] to turn on each transistor WTr included in the memory cells MC[i] to MC[n] sufficiently. Thereby, the data can be held in the memory node of the memory cell MC[i].

[0042] Note that when writing data to the circuit configuration of the semiconductor device shown in FIGS. 1(A) to (C), since the wiring RBL can be independently controlled, there is no need to set it to a specific potential. For example, a low-level potential can be used. can be set to a certain level. Also, the potential of the wiring RWL, that is, the potential of the node N1, can be set to a low level potential. can be set to a certain level. In addition, the potential of the node N2 can also be set to a low level potential. .

[0043] Based on the above, the operation example shown in the timing chart of Fig. 4(A) will be described. . At time T10, the potentials of each of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are all at a low level potential. potential.

[0044] At time T11, high level potentials are supplied to the wirings WWL[1] to WWL[n]. As a result, each of the transistors WTr included in the memory cells MC[1] to MC[n] is in a sufficient on state. And data D 1] is supplied to the wiring WBL. Since each of the transistors WTr included in the memory cells MC[1] to MC[n] is in a sufficient on state, the data D[1] reaches the memory node of the memory cell MC[1] and is written. MC[1] to MC[n] reach the memory node of the memory cell MC[1] and are written. MC[1] and is written. Since each of the transistors WTr included in the memory cells MC[1] to MC[n] is in a sufficient on state, the data D[1] reaches the memory node of the memory cell MC[1] and is written.

[0045] At time T12, a low level potential is supplied to the wiring WWL[1], and high level potentials are continuously supplied to the wirings WWL 2] to WWL[n]. As a result, the transistor WTr included in the memory cell MC[1] is turned off, and each of the transistors WTr included in the memory cells MC[2 to MC[n] is in a sufficient on state. And data D[2] is supplied to the wiring WBL. Each of the transistors WTr included in the memory cells MC[2] to MC[n] is in a sufficient on state. And data D[2] is supplied to the wiring WBL. Each of the transistors WTr included in the memory cells MC[2] to MC[n] is in a sufficient on state. Therefore, the data D[2] reaches the memory node of the memory cell MC[2] and is written in. Also, since the transistor WTr of the memory cell MC[1] is in the off state, the data D[1] held in the memory cell MC[1] is not lost by the writing operation from this time T12 to time T13.

[0046] Between time T13 and time T14, similar to each of the writing operations of the data D[1] to the memory cell MC[1] between time T11 and time T12 and the writing operation of the data D[2] to the memory cell MC[2] between time T12 and time T13, the data D[3] to D[n - 1] are sequentially written to each of the memory cells MC[3] to MC[n - 1]. Specifically, the transistors WTr of the memory cells MC[1] to MC[j - 1] (j is an integer from 3 to n - 1) in which data has already been written are set to the off state, and the transistors WTr of the memory cells MC[j] to MC[n] in which data has not been written are set to a sufficient on state, and the data D[j] is supplied from the wiring WBL and written to the memory node of the memory cell MC[j]. Then, when the writing of the data D[j] to the memory cell MC[j] is completed, the transistor WTr of the memory cell MC[j] is set to the off state, and the data D[j + 1] is supplied from the wiring WBL and written to the memory node of the memory cell MC[j + 1]. Note that the writing operation when j is n - 1 refers to the operation from time T14 to time T15 described below.

[0047] At time T14, low-level potentials are supplied to wirings WWL[1] to WWL[n - 1], and a high-level potential continues to be supplied to wiring WWL[n]. As a result, the transistors WTr included in memory cells MC[1] to MC[n - 1] are turned off, and the respective transistors WTr included in memory cell MC[n] are turned on sufficiently. Then, data D[n] is supplied to wiring WBL. Since the respective transistors WTr included in memory cell MC[n] are turned on sufficiently, data D[n] reaches the memory node of memory cell MC[n] and is written. Also, since the transistors WTr of memory cells MC[1] to MC[n - 1] are in the off state, the data D[1] to D[n - 1] held in each of memory cells MC[1] to MC[n - 1] is not lost by the writing operation from this time T14 to time T15.

[0048] By the above operation, data can be written to the memory cell MC included in any one of the semiconductor devices shown in FIGS. 1(A) to (C).

[0049] FIG. 4(B) shows an example of reading data D[1] to D[n] from memory cells MC[1] to MC[n], respectively. At this time, in order to maintain the data held in each memory cell MC, the transistor WTr is required to be in the off state. Therefore, when reading data from memory cells MC[1] to MC[n], the potentials of wirings WWL[1] to WWL[n] are set to low-level potentials. ​​​​​​​​​​

[0050] In the circuit configuration of the semiconductor device shown in FIG. 1, when reading the data of a specific memory cell MC, after turning on the transistors RTrs of other memory cells MC sufficiently, the transistor RTr of the specific memory cell MC is operated in the saturation region. That is, the current flowing between the source and drain of the transistor RTr of the specific memory cell MC is determined according to the voltage between the source and drain and the data held in the specific memory cell MC.

[0051] For example, consider the case of reading the data held in the memory cell MC[k] (where k is an integer from 1 to n). At this time, in order to turn on the respective transistors RTrs of the memory cells MC[1] to MC[n] excluding the memory cell MC[k] sufficiently, a high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL[k]. On the other hand, in order to turn on the transistor RTr of the memory cell MC[k] according to the held data,

[0052] the wiring RWL[k] needs to be set to the same potential as the wiring RWL[k] when the data was written to the memory cell MC[k]. Here, it is considered that the potential of the wiring RWL[k] during the write operation and the read operation is a low-level potential.

[0053] For example, a potential of +3V is applied to node N1 and 0V to node N2. Then, node N2 is floated and the potential of node N2 after that is measured. When the potentials of the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are set to a high-level potential, the memory cell ​ The transistors of memory cells MC[1] to MC[n] excluding MC[k] The transistor RTr is in a sufficient on state. On the other hand, the transistor The voltage between the first terminal and the second terminal of RTr is determined by the potential of the gate of the transistor RTr and the potential of node N1. Therefore, the potential of node N2 is determined according to the data held in the memory node of memory cell MC[k]. is determined according to the data held in the memory node of memory cell MC[k].

[0054] In this way, the data held in memory cell MC[k] can be read out. can be read out.

[0055] Based on the above, the operation example shown in the timing chart of Fig. 4(B) will be described. At time T20, the potentials of wirings WWL[1] to WWL[n], wirings RWL[1] to RWL[n], wiring WBL, node N1, and node N2 are all at low level potentials. In particular, node N2 is in a floating state. And the memory nodes of memory cells MC[1] to MC[n] hold data D[1] to D[n], respectively.

[0056] At time T21, a low level potential is supplied to wiring RWL[1], and high level potentials are supplied to wirings RWL 2] to WWL[n]. As a result, each transistor RTr of memory cells M C[2] to MC[n] is in a sufficient on state. And the transistor RTr of memory cell MC[1] is in an on state according to the data D[1] held in the memory node of memory cell MC 1]. Also, a potential V is applied to wiring RBL. Ris supplied. As a result, the potential of node N1 becomes V R and the potential of node N 2 is determined according to the potential V of node N1 R and the potential of node N2 and the data held in the memory node of memory cell MC[1]. Here, the potential of node N2 is set to V D[1 ] Let it be so. Then, by measuring the potential V D[1] of node N2, the data D[1] held in the memory node of memory cell M C[1] can be read out.

[0057] At time T22, low-level potentials are supplied to wirings RWL[1] to RWL[n]. Also, a low-level potential is supplied to node N2, and then node N2 enters a floating state. That is, between time T22 and time T23, the potentials of each of wirings RWL[1] to RWL[n] and node N2 are the same as the situation between time T20 and time T 21. Note that a potential V may be continuously supplied to wiring RBL, or a low-level potential may be supplied. In this operation example, it is assumed that wiring RBL continues to be supplied with the potential V R after time T 21. After time T21, it is assumed that the potential V R is continuously supplied.

[0058] At time T23, a low-level potential is supplied to wiring RWL[2], and high-level potentials are supplied to wiring RWL 1], wirings RWL[3] to RWL[n]. As a result, each transistor RTr of memory cell MC[1], memory cell MC[3] to memory cell MC[n] becomes fully on. And the transistor RTr of memory cell MC[2] is based on the data held in the memory node of memory cell MC[2] It becomes an on state according to D[2]. Also, the potential V R is continuously supplied to the wiring RBL. As a result, the potential of node N2 is the potential V of node N1 R and the potential of node N2 is the me asured according to the data held in the memory node of the memory cell MC[2]. Here, no de the potential of node N2 as V D[2] . Then, the potential V of node N2 D[2] is measured to read out the data D[2] held in the memory node of the memory cell MC[2].

[0059] Between time T24 and time T25, the data D[1] readout operation from the memory cell MC[1] between time T20 and time T22 and the data D[2] readout operation from the memory cell MC[2] between time T22 and time T24 are each the same as, and data D 3] to data D[n - 1] are sequentially read out from each of the memory cells MC[3] to MC[n - 1]. Specifically, when reading data D[j] from the memory cell MC[j] (j is an integer from 3 to n - 1), after setting the potential of node N2 to a low level potential and floating node N2, a high level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL [j], and the transistors RTr of the memory cells MC[1] to MC[n] excluding the memory cell MC[j] are turned on sufficiently, and the transistor RT r of the memory cell MC[j] is turned on according to the data D[j]. Next, the potential of node N1 is set to V r of the memory cell MC[j] is turned on according to the data D[j]. Next, the potential of node N1 is set to V r to make the potential of node N2 a potential according to the data D[j], and this potential is measured R to make the potential of node N2 a potential according to the data D[j], and this potential is measured ​Thus, the data D[j] can be read. Note that after the data D[j] held in the memory cell MC[j] has been read, as preparation for the next read operation, a low-level potential is supplied to the wiring RWL [1] to the wiring WWL[n], so that a low-level potential is supplied to the node N2, and then the node N2 is put into a floating state. Note that when j is n - 1, this preparation refers to the operation between time T25 and time T26. [1] to the wiring WWL[n], so that a low-level potential is supplied to the node N2, and then the node N2 is put into a floating state. Note that when j is n - 1, this preparation refers to the operation between time T25 and time T26. Thus, the data D[j] can be read. Note that after the data D[j] held in the memory cell MC[j] has been read, as preparation for the next read operation, a low-level potential is supplied to the wiring RWL [1] to the wiring WWL[n], so that a low-level potential is supplied to the node N2, and then the node N2 is put into a floating state. Note that when j is n - 1, this preparation refers to the operation between time T25 and time T26.

[0060] At time T25, a low-level potential is supplied to the wiring RWL[1] to the wiring WWL[n]. Also, a low-level potential is supplied to the node N2, and then the node N2 becomes a floating state. That is, between time T25 and time T26, the potentials of each of the wiring RWL [1] to the wiring WWL[n] and the node N2 become the same as the situation between time T20 and time T 21. Note that the potential V may be continuously supplied to the wiring RBL, or a low-level potential may be supplied. In this operation example, it is assumed that the potential V is continuously supplied to the wiring RBL after time T21. R is supplied to the wiring RBL, or a low-level potential may be supplied. In this operation example, it is assumed that the potential V is continuously supplied to the wiring RBL after time T21. R is continuously supplied.

[0061] At time T26, a low-level potential is supplied to the wiring RWL[n], and a high-level potential is supplied to the wiring RWL [1] to the wiring WWL[n - 1]. As a result, each transistor RTr of the memory cells MC[1] to MC[n - 1] is turned on fully. And the transistor RTr of the memory cell MC[n] is turned on according to the data D[n] held in the memory node of the memory cell MC[n]. Also, the potential V is continuously supplied to the wiring RBL. As a result, the potential of the node N2 is continuously supplied to the wiring RBL. As a result, the potential of the node N2 is continuously supplied to the wiring RBL. As a result, the potential of the node N2 R is continuously supplied, and thus the potential of the node N2 The potential of node N1 is V R and the potential of node N2 is the memory node of memory cell MC[n] which is determined according to the data held in it. Here, the potential of node N2 is set to V D[n] and let it be so. Then, by measuring the potential V D[n] of node N2, the data D[n] held in the memory node of memory cell MC[n can be read out.

[0062] By the above operation, data can be read out from each memory cell MC of the semiconductor device shown in FIGS. 1(A) to (C).

[0063] <Structural Example and Manufacturing Method Example> Hereinafter, in order to help understand the structure of the semiconductor device of the present embodiment, its manufacturing method will be described as follows.

[0064] FIGS. 5(A) and (B) are schematic diagrams showing the semiconductor device shown in FIGS. 1(A) to (C). FIG. 5(A) shows a top view of the semiconductor device, and FIG. 5(B) shows a cross-sectional view corresponding to the dashed line A1 - A2 in FIG. 5(A).

[0065] The semiconductor device has a structure in which a wiring RWL, a wiring WWL, and an insulator (a region not hatched in FIG. 5) are laminated, and an opening is provided in the structure, and a conductor PG is formed so as to fill the opening. A wiring ER is formed on the conductor PG and thereby, the wiring ER is electrically connected to the wiring RWL or the wiring WWL.

[0066] In addition, with respect to the structure, such that the wiring RWL and the wiring WWL penetrate through it all at once An opening is formed. Then, an insulator, a conductor, and a semiconductor are formed in a region AR through which wiring RWL and wiring WWL penetrate. In order to provide a memory cell MC, an insulator, a conductor, and a semiconductor are formed in the opening. Note that the conductor functions as wiring WBL and wiring RBL, and the semiconductor functions as a channel formation region of transistor WTr and transistor RTr. In FIG. 5, a region where an insulator, a conductor, and a semiconductor are formed in the opening is shown as region HL in the figure. Note that when a back gate is provided for the transistors included in the memory cell MC, the conductor included in region HL may also function as wiring BGL for electrically connecting to the back gate. That is, in FIG. 5, the semiconductor device shown in any one of FIGS. 1(A), (B), and (C) is configured in region SD1, and the semiconductor device shown in FIG. 2 or FIG. 3 is configured in region SD2.

[0067]

[0068]

[0069] <<Fabrication Method Example 1>> FIGS. 6 to 10 are cross-sectional views for explaining a fabrication example of the semiconductor device shown in FIG. 1(A), and particularly show cross-sectional views in the channel length direction of transistor WTr and transistor RTr. In addition, in the cross-sectional views of FIGS. 6 to 10, some elements are omitted for clarity of the figure.

[0070] As shown in FIG. 6(A), the semiconductor device of FIG. 1(A) includes an insulator 101A disposed above a substrate (not shown), a conductor 131A disposed on the insulator 101A, and a conductor disposed on the insulator 101A and a conductor An insulator 101B disposed on 131A and a conductor 132 disposed on the insulator 101B A, an insulator 101C disposed on the conductor 132A, and an insulator 101C disposed on the conductor 131B, an insulator 101D disposed on the conductor 131B, and on the insulator 101D a conductor 132B disposed thereon, and an insulator 101E disposed on the conductor 132B, and having these. Hereinafter, the laminate having these plurality of conductors and plurality of insulators will be referred to as laminate 1 00.

[0071] As the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used For the insulator substrate, for example, there are a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Also, For the semiconductor substrate, for example, a single semiconductor substrate such as silicon or germanium, or carbon silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, oxidized gallium, and other compound semiconductor substrates. Furthermore, a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator ) substrate and the like. For the conductor substrate, there are a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate plate, and the like. Or, a substrate having a metal nitride, a substrate having a metal oxide, and the like exist. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a conductor or an insulator is provided on a semiconductor substrate, a semiconductor or an insulator is provided on a conductor substrate, and the like exist. Or, those in which elements are provided on these substrates may also be used. As the elements provided on the substrate there are a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0072] Also, a flexible substrate may be used as the substrate. Note that, as a method of providing a transistor on the flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to a substrate that is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate, a woven sheet, film, foil, or the like incorporating fibers may also be used. Further, the substrate may have stretchability. Also, as a method of providing a transistor on a flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to a substrate that is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate, a woven sheet, film, foil, or the like incorporating fibers may also be used. Further, the substrate may have stretchability. Also, as a method of providing a transistor on a flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to a substrate that is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate, a woven sheet, film, foil, or the like incorporating fibers may also be used. Further, the substrate may have stretchability. Also, as a method of providing a transistor on a flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to a substrate that is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate, a woven sheet, film, foil, or the like incorporating fibers may also be used. Further, the substrate may have stretchability. Also, as a method of providing a transistor on a flexible substrate, there is also a method of fabricating a transistor on a non-flexible substrate and then peeling off the transistor and transferring it to a substrate that is a flexible substrate. In that case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. Note that, as the substrate, a woven sheet, film, foil, or the like incorporating fibers may also be used. Further, the substrate may have stretchability. Also, the substrate may have a property of returning to its original shape when bending or pulling is stopped. Or, it may have a property of not returning to its original shape. The substrate has a region with a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. Making the substrate thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate thinner, when using glass or the like, there may be cases where it has stretchability or has a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided. μm or less. Making the substrate thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate thinner, when using glass or the like, there may be cases where it has stretchability or has a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided. μm or less. Making the substrate thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate thinner, when using glass or the like, there may be cases where it has stretchability or has a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided. μm or less. Making the substrate thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate thinner, when using glass or the like, there may be cases where it has stretchability or has a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided. μm or less. Making the substrate thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate thinner, when using glass or the like, there may be cases where it has stretchability or has a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided. μm or less. Making the substrate thinner can reduce the weight of the semiconductor device having the transistor. Also, by making the substrate thinner, when using glass or the like, there may be cases where it has stretchability or has a property of returning to its original shape when bending or pulling is stopped. Therefore, impacts applied to the semiconductor device on the substrate due to dropping or the like can be mitigated. That is, a robust semiconductor device can be provided.

[0073] As the substrate that is a flexible substrate, for example, metal, alloy, resin, or glass, or fibers thereof or the like can be used. The substrate that is a flexible substrate is preferably one in which deformation due to the environment is suppressed as much as possible with a low coefficient of linear expansion. As the substrate that is a flexible substrate, for example, the coefficient of linear expansion is 1 × 10 / K or less, 5 × 10 / K or less, or 1 × 10 -3 / K or less -5 / K or less, or 1 × 10 -5 / K or less A certain material may be used. Examples of the resin include polyester, polyolefin, poly amide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. In particular, aramid is suitable as a flexible substrate because of its low coefficient of linear expansion. .

[0074] In the production example described in this embodiment, since heat treatment is included during the process, it is preferable to use a material with high heat resistance and low thermal expansion coefficient as the substrate.

[0075] The conductor 131A (conductor 131B) functions as the wiring WWL shown in FIG. 1(A), and the conductor 132A (conductor 132B) functions as the wiring RWL shown in FIG. 1(A).

[0076] Examples of the conductor 131A, conductor 131B, conductor 132A, and conductor 132B include , materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum , tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used. .

[0077] In addition, as the above-mentioned conductor, particularly the conductor 131A and conductor 131B, a conductive material containing the metal elements and oxygen contained in a metal oxide applicable to the semiconductor 1 51, semiconductor 152, semiconductor 153a, and semiconductor 153b described later may be used. Also, the above-mentioned metal elements and nitrogen A conductive material containing may also be used. For example, nitrogen-containing such as titanium nitride and tantalum nitride A conductive material may be used. Also, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon-added indium tin oxide may be used. Also, indium gallium zinc oxide containing nitrogen may be used. By using such materials, water contaminated from surrounding insulators etc. may be captured.

[0078] Also, as the above conductor, particularly conductor 132A and conductor 132B, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or ruthenium oxide etc. should be used, and it may be a single layer or a laminate. should be used preferably, and it may be a single layer or a laminate. should be used preferably, and it may be a single layer or a laminate.

[0079] Also, a plurality of conductors formed of the above materials may be laminated and used. For example, a laminated structure combining the material containing the above-described metal element and the conductive material containing oxygen may be used . Also, a laminated structure combining the material containing the above-described metal element and the conductive material containing nitrogen may be used . Also, a laminated structure combining the material containing the above-described metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be used . Also, by applying an insulator having an excess oxygen region as the insulator in contact with the periphery of the conductor, oxygen may diffuse in the region where the conductor contacts the insulator . As a result, in the region where the material containing the metal element contacts the oxygen and the insulator, oxygen may diffuse. Thereby, the material containing the metal element and the oxygen and the insulator, oxygen may diffuse. Thereby, the material containing the metal element and the oxygen A laminated structure can be formed by combining a conductive material containing [the above] with [the following]. Similarly, By applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in the region where the conductor is in contact with the insulator. As a result, a laminated structure can be formed by combining a material containing a metal element with a conductive material containing nitrogen. By applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in the region where the conductor is in contact with the insulator. As a result, a laminated structure can be formed by combining a material containing a metal element with a conductive material containing nitrogen. By applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in the region where the conductor is in contact with the insulator. As a result, a laminated structure can be formed by combining a material containing a metal element with a conductive material containing nitrogen. .

[0080] Note that each of the conductors 131A, 131B, 132A, and 132B may be made of the same material as each other or may be made of different materials from each other. That is, the materials to be applied to the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention can be appropriately selected and used respectively. Note that each of the conductors 131A, 131B, 132A, and 132B may be made of the same material as each other or may be made of different materials from each other. That is, the materials to be applied to the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention can be appropriately selected and used respectively. Note that each of the conductors 131A, 131B, 132A, and 132B may be made of the same material as each other or may be made of different materials from each other. That is, the materials to be applied to the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention can be appropriately selected and used respectively. Note that each of the conductors 131A, 131B, 132A, and 132B may be made of the same material as each other or may be made of different materials from each other. That is, the materials to be applied to the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention can be appropriately selected and used respectively.

[0081] As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, 15 molecules / cm 2 As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, 15 molec ules / cm 2 As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, 14 molecules / cm 2 As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, As the insulators 101A to 101E, it is preferable that they are materials with reduced impurity concentrations such as water or hydrogen. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is, in the temperature-programmed desorption spectroscopy (TDS), in the range of 50°C to 500°C, converted to the desorption amount in terms of hydrogen molecules per unit area of any one of the insulators 101A to 101E, It may be formed using an insulator. As described above, the conductor 131A, the conductor 1 31B, the conductor 132A, and the conductor 132B can have a laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined.

[0082] As the insulators 101A to 101E, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a laminate. Further, for example, a material containing silicon oxide or silicon oxynitride can be used. In the present specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Further, in the present specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0083] In the next step, as shown in FIG. 6(B), an opening 191 can be formed in the laminate 100 shown in FIG. 6(A) by forming a resist mask and performing an etching process or the like.

[0084] The resist mask can be formed as appropriate using a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, a photomask is not used.

[0085] Therefore, the manufacturing cost can be reduced. Also, for the etching process, either the dry etching method or the wet etching method may be used, or both may be used. And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied.

[0086] And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied. And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied. And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied. And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied. And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied. And, as shown in FIG. 7(A), by using an etching process or the like, the conductors 132A and 132B on the side surface of the opening 191 are removed, and recesses 192A (recesses 192B) are formed on the side surface portion. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and a material having a higher etching rate than the conductor 131A (conductor 131B)) in the multilayer body 100 from which the conductor 132A (conductor 132B) is selectively removed is applied.

[0087] Also, the recess 192A (recess 192B) may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6(B) by providing a sacrificial layer in the region where the opening 191 and the recess 192A (recess 192B) are formed at the stage of the manufacturing process of the semiconductor device shown in FIG. 6(A). Also, the recess 192A (recess 192B) may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6(B) by providing a sacrificial layer in the region where the opening 191 and the recess 192A (recess 192B) are formed at the stage of the manufacturing process of the semiconductor device shown in FIG. 6(A). Also, the recess 192A (recess 192B) may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6(B) by providing a sacrificial layer in the region where the opening 191 and the recess 192A (recess 192B) are formed at the stage of the manufacturing process of the semiconductor device shown in FIG. 6(A). Also, there may be a case where the recess 192A (recess 192B) can be automatically formed when the opening 191 is formed without providing a sacrificial layer. Also, there may be a case where the recess 192A (recess 192B) can be automatically formed when the opening 191 is formed without providing a sacrificial layer.

[0088] In the next step, as shown in FIG. 7(B), an insulator 102 is formed on the side surface of the opening 191 shown in FIG. 7(A) and on the above-described recess. In the next step, as shown in FIG. 7(B), an insulator 102 is formed on the side surface of the opening 191 shown in FIG. 7(A) and on the above-described recess.

[0089] As the insulator 102, it is preferable to use an insulating material having a function of suppressing oxygen permeation. For example, as the insulator 102, it is preferable to use silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, or the like. As the insulator 102, it is preferable to use an insulating material having a function of suppressing oxygen permeation. For example, as the insulator 102, it is preferable to use silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, or the like. As the insulator 102, it is preferable to use an insulating material having a function of suppressing oxygen permeation. For example, as the insulator 102, it is preferable to use silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, or the like. By forming the nitride insulator 102, oxygen can enter through the insulator 102, preventing the conductivity of the conductor 133 from decreasing due to the oxidation of the conductor 133 described below. .

[0090] In the next step, as shown in FIG. 8(A), the conductor 133 is formed on the side surface of the opening 191 shown in FIG. 7(B) and in the formed concave portion. That is, the conductor 133 is formed on the formation surface of the insulator 102.

[0091] As the conductor 133, the materials applicable to the above-described conductors 131A, 131B, 132A, and 132B can be used. In particular, among these materials, it is preferable to apply a material with high conductivity to the conductor 133.

[0092] In the next step, as shown in FIG. 8(B), the conductor 133 included in the opening 191 is removed by resist mask formation and etching treatment so that only the above-described concave portion remains the conductor 133. As a result, the conductors 133a and 133b are formed. At this time, if the insulators 101A to 101E, the conductor 131A, and the conductor 131B are not exposed to the opening 191, a part of the insulator 102 may be removed. .

[0093] Regarding the formation of the resist mask and the etching treatment, refer to the description of FIG. 6(B).

[0094] Incidentally, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor element CS shown in FIG. 1(A). That is, in the region 181A (region 181B) shown in FIG. 8(B), the capacitor element CS is formed. ​

[0095] In the next step, as shown in FIG. 9A, the insulator 10 located on the side of the opening 191 is 2. A semiconductor 151 is formed on the surface on which the conductor 133a and the conductor 133b are formed.

[0096] The semiconductor 151 is made of a material containing a metal oxide described in the third embodiment. It is preferable to do so.

[0097] By the way, when the semiconductor 151 contains a metal oxide, the insulating layer in contact with the semiconductor 151 The body 102 is an insulator having a function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is preferable to use a conductive material. By forming such an insulator 102, the insulator 1 Impurities such as water or hydrogen penetrate through 02 and react with oxygen contained in the semiconductor 151. When water is generated in the semiconductor 151, the semiconductor 151 can be prevented from becoming water. In some cases, oxygen vacancies may form within the crystal. Impurities such as hydrogen may enter these oxygen vacancies. As a result, electrons that become carriers may be generated in the semiconductor 151. When a region containing a large amount of hydrogen exists, the region is included in the channel formation region. The transistor is prone to normally-on characteristics. To prevent this, the insulator 102 is Insulating material that has the function of suppressing the permeation of impurities such as water and hydrogen as well as oxygen. It is recommended to use the following.

[0098] In addition, when the semiconductor 151 contains a metal oxide, the semiconductor 151 is formed in a region The conductivity may differ depending on the region. Among the regions, the regions on the formation surface of the insulator 102 are illustrated as region 151a and region 151b. The region on the formation surface of the conductor 133a (conductor 133b) is shown as region 151c. . In particular, region 151a is a region that overlaps with the side surface of the conductor 131A (conductor 131B). , region 151b overlaps with the side surface of the insulator 101A (insulators 101B to 101E). Region 151c is in contact with the conductor 133a (conductor 133b). Therefore, there is a possibility that impurities such as hydrogen or water contained in the conductor 133a diffuse into region 151c. As described above, when impurities such as water or hydrogen diffuse into the semiconductor 151, electrons that become carriers may be generated. Therefore, region 151c may have a lower resistance. For this reason, region 151c becomes a region with higher conductivity than region 151a and region 151b. Region 151a is a region that becomes the channel formation region of the transistor. Therefore, when the transistor is in the on state, region 151a has a lower resistance, so it has higher conductivity than region 151b.

[0099]

[0100]

[0100] In the next step, as shown in FIG. 9(B), an insulator 103 and a semiconductor 152 are sequentially formed on the formation surface of the semiconductor 151 located on the side surface of the opening 191.

[0101] As the insulator 103, the materials applicable to the above-described insulator 102 can be used. . In particular, when the semiconductor 151 contains a metal oxide, the insulator 102 is preferably an insulating material that not only has oxygen but also has a function of suppressing the permeation of impurities such as water or hydrogen.

[0102] By the way, in the region 182A (region 182B) shown in FIG. 9(B), as shown in FIG. 1(A). A transistor WTr is configured. Specifically, in region 182A (region 182B), the region 151a of semiconductor 151 functions as the channel formation region of transistor WTr, each of the two regions 151b of semiconductor 151 functions as the source electrode and drain electrode of transistor WTr, and conductor 132A functions as the gate electrode of transistor WTr. In particular, when a material containing a metal oxide is applied as semiconductor 151, transistor WTr is configured to be an OS transistor.

[0103] As semiconductor 152, a material containing a metal oxide described in Embodiment 3 can be used in the same manner as semiconductor 151. Also, as an alternative to semiconductor 152, a semiconductor material such as silicon can be used.

[0104] In the next step, as shown in FIG. 10(A), insulator 104 is formed on the formation surface of semiconductor 152, and conductor 134 is formed so as to fill the remaining opening 191.

[0105] As insulator 104, materials applicable to the above-described insulator 102 and insulator 103 can be used.

[0106] As conductor 134, materials applicable to the above-described conductor 131A, conductor 131B, conductor 132A, conductor 132B, conductor 133a, and conductor 133b can be used.

[0107] By the way, in region 183A (region 183B) shown in FIG. 10(A), a transistor RTr shown in FIG. 1(A) is configured. Specifically, in region 183A (region 183B) In this case, the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor 133b) function as the gate electrode of the transistor RTr, the semiconductor 152 functions as the channel formation region of the transistor RTr, and the conductor 134 functions as the back gate electrode of the transistor RTr. In particular, when a material containing a metal oxide is applied as the semiconductor 152, the transistor RTr constitutes an OS transistor.

[0108] By performing the steps from FIG. 6(A) to FIG. 10(A), the semiconductor device shown in FIG. 1(A) can be fabricated.

[0109] One aspect of the present invention is not limited to the configuration example of the semiconductor device shown in FIG. 10(A). One aspect of the present invention can be a configuration in which the semiconductor device shown in FIG. 10(A) is appropriately

[0110] changed according to the case, the situation, or as necessary. For example, as described above, one aspect of the present invention can be a semiconductor device in which the transistor WTr and the transistor RTr are not provided with a back gate as shown in FIG. 1(C). When fabricating the semiconductor device shown in FIG. 1(C), the steps shown in FIG. 10(B) may be performed instead of the steps shown in FIG. 10(A) in the process of fabricating FIG. 1(A). In FIG. 10(B), instead of the conductor 134 in FIG. 10(A), a step of forming an insulator 105 so as to fill the

[0111] opening 191 is shown. Note that the insulator 105 can be made of, for example, a material For example, the configuration of the gate electrode of the transistor WTr may be changed from the configuration shown in FIG. 10(A). Furthermore, FIGS. 11(A), (B), and FIGS. 12(A), (B) show an example of a method for manufacturing the semiconductor device. In FIG. 11(A), in FIG. 6(B), the conductor 131A (conductor 131B) provided on the side surface of the opening 191 is removed, and the recess 193A (recess 193B) is formed. Here, as the conductor 131A (conductor 131B), a material (conductor 132A (conductor 132B), a material having a higher etching rate than the insulators 101A to 101E) in the laminate 100 that allows the conductor 131A (conductor 131B) to be selectively removed is applied. Here, as the conductor 131A (conductor 131B), a material (conductor 132A (conductor 132B), a material having a higher etching rate than the insulators 101A to 101E) in the laminate 100 that allows the conductor 131A (conductor 131B) to be selectively removed is applied. In the laminate 100, a material (conductor 132A (conductor 132B), a material having a higher etching rate than the insulators 101A to 101E) in which the conductor 131A (conductor 131B) is selectively removed is applied. material (conductor 132A (conductor 132B), a material with a higher etching rate than the insulators 101A to 101E)) is applied. It is assumed that the material is applied.

[0112] Also, the recess 193A (recess 193B) may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6(B) by providing a sacrificial layer in the region where the opening 191 and the recess 193A (recess 193B) are formed at the stage of the manufacturing process of the semiconductor device shown in FIG. 6(A). At the stage of the manufacturing process of the semiconductor device shown in FIG. 6(A), a sacrificial layer is provided in the region where the opening 191 and the recess 193A (recess 193B) are formed, and they may be formed together in the manufacturing process of the semiconductor device shown in FIG. 6(B). Moreover, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess 193B) may be automatically formed in some cases. Also, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess 193B) may be automatically formed in some cases. 93B) may be formed.

[0113] In the next step, as shown in FIG. 11(B), a semiconductor 153 is deposited on the side surface of the opening 191 shown in FIG. 11(A) and the recess 193A (recess 193B). A semiconductor 153 is deposited on the side surface of the opening 191 shown in FIG. 11(A) and the recess 193A (recess 193B).

[0114] As the semiconductor 153, a material containing the metal oxide described in Embodiment 3 is applied. It is assumed that the material is applied.

[0115] In the next step, as shown in FIG. 12(A), resist mask formation, etching treatment, etc. By this, the semiconductor 153 remains only in the aforementioned recess 193A (recess 193B), and the semiconductor 153 contained in the opening part 191 is removed. Also, simultaneously with this process, or after this process, an etching process is performed to remove the conductor 132A (conductor 132B), and a recess 192A (recess 192B) is formed.

[0116] Next, in the same manner as the process of FIG. 8(B), an insulator 102 is formed so as to cover the side surface of the opening 191 with respect to the semiconductor 153a (semi conductor 153b). When a material containing a metal oxide is applied as the semiconductor 153 (semiconductor 153b), the semiconductor 153a (semiconductor 153b ) comes into contact with the insulator 102, and impurities such as hydrogen and water contained in the insulator 102 diffuse into the semiconductor 153a (semiconductor 153b). Also, the semiconductor 153a (semiconductor 153b) comes into contact with the conductor 133a (conductor 133b), and impurities such as hydrogen and water contained in the conductor 133a (conductor 133b) diffuse into the semiconductor 153a (semiconductor 153b). That is, the semiconductor 153a (semiconductor 153b) has a role of collecting impurities such as hydrogen and water. As a result, the semiconductor 153a (semiconductor 153b) has a lower resistance and can function as the gate electrode of the transistor WT r. After this, by performing the same processes as those from FIG. 9(A) to FIG. 10(A), a semiconductor device shown in FIG. 12(B) can be configured. Also, for example, one aspect of the present invention is to reduce the electrical resistance between the first terminal or the second terminal of the transistor WTr shown in FIG. 1(A) and the gate of the transistor RTr. Therefore, the configuration of the gate electrode of the transistor RTr is changed from the configuration shown in FIG. 10(A).

[0117] ​​​​​​​​This is also acceptable. FIGS. 13(A) and (B) show an example of a method for manufacturing the semiconductor device. FIG. 1 In FIG. 13(A), not only the conductor 132A (conductor 132B) on the side surface of the opening 191 in FIG. 7(A) is removed, but also the insulators 101A to 101E are removed to show a process of forming the recess 194B (recess 194A, recess 194C). Here it is assumed that materials (materials with a higher etching rate than the conductor 131A (conductor 131B)) are applied as the conductor 132A (conductor 132B) and the insulators 101A to 101E such that the conductor 132A (conductor 132B) and the insulators 101A to 101E in the laminate 100 are selectively removed.

[0118] Also, the recess 194B (recess 194A, recess 194C) may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in FIG. 6(B) by providing a sacrificial layer in the region where the opening 191 and the recess 194B (recess 194A, recess 194C) are formed at the stage of the manufacturing process of the semiconductor device shown in FIG. 6(A). Further, when the opening 191 is formed without providing a sacrificial layer, the recess 194B (recess 194A, recess 194C) may be formed automatically in some cases.

[0119] Also, in FIG. 13(A), in the recess 194B (recess 194A, recess 194C), the conductor 132A (conductor 132B) is removed more greatly than the insulators 101B and 101C (insulators 101A, 101D, 101E), but the insulators 101B and 101C (insulators 101A, 101D, 101E) may be removed more greatly than the conductor 132A (conductor 132B). Also, the insulator 101B ​​​​​​​​​​​, the insulator 101C (insulator 101A, insulator 101D, insulator 101E) and the conductor 13 2A (conductor 132B) may be formed to have the same depth.

[0120] FIG. 13(B) shows a configuration example of a semiconductor device in the case of passing through the process of FIG. 13(A). After the process of FIG. 13(A), the conductor 133 is formed so as to fill the recess 194B (recess 194A, recess 194C), and the gate electrode of the transistor RTr is formed. In FIG. 1 3(A), the conductors 133a, 133b, and 133c that function as the gate electrode of the transistor RTr are shown. After this, by performing the same processes from FIG. 9(A) to FIG. 10(A), the semiconductor device shown in FIG. 13(B) can be configured . This semiconductor device has a configuration in which the contact area between the semiconductor 151 and the conductor 13 3a (conductor 133b) is larger than that of the semiconductor device shown in FIG. 10(A). When a material having a metal oxide is applied to the semiconductor 151, the semiconductor device shown in FIG. 13(B) does not have the region 151b shown in FIG. 10(A), so the electrical resistance between the first terminal or the second terminal of the transistor WTr and the gate of the transistor RTr can be reduced. . the gate of the transistor RTr can be reduced. When a material having a metal oxide is applied to the semiconductor 151, the semiconductor device shown in FIG. 13(B) does not have the region 151b shown in FIG. 10(A), so the electrical resistance between the first terminal or the second terminal of the transistor WTr and the gate of the transistor RTr can be reduced. the gate of the transistor RTr can be reduced.

[0121] <<Example of manufacturing method 2>> Here, as the semiconductor device of the present embodiment, an example of a structure different from that of the manufacturing method example 1 will be described with reference to FIGS. 14 to 16. using FIGS. 14 to 16.

[0122] 14 to 16 are cross-sectional views for explaining an example of manufacturing the semiconductor device shown in FIG. 1(A), similar to FIGS. 6 to 10. In particular, the channels of the transistors WTr and RTr are shown. 14 to 16 are cross-sectional views in the longitudinal direction of the panel. As with FIG. 0, some elements have been omitted for clarity.

[0123] The first step is the same as that described in the first embodiment of the manufacturing method from FIG. 6(A) to FIG. 7(B). Please refer to the description.

[0124] The process shown in FIG. 14(A) is a continuation of the process shown in FIG. 7(B). In (A), a semiconductor is applied to the side surface of the opening 191 shown in FIG. 7(B) and the recess formed therein. That is, the semiconductor 151 is formed on the formation surface of the insulator 102.

[0125] As the semiconductor 151, it is preferable to use the semiconductor described in the third embodiment.

[0126] In the next step, as shown in FIG. 14(B), the side surface of the opening 191 shown in FIG. A conductor 133 is then formed in the recess.

[0127] For the conductor 133, the description of the conductor 133 in the manufacturing method example 1 can be referred to.

[0128] In the next process, as shown in FIG. 15(A), a resist mask is formed and an etching process is performed. Thus, the conductor 133 in the opening 191 is removed so that the conductor 133 remains only in the recess. As a result, the conductor 133a and the conductor 133b are formed. At this time, if the insulator 102 is not exposed in the opening 191, the semiconductor 151 A portion may be removed.

[0129] For details of the formation of the resist mask and the etching process, refer to the explanation of FIG. 6(B). To pour drinks.

[0130] Incidentally, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor element CS shown in FIG. 1(A). That is, the capacitor element CS is formed in the region 181A (region 181B) shown in FIG. 15(A). For the semiconductor 151, refer to the description of the semiconductor 151 explained in Production Method Example 1. Also, when the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c. For the region 151a, the region 151b, and the region 151c, refer to the description of the region 151a, the region 151b, and the region 151c explained in Production Method Example 1.

[0131] For the semiconductor 151, refer to the description of the semiconductor 151 explained in Production Method Example 1. Also, when the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c. For the region 151a, the region 151b, and the region 151c, refer to the description of the region 151a, the region 151b, and the region 151c explained in Production Method Example 1. For the semiconductor 151, refer to the description of the semiconductor 151 explained in Production Method Example 1. Also, when the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c. For the region 151a, the region 151b, and the region 151c, refer to the description of the region 151a, the region 151b, and the region 151c explained in Production Method Example 1. For the semiconductor 151, refer to the description of the semiconductor 151 explained in Production Method Example 1. Also, when the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c. For the region 151a, the region 151b, and the region 151c, refer to the description of the region 151a, the region 151b, and the region 151c explained in Production Method Example 1. For the semiconductor 151, refer to the description of the semiconductor 151 explained in Production Method Example 1. Also, when the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c. For the region 151a, the region 151b, and the region 151c, refer to the description of the region 151a, the region 151b, and the region 151c explained in Production Method Example 1.

[0132] In the next step, as shown in FIG. 15(B), an insulator 103 is formed on the formation surfaces of the conductor 133a, the conductor 133b, and the semiconductor 151 located on the side surface of the opening 191, and then, a semiconductor 152 is formed on the formation surface of the insulator 103. In the next step, as shown in FIG. 15(B), an insulator 103 is formed on the formation surfaces of the conductor 133a, the conductor 133b, and the semiconductor 151 located on the side surface of the opening 191, and then, a semiconductor 152 is formed on the formation surface of the insulator 103. In the next step, as shown in FIG. 15(B), an insulator 103 is formed on the formation surfaces of the conductor 133a, the conductor 133b, and the semiconductor 151 located on the side surface of the opening 191, and then, a semiconductor 152 is formed on the formation surface of the insulator 103.

[0133] For the insulator 103, refer to the description of the insulator 103 explained in Production Method Example 1.

[0134] For the semiconductor 152, refer to the description of the semiconductor 152 explained in Production Method Example 1.

[0135] Incidentally, in the region 182A (region 182B) shown in FIG. 15(B), the transistor WTr shown in FIG. 1(A) is configured. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as the channel formation region of the transistor WTr, and each of the two regions 151b of the semiconductor 151 functions as the source electrode of the transistor WTr. Incidentally, in the region 182A (region 182B) shown in FIG. 15(B), the transistor WTr shown in FIG. 1(A) is configured. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as the channel formation region of the transistor WTr, and each of the two regions 151b of the semiconductor 151 functions as the source electrode of the transistor WTr. Incidentally, in the region 182A (region 182B) shown in FIG. 15(B), the transistor WTr shown in FIG. 1(A) is configured. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as the channel formation region of the transistor WTr, and each of the two regions 151b of the semiconductor 151 functions as the source electrode of the transistor WTr. Incidentally, in the region 182A (region 182B) shown in FIG. 15(B), the transistor WTr shown in FIG. 1(A) is configured. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as the channel formation region of the transistor WTr, and each of the two regions 151b of the semiconductor 151 functions as the source electrode of the transistor WTr. ​​functions as a source and a drain electrode, and the conductor 132A functions as a gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is applied as the semiconductor 151, the transistor WTr constitutes an OS transistor. In the next step, as shown in FIG. 16(A), the insulator 104 is formed on the formation surface of the semiconductor 152, and the conductor 134 is formed so as to fill the remaining opening 191. Regarding the insulator 104, refer to the description of the insulator 104 in Production Method Example 1.

[0136] Regarding the conductor 134, refer to the description of the conductor 134 in Production Method Example 1. In the region 183A (region 183B) shown in FIG. 16(A), the transistor RTr shown in FIG. 1(A) is formed. Specifically, in the region 183A (region 183B), the region 151c of the semiconductor 151, the two regions 151b, and the conductor 133a (conductor 133b) function as a gate electrode of the transistor RTr, the semiconductor 152 functions as a channel formation region of the transistor RTr, and the conductor 134 functions as a back gate electrode of the transistor RTr. In particular, when a material containing a metal oxide is applied as the semiconductor 152, the transistor RTr constitutes an OS transistor.

[0137] By performing the steps from FIG. 6(A) to FIG. 7(B) and from FIG. 14(A) to FIG. 16(A), the semiconductor device shown in FIG. 1(A) can be manufactured.

[0138]

[0139]

[0140]

[0141] ​​​​​​​​​​One aspect of the present invention is not limited to the configuration example of the semiconductor device shown in Fig. 16(A). The present invention in one aspect can, in some cases, according to the situation, or as necessary, have a configuration in which the semiconductor device shown in Fig. 16(A) is appropriately modified.

[0142] For example, as described above, one aspect of the present invention can also be a semiconductor device in which no back gate is provided for transistor WTr and transistor RTr as shown in Fig. 1(C). When manufacturing the semiconductor device shown in Fig. 1(C), in the process of manufacturing Fig. 1(A), the process shown in Fig. 16(B) may be performed instead of the process shown in Fig. 16(A). Fig. 16(B) shows a process in which an insulator 105 is formed so as to fill the opening 191 instead of the conductor 134 in Fig. 16(A). Note that the insulator 105 can use, for example, a material applicable as the insulator 104.

[0143] Also, for example, one aspect of the present invention can change the configuration of the gate electrode of transistor WTr from the configuration shown in Fig. 16(A) in order to improve the switching characteristics of transistor WTr. Fig. 17 shows a configuration example of the semiconductor device. When manufacturing the semiconductor device shown in Fig. 17, a semiconductor 153a (semiconductor 153b) is formed so as to fill the recess 193A (recess 193B) as in the configuration example shown in Fig. 12(B) described in Manufacturing Method Example 1. Next, an insulator 102 is formed so as to cover the semiconductor 153a (semiconductor 153b) on the side surface of the opening 191. After that, the semiconductor device shown in Fig. 17 can be configured by performing the same processes as those from Fig. 14(A) to Fig. 16(A). Note that Fig. 17 can be configured The effects achieved by [the method] are to be considered in light of the descriptions in FIGS. 11(A) and (B) and FIGS. 12(A) and ( B) as explained in Production Method Example 1.

[0144] Also, for example, one aspect of the present invention is to reduce the electrical resistance between the first terminal, or the second terminal, of the transistor WTr shown in FIG. 1(A) and the gate of the transistor RTr. To this end, the configuration of the gate electrode of the transistor RTr may be changed from the configuration shown in FIG. 16(A). FIG. 18 shows a configuration example of the semiconductor device. When manufacturing the semiconductor device shown in FIG. 18, a configuration example shown in FIG. 13(A) as explained in Production Method Example 1 is manufactured. Thereafter, by performing the same steps from FIG. 14(A) to FIG. 16(A), the semiconductor device shown in FIG. 18 can be configured. Note that the effects achieved by configuring FIG. 18 are to be considered in light of the description of FIG. 13(B) as explained in Production Method Example 1.

[0145] By the above-described Production Method Example 1 or Production Method Example 2, a semiconductor device capable of holding a large amount of data can be manufactured.

[0146] Here, FIG. 19 shows a structure in which a cross-sectional view of the semiconductor device shown in FIG. 10(A) (circuit configuration of FIG. 1(A)) is applied to the region SD2 of the semiconductor device shown in FIG. 5(B). Note that the region SD1 corresponds to the memory cell MC. As shown in FIG. 19, by collectively providing openings in the structure formed by laminating conductors such as the wiring RWL and the wiring WWL and an insulator, and performing the manufacturing as described in the above-described Production Method Example 1 or Production Method Example 2, the circuit configuration of FIG. 1(A) can be realized.

[0147] <Example of Connection with Peripheral Circuit> The semiconductor device shown in Fabrication Method Example 1 or Fabrication Method Example 2 may have peripheral circuits such as a read circuit and a recharge circuit formed thereunder. In this case, Si transistors are formed on a silicon substrate or the like to constitute the peripheral circuits, and then, in Fabrication Method Example 1 or Fabrication Method Example 2, a semiconductor device according to one aspect of the present invention is formed on the peripheral circuits. FIG. 20(A) is a cross-sectional view in which a peripheral circuit is constituted by planar-type Si transistors and a semiconductor device according to one aspect of the present invention is formed thereon. Also, FIG. 21(A) is a cross-sectional view in which a peripheral circuit is constituted by FIN-type Si transistors and a semiconductor device according to one aspect of the present invention is formed thereon. Note that the semiconductor devices shown in FIGS. 20(A) and 20(B) apply the configuration of FIG. 10(A) as an example. In FIGS. 20(A) and 21(A), the Si transistors constituting the peripheral circuits are formed on a substrate 1700. An element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as sources and drains of the Si transistors. A conductor 1730 is formed to extend in the channel width direction and is connected to other Si transistors or the conductors 1712 (not shown). As the substrate 1700, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used. Also, as the substrate 1700, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a bonded film, paper containing a fibrous material, or a base film can be used.

[0148]

[0149]

[0150] ​ Any of them may be used. Also, a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. In FIGS. 20(A) and 21(A), as an example, an example using a single-crystal silicon wafer for substrate 170 0 is shown.

[0151] Here, the details of the Si transistor will be described. The planar-type Si transistor shown in FIG. 20(A) shows a cross-sectional view in the channel length direction, and the planar-type Si transistor shown in FIG. 20(B) shows a cross-sectional view in the channel width direction. The Si transistor includes a channel formation region 1793 provided in well 1792, a low-concentration impurity region 1794 and a high-concentration impurity region 1795 (collectively also simply referred to as the impurity region), a conductive region 1796 provided in contact with the impurity region, a gate insulating film 1797 provided on the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, and sidewall insulating layers 1798 and 1799 provided on the side surfaces of the gate electrode 1790. Note that a metal silicide or the like may be used for the conductive region 1796.

[0152] Also, the FIN-type Si transistor shown in FIG. 21(A) shows a cross-sectional view in the channel length direction, and the FIN-type Si transistor shown in FIG. 21(B) shows a cross-sectional view in the channel width direction. The Si transistors shown in FIGS. 21(A) and (B) have a convex channel formation region 1793, and a gate insulating film 1797 and a gate electrode 179 0 are provided along the side surfaces and the upper surface thereof. In the present embodiment, a case where a convex portion is formed by processing a part of the semiconductor substrate is shown, but an SOI substrate may be processed to form a semiconductor layer having a convex shape. Note that The reference numerals shown in FIGS. 21(A) and (B) are the same as those shown in FIGS. 20(A) and (B).

[0153] Note that insulators, conductors, semiconductors, etc. disclosed in this specification and the like can be formed by PVD (Physical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method. As the PVD method, for example, sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed Laser Deposition) method, etc. can be mentioned. Also, as the CVD method, plasma CVD method, thermal CVD method, etc. can be used for formation. In particular, as the thermal CVD method, for example, MOCVD (Metal Organic Chemical Vapor Deposition) method, ALD (Atomic Layer Deposition) method, etc. can be mentioned. cal Vapor Deposition) method, CVD (Chemical Vapo r Deposition) method can be used to form them. As the PVD method, for example , sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed La ser Deposition) method, etc. can be mentioned. Also, as the CVD method, plasma CVD method, thermal CVD method can be used for formation. In particular, as the thermal CVD method, for example , MOCVD(Metal Organic Chemical Vepor Dep osition) method, ALD(Atomic Layer Deposition) method can be mentioned.

[0154] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not caused by plasma damage. formed.

[0155] In the thermal CVD method, the source gas and the oxidant are simultaneously fed into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and the reaction is carried out near the substrate or on the substrate to deposit on the substrate to form a film may be performed.

[0156] Also, in the ALD method, the chamber is under atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially introduced into the chamber, and the film formation may be carried out by repeating the order of the gas introduction . For example, by switching each switching valve (also called a high-speed valve), two or more types Supply the raw material gas above to the chamber in sequence, and introduce an inert gas (such as argon or nitrogen) simultaneously with or after the first raw material gas so that multiple types of raw material gases do not mix, and introduce the second raw material gas. When introducing the inert gas simultaneously, the inert gas becomes the carrier gas, and it is also possible to introduce the inert gas simultaneously when introducing the second raw material gas. Also, instead of introducing the inert gas, after discharging the first raw material gas by vacuum exhaust, the second raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form the first thin layer, and reacts with the second raw material gas introduced later, so that the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction sequence multiple times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for fabricating fine FETs.

[0157] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In-G a-Zn-O film, trimethylindium (In(CH3)3), tri methylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Moreover, it is not limited to these combinations, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. ( Zn(C2H5)2) can also be used.

[0158] For example, when forming a hafnium oxide film using a film-forming apparatus that utilizes ALD, a solvent and a liquid containing a hafnium precursor compound (such as hafnium alkoxide, or hafnium amide such as tetrakis(dimethyl amide)hafnium (TDMAH, Hf[N(CH3)2]4)) are used as two types of gas: a source gas in which the above is vaporized, and ozone (O3) as an oxidizing agent. Also, other materials include tetrakis(ethylmethylamide)hafnium and the like.

[0159] For example, when forming an aluminum oxide film using a film-forming apparatus that utilizes ALD, a sol vent and a liquid containing an aluminum precursor compound (such as trimethylaluminum (TMA, Al(C H3)3), etc.) are used as two types of gas: a source gas in which the above is vaporized, and H2O as an oxidizing agent . Also, other materials include tris(dimethylamide)aluminum, triisobutylal uminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0160] For example, when forming a silicon oxide film using a film-forming apparatus that utilizes ALD, hexachloro disilane is adsorbed on the film-forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed substance.

[0161] For example, when forming a tungsten film using a film-forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF 6 gas and H2 gas are sequentially and repeatedly introduced to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0162] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn- O film, using a film-forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In -O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form a Ga O layer. Further, after that, Zn(CH3)2 gas and O3 gas are sequentially and repeatedly introduced to form a Zn O layer. Note that the order of these layers is not limited to this example. Also, these gases can be used to form a mixed oxide layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer as well. Note that instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar can be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In (CH3)3 gas, In(C2H5)3 gas can be used. Also, instead of Ga(CH 3)3 gas, Ga(C2H5)3 gas can be used. Also, Zn(CH3)2 gas can be used.

[0163] Note that each configuration example of the semiconductor device described in this embodiment can be appropriately combined with each other .

[0164] Note that this embodiment can be appropriately combined with other embodiments shown in this specification .

[0165] (Embodiment 2) In this embodiment, a memory device having the semiconductor device described in the above embodiment will be described .

[0166] FIG. 22 shows an example of the configuration of a memory device. The memory device 2600 includes a peripheral circuit 2601 and a memory cell array 2610. The peripheral circuit 2601 includes a row decoder 2621, a word ​Word line driver circuit 2622, bit line driver circuit 2630, output circuit 2640, control has a roll logic circuit 2660.

[0167] The semiconductor device illustrated in FIGS. 1(A), (B), or (C) described in Embodiment 1 can be applied to the memory cell array 2610.

[0168] The bit line driver circuit 2630 includes a column decoder 2631, a precharge circuit 263 2, a sense amplifier 2633, and a write circuit 2634. The precharge circuit 26 32 has a function of precharging the node N1 (not illustrated in FIG. 22) of the wiring RBL described in Embodiment 1 to a predetermined potential. The sense amplifier 2633 has a function of acquiring the potential of the read node N2 as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the storage device 2600 as a digital data signal RDATA via the output circuit 2640.

[0169] Further, a low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 2601, and a high power supply voltage (VIL) for the memory cell array 2610 are supplied to the storage device 2600. L) is supplied.

[0170] Further, a control signal (CE, WE, RE), an address signal ADDR , and a data signal WDATA are input to the storage device 2600 from the outside. The address signal ADDR is input to the row decoder 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit 2634.

[0171] The control logic circuit 2660 processes input signals (CE, WE, RE) from the outside It processes and generates control signals for the row decoder 2621 and the column decoder 2631. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 2660 are not limited to this , and other control signals may be input as necessary.

[0172] Note that each of the above circuits or signals can be appropriately selected or discarded as necessary.

[0173] Also, by using a p-channel type Si transistor and a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in the channel formation region of the oxide semiconductor transistor described later in the embodiment for the memory device 2600, a small-sized memory device 2600 can be provided. Also, a memory device 2600 capable of reducing power consumption can be provided. Also, a memory device 2600 capable of improving the operation speed can be provided. In particular, by assuming that the Si transistor is of the p-channel type , the manufacturing cost can be kept low.

[0174] Note that the configuration example of this embodiment is not limited to the configuration of FIG. 22. For example, a part of the peripheral circuit 26 01, for example, the precharge circuit 2632 or / and the sense amplifier 2633 may be provided under the memory

[0175] cell array 2610, and the configuration may be appropriately changed as such. Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0176] (Embodiment 3) In this embodiment, included in the channel formation region of the OS transistor used in the above embodiment ​The rare metal oxide will be described.

[0177] The metal oxide preferably contains at least indium or zinc. Particularly, it preferably contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, or the like. Further, it may contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M.

[0178] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, tin, or the like. Applicable elements to other element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like. However, there may be cases where a plurality of the aforementioned elements may be combined as element M.

[0179] Next, with reference to FIGS. 23(A), 23(B), and 23(C), the preferable ranges of the atomic ratios of indium, element M, and zinc that the metal oxide according to the present invention has will be described. Note that FIGS. 23(A), 23(B), and 23(C) do not describe the atomic ratio of oxygen. Also, let each term of the atomic ratios of indium, element M, and zinc that the metal oxide has be [In], [M], and [Zn]. Next, with reference to FIGS. 23(A), 23(B), and 23(C), the preferable ranges of the atomic ratios of indium, element M, and zinc that the metal oxide according to the present invention has will be described. Note that FIGS. 23(A), 23(B), and 23(C) do not describe the atomic ratio of oxygen. Also, let each term of the atomic ratios of indium, element M, and zinc that the metal oxide has be [In], [M], and [Zn]. Next, with reference to FIGS. 23(A), 23(B), and 23(C), the preferable ranges of the atomic ratios of indium, element M, and zinc that the metal oxide according to the present invention has will be described. Note that FIGS. 23(A), 23(B), and 23(C) do not describe the atomic ratio of oxygen. Also, let each term of the atomic ratios of indium, element M, and zinc that the metal oxide has be [In], [M], and [Zn]. Next, with reference to FIGS. 23(A), 23(B), and 23(C), the preferable ranges of the atomic ratios of indium, element M, and zinc that the metal oxide according to the present invention has will be described. Note that FIGS. 23(A), 23(B), and 23(C) do not describe the atomic ratio of oxygen. Also, let each term of the atomic ratios of indium, element M, and zinc that the metal oxide has be [In], [M], and [Zn]. Next, with reference to FIGS. 23(A), 23(B), and 23(C), the preferable ranges of the atomic ratios of indium, element M, and zinc that the metal oxide according to the present invention has will be described. Note that FIGS. 23(A), 23(B), and 23(C) do not describe the atomic ratio of oxygen. Also, let each term of the atomic ratios of indium, element M, and zinc that the metal oxide has be [In], [M], and [Zn].

[0180] In FIGS. 23(A), 23(B), and 23(C), the dashed lines represent lines with an atomic ratio of [In]:[M :[Zn]=(1 + α):(1 - α):1 (-1 ≦ α ≦ 1), lines with an atomic ratio of [In]:[M]:[Zn]=(1 + α):(1 - α):2, lines with an atomic ratio of In]:[M]:[Zn]=(1 + α):(1 - α):3, [I lines with an atomic ratio of n]:[M]:[Zn]=(1 + α):(1 - α):4, and lines with an atomic ratio of [In]:[M]:[Zn]=(1 + α):(1 - α):5. That is,

[0181] Also, the dashed-dotted lines represent lines with an atomic ratio of [In]:[M]:[Zn]=5:1:β (β ≧ 0), lines with an atomic ratio of [In]:[M]:[Zn]=2:1:β, [In :[M]:[Zn]=1:1:β, [In]:[M]:[Zn =1:2:β, [In]:[M]:[Zn]=1:3:β, lines with an atomic ratio of [In]:[M]:[Zn]=1:4:β, and lines with an atomic ratio of [In]:[M]:[Zn]=1:4:β.

[0182] Also, the metal oxides shown in FIGS. 23(A), 23(B), and 23(C) with an atomic ratio of [In]:[M]: [Zn]=0:2:1 and its vicinity values are likely to have a spinel-type crystal structure.

[0183] Also, there may be a case where multiple phases coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is in the vicinity of [In]:[M]:[Zn]=0:2:1, two phases of a spinel type crystal structure and a layered crystal structure are likely to coexist. Also, when the atomic ratio is [In]: When the value is near [M]:[Zn]=1:0:0, a two-phase coexistence of a perovskite-type crystal structure and a layered crystal structure is likely to occur. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

[0184] Region A shown in Fig. 23(A) shows an example of a preferable range of the atomic ratio of indium, element M, and zinc in the metal oxide. Region A shown in Fig. 23(A) shows an example of a preferable range of the atomic ratio of indium, element M, and zinc in the metal oxide.

[0185] By increasing the indium content in the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide with a high indium content has a higher carrier mobility than a metal oxide with a low indium content. By increasing the indium content in the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide with a high indium content has a higher carrier mobility than a metal oxide with a low indium content. By increasing the indium content in the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide with a high indium content has a higher carrier mobility than a metal oxide with a low indium content.

[0186] On the other hand, when the indium and zinc contents in the metal oxide decrease, the carrier mobility decreases. Therefore, when the atomic ratio is [In]:[M]:[Zn]=0:1:0 and its vicinity values (for example, region C shown in Fig. 23(C)), the insulating property becomes high. On the other hand, when the indium and zinc contents in the metal oxide decrease, the carrier mobility decreases. Therefore, when the atomic ratio is [In]:[M]:[Zn]=0:1:0 and its vicinity values (for example, region C shown in Fig. 23(C)), the insulating property becomes high. On the other hand, when the indium and zinc contents in the metal oxide decrease, the carrier mobility decreases. Therefore, when the atomic ratio is [In]:[M]:[Zn]=0:1:0 and its vicinity values (for example, region C shown in Fig. 23(C)), the insulating property becomes high.

[0187] Therefore, the metal oxide according to one aspect of the present invention preferably has an atomic ratio shown in region A of Fig. 23(A), which is likely to have a layered structure with high carrier mobility and few grain boundaries. Therefore, the metal oxide according to one aspect of the present invention preferably has an atomic ratio shown in region A of Fig. 23(A), which is likely to have a layered structure with high carrier mobility and few grain boundaries. Therefore, the metal oxide according to one aspect of the present invention preferably has an atomic ratio shown in region A of Fig. 23(A), which is likely to have a layered structure with high carrier mobility and few grain boundaries.

[0188] In particular, in region B shown in Fig. 23(B), among region A, a high-quality metal oxide that is likely to become CAAC (c-axis aligned crystalline)-OS and has high carrier mobility can be obtained. In particular, in region B shown in Fig. 23(B), among region A, a high-quality metal oxide that is likely to become CAAC (c-axis aligned crystalline)-OS and has high carrier mobility can be obtained. In particular, in region B shown in Fig. 23(B), among region A, a high-quality metal oxide that is likely to become CAAC (c-axis aligned crystalline)-OS and has high carrier mobility can be obtained.

[0189] CAAC-OS has c-axis orientation and a plurality of nanocrystals are connected in the a-b plane direction. It is a crystal structure that is bonded and has strain. Note that strain refers to the region where a plurality of nanocrystals are connected where the direction of the lattice arrangement changes between a region with an aligned lattice arrangement and another region with an aligned lattice arrangement. points to the location where the

[0190] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons There are cases. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons . Note that in CAAC-OS, even in the vicinity of the strain, no distinct grain boundaries (also called grain boundaries) can be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS has a dense oxygen atom arrangement in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements, etc., so it is considered that strain can be tolerated. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This indicates that the formation of grain boundaries is suppressed due to the strain of the lattice arrangement. This is thought to be because CAAC-OS has a non-dense oxygen atom arrangement in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements, etc., so that strain can be tolerated. This is considered to be because CAAC-OS can tolerate strain due to factors such as the non-dense arrangement of oxygen atoms in the a-b plane direction and the change in the interatomic bond distance due to the substitution of metal elements.

[0191] CAAC-OS is a highly crystalline metal oxide. On the other hand, since no distinct grain boundaries can be confirmed in CAAC-OS, it can be said that the decrease in electron mobility due to grain boundaries does not occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects, etc., CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, it can be said that the decrease in electron mobility due to grain boundaries does not occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities and the generation of defects, etc., CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, it can be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. Therefore, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0192] Note that region B includes [In]:[M]:[Zn]=4:2:3 to 4.1 and its nearby values. Nearby values include, for example, [In]:[M]:[Zn]=5:3:4 . Further, Region B includes [In]:[M]:[Zn] = 5:1:6 and its vicinity values, as well as [In]:[M]:[Zn] = 5:1:7 and its vicinity values.

[0193] Note that the properties of the metal oxide are not uniquely determined by the atomic ratio. Even with the same atomic ratio, the properties of the metal oxide may vary depending on the formation conditions. For example, when forming a film of the metal oxide using a sputtering apparatus, a film with an atomic ratio deviated from the atomic ratio of the target is formed. Also, depending on the substrate temperature during film formation, the [Zn] of the film may be smaller than the [Zn] of the target. Therefore, the illustrated regions indicate regions where the metal oxide tends to have specific properties, and the boundaries between Region A to Region C are not strict.

[0194] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0195] (Embodiment 4) In this embodiment, a CPU including the semiconductor device of the above embodiment will be described.

[0196] FIG. 24 is a block diagram showing an example configuration of a CPU that partially uses the semiconductor device described in Embodiment 1.

[0197] The CPU shown in FIG. 24 includes, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, registers 1196, a register controller 1197, and a bus interface ​ 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 24 is just an example shown with its configuration simplified, and an actual CPU has various configurations depending on its application. For example, a configuration including the CPU or the arithmetic circuit shown in FIG. 24 is taken as one core, and a plurality of such cores are included, and a configuration in which each core operates in parallel, that is, a configuration like a GPU may be adopted. Also, the number of bits that the CPU can handle with the internal arithmetic circuit and the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0198] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195. Based on the decoded instructions, the ALU controller 1192, the interrupt controller 1194, the register controller 1197,

[0199] and the timing controller 1195 perform various controls. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, during the execution of the CPU's program, the interrupt controller 1194 determines the priority and mask of interrupt requests from external input / output devices and peripheral circuits. of interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program. of interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program. Judge from the Q state and process. The register controller 1197 generates the address of the register 1196 and reads from and writes to the register 1196 according to the state of the CPU. .

[0200] Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 has an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0201] In the CPU shown in FIG. 24, memory cells are provided in the register 1196. As the memory cells of the register 1196, the transistors shown in the previous embodiment can be used.

[0202] In the CPU shown in FIG. 24, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, in the memory cells included in the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, the supply of the power supply voltage to the memory cells in the register 1196 is performed. When holding data in the capacitive element is selected, data can be written to the capacitive element, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0203] Note that this embodiment can be appropriately combined with other embodiments described in this specification. It can be.

[0204] (Embodiment 5) A memory card (e.g., SD card) that can include the storage device of the above embodiment , USB (Universal Serial Bus) memory, SSD (Solid State Drive), etc., can be applied to various removable storage devices. In this embodiment, several configuration examples of the removable storage device will be described with reference to FIG. 25. It will be explained.

[0205] FIG. 25(A) is a schematic diagram of a USB memory. The USB memory 5100 includes a housing 5101 , a cap 5102, a USB connector 5103, and a substrate 5104. The substrate 5104 is housed in the housing 5101. The substrate 5104 is provided with a storage device and a circuit for driving the storage device. For example, a memory chip 5105 and a controller chip 5106 are attached to the substrate 5104. The memory chip 5105 incorporates the memory cell array 2610, word line driver circuit 2622, row decoder 26 21, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc., described in Embodiment 3. The controller chip 5106 specifically incorporates a processor, work memory, ECC circuit, etc. Note that the circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation or the occasion. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc., are incorporated. The controller chip 5106 specifically incorporates a processor, work memory, ECC circuit, etc. In addition, the respective circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to the above description, and may be appropriately changed according to the situation or the occasion. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. The specific circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to the above description and may be changed as appropriate according to the situation or the occasion. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. The respective circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to the above description and may be appropriately changed according to the situation or the occasion. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder Rather than the order 2631 being incorporated into the memory chip 5105, it may be incorporated into the controller chip 5106. This may be the configuration. The USB connector 5103 functions as an interface for connecting to an external device.

[0206] Figure 25(B) is a schematic diagram of the appearance of the SD card, and Figure 25(C) is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. On the substrate 5113, a storage device and a circuit for driving the storage device are provided. For example, a memory chip 5114 and a controller chip 5115 are attached to the substrate 5113. The memory cell array 2610, word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. described in Embodiment 3 are incorporated into the memory chip 5114. A processor, work memory, ECC circuit, etc. are incorporated into the controller chip 5115. Note that the circuit configurations of the memory chip 5114 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation or case. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631 may be incorporated into the controller chip 5115 instead of the memory chip 5114.

[0207] By providing the memory chip 5114 also on the back side of the substrate 5113, the SD card 5110 ​​​​​​​​​​​​​​The capacity can be increased. Also, a wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between the external device and the SD card 5110, and allows data to be read from and written to the memory chip 5114.

[0208] FIG. 25(D) is a schematic diagram of the appearance of the SSD, and FIG. 25(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. On the substrate 5153, a storage device and a circuit for driving the storage device are provided. For example, a memory chip 5154, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. The memory chip 5154 incorporates the memory cell array 2610, word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. described in Embodiment 3. By providing a memory chip 5154 on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, etc. Note that the circuit configurations of the memory chip 5154, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and may be appropriately changed according to the situation or circumstances. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, etc. Note that the circuit configurations of the memory chip 5154, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and may be appropriately changed according to the situation or circumstances. That is, they are not limited to the above description, and may be appropriately changed according to the situation or circumstances. For example, the controller ​A memory that functions as a work memory may also be provided in the - latch 5156.

[0209] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. It can be.

[0210] (Embodiment 6) In this embodiment, an example of an electronic device to which the storage device of the above embodiment can be applied will be described. will be described.

[0211] <Notebook personal computer> FIG. 26(A) shows a notebook personal computer, which includes a housing 5401, a display unit 540 2, a keyboard 5403, a pointing device 5404, etc. One aspect of the present invention The storage device can be provided in a notebook personal computer.

[0212] <Smartwatch> FIG. 26(B) shows a smartwatch, which is a type of wearable terminal, and includes a housing 5901 , a display unit 5902, operation buttons 5903, operating elements 5904, a band 5905, etc. . One aspect of the storage device of the present invention can be provided in a smartwatch. Also, the display unit 5902 may use a display device with a function as a position input device. Also, the function as a position input device can be added by providing a touch panel on the display device. It can be done. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. Also, the operation button 5903 includes a power switch for starting the smartwatch, a button for operating the application tion of the smartwatch, a volume adjustment button, or a button for turning on or off the display unit 5902. It can be equipped with any of the switches to be operated. Also, in the smartwatch shown in Fig. 26(B), the number of operation buttons 5903 is shown as two, but the number of operation buttons that the smartwatch has is not limited to this. Also, the operator 5904 functions as a rheostat for adjusting the time of the smartwatch. Also, the operator 5904 can be used as an input interface for operating the applications of the smartwatch, in addition to time adjustment. Note that in the smartwatch shown in Fig. 26(B), it has a configuration with the operator 5904, but it is not limited to this, and it may have a configuration without the operator 5904.

[0213] <Video camera> Fig. 26(C) shows a video camera, which has a first housing 5801, a second housing 5802, a display unit 5803, operation keys 5804, a lens 5805, a connection part 5806, etc. One aspect of the present invention, a storage device can be provided in the video camera. The operation keys 5804 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. And the first housing 5801 and the second housing 5802 are connected by the connection part 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection part 5806. The video on the display unit 5803 may be switched

[0214] <Mobile phone> Fig. 26(D) shows a mobile phone having the functions of an information terminal, which has a housing 5501, a display unit 5502, a microphone 5503, a speaker 5504, and A memory device of this kind can be provided in a mobile phone. Also, a display device with a function as a position input device may be used for the display unit 5502. Further, the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. Also, the operation button 5505 may be provided with any one of a power switch for starting the mobile phone, a button for operating an application of the mobile phone, a volume adjustment button, or a switch for turning on or off the display unit 5502.

[0215] Also, in the mobile phone shown in FIG. 26(D), the number of operation buttons 5505 is shown as two, but the number of operation buttons of the mobile phone is not limited to this. Also, although not shown, the mobile phone shown in FIG. 26(D) may have a configuration having a flashlight or a light emitting device for illumination use.

[0216] <Television device> FIG. 26(E) is a perspective view showing a television device. The television device includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), and the like. A memory device according to one aspect of the present invention can be provided in the television device. It is possible. The television device can incorporate a large screen, for example, 50 inches or more, or 100 inches or more of the display unit 9001.

[0217] <Mobile body> The above-described display device can also be applied to the vicinity of the driver's seat of an automobile, which is a mobile body.

[0218] For example, FIG. 26(F) is a diagram showing the vicinity of the windshield in the interior of an automobile. In FIG. 26(F), in addition to the display panels 5701, 5 702, and 5703 attached to the dashboard, the display panel 5704 attached to the pillar is illustrated here.

[0219] The display panels 5701 to 5703 can provide various information such as navigation information, speedometer - or tachometer, mileage, fuel supply amount, gear state, air conditioner settings, and other various information The display items and layout displayed on the display panel, etc. can be appropriately changed according to the user's preference, and it is possible to enhance the designability The display panels 5701 to 5703 can also be used as lighting devices as well.

[0220] The display panel 5704 can project the video from the imaging means provided on the vehicle body, thereby complementing the visual field (blind spot) blocked by the pillar. That is, by displaying the image from the imaging means provided outside the automobile, the blind spot can be compensated for and the safety can be enhanced In addition, by projecting the video that complements the invisible part, it is possible to perform a safety check more naturally without a sense of discomfort The display panel 5704 can also be used as a lighting device as well. ​

[0221] A memory device according to one aspect of the present invention can be provided in a moving body. The memory device according to one aspect of the present invention can be used, for example, for a frame memory that temporarily stores image data used when displaying an image on display panels 5701 to 5704, or a memory device that stores a program for driving a system of the moving body. Although not shown, the electronic devices shown in FIGS. 26(A) to (C), (E), and (F) may have a configuration including a microphone and a speaker. With this configuration, for example, a voice input function can be added to the above-described electronic device.

[0222] Although not shown, the electronic devices shown in FIGS. 26(A), (B), (D) to (F) may have a configuration including a camera.

[0223]

[0224] Although not shown, the electronic devices shown in FIGS. 26(A) to (F) may have a configuration including a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays, etc.) inside the housing. In particular, by providing a detection device having sensors for detecting inclination such as a gyro and an acceleration sensor in the mobile phone shown in FIG. 26(D), the orientation of the mobile phone (which direction the mobile phone is facing with respect to the vertical direction) can be determined, and the screen display of the display unit 5502 can be automatically switched according to the orientation of the mobile phone.

[0225] Although not shown, the electronic devices shown in FIGS. 26(A) to (F) may have a configuration including fingerprint, vein,​​​​​​​​​​​​​ It may also be configured to include a device that acquires biological information such as an iris or a voiceprint. By applying this configuration, an electronic device with a biometric authentication function can be realized.

[0226] In addition, as the display unit of the electronic device shown in FIGS. 26(A) to (F), a flexible base material may be used. Specifically, the display unit may be configured such that transistors, capacitor elements, display elements, etc. are provided on a flexible base material. By applying this configuration, not only a housing having a flat surface like the electronic device shown in FIGS. 26(A) to (F), but also an electronic device with a housing having a curved surface can be realized.

[0227] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0228] (Supplementary Note Regarding the Description in this Specification, etc.) Regarding the description of each configuration in the above embodiments, the following supplementary note is provided.

[0229] <Supplementary Note Regarding One Aspect of the Present Invention Described in the Embodiment> The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0230] Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with at least one of the content described in another part of the same embodiment (even part of the content) and the content described in one or more other embodiments (even part of the content). ​

[0231] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0232] Note that the figure (even a part thereof) described in one embodiment can be combined with another part of that figure with another figure (even a part thereof) described in that embodiment, and with at least one figure described in one or more other embodiments (even a part thereof) to form even more figures.

[0233] <Appendix regarding ordinal numbers> In this specification and the like, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of components. Therefore, they do not limit the number of components. Also they do not limit the order of components. Also, for example, a component referred to as "first" in one of the embodiments of this specification and the like may be a component referred to as "second" in other embodiments or in the claims. Also, for example, a component referred to as "first" in one of the embodiments of this specification and the like may be omitted in other embodiments or in the claims.

[0234] <Appendix regarding the description of the drawings> The embodiments are described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention It should not be construed as being limited to the description of the embodiments. In the invention of the embodiments, for parts having the same or similar functions in the configuration, the same reference numerals are used commonly among different drawings, and repeated descriptions thereof are omitted.

[0235] Also, in this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. The positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, terms indicating arrangements are not limited to the descriptions

[0236] given in the specification and can be appropriately rephrased according to the situation. Also, the terms "above" and "below" do not limit the positional relationship of components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed directly in contact with

[0237] insulating layer A, and those including other components between insulating layer A and electrode B are not excluded. Also, in the drawings, the size, layer thickness, or area is shown arbitrarily for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity and are not limited to the shapes or values shown in the drawings.

[0238] For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0239] In the drawings, the same elements, elements having similar functions, elements of the same material, or elements formed simultaneously may be given the same reference numerals, and repeated descriptions thereof may be omitted. When explaining the connection relationship of transistors in this specification and the like, one of the source and the drain is expressed as "one of the source or the drain" (or the first electrode, or the first terminal), and the other of the source and the drain is expressed as "the other of the source or the drain" (or the second electrode, or the second terminal). This is because the source and the drain of a transistor

[0240] <Supplementary Note Regarding Descriptions That Can Be Reworded> change depending on the structure or operating conditions of the transistor. Regarding the names of the source and the drain of a transistor, they can be appropriately rephrased according to the situation, such as the source (drain) terminal or the source (drain) electrode. In this specification and the like, when referring to two terminals other than the gate, they may be called the first terminal and the second terminal, or the third terminal and the fourth terminal. In this specification and the like, the channel formation region refers to the region where a channel is formed by applying a potential to the gate, and when this region is formed, current can flow between the source and the drain. Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain are considered to be interchangeable. When there are two or more gates in the transistors described in this specification and the like (this configuration ... ... ...

[0241] Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes during circuit operation. For this reason, in this specification and the like, the terms source and drain are considered to be interchangeable. ... ...

[0242] When the transistors described in this specification and the like have two or more gates (this configuration may be referred to as a dual-gate structure, and those gates may be called the first gate and the second gate, or may be called the front gate and the back gate. In particular, the term "front gate" can simply be mutually interchanged with the term "gate". Also, the term "back gate" can simply be mutually interchanged with the term "gate". Note that the bottom gate refers to a terminal formed prior to the channel formation region during the fabrication of a transistor, and the "top gate" refers to a terminal formed after the channel formation region during the fabrication of a transistor. Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring",

[0243] and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and " wirings" are integrally formed. Also, in this specification and the like, voltage and potential can be appropriately interchanged. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground potential (ground potential), the voltage can be interchanged with the potential. The ground potential does not necessarily

[0244] mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to a wiring or the like may be changed. Also, in this specification and the like, terms such as "film" and "layer" can, in some cases or depending on the situation, be mutually interchanged. For example, the term "conductive layer" can be changed to "conductive film".

[0245] film", etc. It may be possible to change it to the term "electrical film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases or depending on the situation, it may be possible to replace it with another term without using words such as "film" or "layer". For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0246] In this specification, etc., terms such as "wiring", "signal line", and "power supply line" may, in some cases or depending on the situation, be interchangeable with each other. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to terms such as "power supply line". Also conversely, terms such as "signal line" and "power supply line" may be changed to the term "wiring". Terms such as "power supply line" may be changed to terms such as "signal line". Also conversely, terms such as "signal line" may be changed to terms such as "power supply line". Also, the term "potential" applied to the wiring may, in some cases or depending on the situation, be changed to a term such as "signal". Also conversely, terms such as "signal" may be changed to the term "potential".

[0247] <Appendix on the Definition of Terms> Hereinafter, the definitions of the terms mentioned in the above embodiments will be described.

[0248] <<Regarding Impurities in Semiconductors>> Impurities in semiconductors refer to, for example, components other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic% are impurities. When impurities are included, for example, DOS (Density of States) may be formed in the semiconductor, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, for example, the incorporation of impurities such as hydrogen may form oxygen deficiencies. Also, when the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, etc., excluding oxygen and hydrogen.

[0249] <<Regarding Switches>> In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to allow current to flow. Or, a switch refers to a device that has a function of selecting and switching the path through which current flows.

[0250] As an example, an electrical switch or a mechanical switch can be used. That is, the switch only needs to be able to control current and is not limited to a specific type.

[0251] ​​​As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) di odes, MIS (Metal Insulator Semiconductor) di odes, transistor connected in diode configuration, etc.), or logic circuits combining these and the like.

[0252] When a transistor is used as a switch, the "conducting state" of the transistor means a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conducting state" of the transistor means a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When operating the transistor simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0253] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology, such as a digital micromirror device (DMD). The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0254] <<Regarding Connections>> In this specification and the like, when it is described that X and Y are connected, it shall include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Therefore, a predetermined connection relationship, for example, in a figure or It is not limited to the connection relationships shown in the article, and also includes those other than the connection relationships shown in the figures or the article. Let it be so.

[0255] X, Y, etc. used here are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals , conductive films, layers, etc.).

[0256] As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitor element, an inductor, a resistor element, a diode , a display element, a light-emitting element, a load, etc.) that enables the electrical connection between X and Y can be connected by one or more between X and Y. Note that the switch has a function of controlling on / off. That is, the switch becomes a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Let it be so. Let it be so.

[0257] As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit ( a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal such as), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or the amount of current, an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected by one or more between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. Let it be so.

[0258] In addition, when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, connected with another element or another circuit interposed therebetween), the case where X and Y are functionally connected (that is, functionally connected with another circuit interposed therebetween), and the case where X and Y are directly connected (that is, connected without interposing another element or another circuit therebetween). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as the case where it is only explicitly described that they are connected continuously. For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, it can be expressed as "X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, " The source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected to each other, and are electrically connected in the order of the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y, and then to X." (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected to each other, and are electrically connected in the order of the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y, and then to X." In addition, when it is explicitly described that X and Y are electrically connected, it is considered to be the same as the case where it is only explicitly described that they are connected continuously. That is, when it is explicitly described that they are electrically connected, it is considered to be the same as the case where it is only explicitly described that they are connected continuously.

[0259] In addition, for example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. It can be expressed as follows.

[0260] For example, it can be expressed as "X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, " The source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected to each other, and are electrically connected in the order of the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y, and then to X." (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected to each other, and are electrically connected in the order of the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y, and then to X." That is, when it is explicitly described that they are electrically connected, it is considered to be the same as the case where it is only explicitly described that they are connected continuously. The terminal of 1 (such as the terminal) is electrically connected to X, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y. X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. It can be expressed as "". Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor. X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order." It can be expressed as such. By using an expression method similar to these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished, and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Even when components that are independent on the circuit diagram are shown as being electrically connected, there are cases where one component has the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode components. Therefore, in this specification, electrical connection includes such cases where one conductive film has the functions of multiple components within its scope. <<Regarding parallel and perpendicular>>

[0261]

[0262] ​​​​​​​​​​​​​​In this specification, "parallel" means a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" means a state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" means a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

Explanation of Signs

[0263] MC[1] Memory cell MC[2] Memory cell MC[n] Memory cell MC[1,1] Memory cell MC[j,1] Memory cell MC[n,1] Memory cell MC[1,i] Memory cell MC[j,i] Memory cell MC[n,i] Memory cell MC[1,m] Memory cell MC[j,m] Memory cell MC[n,m] Memory cell WWL[1] Wiring WWL[2] Wiring WWL[j] Wiring WWL[n] Wiring RWL[1] Wiring RWL[2] Wiring RWL[j] Wiring RWL[n] Wiring WBL Wiring WBL[1] Wiring WBL[i] Wiring WBL[m] Wiring RBL Wiring RBL[1] Wiring RBL[i] Wiring RBL[m] wiring BGL wiring BGL[1] wiring BGL[i] wiring BGL[m] wiring WTr transistor RTr transistor CS capacitor element N1 node N2 node PG conductor WWL wiring RWL wiring ER wiring HL region AR region SD1 region SD2 region 100 laminate 101A insulator 101B insulator 101C insulator 101D insulator 101E insulator 102 insulator 103 insulator 104 insulator 105 insulator 131A conductor 131B conductor 132A conductor 132B conductor 133 conductor 133a conductor 133b conductor 133c conductor 134 conductor 151 semiconductor 151a region 151b region 151c region 152 semiconductor 153 semiconductor 153a semiconductor 153b semiconductor 181A region 181B region 182A region 182B region 183A region 183B area 191 opening 192A recess 192B recess 193A recess 193B recess 194A recess 194B recess 194C recess 1191 ALU 1192 ALU controller 1193 instruction decoder 1194 interrupt controller 1195 timing controller 1196 register 1197 register controller 1198 bus interface 1199 ROM 1189 ROM interface 1190 substrate 1700 substrate 1701 element isolation layer 1712 conductor 1730 conductor 1790 gate electrode 1792 well 1793 channel formation region 1794 low-concentration impurity region 1795 high-concentration impurity region 1796 conductive region 1797 gate insulating film 1798 sidewall insulating layer 1799 sidewall insulating layer 2600 memory device 2601 peripheral circuit 2610 memory cell array 2621 row decoder 2622 word line driver circuit 2630 bit line driver circuit 2631 column decoder 2632 precharge circuit 2633 sense amplifier 2634 Writing Circuit 2640 Output Circuit 2660 Control Logic Circuit 5100 USB Memory 5101 Housing 5102 Cap 5103 USB Connector 5104 Substrate 5105 Memory Chip 5106 Controller Chip 5110 SD Card 5111 Housing 5112 Connector 5113 Substrate 5114 Memory Chip 5115 Controller Chip 5150 SSD 5151 Housing 5152 Connector 5153 Substrate 5154 Memory Chip 5155 Memory Chip 5156 Controller Chip 5401 Housing 5402 Display Unit 5403 Keyboard 5404 Pointing Device 5501 Housing 5502 Display Unit 5503 Microphone 5504 Speaker 5505 Operation Button 5701 Display Panel 5702 Display Panel 5703 Display Panel 5704 Display Panel 5801 First Housing 5802 Second Housing 5803 Display Unit 5804 Operation Key 5805 Lens 5806 Connection Part 5901 Housing 5902 Display Unit 5903 Operation Button 5904 Operator 5905 Band 9000 Housing 9001 Display Unit 9003 Speaker 9005 Operation Key 9006 Connection Terminal 9007 Sensor

Claims

【Claim 1】 A semiconductor device having a memory cell, wherein the memory cell includes: a first conductor; a first oxide semiconductor having a region surrounding the first conductor via a first insulator; a second oxide semiconductor having a region surrounding the first oxide semiconductor via a second insulator; a second conductor having a region in contact with the second oxide semiconductor and a region surrounding the second oxide semiconductor; a third conductor having a region surrounding the second conductor via a third insulator; a fourth conductor having a region surrounding the second oxide semiconductor via the third insulator; and a fifth conductor having a region in contact with the fourth conductor and a region surrounding the fourth conductor; wherein the first conductor has a region that functions as a first gate electrode of a first transistor; the first oxide semiconductor has a region that functions as a channel formation region of the first transistor; the second oxide semiconductor has a region that functions as a channel formation region of a second transistor; the second conductor has a region that functions as a second gate electrode of the first transistor and a region that functions as one electrode of a capacitor element; the third conductor has a region that functions as the other electrode of the capacitor element; the fourth conductor has a function of serving as a second gate electrode of the second transistor; and the second conductor has a region located above or below the fourth conductor.

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