Semiconductor drive device and power conversion device

Abstract

A semiconductor driving device (100) of the present disclosure comprises: a timing generation unit (12) which generates respective gate-on command signals for a plurality of gate terminals on the basis of an on-off command signal from the outside; a gate command waveform generation unit (13) which generates, on the basis of the gate-on command signal, a first gate command waveform corresponding to at least one first gate terminal and a second gate command waveform corresponding to at least one second gate terminal among the plurality of gate terminals, and controls any one or both waveforms among the first gate command waveform and the second gate command waveform during any one or both of a transition from a non-conduction state to a conduction state and a transition from the conduction state to the non-conduction state of a multi-gate semiconductor switching element (20); and a signal amplification unit (14) which adopts, as an input waveform, any one or both of the first gate command waveform and the second gate command waveform and amplifies the input waveform so that an output waveform follows the input waveform.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor drive device and a power conversion device.

Background Art

[0002] As one of the measures against global warming, expectations for energy saving by power electronics technology are increasing. In particular, towards higher efficiency of power conversion devices realized by the operation of turning on / off a plurality of semiconductor switching elements, reduction of the loss of semiconductor switching elements constituting the power conversion device is required.

[0003] Typical semiconductor switching elements include voltage-driven semiconductor switching elements such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and a diode arranged in parallel with the semiconductor switching element to perform a rectifying function.

[0004] As a means for improving the trade-off between the conduction loss and the switching loss of a semiconductor switching element, there is an application of a double-gate type semiconductor switching element having two independent gate terminals. The double-gate type semiconductor switching element is characterized in that, for example, during a turn-off operation, after one gate terminal is turned off sufficiently ahead of the other gate terminal, the other gate terminal is controlled to be turned off. According to such a control method, since the turn-off operation is performed with some carriers in the double-gate type semiconductor switching element pulled out in advance, the carrier extraction time can be shortened, so that the turn-off loss can be reduced.

[0005] Furthermore, by shortening the time difference between the ON / OFF operations of the two gate terminals so that the timing of turning the other gate terminal ON / OFF after turning one gate terminal ON / OFF falls within the switching operation period, it is possible to transiently vary the switching characteristics, that is, to obtain the active gate effect.

[0006] For example, as an example of the active gate effect of a single-gate semiconductor switching element, there is a method of switching the gate resistance during the turn-on operation period. By applying such a switching method, it is known to improve the trade-off relationship between the turn-on loss of the semiconductor switching element and the rate of change of the recovery voltage dV / dt of the diode in the antiparallel arm. On the other hand, in a double-gate semiconductor switching element, an effect similar to the above-described switching method can be obtained by driving with a time difference at the two gate terminals.

[0007] As a method of driving a double-gate conductor switching element with a time difference applied to the two gate terminals, for example, in the semiconductor device and the control method of the semiconductor device disclosed in Patent Document 1, a delay unit that delays the signal input to the control signal input terminal by a delay time L, and a logical product unit that calculates the logical product of the signal input to the control signal input terminal and the signal delayed by the delay unit are provided, and a configuration in which the output of the delay unit and the output of the logical product unit are connected to each of the two gate terminals of the double-gate IGBT is shown. In the configuration of the semiconductor device disclosed in Patent Document 1, when the time difference of the voltage waveforms applied to the two gate terminals is set short, the above-described active gate effect can be obtained.

[0008] Also, in the semiconductor device and the method of driving the semiconductor device described in Patent Document 2, when transitioning from the non-conducting state to the conducting state of a double-gate IGBT, a voltage equal to or higher than the threshold voltage is applied to the first gate terminal a first predetermined time ahead of the second gate terminal, and when transitioning from the conducting state to the non-conducting state, a voltage lower than the threshold voltage is applied to the second gate terminal a second predetermined time ahead of the first gate terminal. A method is disclosed for variably controlling the first predetermined time and the second predetermined time so that the time change of the collector voltage generated when transitioning from the non-conducting state to the conducting state and when transitioning from the conducting state to the non-conducting state is substantially constant.

[0009] In the above configuration, when the time difference between the voltage waveforms applied to the two gate electrodes is set short, the voltage change rate dV / dt due to noise, the load current, and the robustness against temperature and the like of the surge voltage can be improved by changing the time difference of the voltage waveforms.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0011] However, for example, in the semiconductor device and the control method of the semiconductor device described in Patent Document 1, when trying to obtain the above-described active gate effect by setting a short time difference so that the timing of turning on / off the other gate terminal after turning on / off one gate terminal of the double gate type IGBT is within the switching operation period, due to the control signal input terminal being delayed within the switching operation period turning on, there is a first problem that noise and surge voltage increase, and in the driving method of turning on the control signal input terminal delayed within the switching operation period, there is a second problem of robustness against various conditions such as load current, temperature, and gate threshold voltage variation, which is a general problem of active gate driving.

[0012] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor driving device and a power conversion device having excellent robustness that improve the trade-off between noise and surge voltage generated during the switching operation of a multi-gate type semiconductor switching element and switching loss.

Means for Solving the Problems

[0013] The semiconductor driving device according to the present disclosure is a semiconductor driving device that drives a multi-gate type semiconductor switching element having a plurality of gate terminals, a timing generation unit that turns on / off a gate on command signal for each of the plurality of gate terminals based on an on / off command signal from the outside, generating a first gate command waveform corresponding to at least one first gate terminal and a second gate command waveform corresponding to at least one second gate terminal among the plurality of gate terminals based on the on / off of the gate on command signal, and in either or both of the transition from the non-conducting state to the conducting state and the transition from the conducting state to the non-conducting state of the multi-gate type semiconductor switching element, either or both of the first gate command waveform and the second gate command waveform Output a gate command waveform generation unit that performs A signal amplification unit that amplifies the input waveform so that the output waveform follows the input waveform, using either one or both of the first gate command waveform and the second gate command waveform as the input waveform. The first gate command waveform and the second gate command waveform have the same waveform shape with a preset time difference.

[0014] The power conversion device according to the present disclosure Has a multi-gate type semiconductor switching element as a semiconductor switching element, and includes any one of an inverter device that converts DC power into AC power, a boost converter device that boosts the voltage of DC power, a buck converter device that steps down the voltage of DC power, an AC-DC converter device that converts AC power into DC power, a boost type inverter device that includes the boost converter device and the inverter device, and a buck type inverter device that includes the buck converter device and the inverter device, A semiconductor drive device that drives the above-described multi-gate type semiconductor switching element, And is provided with.

Advantages of the Invention

[0015] According to the semiconductor drive device and the power conversion device using the semiconductor drive device according to the present disclosure, since the gate drive of the double-gate type semiconductor switching element is realized by feed-forward control that follows the gate command waveform, it is possible to freely suppress the change rate of the gate terminal voltage. As a result, even in the case of driving with a short-time time difference between the gate terminals of the double-gate type semiconductor switching element, noise and surge voltage can be suppressed.

Brief Description of the Drawings

[0016]

Figure 1

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Embodiments for Carrying Out the Invention

[0017] Embodiment 1. Hereinafter, Embodiment 1 will be described with reference to the drawings. In the following description, the same reference numerals are given to the same components or corresponding components. Note that elements such as an isolator component for insulating an on-off command signal from the upper level input to the semiconductor drive device 100, for example, a photocoupler, an optical fiber module, a pulse transformer, etc., and a clamp diode for voltage protection of the gate and a short-circuit protection circuit are omitted from the description.

[0018] <Configuration of the Semiconductor Drive Device According to Embodiment 1> FIG. 1 is a block diagram showing the configuration of a semiconductor drive device 100 according to Embodiment 1. In FIG. 1, as an example of the semiconductor drive device 100, a configuration for driving an IGBT module 25 combining a double-gate IGBT 20 and a diode 21 is shown. The drive voltage applied to the gate terminal of the double-gate IGBT 20, that is, the gate voltage Vge, has a positive voltage VP and a negative voltage VN with respect to the emitter potential FG.

[0019] The semiconductor drive device 100 according to Embodiment 1 includes a timing generation unit 12, a gate command waveform generation unit 13, a signal amplification unit 14, and a drive voltage generation unit 15. The gate command waveform generation unit 13 further includes a first gate command waveform generation unit 13A and a second gate command waveform generation unit 13B. The signal amplification unit 14 further includes a first signal amplification unit 14A and a second signal amplification unit 14B.

[0020] Based on the on / off command signal Sgd input from outside the semiconductor drive device 100, the timing generation unit 12 generates the drive timing of the first gate terminal Gs, which is the switching gate of the double-gate IGBT 20, and the drive timing of the second gate terminal Gc, which is the control gate of the double-gate IGBT 20, and outputs them as a first gate on command signal Sg1 and a second gate on command signal Sg2. The first gate on command signal Sg1 is a signal corresponding to the first gate terminal Gs of the double-gate IGBT 20, and the second gate on command signal Sg2 is a signal corresponding to the second gate terminal Gc of the double-gate IGBT 20.

[0021] Based on the first gate on command signal Sg1 output from the timing generation unit 12, the gate command waveform generation unit 13 generates a first gate command waveform Vgr1 in the first gate command waveform generation unit 13A. Also, based on the second gate on command signal Sg2 output from the timing generation unit 12, the gate command waveform generation unit 13 generates a second gate command waveform Vgr2 in the second gate command waveform generation unit 13B.

[0022] The signal amplification unit 14 amplifies the first gate command waveform Vgr1 and the second gate command waveform Vgr2 output from the gate command waveform generation unit 13, and outputs them to the double-gate IGBT 20 provided outside the semiconductor drive device 100. That is, the first signal amplification unit 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS, and the second signal amplification unit 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC to the double-gate IGBT 20 provided outside the semiconductor drive device 100. The first gate voltage VgeS is applied to the first gate terminal Gs of the double-gate IGBT 20, and the second gate voltage VgeC is applied to the second gate terminal Gc of the double-gate IGBT 20, respectively.

[0023] In the semiconductor drive device 100 according to the first embodiment, the gate command waveform generation unit 13 generates a gate command waveform in a desired waveform in advance, and the signal amplification unit 14 amplifies the gate command waveform, so that the double-gate IGBT 20 follows the gate command waveform, that is, the gate drive of the double-gate semiconductor switching element is realized by feedforward control. This is a characteristic point.

[0024] <Configuration of each part of the semiconductor drive device according to the first embodiment> The specific configurations of each part constituting the semiconductor drive device 100 according to the first embodiment, that is, the timing generation unit 12, the gate command waveform generation unit 13, and the signal amplification unit 14, will be described below. Note that each part is not limited to the illustrated configuration, and can be combined with the illustrated configuration, components can be added, or it can be configured with another configuration that realizes the same function.

[0025] <Specific configuration example of the signal amplification unit 14> Figures 2A, 2B, 2C, and 2D are circuit diagrams showing an example of the specific configurations of a first signal amplification unit 14A and a second signal amplification unit 14B in a signal amplification unit 14 of a semiconductor drive device 100 according to Embodiment 1. In Figures 2A, 2B, 2C, and 2D, the description of the base resistance is omitted for simplification of the configuration, but the base resistance may be added as necessary. The signal amplification unit 14 amplifies an input waveform such that an output waveform follows the input waveform, using either one or both of a first gate command waveform and a second gate command waveform as the input waveform.

[0026] The above "amplifies the input waveform such that the output waveform follows the input waveform." will be described below. As the semiconductor drive device 100, it is desired to apply a gate command waveform, which is an input signal, to the gate terminal. However, when the load capacitance connected to the semiconductor drive device 100 is large, the output voltage waveform will differ from the waveform of the input signal. For example, in the gate command waveform, a mirror period (a terraced stagnation period) tends to appear due to dynamic changes in the load capacitance. However, the signal amplification unit 14 operates so as to pass a large current during the mirror period and match, that is, follow, the gate command waveform. Conversely, as the load impedance increases, the signal amplification unit 14 reduces the current to match, that is, follow, the gate command waveform. For example, if the signal amplification unit 14 has the configuration of Figure 2A, the current is automatically adjusted so that the output voltage on the right side of Figure 2A matches the base voltage on the left side of Figure 2A. Such adjustment can be said to amplify the input waveform such that the output waveform follows the input waveform. Therefore, the voltage amplification factor of the signal amplification unit 14 may be 1.

[0027] Figure 2A is a circuit diagram showing the configuration of a signal amplification unit 14P. The signal amplification unit 14P is configured by a complementary emitter follower circuit including an NPN transistor Q1 and a PNP transistor Q2. In the constant voltage drive circuit of the comparative example shown in Figure 12, which will be described later, the gate current was limited by a gate resistance. In the configuration of the signal amplification unit 14P of the semiconductor drive device 100 according to Embodiment 1, the gate current is automatically adjusted so that the output waveform follows the input voltage waveform.

[0028] In the signal amplification unit 14P, the output voltage decreases only by the threshold voltages of the NPN transistor Q1 and the PNP transistor Q2, and the maximum value of the gate current is limited by the current driving performance of the NPN transistor Q1 and the PNP transistor Q2. Therefore, there may be a waveform difference between the input voltage waveform and the output waveform. As a method for preventing the defect that distortion of the output waveform occurs due to the threshold voltages of the NPN transistor Q1 and the PNP transistor Q2, a known method of adding a diode for compensating the threshold voltage to the base terminal may be applied.

[0029] FIG. 2B is a circuit diagram showing the configuration of the signal amplification unit 14Q. The signal amplification unit 14Q is composed of complementary emitter follower circuits respectively constituted by an NPN transistor Q1 and a PNP transistor Q2 and an NPN transistor Q3 and a PNP transistor Q4. The above-described signal amplification unit 14P is constituted by a single-stage complementary emitter follower circuit, whereas the signal amplification unit 14Q is characterized in that it is constituted by a two-stage complementary emitter follower circuit. According to the configuration of the signal amplification unit 14Q, there is an effect of further increasing the current driving force as the signal amplification unit 14.

[0030] FIG. 2C is a circuit diagram showing the configuration of the signal amplification unit 14R. The signal amplification unit 14R is configured by adding a voltage follower circuit using an operational amplifier OP1 (operational amplifier) in front of the complementary emitter follower circuit constituted by the NPN transistor Q1 and the PNP transistor Q2. According to the configuration of the signal amplification unit 14R, there is an effect of preventing the input voltage waveform from changing due to current consumption as the base currents of the NPN transistor Q1 and the PNP transistor Q2 in the subsequent complementary emitter follower circuit.

[0031] FIG. 2D is a circuit diagram showing the configuration of the signal amplification unit 14S. The signal amplification unit 14S is configured by adding a gate resistor R2 to the off side of a complementary emitter follower circuit composed of an NPN transistor Q1 and a PNP transistor Q2. According to the configuration of the signal amplification unit 14S, by applying the signal amplification unit 14S during a high turn-on operation of the effects exhibited by the semiconductor drive device 100 according to Embodiment 1, the configuration of the gate command waveform generation unit 13 can be simplified by using conventional constant voltage driving during the turn-off operation.

[0032] <Specific Configuration Example I of Gate Command Waveform Generation Unit 13> FIGS. 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing an example of the specific configuration of the first gate command waveform generation unit 13A and the second gate command waveform generation unit 13B in the gate command waveform generation unit 13 of the semiconductor drive device 100 according to Embodiment 1. The gate command waveform generation unit 13 is characterized by controlling the waveform by controlling either one or both of the differential values of the first gate command waveform and the differential value of the second gate command waveform.

[0033] FIG. 3A is a circuit diagram showing the gate command waveform generation unit 13P. The gate command waveform generation unit 13P generates, as a gate command waveform, a CR charge / discharge waveform by a resistor R3 and a capacitor C1, that is, a waveform in which the second derivative value of the voltage is less than zero (d 2 V / dt 2 <0). The resistor R4 serves as a base resistor that limits the base current of the subsequent signal amplification unit 14. Note that at least a part of at least one gate command waveform may include a charging voltage shape or a discharging voltage shape generated by a capacitor and a resistor.

[0034] FIG. 3B is a circuit diagram showing the gate command waveform generation unit 13Q. The gate command waveform generation unit 13Q has a configuration in which constant current diodes DS1 and DS2 are used instead of the resistor R3 of the gate command waveform generation unit 13P shown in FIG. 3A. The gate command waveform generation unit 13Q generates a ramp-type waveform with a constant slope, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0).

[0035] Figure 3C is a circuit diagram showing the gate command waveform generation unit 13R. The gate command waveform generation unit 13R has a configuration in which a Zener diode DZ1, a Zener diode DZ2, and a resistor R5 are provided in parallel to the resistor R3 of the gate command waveform generation unit 13P shown in FIG. 3A. The gate command waveform generation unit 13R functions to increase the slope of the gate command waveform by increasing the charging current and the discharging current of the capacitor C1 immediately after the start of turn-on and immediately after the start of turn-off.

[0036] Figure 3D is a circuit diagram showing the gate command waveform generation unit 13S. The gate command waveform generation unit 13S has a configuration in which the same changes as the changes from the gate command waveform generation unit 13P shown in FIG. 3A to the gate command waveform generation unit 13R shown in FIG. 3C are applied to the gate command waveform generation unit 13Q shown in FIG. 3B. That is, a configuration in which a Zener diode DZ1, a Zener diode DZ2, and a resistor R5 are provided in parallel to the constant current diodes DS1 and DS2 of the gate command waveform generation unit 13Q shown in FIG. 3B.

[0037] Figure 3E is a circuit diagram showing the gate command waveform generation unit 13T. The gate command waveform generation unit 13T is configured to make the gate command waveform rectangular during the turn-off operation by adding a diode D2 and a resistor R5 in parallel to the resistor R3 of the gate command waveform generation unit 13P shown in FIG. 3A, and to assume a turn-off operation with constant voltage drive in combination with the signal amplification unit 14S shown in FIG. 2D.

[0038] Figure 3F is a circuit diagram showing the gate command waveform generation unit 13U. The gate command waveform generation unit 13U is obtained by applying the same changes as the changes from the gate command waveform generation unit 13P shown in FIG. 3A to the gate command waveform generation unit 13T shown in FIG. 3E to the gate command waveform generation unit 13Q shown in FIG. 3B. That is, a configuration in which a diode D2 and a resistor R5 are added in parallel to the resistor R3 of the gate command waveform generation unit 13P shown in FIG. 3B.

[0039] <Specific Configuration Example II of Gate Command Waveform Generation Unit 13> Each configuration example of the gate command waveform generation unit 13 shown in FIGS. 3A to 3F described above was a configuration using resistors, capacitors, and diodes. On the other hand, each example of the gate command waveform generation unit 13 shown in FIGS. 4A and 4B described below is a configuration example using an operational amplifier (operational amplifier), a comparator, etc.

[0040] FIG. 4A is a circuit diagram showing the gate command waveform generation unit 13V. The gate command waveform generation unit 13V is a configuration combining an inverter circuit INV1, an operational amplifier OP2 (operational amplifier), a resistor R6, a resistor R7, and an integration circuit composed of a capacitor C2. The gate command waveform generation unit 13V has the same waveform as the gate command waveform generation unit 13P shown in FIG. 3B, that is, a ramp-type waveform with a constant slope, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 = 0).

[0041] FIG. 4B is a circuit diagram showing the gate command waveform generation unit 13W. The gate command waveform generation unit 13W includes a window comparator that determines a reference range of VrefL or more and less than VrefH, which is composed of comparators CP1 and CP2, a voltage limiting circuit composed of a Zener diode DZ3 and an NPN transistor Q3, two identical ramp-type waveform generation circuits of a constant current diode DS3, DS4 and a capacitor C3, and a constant current diode DS5, DS6 and a capacitor C4, and a resistor R8 and a resistor R9. The waveform generated by the gate command waveform generation unit 13W can be provided with a terrace-type waveform determined by the Zener voltage of DZ3 in the output ramp-type waveform when the reference ramp-type waveform is within the reference range of VrefL or more and less than VrefH, that is, a waveform in which the first derivative value of the voltage is zero (dV / dt = 0).

[0042] <Operation of the semiconductor drive device according to Embodiment 1> FIG. 5 is a diagram showing an example of a timing chart of each signal representing the operation of the semiconductor drive device 100 according to the first embodiment. As a specific configuration of the gate command waveform generation unit 13 of the semiconductor drive device 100 according to the first embodiment, the gate command waveform generation unit 13P shown in FIG. 3A is applied. The gate command waveform generation unit 13P generates, as a gate command waveform, a CR charge / discharge waveform by the resistor R3 and the capacitor C1, that is, a waveform in which the second derivative value of the voltage is less than zero (d 2 V / dt 2 <0). Note that at least a part of one gate command waveform may include a charging voltage shape or a discharging voltage shape generated by a capacitance and a resistor.

[0043] Each waveform shown in FIG. 5 is, in order from the top, the on / off command signal Sgd, the first gate on command signal Sg1, the second gate on command signal Sg2, the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the first gate voltage VgeS, the second gate voltage VgeC, the collector current Ic, and the collector voltage Vce.

[0044] Hereinafter, the operation of the semiconductor drive device 100 according to the first embodiment will be described with reference to FIG. 5. <Turn-on operation of the semiconductor drive device according to the first embodiment> First, when the on / off command signal Sgd changes from off to on, that is, a series of operations of each signal during the turn-on operation will be described. At time t5, the external on / off command signal Sgd changes from off to on. That is, the on / off command signal Sgd changes from the Lo state to the Hi state. At time t5, based on the on operation of the on / off command signal Sgd, the timing generation unit 12 outputs the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Lo state to the Hi state.

[0045] At time t6, based on the on operation of the on / off command signal Sgd, the timing generation unit 12 outputs the second gate on command signal Sg2. The second gate on command signal Sg2 is output with a preset time with respect to the first gate on command signal Sg1, that is, the time difference of t6 - t5, being delayed.

[0046] At time t5, based on the ON operation of the first gate ON command signal Sg1, the first gate command waveform generation unit 13A generates the first gate command waveform Vgr1. The first gate command waveform Vgr1 rises from time t5. However, since the circuit configuration of the gate command waveform generation unit 13P is applied as the first gate command waveform generation unit 13A, the waveform that limits the voltage increase rate, that is, the waveform in which the second derivative value of the voltage is less than zero (d 2 V / dt 2 <0) is presented.

[0047] At time t6, based on the ON operation of the second gate ON command signal Sg2, the second gate command waveform generation unit 13B generates the second gate command waveform Vgr2. The second gate command waveform Vgr2 rises from time t6. However, since the circuit configuration of the gate command waveform generation unit 13P is applied as the second gate command waveform generation unit 13B, the waveform that limits the voltage increase rate, that is, the waveform in which the second derivative value of the voltage is less than zero (d 2 V / dt 2 <0) is presented. Also, the second gate command waveform Vgr2 is output with a preset time delay with respect to the first gate command waveform Vgr1, that is, the time difference of t6 - t5.

[0048] At time t5, the first signal amplification unit 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and has a waveform that limits the voltage increase rate, that is, the waveform in which the second derivative value of the voltage is less than zero (d 2 V / dt 2 <0) is presented.

[0049] At time t6, the second signal amplification unit 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and has a waveform that limits the voltage increase rate, that is, the waveform in which the second derivative value of the voltage is less than zero (d 2 V / dt 2It exhibits a waveform where <0). Also, the second gate voltage VgeC is output with a preset time delay with respect to the first gate voltage VgeS, that is, the time difference between t6 - t5.

[0050] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double - gate type IGBT20 provided outside the semiconductor drive device 100.

[0051] At time t7 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector current Ic of the double - gate type IGBT20 rises from the zero state before time t7, and at time t8 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth, it becomes a constant value.

[0052] At time t7 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector voltage Vce of the double - gate type IGBT20 decreases from the state of VB + Vf before time t7, and at time t8 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth, it becomes the on - voltage Von which is a constant value. The above is a series of operations of each signal during the turn - on operation when the on - off command signal Sgd changes from off to on.

[0053] <Turn - off operation of the semiconductor drive device according to Embodiment 1> Next, a series of operations of each signal during the turn - off operation when the on - off command signal Sgd changes from on to off will be described.

[0054] At time t9, the external on - off command signal Sgd changes from on to off. That is, the on - off command signal Sgd changes from the Hi state to the Lo state. At time t9, based on the off operation of the on - off command signal Sgd, the timing generation unit 12 turns off the first gate - on command signal Sg1. That is, the first gate - on command signal Sg1 changes from the Hi state to the Lo state.

[0055] At time t10, based on the OFF operation of the on-off command signal Sgd, the timing generation unit 12 turns OFF the second gate-on command signal Sg2. The OFF operation of the second gate-on command signal Sg2 is output with a preset time delay with respect to the OFF operation of the first gate-on command signal Sg1, that is, the time difference of t10 - t9.

[0056] At time t9, based on the OFF operation of the first gate-on command signal Sg1, the first gate command waveform generation unit 13A turns OFF the first gate command waveform Vgr1. The first gate command waveform Vgr1 starts to fall at time t9. However, since the circuit configuration of the gate command waveform generation unit 13P is applied as the first gate command waveform generation unit 13A, the waveform that limits the voltage decrease rate, that is, the waveform whose second derivative value of the voltage is greater than zero (d 2 V / dt 2 >0) is presented.

[0057] At time t10, based on the OFF operation of the second gate-on command signal Sg2, the second gate command waveform generation unit 13B turns OFF the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to fall at time t10. However, since the circuit configuration of the gate command waveform generation unit 13P is applied as the second gate command waveform generation unit 13B, the waveform that limits the voltage decrease rate, that is, the waveform whose second derivative value of the voltage is greater than zero (d 2 V / dt 2 >0) is presented. Also, the OFF operation of the second gate command waveform Vgr2 occurs with a preset time delay with respect to the OFF operation of the first gate command waveform Vgr1, that is, the time difference of t10 - t9.

[0058] At time t9, the first signal amplification unit 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and presents a waveform that limits the voltage decrease rate, that is, the waveform whose second derivative value of the voltage is greater than zero (d 2 V / dt 2 >0).

[0059] At time t10, the second signal amplification unit 14B amplifies the input second gate command waveform Vgr2 and outputs a second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and has a waveform that limits the voltage decrease rate, that is, a waveform in which the second derivative value of the voltage is greater than zero (d 2 V / dt 2 >0). Also, the turn-off operation of the second gate voltage VgeC is delayed and output by a preset time with respect to the turn-off operation of the first gate voltage VgeS, that is, the time difference t10 - t9.

[0060] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor drive device 100.

[0061] At time t10 when the turn-off operation of the second gate on command signal Sg2 starts, the collector current Ic of the double-gate IGBT 20 rises from the previous constant state and becomes zero at time t12 when the second gate voltage VgeC becomes less than the threshold voltage Vth.

[0062] At time t9 when the turn-off operation of the first gate on command signal Sg1 starts, the collector voltage Vce of the double-gate IGBT 20 rises from the previous on voltage Von state and returns to a constant value VB + Vf at time t12 when the second gate voltage VgeC becomes less than the threshold voltage Vth. The above is a series of operations of each signal when the on-off command signal Sgd changes from on to off, that is, during the turn-off operation.

[0063] In the semiconductor drive device 100 according to Embodiment 1, as shown in FIG. 5, waveforms that limit the increase rates of the first gate command waveform Vgr1 and the second gate command waveform Vgr2 during the turn-on operation, that is, waveforms in which the second derivative value of the voltage is less than zero (d 2 V / dt 2By setting <0)>, it becomes possible to suppress an increase in the collector current change rate dIc / dt that occurs when the second gate terminal Gc, which is a control gate, operates in the on state. As a result, noise during the switching operation can be suppressed.

[0064] Also, in the semiconductor drive device 100 according to Embodiment 1, as shown in FIG. 5, a waveform that limits the decrease rate of the first gate command waveform Vgr1 and the second gate command waveform Vgr2 during the turn-off operation, that is, a waveform in which the second derivative value of the voltage is greater than zero (d 2 V / dt 2 >0) is used, it becomes possible to suppress a decrease in the collector current change rate dIc / dt that occurs when the second gate terminal Gc, which is a control gate, operates in the off state. As a result, the surge voltage can be suppressed. Furthermore, by making the CR time constants of the first gate command waveform Vgr1 and the second gate command waveform Vgr2, which are two gate command waveforms, the same, the effect of improving the robustness described above is achieved.

[0065] Comparative example. FIG. 12 is an example of a constant voltage drive circuit that realizes the constant voltage drive method applied in the semiconductor drive device according to the comparative example, and FIG. 13 shows a schematic waveform when the double gate type IGBT 20 is driven by giving a short time difference to two gate voltage waveforms in the semiconductor drive device according to the comparative example. Hereinafter, the problems in the semiconductor drive device according to the comparative example will be described.

[0066] The configuration of the semiconductor drive device according to the comparative example is disclosed in, for example, Patent Document 1. In the semiconductor drive device according to the comparative example, when trying to obtain the above-described active gate effect by setting a short time difference so that the timing of turning on / off one gate terminal of the double gate type IGBT 20 and then turning on / off the other gate terminal is within the switching operation period, the following two problems occur.

[0067] First, the first problem will be described. The constant-voltage drive circuit shown in FIG. 12 is configured such that a rectangular wave signal input from the left side of FIG. 12 is current-amplified by a buffer circuit composed of an NPN transistor Q1 and a PNP transistor Q2 via a base resistor R10. In the constant-voltage drive method such as the comparative example, it is a drive method in which the gate current value is limited by the gate resistor R11 and the gate resistor R12.

[0068] FIG. 13 shows a schematic waveform when a semiconductor drive device according to a comparative example is operated by a constant-voltage drive method and the double-gate IGBT 20 is driven by giving a short time difference to two gate voltage waveforms. In FIG. 13, the drive waveform of the single-gate IGBT in the comparative example is represented by a broken line, and the drive waveform of the double-gate IGBT 20 in the comparative example is represented by a solid line.

[0069] In the double-gate IGBT 20 driven by the semiconductor drive device according to the comparative example, a short time difference (t2 - t1) is given to the gate voltages applied to the switching gate Gs responsible for switching and the control gate Gc for controlling the carrier injection amount, respectively. The collector current Ic starts to flow at the time t3 when the switching gate Gs exceeds the threshold voltage Vth. However, since it is a part of the cells connected to the switching gate Gs that is responsible for the inflow of the collector current Ic, in order to obtain the same collector current change rate dIc / dt as that of the single-gate IGBT, it is necessary to apply a larger gate voltage Vge under a larger voltage change rate dVge / dt.

[0070] After the start of the inflow of the collector current Ic, when the time t4 is reached at which the control gate Gc of the double-gate IGBT 20 reaches the threshold voltage Vth, current flows through the entire double-gate IGBT 20, improving the conduction performance, and the effect of the collector voltage Vce becomes steep, resulting in the effect of reducing the switching loss. At the same time, due to the improvement of the conduction performance, the collector current change rate dIc / dt increases after the time t4. However, it is known that the increase in dIc / dt causes an increase in noise due to the increase in the voltage change rate dV / dt between the cathode and the anode accompanying the recovery operation of the antiparallel diode constituting the inverter. Also, for the same reason, it is known that a surge voltage increases during the turn-off operation. As described above, when the delayed control gate Gc is turned on during the switching operation period, the increase in noise and surge voltage is the first problem of the semiconductor drive device according to the comparative example.

[0071] In the driving method of turning on the control gate Gc delayed during the switching operation period in the semiconductor drive device according to the comparative example, there arises the second problem of the semiconductor drive device according to the comparative example, that is, the deterioration of the robustness against various conditions such as load current, temperature, and gate threshold voltage variation, which is a general problem of active gate driving. The second problem is caused by the fact that the time difference between the two gate voltages near the mirror voltage level is not constant with respect to the change in the mirror voltage level that occurs depending on the above-mentioned various conditions.

[0072] As a clear example of the second problem, there is a case where an attempt is made to shorten the switching period by making the gate resistance of the control gate Gc of the double-gate IGBT 20 smaller than the gate resistance of the switching gate Gs. In such a case, the problem of robustness becomes apparent due to the increased voltage level dependence of the time difference between the two gate voltages.

[0073] <Effect of Embodiment 1> According to the semiconductor drive device according to Embodiment 1 described above, it is possible to solve the above-described problems that occur in the comparative example, and it is possible to improve the trade-off between the noise and surge voltage generated during the switching of the multi-gate semiconductor switching element and the switching loss, and an effect is achieved in that a semiconductor drive device with excellent robustness can be obtained.

[0074] Modification Example 1 of Embodiment 1. FIG. 6 is a diagram showing an example of a timing chart of each signal in the semiconductor drive device according to Modification Example 1 of Embodiment 1. As a specific configuration of the gate command waveform generation unit 13 of the semiconductor drive device according to Modification Example 1 of Embodiment 1, the gate command waveform generation unit 13S shown in FIG. 3D is applied. The gate command waveform generation unit 13S generates a waveform having a ramp type shape, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0) in a part of the gate command waveform.

[0075] Each waveform shown in FIG. 6 is, in order from the top, the on-off command signal Sgd, the first gate on command signal Sg1, the second gate on command signal Sg2, the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the first gate voltage VgeS, the second gate voltage VgeC, the collector current Ic, and the collector voltage Vce.

[0076] <Operation of the semiconductor drive device according to Modification Example 1 of Embodiment 1> Hereinafter, the operation of the semiconductor drive device according to Modification Example 1 of Embodiment 1 will be described with reference to FIG. 6.

[0077] <Turn-on operation of the semiconductor drive device according to Modification Example 1 of Embodiment 1> First, when the on-off command signal Sgd changes from off to on, that is, a series of operations of each signal during the turn-on operation will be described. At time t13, the external on-off command signal Sgd changes from off to on. That is, the on-off command signal Sgd changes from the Lo state to the Hi state. At time t13, based on the on operation of the on-off command signal Sgd, the timing generation unit 12 outputs the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Lo state to the Hi state.

[0078] At time t14, based on the on operation of the on-off command signal Sgd, the timing generation unit 12 outputs the second gate on command signal Sg2. The second gate on command signal Sg2 is output with a preset time delay with respect to the first gate on command signal Sg1, that is, the time difference t14 - t13.

[0079] At time t13, based on the on operation of the first gate on command signal Sg1, the first gate command waveform generation unit 13A generates the first gate command waveform Vgr1. The first gate command waveform Vgr1 rises from time t13. However, since the circuit configuration of the gate command waveform generation unit 13S is applied as the first gate command waveform generation unit 13A, a ramp-type shape that limits the voltage increase rate in a part of the first gate command waveform Vgr1, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 = 0) is generated.

[0080] At time t14, based on the on operation of the second gate on command signal Sg2, the second gate command waveform generation unit 13B generates the second gate command waveform Vgr2. The second gate command waveform Vgr2 rises from time t14. However, since the circuit configuration of the gate command waveform generation unit 13S is applied as the second gate command waveform generation unit 13B, a ramp-type shape that limits the voltage increase rate in a part of the second gate command waveform Vgr2, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 = 0) is generated. Also, the second gate command waveform Vgr2 is output with a preset time delay with respect to the first gate command waveform Vgr1, that is, the time difference t14 - t13.

[0081] At time t13, the first signal amplifier section 14A amplifies the input first gate command waveform Vgr1 and outputs a first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and has a ramp-shaped waveform that limits the voltage increase rate in part of the first gate voltage VgeS, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 = 0) is generated.

[0082] At time t14, the second signal amplifier section 14B amplifies the input second gate command waveform Vgr2 and outputs a second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and has a ramp-shaped waveform that limits the voltage increase rate in part of the second gate voltage VgeC, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 = 0) is generated. Also, the second gate voltage VgeC is output with a preset time delay with respect to the first gate voltage VgeS, that is, the time difference of t14 - t13.

[0083] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double gate type IGBT 20 provided outside the semiconductor drive device 100.

[0084] At time t15 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector current Ic of the double gate type IGBT 20 rises from the zero state before time t15, and at time t16 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth, it becomes a constant value.

[0085] At time t15 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector voltage Vce of the double gate type IGBT 20 decreases from the state of VB + Vf before time t15, and at time t16 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth, it becomes an on voltage Von which is a constant value. The above is a series of operations of each signal when the on-off command signal Sgd changes from off to on, that is, during the turn-on operation.

[0086] <Turn-off operation of the semiconductor drive device according to Modification 1 of Embodiment 1> Next, a series of operations of each signal when the on-off command signal Sgd changes from on to off, that is, during the turn-off operation, will be described.

[0087] At time t17, the external on-off command signal Sgd changes from on to off. That is, the on-off command signal Sgd changes from the Hi state to the Lo state. At time t17, based on the on state of the on-off command signal Sgd, the timing generation unit 12 turns off the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Hi state to the Lo state.

[0088] At time t18, based on the off operation of the on-off command signal Sgd, the timing generation unit 12 turns off the second gate on command signal Sg2. The off operation of the second gate on command signal Sg2 is output with a preset time difference from the off operation of the first gate on command signal Sg1, that is, the time difference between t18 and t17, with a delay.

[0089] At time t17, based on the off operation of the first gate on command signal Sg1, the first gate command waveform generation unit 13A turns off the first gate command waveform Vgr1. The first gate command waveform Vgr1 starts to fall at time t17, but since the circuit configuration of the gate command waveform generation unit 13S is applied as the first gate command waveform generation unit 13A, a ramp-type shape that limits the voltage decrease rate in a part of the first gate command waveform Vgr1, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0) is generated.

[0090] At time t18, based on the OFF operation of the second gate-on command signal Sg2, the second gate command waveform generation unit 13B turns off the second gate command waveform Vgr2. Although the second gate command waveform Vgr2 starts to fall from time t18, since the circuit configuration of the gate command waveform generation unit 13S is applied as the second gate command waveform generation unit 13B, it has a ramp-shaped waveform that restricts the voltage decrease rate in a part of the second gate command waveform Vgr2, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0). Also, the OFF operation of the second gate command waveform Vgr2 occurs with a preset time delay with respect to the OFF operation of the first gate command waveform Vgr1, that is, the time difference t18 - t17.

[0091] At time t17, the first signal amplification unit 14A amplifies the input first gate command waveform Vgr1 and outputs the first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and has a ramp-shaped waveform that restricts the voltage decrease rate in a part of the first gate voltage VgeS, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0).

[0092] At time t18, the second signal amplification unit 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and has a ramp-shaped waveform that restricts the voltage decrease rate in a part of the second gate voltage VgeC, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0). Also, the OFF of the second gate voltage VgeC is output with a preset time delay with respect to the OFF of the first gate voltage VgeS, that is, the time difference t18 - t17.

[0093] The first gate voltage VgeS and the second gate voltage VgeC are output to the first gate terminal Gs and the second gate terminal Gc of the double-gate IGBT 20 provided outside the semiconductor drive device according to the first modification of the first embodiment, respectively.

[0094] At the time t19 when the first gate voltage VgeS becomes less than the threshold voltage Vth, the collector current Ic of the double-gate IGBT 20 falls from the previous constant state, and becomes zero at the time t20 when the second gate voltage VgeC becomes less than the threshold voltage Vth.

[0095] At the time t19 when the first gate voltage VgeS becomes less than the threshold voltage Vth, the collector voltage Vce of the double-gate IGBT 20 rises from the previous on-voltage Von state, and returns to a constant value of VB + Vf at the time t20 when the second gate voltage VgeC becomes less than the threshold voltage Vth. The above is a series of operations of each signal during the turn-off operation, that is, when the on-off command signal Sgd changes from on to off.

[0096] <Effect of the first modification of the first embodiment> As described above, in the semiconductor drive device according to the first modification of the first embodiment, a waveform that restricts the increase rate of the gate command waveform during the turn-on operation, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 = 0), suppresses the increase in the collector current change rate dIc / dt that occurs when the control gate Gc turns on. As a result, noise during the switching operation can be suppressed. In the semiconductor drive device according to the first modification of the first embodiment, particularly because the second derivative value of the voltage is zero (d 2 V / dt 2 = 0), the time difference between the two gate voltages can be controlled so as not to depend on the voltage level, and thus the robustness is optimized. Note that the turn-off operation also has the same effect, so the description is omitted.

[0097] Second modification of the first embodiment. FIG. 7 is a diagram showing an example of a timing chart of each signal in the semiconductor drive device according to Modification 2 of Embodiment 1. As a specific configuration of the gate command waveform generation unit of the semiconductor drive device according to Modification 2 of Embodiment 1, the gate command waveform generation unit 13W shown in FIG. 4B is applied. The gate command waveform generation unit 13W generates a waveform provided with a terraced waveform in which the first derivative value of the voltage becomes zero (dV / dt = 0) in a part of the ramp-shaped waveform.

[0098] That is, the semiconductor drive device according to Modification 2 of Embodiment 1 shown in FIG. 7 matches the rising and falling timings of the signals in the first gate-on command signal Sg1 and the second gate-on command signal Sg2, which are two gate-on commands, in Modification 1 of Embodiment 1 shown in FIG. 6, and further, a terraced period is provided in the middle, that is, a part of the ramp-shaped waveform.

[0099] Each waveform shown in FIG. 7 is, in order from the top, the on-off command signal Sgd, the first gate-on command signal Sg1, the second gate-on command signal Sg2, the first gate command waveform Vgr1 and the second gate command waveform Vgr2, the first gate voltage VgeS, the second gate voltage VgeC, the collector current Ic, and the collector voltage Vce.

[0100] <Operation of the semiconductor drive device according to Modification 2 of Embodiment 1> Hereinafter, the operation of the semiconductor drive device according to Modification 2 of Embodiment 1 will be described with reference to FIG. 7.

[0101] <Turn-on operation of the semiconductor drive device according to Modification 2 of Embodiment 1> First, when the on-off command signal Sgd changes from off to on, that is, a series of operations of each signal during the turn-on operation will be described. At time t21, the external on-off command signal Sgd changes from off to on. That is, the on-off command signal Sgd changes from the Lo state to the Hi state. At time t21, based on the on operation of the on-off command signal Sgd, the timing generation unit 12 outputs the first gate-on command signal Sg1. That is, the first gate-on command signal Sg1 changes from the Lo state to the Hi state.

[0102] At time t21, based on the ON operation of the on-off command signal Sgd, the timing generation unit 12 outputs a second gate ON command signal Sg2. The second gate ON command signal Sg2 is output simultaneously with the first gate ON command signal Sg1.

[0103] At time t21, based on the ON operation of the first gate ON command signal Sg1, the first gate command waveform generation unit 13A generates a first gate command waveform Vgr1. The first gate command waveform Vgr1 rises from time t21. However, since the circuit configuration of the gate command waveform generation unit 13S is applied as the first gate command waveform generation unit 13A, the first gate command waveform Vgr1 has a ramp-type shape, that is, a waveform that limits the voltage decrease rate after a steep rising waveform, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0).

[0104] At time t21, based on the ON operation of the second gate ON command signal Sg2, the second gate command waveform generation unit 13B generates a second gate command waveform Vgr2. The second gate command waveform Vgr2 rises from time t22. However, since the circuit configuration of the gate command waveform generation unit 13W is applied as the second gate command waveform generation unit 13B, the second gate command waveform Vgr2 has a waveform in which the voltage increase rate is limited in a part of the waveform, and a terrace-type waveform in which the first derivative value of the voltage is zero (dV / dt = 0) is provided in a part of the ramp-type waveform.

[0105] At time t21, the first signal amplification unit 14A amplifies the input first gate command waveform Vgr1 and outputs a first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and has a waveform with a ramp-type shape in which the voltage increase rate is limited in a part of the first gate voltage VgeS.

[0106] At time t23, the second signal amplifier 14B amplifies the input second gate command waveform Vgr2 and outputs the second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and has a waveform in which a part of the second gate voltage VgeC has a waveform of a ramp type that limits the voltage increase rate, and a terrace type waveform in which the first derivative value of the voltage becomes zero (dV / dt = 0) is provided.

[0107] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double gate type IGBT 20 provided outside the semiconductor drive device according to the second modification of the first embodiment.

[0108] At time t22 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector current Ic of the double gate type IGBT 20 rises from the zero state before time t22, and becomes a constant value at time t23 when the second gate voltage VgeC becomes equal to or higher than the threshold voltage Vth.

[0109] At time t22 when the first gate voltage VgeS becomes equal to or higher than the threshold voltage Vth, the collector voltage Vce of the double gate type IGBT 20 decreases from the state of VB + Vf until then, and becomes the on voltage Von which is a constant value after time t23. The above is a series of operations of each signal when the on-off command signal Sgd changes from off to on, that is, during the turn-on operation.

[0110] <Semiconductor drive device turn-off operation according to the second modification of the first embodiment> Next, a series of operations of each signal when the on-off command signal Sgd changes from on to off, that is, during the turn-off operation, will be described.

[0111] At time t24, the on / off command signal Sgd from the outside changes from on to off. That is, the on / off command signal Sgd changes from the Hi state to the Lo state. At time t24, based on the on state of the on / off command signal Sgd, the timing generation unit 12 turns off the first gate on command signal Sg1. That is, the first gate on command signal Sg1 changes from the Hi state to the Lo state.

[0112] At time t24, based on the off operation of the on / off command signal Sgd, the timing generation unit 12 turns off the second gate on command signal Sg2.

[0113] At time t24, based on the off operation of the first gate on command signal Sg1, the first gate command waveform generation unit 13A turns off the first gate command waveform Vgr1. The first gate command waveform Vgr1 starts to fall from time t24. However, since the circuit configuration of the gate command waveform generation unit 13S is applied as the first gate command waveform generation unit 13A, the first gate command waveform Vgr1 has a ramp-type shape that limits the voltage decrease rate after a steep falling waveform, that is, a waveform in which the second derivative value of the voltage is zero (d 2 V / dt 2 =0).

[0114] At time t24, based on the off operation of the second gate on command signal Sg2, the second gate command waveform generation unit 13B turns off the second gate command waveform Vgr2. The second gate command waveform Vgr2 starts to fall from time t24. However, since the circuit configuration of the gate command waveform generation unit 13W is applied as the second gate command waveform generation unit 13B, the second gate command waveform Vgr2 has a ramp-type shape that limits the voltage decrease rate in a part of it, that is, a waveform in which a terrace period is provided in a part of it.

[0115] At time t24, the first signal amplification unit 14A amplifies the input first gate command waveform Vgr1 and outputs a first gate voltage VgeS. The first gate voltage VgeS reflects the waveform of the first gate command waveform Vgr1 and exhibits a waveform with a ramp-shaped waveform in which the voltage decrease rate is limited in a part of the first gate voltage VgeS.

[0116] At time t25, the second signal amplification unit 14B amplifies the input second gate command waveform Vgr2 and outputs a second gate voltage VgeC. The second gate voltage VgeC reflects the waveform of the second gate command waveform Vgr2 and exhibits a waveform in the middle of a ramp-shaped waveform in which the voltage decrease rate is limited in a part of the second gate voltage VgeC, that is, a waveform provided with a terrace period in a part.

[0117] The first gate voltage VgeS and the second gate voltage VgeC are respectively output to the first gate terminal Gs and the second gate terminal Gc of the double gate type IGBT 20 provided outside the semiconductor drive device according to the first modification of the first embodiment.

[0118] At time t25 when the first gate voltage VgeS becomes less than the threshold voltage Vth, the collector current Ic of the double gate type IGBT 20 falls from the previous constant state, and at time t25 when the second gate voltage VgeC becomes less than the threshold voltage Vth, it becomes zero.

[0119] At time t25 when the first gate voltage VgeS becomes less than the threshold voltage Vth, the collector voltage Vce of the double gate type IGBT 20 rises from the previous on voltage Von state, and at time t26 when the second gate voltage VgeC becomes less than the threshold voltage Vth, it returns to a constant value of VB + Vf. The above is a series of operations of each signal when the on-off command signal Sgd changes from on to off, that is, during the turn-off operation.

[0120] <Effect of the second modification according to the first embodiment> In the semiconductor drive device of Modification 2 according to Embodiment 1 described above, by making the slopes of the rise and fall of the signals in the first gate-on command signal Sg1 and the second gate-on command signal Sg2 steep, the conduction performance is increased, and the effect of suppressing the slowdown of the rise and fall of the collector current Ic generated by the time difference drive of the ramp-type waveform shown in FIG. 7 is achieved. On the other hand, as the collector current Ic increases, a terrace period is provided in a part of the second gate-on command signal Sg2 to reduce the conduction performance, thereby achieving the effect of suppressing the increase in dIc / dt, which is the rate of change of the collector current over time after the rise.

[0121] Embodiment 2. <Configuration of the semiconductor drive device according to Embodiment 2> FIG. 8 is a block diagram showing the configuration of a semiconductor drive device 100A according to Embodiment 2. The semiconductor drive device 100A according to Embodiment 2 includes a timing generation unit 12, a gate command waveform generation unit 13, a signal amplification unit 14, and a drive voltage generation unit 15. The gate command waveform generation unit 13 includes a first gate command waveform generation unit 13C. The signal amplification unit 14 further includes a first signal amplification unit 14A and a constant voltage drive unit 16.

[0122] The difference between the semiconductor drive device 100A according to Embodiment 2 and the configuration of the semiconductor drive device 100 according to Embodiment 1 is that the gate command waveform generation unit 13 of the semiconductor drive device 100 according to Embodiment 1 is composed of a first gate command waveform generation unit 13A and a second gate command waveform generation unit 13B, while the gate command waveform generation unit 13 of the semiconductor drive device 100A according to Embodiment 2 is composed of only the first gate command waveform generation unit 13C.

[0123] In the semiconductor drive device 100A according to Embodiment 2, among the two gate voltages, namely the first gate voltage VgeS and the second gate command waveform Vgr2, the first gate voltage VgeS is driven to follow the gate command waveform, and the second gate voltage VgeC is driven at a constant voltage. Since the second gate voltage VgeC is driven at a constant voltage, for example, the constant voltage drive unit 16 may be configured by the constant voltage circuit shown in FIG. 12.

[0124] <Effect of Embodiment 2> As described above, according to the semiconductor drive device 100A according to Embodiment 2, although the above-described deterioration of robustness becomes apparent, there is an effect of enhancing the effect of the active gate.

[0125] Embodiment 3. <Configuration of Power Conversion Device According to Embodiment 3> FIG. 9 is a block diagram showing the configuration of a power conversion device 200 according to Embodiment 3. As shown in FIG. 9, the power conversion device 200 includes a power converter 30 having a total of six double-gate semiconductor switching elements 50a, 50b, 50c, 50d, 50e, 50f, a smoothing capacitor 40, and either the semiconductor drive device 100 according to Embodiment 1 or the semiconductor drive device 100A according to Embodiment 2 that drives each of the double-gate semiconductor switching elements 50a to 50f in the power converter 30. As an example in which the power conversion device 200 according to Embodiment 3 is applied, an inverter device that converts DC power from a DC power source 60 into AC power and supplies it to an AC motor 70 is given.

[0126] <Effect of Embodiment 3> In the power conversion device 200 according to Embodiment 3, by using the semiconductor drive device 100 according to Embodiment 1 or the semiconductor drive device 100A according to Embodiment 2 described above for signal generation for driving the double-gate semiconductor switching elements 50a to 50f, it is possible to provide an inverter device that achieves both energy savings due to the low-loss effect of the double-gate semiconductor switching elements and low noise such as radiated noise generated within the device.

[0127] Note that, as an example of the power conversion device 200 according to Embodiment 3, a three-phase inverter device that outputs a two-level AC voltage of positive and negative is shown, but an inverter device capable of multi-level voltage output in which an arbitrary number of double-gate semiconductor switching elements are connected in series and parallel may also be used.

[0128] Embodiment 4. FIG. 10 is a block diagram showing the configuration of the power conversion device 200A according to Embodiment 4. Hereinafter, only the differences from the power conversion device 200 according to Embodiment 3 will be briefly described.

[0129] <Configuration of the power conversion device according to Embodiment 4> The power conversion device 200A according to Embodiment 4 includes a power converter 31 configured with a plurality of double-gate semiconductor switching elements 51a and 51b, and one of the semiconductor drive devices 100 according to Embodiment 1 and the semiconductor drive device 100A according to Embodiment 2 that drive each of the double-gate semiconductor switching elements 51a and 51b in the power converter 31. When the semiconductor drive device 100A according to Embodiment 2 is applied, the power conversion device 200A operates as a boost converter device that boosts the DC voltage of the DC power supply 60 and supplies it to the DC load 70A.

[0130] The power converter 31 includes a leg in which the double-gate semiconductor switching elements 51a and 51b are connected in series, an input-side smoothing capacitor 41, an output-side smoothing capacitor 42, and a boost reactor 43.

[0131] Also in the power conversion device 200A according to Embodiment 4, by using either the semiconductor drive device 100 according to Embodiment 1 or the semiconductor drive device 100A according to Embodiment 2, it is possible to provide a boost converter device that achieves both energy saving due to the low-loss effect of the double-gate semiconductor switching element and low noise such as radiation noise generated from the inverter. Furthermore, by utilizing the low-loss effect and improving the drive frequency of the boost converter device in a state where the losses are equivalent, it is possible to reduce the size of the boost reactor 43.

[0132] Although a boost converter device is shown as an example of the power conversion device 200A according to Embodiment 4, it can be similarly applied to a buck converter device or a buck-boost converter device that combines a boost converter device and a buck converter device.

[0133] Embodiment 5. <Configuration of Power Conversion Device According to Embodiment 5> FIG. 11 is a block diagram showing the configuration of a power conversion device 200B according to Embodiment 5. Hereinafter, only the differences from Embodiment 3 will be briefly described. The power conversion device 200B according to Embodiment 5 includes a power converter 30 that constitutes the power conversion device 200 according to Embodiment 3 shown in FIG. 9, a power converter 31 that constitutes the power conversion device 200A according to Embodiment 3 shown in FIG. 10 and is connected to the DC side of the power converter 30, and any one of the semiconductor drive devices 100 and 100A shown in Embodiments 1 and 2 that drive the double-gate type semiconductor switching elements 50a to 50f.

[0134] The power conversion device 200B boosts the DC voltage of the DC power supply 60 by the power converter 31, and the boosted DC power is converted into AC power by the power converter 30 and supplied to the AC motor 74. The power conversion device 200B operates as a boost-type inverter system and is applied to, for example, an electric vehicle. Note that the power converter 30 in the power conversion device 200B may be an inverter device capable of multi-level voltage output. Also, the power converter 31 in the power conversion device 200B is not limited to a boost converter, and can be similarly applied to a buck converter device or a buck-boost converter device that combines a boost converter device and a buck converter device.

[0135] By using either of the semiconductor drive devices 100 and 100A shown in Embodiments 1 and 2, the power conversion device 200B according to Embodiment 5 can provide a boost-type inverter system that achieves both energy saving due to the low-loss effect of the double-gate type semiconductor switching element and low noise such as radiated noise generated from the inverter device. Furthermore, by utilizing the low-loss effect and improving the drive frequency of the converter while maintaining the same loss, miniaturization of the boost reactor 43 can be achieved.

[0136] In the above-described Embodiments 1 to 5, all of the multi-gate semiconductor switching elements were described by taking the double-gate IGBT as an example. However, as the multi-gate semiconductor switching element, all multi-gate IGBTs such as the triple-gate IGBT can be applied. Further, a hybrid element in which a part is replaced with a single-gate IGBT or a single-gate MOSFET structure may be used. Also, the multi-gate semiconductor switching element may be any of an RC (Reverse-Conducting)-IGBT, an IGBT, and a hybrid element in which an IGBT and a MOSFET are arranged in parallel. Also, the first gate terminal Gs (switching gate) may be composed of a plurality, and the second gate terminal Gc (control gate) may also be composed of a plurality.

[0137] Note that in the configurations of the semiconductor drive devices 100, 100A and the power conversion devices 200, 200A, 200B according to the above-described Embodiments 1 to 5, although a part of the semiconductor drive devices 100, 100A and the power conversion devices 200, 200A, 200B is described as a functional block, FIG. 14 shows an example of the configuration as hardware for storing the semiconductor drive devices 100, 100A and the power conversion devices 200, 200A, 200B. The hardware 800 is composed of a processor 801 and a storage device 802. Although not shown, the storage device 802 includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory.

[0138] Also, an auxiliary storage device of a hard disk may be provided instead of the flash memory. The processor 801 executes a program input from the storage device 802. In this case, the program is input to the processor 801 from the auxiliary storage device via the volatile storage device. Also, the processor 801 may output data such as calculation results to the volatile storage device of the storage device 802, or may store the data in the auxiliary storage device via the volatile storage device.

[0139] Although various exemplary embodiments and examples are described, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable to the embodiments alone or in various combinations.

[0140] Accordingly, numerous variations not illustrated are envisioned within the scope of the technology disclosed in this specification. For example, it is to be included that when at least one component is modified, added, or omitted, and further, when at least one component is extracted and combined with the components of other embodiments.

Description of Reference Numerals

[0141] 12 Timing generation unit, 13, 13P, 13Q, 13R, 13S, 13T, 13U, 13V, 13W Gate command waveform generation units, 13A, 13C First gate command waveform generation units, 13B Second gate command waveform generation unit, 14, 14P, 14Q, 14R, 14S Signal amplification units, 14A First signal amplification unit, 14B Second signal amplification unit, 15 Drive voltage generation unit, 16 Constant voltage drive unit, 20 Double-gate IGBT, 21 Diode, 25 IGBT module, 30, 31 Power converters, 40, 41, 42 Smoothing capacitors, 43 Boost reactor, 50a, 50b, 50c, 50d, 50e, 50f, 51a, 51b Double-gate semiconductor switching elements, 60 DC power supply, 70, 74 AC motors, 70A Load, 100, 100A Semiconductor drive devices, 200, 200A, 200B Power conversion devices, 800 Hardware, 801 Processor, 802 Memory device, C1, C2, C3, C4 Capacitors, D2 Diode, DS1, DS2, DS3, DS4, DS5, DS6 Constant current diodes, DZ1, DZ2, DZ3 Zener diodes, Gs First gate terminal, Gc Second gate terminal, OP1, OP2 Operational amplifiers, Q1, Q3 NPN transistors, Q2, Q4 PNP transistors, R2, R11, R12 Gate resistors, R3, R4, R5, R6, R7, R8, R9 Resistors, R10 Base resistor, Sgd On-off command signal, Sg1 First gate on command signal, Sg2 Second gate on command signal, Vce Collector voltage, Vge Gate voltage, VgeS First gate voltage, VgeC Second gate voltage, Vgr1 First gate command waveform, Vgr2 Second gate command waveform, Von On voltage, Vth Threshold voltage

Claims

1. A semiconductor drive device for driving a multi-gate semiconductor switching element having a plurality of gate terminals, comprising: a timing generation unit that turns on and off a gate-on command signal for each of the plurality of gate terminals based on an on / off command signal from the outside; a gate command waveform generation unit that generates a first gate command waveform corresponding to at least one first gate terminal and a second gate command waveform corresponding to at least one second gate terminal among the plurality of gate terminals based on the on / off of the gate-on command signal, and outputs either or both of the first gate command waveform and the second gate command waveform at least in one or both of a transition from a non-conducting state to a conducting state and a transition from a conducting state to a non-conducting state of the multi-gate semiconductor switching element; a signal amplification unit that amplifies the input waveform such that the output waveform follows the input waveform, with either or both of the first gate command waveform and the second gate command waveform as the input waveform; The semiconductor drive device, wherein the first gate command waveform and the second gate command waveform have the same waveform shape with a preset time difference.

2. A semiconductor drive device for driving a multi-gate semiconductor switching element having a plurality of gate terminals, comprising: a timing generation unit that turns on and off a gate-on command signal for each of the plurality of gate terminals based on an on / off command signal from the outside; a gate command waveform generation unit that generates a first gate command waveform corresponding to at least one first gate terminal and a second gate command waveform corresponding to at least one second gate terminal among the plurality of gate terminals based on the on / off of the gate-on command signal, the second gate command waveform having a preset time difference with respect to the first gate command waveform, and outputs the first gate command waveform and the second gate command waveform at both a transition from a non-conducting state to a conducting state and a transition from a conducting state to a non-conducting state of the multi-gate semiconductor switching element; a signal amplification unit that amplifies the input waveform such that the output waveform follows the input waveform, with the first gate command waveform and the second gate command waveform as the input waveform; The gate command waveform generation unit includes, in a part of the second gate command waveform when the multi-gate semiconductor switching element transitions from a non-conducting state to a conducting state, a shape in which a first-order differential value of the second gate command waveform decreases discontinuously, and includes, in a part of the second gate command waveform when the multi-gate semiconductor switching element transitions from a conducting state to a non-conducting state, a shape in which the first-order differential value of the second gate command waveform increases discontinuously. A semiconductor drive device characterized by this.

3. The semiconductor drive device according to claim 1 or 2, characterized in that a voltage equal to or higher than a threshold voltage is applied to at least the first gate terminal of the multi-gate semiconductor switching element earlier in time than other gate terminals including the second gate terminal.

4. The semiconductor drive device according to claim 1 or 2, characterized in that a voltage lower than a threshold voltage is applied to at least the first gate terminal of the multi-gate semiconductor switching element earlier in time than other gate terminals including the second gate terminal.

5. The semiconductor drive device according to claim 1 or 2, characterized in that the gate command waveform generation unit includes at least one operational amplifier.

6. The semiconductor drive device according to claim 1 or 2, characterized in that the multi-gate semiconductor switching element is any one of a multi-gate IGBT, an RC-IGBT, a hybrid element in which an IGBT and a MOSFET are arranged in parallel.

7. An inverter device having a multi-gate semiconductor switching element as a semiconductor switching element, for converting DC power into AC power, a boost converter device for boosting the voltage of DC power, a buck converter device for reducing the voltage of DC power, an AC-DC converter device for converting AC power into DC power, a boost type inverter device including the boost converter device and the inverter device, a buck type inverter device including the buck converter device and the inverter device, any one of them, The semiconductor drive device according to claim 1 or 2 for driving the multi-gate semiconductor switching element, A power conversion device comprising.

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