Battery device

Abstract

To provide a charge / discharge control circuit capable of securely shifting to a power-down state, when shifting to the power-down state by a control signal from an external controller using a secondary battery as power supply.SOLUTION: A charge / discharge control circuit 11 can be controlled by a control signal from an external controller 14. The charge / discharge control circuit 11 includes a control circuit 112 that latches a power-down control signal and cuts off a discharge path from a secondary battery SC to the controller 14, when the power-down control signal that shifts to a power-down state is input from the controller 14.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention , ba relates to a battery device.

Background Art

[0002] Generally, a battery device includes a charge / discharge control circuit that detects over-discharge, over-charge, etc. and controls the charge and discharge of a secondary battery in order to protect the secondary battery. When this charge / discharge control circuit detects over-discharge, it shuts off the discharge path from the secondary battery to the load, and when it detects over-charge, it shuts off the charge path from the charger to the secondary battery.

[0003] Some of these charge / discharge control circuits have a power-down function that reduces the current consumption inside the circuit so that the secondary battery does not discharge from when the product to which the battery device is connected is shipped until it is operated (see, for example, Patent Document 1). Further, by connecting a controller to such a charge / discharge control circuit, the charge / discharge control circuit can be shifted externally from the "normal state" in which charge and discharge are possible to a "power-down state" in which internal circuits and the like are stopped to reduce current consumption.

[0004] FIG. 4 is a block diagram of a conventional battery device having a charge / discharge control circuit and a controller. A conventional battery device 50 includes a secondary battery SC, a charge / discharge control circuit 51 connected to the secondary battery SC, a discharge control FET 52, a charge control FET 53, a controller 54 capable of outputting a signal for shifting to a power-down state to the charge / discharge control circuit 51, resistors 55, 56, a capacitor 57, an external positive terminal EB+, and an external negative terminal EB-. A load LD is connected between the external positive terminal EB+ and the external negative terminal EB-. This controller 54 uses the secondary battery SC as a power source, and when it outputs a signal for shifting to a power-down state to the charge / discharge control circuit 51, the discharge control FET 52 is turned off via the control circuit 512, thereby shutting off the discharge path from the secondary battery SC by itself.

[0005] The charge and discharge control circuit 51 includes a charge and discharge monitoring circuit 511, a control circuit 512, a detector 513, switches 514 and 515, a positive power supply terminal VDD, a negative power supply terminal VSS, a discharge control terminal DO, a charge control terminal CO, an external negative voltage input terminal VM, and a control signal input terminal CTL. Each circuit and each terminal are connected as shown in FIG. 4.

[0006] When the controller 54 outputs a power-down control signal for shifting to the power-down state to the control signal input terminal CTL, the battery device 50 detects the power-down control signal by the detector 513, and the control circuit 512 turns off the discharge control FET 52 via the discharge control terminal DO. Then, the discharge path from the secondary battery SC to the load LD and the controller 54 is cut off, and the external negative voltage input terminal VM is pulled up through the load LD and the resistor 56, and rises to near the voltage of the external positive terminal EB+, that is, the positive terminal of the secondary battery SC. When the charge and discharge monitoring circuit 511 detects that the external negative voltage input terminal VM has exceeded a predetermined voltage (hereinafter referred to as the "power-down threshold voltage") for determining that the external negative voltage input terminal VM has been pulled up, the charge and discharge monitoring circuit 511 outputs a pull-up signal to the control circuit 512. The control circuit 512 to which the pull-up signal is input turns off the switches 514 and 515 to also cut off the discharge path from the secondary battery SC to the charge and discharge monitoring circuit 511 and the detector 513.

[0007] In this way, when the controller 54 outputs a power-down control signal to the control signal input terminal CTL, the conventional battery device 50 can shift to the power-down state in which the discharge paths to the load LD, the controller 54, the charge and discharge monitoring circuit 511, and the detector 513 are cut off to reduce the consumption current.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] However, in the battery device 50 shown in FIG. 4, the following problems may occur. When the controller 54 outputs a power-down control signal to the control signal input terminal CTL to turn off the discharge control FET 52, not only the load LD but also the discharge path to the controller 54 is cut off. At this time, since the negative terminal of the controller 54 is connected to the external negative terminal EB-, it is pulled up to the potential of the positive terminal of the secondary battery SC through the load LD. Then, the controller 54 cannot secure its own power supply sufficiently, and when it falls below the minimum operating voltage, the operation becomes unstable, so there is a risk of erroneously outputting a normal control signal for transitioning to the normal state. In particular, when the capacitance of the load LD connected in parallel with the controller 54 is large, the discharge time of that capacitance becomes long. For this reason, the controller 54 may remain in a state below the minimum operating voltage for a long time, and the time during which the operation is unstable may become long. Then, in the battery device 50 that has unintentionally transitioned to the normal state, there may be a problem that the secondary battery discharges before it is operated for the first time after the product is shipped.

[0010] The present invention has been made in view of the above problems, and in one aspect of the present invention, an object is to provide a charge-discharge control circuit that can surely transition to a power-down state when transitioning to a power-down state by a control signal from an external controller using a secondary battery as a power source.

Means for Solving the Problems

[0011] In order to solve the above problems, the charge-discharge control circuit in one embodiment of the present invention is a charge-discharge control circuit controllable by a control signal from an external controller, and has a control circuit that latches the power-down control signal and cuts off the discharge path from the secondary battery to the controller when the power-down control signal for transitioning to the power-down state is input from the controller.

Effects of the Invention

[0012] In one aspect of the present invention, when shifting to a power-down state by a control signal from an external controller using a secondary battery as a power source, a charge / discharge control circuit capable of surely shifting to the power-down state can be provided.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0015] FIG. 1 is a block diagram showing a battery device in one embodiment of the present invention. The battery device 10 of this embodiment includes a secondary battery SC, a charge / discharge control circuit 11 connected to the secondary battery SC, a discharge control FET 12, a charge control FET 13, a controller 14 capable of outputting a control signal, resistors 15 and 16, a capacitor 17, an external positive electrode terminal EB+, and an external negative electrode terminal EB-. A load LD for operating a product to which the battery device 10 is connected is connected between the external positive electrode terminal EB+ and the external negative electrode terminal EB-. Further, the charge / discharge control circuit 11 and the controller 14 operate using the secondary battery SC as a power source, similar to the load LD. When charging the secondary battery SC, the charger is connected between the external positive electrode terminal EB+ and the external negative electrode terminal EB- instead of or in parallel with the load LD.

[0016] The charge and discharge control circuit 11 includes a charge and discharge monitoring circuit 111, a control circuit 112, a detector 113, switches 114 and 115, a VM detector 116, a positive power supply terminal VDD, a negative power supply terminal VSS, a discharge control terminal DO, a charge control terminal CO, an external negative voltage input terminal VM, and a control signal input terminal CTL.

[0017] The positive power supply terminal VDD is connected to the positive electrode of the secondary battery SC and the external positive electrode terminal EB+ via a resistor 15 for suppressing the occurrence of electrostatic breakdown and power supply fluctuations. The negative power supply terminal VSS is connected to the negative electrode of the secondary battery SC and the ground potential.

[0018] Between the positive power supply terminal VDD and the negative power supply terminal VSS, the charge and discharge monitoring circuit 111, the control circuit 112, and the detector 113 are connected in parallel. Voltages between VDD and VSS are applied to operate the charge and discharge monitoring circuit 111, the control circuit 112, and the detector 113, respectively. Among these, the charge and discharge monitoring circuit 111 and the detector 113 have voltages between VDD and VSS applied thereto via switches 114 and 115 that can be turned on and off by the control circuit 112. These switches 114 and 115 are turned off from on when transitioning from the normal state to the power-down state, and are turned on from off when transitioning from the power-down state to the normal state.

[0019] Here, in the battery device 10, the "normal state" refers to a state in which the secondary battery SC is chargeable and dischargeable, and the charge and discharge monitoring circuit 111, the control circuit 112, the detector 113, and the VM detector 116 are operating. The "power-down state" refers to a state in which the discharge path of the secondary battery SC is blocked, and the operation of the charge and discharge monitoring circuit 111 and the detector 113 is stopped by the switches 114 and 115 to reduce the consumption current.

[0020] Note that one end of the capacitor 17 is connected to the positive power supply terminal VDD and the other end is connected to the negative power supply terminal VSS in order to suppress voltage fluctuations between VDD and VSS.

[0021] The charge / discharge monitoring circuit 111 detects overcharging of the secondary battery SC and outputs an overcharge detection signal to the control circuit 112. Also, the charge / discharge monitoring circuit 111 detects over-discharging of the secondary battery SC and outputs an over-discharge detection signal to the control circuit 112.

[0022] The control signal input terminal CTL is a terminal to which a power-down control signal from the controller 14 is input, and is connected to the detector 113.

[0023] The detector 113 outputs the power-down control signal input from the controller 14 to the latch section 112a. If this detector 113 is, for example, a buffer using a Schmitt trigger, even if the voltage level of the input power-down control signal fluctuates due to noise or the like, the power-down control signal can be more reliably output to the latch section 112a.

[0024] The external negative voltage input terminal VM is a terminal for detecting the voltage of the external negative terminal EB-, and is connected to the external negative terminal EB- via a resistor 16 for suppressing the occurrence of electrostatic breakdown and damage when the charger is connected in reverse.

[0025] The VM detector 116 detects whether the external negative voltage input terminal VM has been pulled up by detecting the voltage of the external negative voltage input terminal VM based on a predetermined voltage value (which may be referred to as the "power-down detection threshold"). When the VM detector 116 detects that the external negative voltage input terminal VM has been pulled up, it outputs a pull-up signal (a non-reset signal at the L level in this embodiment) to the latch section 112a of the control circuit 112. Further, when the VM detector 116 detects that a charger is connected to the external negative voltage input terminal VM and the voltage of the external negative voltage input terminal VM has become equal to or lower than another predetermined voltage value (which may be referred to as the "power-down release threshold") and has not been pulled up, it outputs a pull-up release signal (a reset signal at the H level in this embodiment) to the latch section 112a of the control circuit 112. As the VM detector 116, similar to the detector 113, for example, if it is a buffer using a Schmitt trigger, even if the voltage level of the input pull-up signal or pull-up release signal fluctuates due to noise or the like, each signal can be output to the latch section 112a.

[0026] In this way, the charge / discharge monitoring circuit 111, the detector 113, and the VM detector 116 input the signals they output to the control circuit 112 respectively.

[0027] When the control circuit 112 receives an overcharge detection signal from the charge / discharge monitoring circuit 111, it turns off the charge control FET 13 and outputs a charge prohibition signal for prohibiting charging to the charge control terminal CO. Further, when the control circuit 112 permits charging of the secondary battery SC, it turns on the charge control FET 13 and outputs a charge permission signal for permitting charging to the charge control terminal CO.

[0028] When the control circuit 112 receives an over-discharge detection signal from the charge / discharge monitoring circuit 111, it turns off the discharge control FET 12 and outputs a discharge prohibition signal for prohibiting discharge to the discharge control terminal DO. Further, when the control circuit 112 permits discharge of the secondary battery SC, it turns on the discharge control FET 12 and outputs a discharge permission signal for permitting discharge to the discharge control terminal DO.

[0029] In this way, based on the signal from the charge / discharge monitoring circuit 111, the control circuit 112 can control the charge and discharge of the secondary battery SC by using the discharge control FET 12 and the charge control FET 13.

[0030] After the power-down control signal is input from the detector 113 to this control circuit 112, the control circuit 112 is provided with a latch section 112a and a driver 112b so that it can shift to the power-down state even when a signal other than the power-down control signal is input due to a malfunction of the controller 14 that has fallen below the minimum operating voltage.

[0031] When the power-down control signal is input from the detector 113 to the latch section 112a, the latch section 112a latches the power-down control signal. As a result, even if a signal other than the power-down control signal is input to the latch section 112a from the detector 113 via the controller 14 that has malfunctioned while the control circuit 112 is shifting to the power-down state, the control circuit 112 does not receive the signal and can more surely shift to the power-down state.

[0032] In particular, when the capacitance of the load LD connected in parallel with the controller 14 is large, the discharge time to the controller 14 becomes long after the discharge path of the secondary battery SC is cut off. Therefore, the controller 14 may be in a state below the minimum operating voltage for a long time, and the operation may be unstable for a long time. Even in such a case, the control circuit 112 can more surely shift to the power-down state.

[0033] In addition, the latch section 112a latches the power-down control signal and outputs a latch signal corresponding to the power-down control signal to the driver 112b.

[0034] The driver 112b performs on / off control of the discharge control terminal DO and the charge control terminal CO according to the latch signal input from the latch section 112a. When the latch signal corresponding to the power-down control signal is input from the latch section 112a, the driver 112b outputs a discharge inhibition signal for turning off the discharge control FET 12.

[0035] When the discharge control FET 12 turns off to cut off the discharge path, the latch section 112a receives a pull-up signal from the VM detector 116 that has determined that the external negative voltage input terminal VM has been pulled up. Then, the control circuit 112 outputs switch-off signals to turn off the switches 114 and 115 to the switches 114 and 115, respectively. As a result, the charge and discharge control circuit 11 can shift to a power-down state that reduces the current consumption in the charge and discharge monitoring circuit 111 and the detector 113.

[0036] When the charger is connected to the battery device 10 that has shifted to the power-down state, the VM detector 116 that has determined that the external negative voltage input terminal VM is not pulled up outputs a pull-up release signal to the latch section 112a, enabling the device to shift from the power-down state to a normal state where charge and discharge are possible.

[0037] One end of the discharge control FET 12 is connected to the charge control FET 13, and the other end is connected to the negative electrode of the secondary battery SC. The gate of the discharge control FET 12 is connected to the discharge control terminal DO and is turned on and off by a discharge control signal output from the driver 112b. There are two types of discharge control signals: a discharge prohibition signal and a discharge permission signal.

[0038] One end of the charge control FET 13 is connected to the external negative terminal EB-, and the other end is connected to one end of the discharge control FET 12. The gate of the charge control FET 13 is connected to the charge control terminal CO and is turned on and off by a charge control signal output from the driver 112b. There are two types of charge control signals: a charge prohibition signal and a charge permission signal.

[0039] The controller 14 can output a power-down control signal and a normal control signal. In this embodiment, when the controller 14 outputs a power-down control signal to the charge / discharge control circuit 11, the discharge path from the secondary battery SC is cut off by the charge / discharge control circuit 11, and thus the external negative voltage input terminal VM is pulled up. As a result, when the controller 14 cannot ensure sufficient power supply for itself and its operation becomes unstable when it drops below the minimum operating voltage, there is a possibility that it may output a normal control signal due to malfunction.

[0040] FIG. 2 is a block diagram showing the latch section in this embodiment. The latch section 112a includes two OR gates A and B, and two SR latch circuits C and D. Since the two SR latch circuits C and D each include a delay circuit, they may also be referred to as latched circuits with delay.

[0041] For the OR gate A, the output terminal of the detector 113 shown in FIG. 1 and the Q terminal of the SR latch circuit C are respectively connected to the input terminals. The output terminal of the OR gate A is connected to the S terminal of the SR latch circuit C.

[0042] For the SR latch circuit C, the R terminal is connected to the Q terminal of the SR latch circuit D, and as described above, the S terminal is connected to the output terminal of the OR gate A. The Q terminal of the SR latch circuit C is connected to the input terminal of the OR gate A, the input terminal of the OR gate B, and the S terminal of the SR latch circuit D.

[0043] For the SR latch circuit D, the R terminal is connected to the output terminal of the VM detector 116 shown in FIG. 1, and as described above, the S terminal is connected to the Q terminal of the SR latch circuit C. The Q terminal of the SR latch circuit D is connected to the input terminal of the OR gate B, and as described above, it is also connected to the R terminal of the SR latch circuit C.

[0044] As described above, the OR gate B has the Q terminal of the SR latch circuit C and the Q terminal of the SR latch circuit D connected to the input terminals respectively. The output terminal of the OR gate B is connected to the input terminal of the driver 112b shown in FIG. 1.

[0045] Next, the operation of the battery device 10 when transitioning from the normal state to the power-down state will be described with reference to FIGS. 1 and 2. Here, at the time of product shipment, an operation of outputting a power-down control signal from the controller 14 to change the battery device 10 from the normal state to the power-down state with a load LD connected between the external positive terminal EB+ and the external negative terminal EB- will be described. It is assumed that the secondary battery SC is charged to a voltage that does not exceed the overcharge voltage, and both the discharge control FET 12 and the charge control FET 13 are turned on.

[0046] The charge / discharge control circuit 11 receives the power-down control signal output from the controller 14 to the control signal input terminal CTL through the detector 113 in the control circuit 112. The control circuit 112 latches the power-down control signal by the latch section 112a and outputs a latch signal corresponding to the power-down control signal to the driver 112b. The driver 112b turns off the discharge control FET 12 via the discharge control terminal DO according to the latch signal.

[0047] Next, the operation of the latch section 112a at this time will be described in detail with reference to FIG. 2. When the SR latch circuit C of the latch section 112a receives the power-down control signal from the detector 113 shown in FIG. 1 at the S terminal via the OR gate A, it returns to the input terminal of the OR gate A and latches it. Further, the SR latch circuit C outputs a signal (H level) for turning off the discharge control FET 12 to the driver 112b via the OR gate B and also outputs it to the S terminal of the SR latch circuit D.

[0048] The SR latch circuit D receives a signal (H level) from the SR latch circuit C at the S terminal and a pull-up signal (L level non-reset signal) from the VM detector 116 shown in FIG. 1. Then, the SR latch circuit D outputs a set signal. This set signal is a signal (H level) that continues to turn off the discharge control FET 12, is output to the driver 112b via the OR gate B, and is also input to the R terminal of the SR latch circuit C. As a result, the Q terminal of the SR latch circuit C is reset (L level).

[0049] Returning to FIG. 1, when the discharge control FET 12 is turned off, the discharge path from the secondary battery SC to the load LD and the controller 14 is interrupted. At this time, when the voltage of the external negative voltage input terminal VM rises to near the voltage of the positive terminal of the secondary battery SC, the voltage applied to the controller 14 drops below the minimum operating voltage and the operation becomes unstable, and there may be a case where a normal control signal is output after outputting a power-down control signal. Especially when the capacity of the load LD is large, the discharge time to the controller 14 becomes long after the discharge path of the secondary battery SC is interrupted, so the controller 14 may be in a state below the minimum operating voltage for a long time and the operation may be unstable for a long time. Even in such a case, the battery device 10 of the present embodiment can more reliably shift to the power-down state because the power-down control signal is latched by the latch unit 112a.

[0050] Also, when the discharge path from the secondary battery SC is interrupted, the external negative voltage input terminal VM is pulled up to near the voltage of the positive terminal of the secondary battery SC through the load LD and the resistor 16. When the VM detector 116 detects that the voltage of the external negative voltage input terminal VM has exceeded a predetermined voltage value, it outputs a pull-up signal to the control circuit 112. When the pull-up signal is input, the control circuit 112 turns off the switches 114 and 115 to put the charge / discharge monitoring circuit 111 and the detector 113 into the power-down state.

[0051] When a charger is connected to the battery device 10 and it transitions from the power-down state to the normal state, when the SR latch circuit D shown in FIG. 2 receives a pull-up release signal from the VM detector 116, it outputs a signal (L level) for releasing the latch to the R terminal of the SR latch circuit C and the OR gate B respectively to turn on the discharge control FET 12. At the same time, the control circuit 112 turns on the switches 114 and 115 to operate the charge / discharge monitoring circuit 111 and the detector 113, thereby transitioning to the normal state.

[0052] As described above, according to the charge / discharge control circuit 11 of the present embodiment, when a power-down control signal is input from the controller 14, it latches the power-down control signal and has a control circuit 112 that cuts off the discharge path from the secondary battery SC to the controller 14. Thereby, even if a normal control signal is input due to a malfunction of the controller 14 whose discharge path is cut off and whose voltage has dropped below the minimum operating voltage, the charge / discharge control circuit 11 can surely transition to the power-down state.

[0053] Although one embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to the above embodiment, and various changes and combinations are possible without departing from the spirit of the present invention.

[0054] In the present embodiment, the discharge control FET 12 and the charge control FET 13 are connected to the negative electrode side of the secondary battery SC. However, for example, they may be connected to the positive electrode side of the secondary battery SC as in the modified example shown in FIG. 3. Also, although the discharge control FET 12 and the charge control FET 13 are Nch, they are not limited to this and may be Pch.

Description of Reference Numerals

[0055] 10 Battery device 11 Charge / discharge control circuit 111 Charge / discharge monitoring circuit 112 Control circuit 112a Latch section 112b Driver 113 Detector (buffer) 114, 115 Switch 116 VM Detector 12 Discharge Control FET 13 Charge Control FET VDD Positive Power Supply Terminal VSS Negative Power Supply Terminal DO Discharge Control Terminal CO Charge Control Terminal VM External Negative Voltage Input Terminal CTL Control Signal Input Terminal EB+ External Positive Terminal EB- External Negative Terminal SC Secondary Battery LD Load

Claims

1. A secondary battery, a load including a capacitance connected to the secondary battery, a controller to which the secondary battery and the load including the capacitance are respectively connected in parallel and which outputs a power-down control signal for shifting to a power-down state, a discharge control FET connected between the secondary battery and the controller and connected to a common discharge path of the secondary battery, the load, and the controller, a charge / discharge control circuit connected to the secondary battery in parallel with the controller, a battery device having: wherein the charge / discharge control circuit has a detector for detecting that the power-down control signal has been input from the controller, a control circuit that latches the power-down control signal output from the detector, cuts off a common discharge path of the secondary battery, the load, and the controller, and turns off a switch connected to a power supply line of the detector from on, a battery device characterized by having.

2. The battery device according to claim 1, wherein the control circuit outputs a discharge inhibition signal for turning off a discharge control FET connected between the secondary battery and the controller and cuts off the discharge path.

3. The control circuit has a latch unit that latches the power-down control signal input from the controller and outputs a latch signal according to the latched power-down control signal, a driver that outputs the discharge inhibition signal when the latch signal is input from the latch unit, The battery device according to claim 2, comprising.

4. The battery device according to any one of claims 1 to 3, wherein the detector is a buffer using a Schmitt trigger.

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