Semiconductor device

Abstract

To provide a semiconductor device with a novel structure and a manufacturing method for the same, and for example, to improve reliability of a transistor driven at high voltage or large current.SOLUTION: In order to improve reliability of a transistor, a buffer layer that relieves electric field concentration is provided between a drain electrode layer (or a source electrode layer) and an oxide semiconductor layer, and an end of the buffer layer has a sectional shape that projects through a side face of the drain electrode layer (or the source electrode layer). The buffer layer is composed of a lamination layer including a single layer or a plurality of layers, for example, an In-Ga-Zn-O film including nitrogen, an In-Sn-O film including nitrogen, an In-Sn-O film including SiOx, or the like is used.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention includes a transistor or a circuit including a transistor. The present invention relates to a semiconductor device, for example, a transistor in which a channel formation region is formed using an oxide semiconductor. The present invention relates to a semiconductor device having a circuit including a transistor. [Background technology]

[0002] A transistor or the like is manufactured using an oxide semiconductor film in the channel formation region, and the transistor is applied to a display device. For example, a technology that uses zinc oxide (ZnO) as an oxide semiconductor film is Transistors, InGaO3(ZnO) m These include transistors that use A transistor using the oxide semiconductor film is formed over a light-transmitting substrate, and an image display device is manufactured using the transistor. Patent Documents 1 and 2 disclose techniques for use in switching elements of semiconductor devices.

[0003] An oxide semiconductor film containing In, Ga, and Zn is used as the semiconductor layer. A reverse staggered type (battery) with a buffer layer made of metal oxide between the electrode and drain electrode layers. A transistor having a Tom gate structure is disclosed in Patent Document 3. This transistor has the following features: A metal oxide layer is provided between the source electrode layer and the drain electrode layer and the semiconductor layer as a buffer layer. By intentionally providing it, an ohmic contact is formed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-056539 [Summary of the Invention] [Problems to be Solved by the Invention]

[0005] By the way, there are various types of display devices. In liquid crystal display devices, blue phase liquid crystals have attracted attention. In addition, in a display device called electronic paper, a medium whose contrast can be electrically varied (also called electronic ink, etc.) is used. Furthermore, a self-luminous display device using an electroluminescent material is also being put into practical use. In order to cope with such new display methods, transistors used in display devices are required to have higher breakdown voltages.

[0006] Also, for the transistor used in the display device, it is desirable that the channel be formed at a positive threshold voltage as close to 0V as possible. If the threshold voltage value of the transistor is minus, a current tends to flow between the source electrode and the drain electrode even when the gate voltage is 0V, which is so-called normally on. In an active matrix type display device, the electrical characteristics of the transistors constituting the circuit are important, and this electrical characteristic affects the performance of the display device. In particular, among the electrical characteristics of the transistor, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is minus, it is difficult to control as a circuit. A transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a transistor used in a circuit.

[0007] ​​​​​​​​​​​In view of the above problems, one aspect of the present invention is a semiconductor device having a novel structure or a method for manufacturing the same. An object of the present invention is to provide such a semiconductor device or manufacturing method.

[0008] One object of the present invention is to provide a semiconductor device having a structure capable of making the threshold voltage value of a transistor positive and realizing a so-called normally-off switching element. Another object of the present invention is to provide a semiconductor device having a structure capable of making the threshold voltage value of a transistor positive and realizing a so-called normally-off switching element.

[0009] Even when the manufactured transistor does not become normally-off depending on materials and manufacturing conditions, it is important to approach the normally-off characteristics. Another object of the present invention is to provide a configuration and a manufacturing method thereof for making the threshold voltage value of a transistor approach zero even when the transistor is so-called normally-on and has a negative threshold voltage value. Even when the manufactured transistor does not become normally-off depending on materials and manufacturing conditions, it is important to approach the normally-off characteristics. Another object of the present invention is to provide a configuration and a manufacturing method thereof for making the threshold voltage value of a transistor approach zero even when the transistor is so-called normally-on and has a negative threshold voltage value. Even when the manufactured transistor does not become normally-off depending on materials and manufacturing conditions, it is important to approach the normally-off characteristics. Another object of the present invention is to provide a configuration and a manufacturing method thereof for making the threshold voltage value of a transistor approach zero even when the transistor is so-called normally-on and has a negative threshold voltage value. Even when the manufactured transistor does not become normally-off depending on materials and manufacturing conditions, it is important to approach the normally-off characteristics. Another object of the present invention is to provide a configuration and a manufacturing method thereof for making the threshold voltage value of a transistor approach zero even when the transistor is so-called normally-on and has a negative threshold voltage value.

[0010] Another object of the present invention is to improve the reliability of a transistor driven by a high voltage or a large current. Another object of the present invention is to improve the reliability of a transistor driven by a high voltage or a large current.

Means for Solving the Problems

[0011] One aspect of the present invention includes an oxide semiconductor layer, a buffer layer in contact with the oxide semiconductor layer, a source electrode layer or a drain electrode layer overlapping the oxide semiconductor layer via the buffer layer, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode layer overlapping the oxide semiconductor layer via the gate insulating layer. The gate electrode layer has a stacked structure, and one layer of the gate electrode layer in contact with the gate insulating layer is a metal oxide containing nitrogen, and the buffer layer is a metal oxide containing nitrogen. One aspect of the present invention includes an oxide semiconductor layer, a buffer layer in contact with the oxide semiconductor layer, a source electrode layer or a drain electrode layer overlapping the oxide semiconductor layer via the buffer layer, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode layer overlapping the oxide semiconductor layer via the gate insulating layer. The gate electrode layer has a stacked structure, and one layer of the gate electrode layer in contact with the gate insulating layer is a metal oxide containing nitrogen, and the buffer layer is a metal oxide containing nitrogen. One aspect of the present invention includes an oxide semiconductor layer, a buffer layer in contact with the oxide semiconductor layer, a source electrode layer or a drain electrode layer overlapping the oxide semiconductor layer via the buffer layer, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode layer overlapping the oxide semiconductor layer via the gate insulating layer. The gate electrode layer has a stacked structure, and one layer of the gate electrode layer in contact with the gate insulating layer is a metal oxide containing nitrogen, and the buffer layer is a metal oxide containing nitrogen. One aspect of the present invention includes an oxide semiconductor layer, a buffer layer in contact with the oxide semiconductor layer, a source electrode layer or a drain electrode layer overlapping the oxide semiconductor layer via the buffer layer, a gate insulating layer in contact with the oxide semiconductor layer, and a gate electrode layer overlapping the oxide semiconductor layer via the gate insulating layer. The gate electrode layer has a stacked structure, and one layer of the gate electrode layer in contact with the gate insulating layer is a metal oxide containing nitrogen, and the buffer layer is a metal oxide containing nitrogen. One layer of the gate electrode layer in contact with the gate insulating layer is a metal oxide containing nitrogen, specifically, A semiconductor device characterized in that the buffer layer is a metal oxide containing nitrogen.

[0012] As one layer of the gate electrode layer in contact with the gate insulating layer, a metal oxide containing nitrogen, specifically, In-Ga-Zn-O films containing nitrogen, In-Sn-O films containing nitrogen, In -Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, Sn-O films containing nitrogen, In-O films, or metal nitride films (such as InN and SnN) are used. These films have a work function of 5 electron volts , preferably 5.5 electron volts or more. When used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, realizing a so-called normally-off switching element.

[0013] In addition, in order to improve the reliability of the transistor, the end of the buffer layer is formed into a cross-sectional shape protruding from the side surface of the drain electrode layer (or the source electrode layer), thereby relaxing the electric field concentration.

[0014] As the material used for the oxide semiconductor layer, it is preferably contains at least indium (In) or zinc (Z n). In particular, it is preferably contains In and Zn. Also, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide, in addition to these, it is preferably has gallium (Ga). Also, as a stabilizer, it is preferably has tin (S n). Also, as a stabilizer, it is preferably has hafnium (Hf) . Also, as a stabilizer, it is preferably has aluminum (Al) .

[0015] Also, as other stabilizers, lanthanum (La), cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol ​It may have any one or more of holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0016] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, ternary metal oxides such as In-Ga-Zn-based oxide (also denoted as IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide (also denoted as ITZO (registered trademark)), Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, quaternary metal oxides such as In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide can be used. The oxide semiconductor may be single crystal or polycrystal. In the latter case, it may be amorphous or polycrystalline. It may also have a structure including a crystalline part in the amorphous, or be non-amorphous.

[0017] The oxide semiconductor may be single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. It may also have a structure including a crystalline part in the amorphous, or be non-amorphous. ​​​​​​​

[0018] The buffer layer is composed of a single layer or a laminate of multiple layers, and for example, an In-Ga- Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Sn-O film containing SiOx, etc. are used. If the buffer layer is an In-Ga-Zn-O film containing nitrogen, its resistance value can be appropriately set by adjusting the nitrogen content. If it is an In-Sn-O film containing SiOx, its resistance value can be appropriately set by adjusting the SiOx content. Further, since the buffer layer has a structure laminated with the oxide semiconductor layer forming the channel formation region, the resistance value of the buffer layer can also be adjusted by adjusting the thickness of the buffer layer. Also, the light transmittance of the buffer layer is made lower than that of the oxide semiconductor layer. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, since the light transmittance is lower than that of the In-Ga-Zn-O film and it has light-shielding properties, light irradiation to the region of the oxide semiconductor layer overlapping with the buffer layer can be prevented. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, the nitrogen concentration contained in the buffer layer is made higher than that of the oxide semiconductor layer in contact with the buffer layer. Also, the buffer layer overlaps at least partially with the gate electrode layer via the oxide semiconductor layer and the gate insulating layer.

[0019] As the gate electrode layer, it is preferably a laminate using at least one layer of aluminum, copper, etc. When using copper as one layer of the gate electrode layer, the process temperature after forming the gate electrode layer is set to 450°C or lower. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, since the light transmittance is lower than that of the In-Ga-Zn-O film and it has light-shielding properties, light irradiation to the region of the oxide semiconductor layer overlapping with the buffer layer can be prevented. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, since the light transmittance is lower than that of the In-Ga-Zn-O film and it has light-shielding properties, light irradiation to the region of the oxide semiconductor layer overlapping with the buffer layer can be prevented. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, since the light transmittance is lower than that of the In-Ga-Zn-O film and it has light-shielding properties, light irradiation to the region of the oxide semiconductor layer overlapping with the buffer layer can be prevented. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, the nitrogen concentration contained in the buffer layer is made higher than that of the oxide semiconductor layer in contact with the buffer layer. When using an In-Ga-Zn-O film containing nitrogen as the buffer layer, the nitrogen concentration contained in the buffer layer is made higher than that of the oxide semiconductor layer in contact with the buffer layer.

[0020] Also, the buffer layer overlaps at least partially with the gate electrode layer via the oxide semiconductor layer and the gate insulating layer. As the gate electrode layer, it is preferably a laminate using at least one layer of aluminum, copper, etc. When using copper as one layer of the gate electrode layer, the process temperature after forming the gate electrode layer is set to 450°C or lower.

[0021] As the gate electrode layer, it is preferably a laminate using at least one layer of aluminum, copper, etc. When using copper as one layer of the gate electrode layer, the process temperature after forming the gate electrode layer is set to 450°C or lower. When using copper as one layer of the gate electrode layer, the process temperature after forming the gate electrode layer is set to 450°C or lower. When using copper as one layer of the gate electrode layer, the process temperature after forming the gate electrode layer is set to 450°C or lower.

[0022] Also, when using aluminum as one layer of the gate electrode layer, after forming the gate electrode layer, the processing temperature is 250°C or higher and 380°C or lower, preferably 300°C or higher and 350°C or lower. Also, when using aluminum as the material of the gate electrode layer, since there is a risk that an oxide (such as alumina) may be formed on the aluminum surface in contact with the oxide film, tantalum nitride or titanium nitride is used as the barrier layer.

[0023] As one layer of the gate electrode layer, further, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In-O film containing nitrogen, or a metal nitride film (such as InN or SnN) is preferably laminated to form the gate electrode layer. Among the laminated gate electrode layers, one layer is made of the same material as the buffer layer, so that the same common sputtering target can be used, and the manufacturing cost can be reduced.

[0024] The gate insulating layer can be formed as a single layer or laminated using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, gallium oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, or a mixed material thereof by a plasma CVD method, a sputtering method, or the like. However, considering the function as the gate insulating layer of the transistor, hafnium oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium aluminate (HfAlxOy (x>0, y>0)), hafnium with nitrogen added Materials with high relative dielectric constants, such as silicate and nitrogen-added hafnium aluminate, may be adopted. In terms of being less likely to be contaminated with hydrogen, water, etc., the sputtering method is preferable.

[0025] When crystallizing the oxide semiconductor layer, a material that is compatible with the crystal structure contained in the oxide semiconductor layer is preferable as the material of the gate insulating layer in contact with the oxide semiconductor layer or the passivation layer in contact with the oxide semiconductor layer. When using a Ga-Zn-O film or an α-Ga2O3 film having a hexagonal crystal structure, it is preferable because the crystal of the oxide semiconductor layer and the crystal of the gate insulating layer or the passivation layer can be continuously aligned. For example, it is preferable to form a transistor including a stacked structure having an oxide semiconductor layer in contact with a first Ga-Zn-O film and a second Ga-Zn-O film in contact with the oxide semiconductor layer.

Advantages of the Invention

[0026] The threshold voltage value of the transistor can be made positive, and a so-called normally-off switching element can be realized. Further, even if the transistor is normally on, the threshold of the transistor can be made close to zero. In addition, the reliability of a transistor driven at a high voltage or a large current can be improved.

Brief Description of the Drawings

[0027]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below.

[0029] (Embodiment 1) In this embodiment, an example of manufacturing a transistor on a substrate will be described with reference to FIGS. 1(A), 1(B), and 1(C).

[0030] First, three conductive films made of different materials are formed on the substrate 101, and a resist mask is formed on these conductive films using a first photomask, and selectively etched to form a gate electrode layer. Then, the resist mask is removed. If necessary, an underlying insulating film such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide may be provided before forming the conductive film. The substrate 101 uses a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass. For mass production, the substrate 101 is the 8th generation (2

[0031] ​​​​​​​160mm x 2460mm), 9th generation (2400mm x 2800mm, or 2450 10th generation (2950mm x 3400mm) mother glass It is preferable to use mother glass. If the processing temperature is high and the processing time is long, the mother glass will shrink significantly. Therefore, when using mother glass for mass production, the heat treatment in the manufacturing process is 600 It is desirable to set the temperature at or below 450°C, preferably at or below 450°C.

[0032] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material can also be used as the substrate 101. Alternatively, crystallized glass or the like can be used. Furthermore, the surface of a semiconductor substrate such as a silicon wafer or a metal material can be used. A conductive substrate having an insulating layer formed on the surface thereof may also be used.

[0033] The first electrode layer 102a is a low-resistance conductive film, specifically an aluminum film or a copper film, or These films are then coated with titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo ), chromium (Cr), Nd (neodymium), and Sc (scandium) Alternatively, an alloy film in which a plurality of layers are combined is used.

[0034] The second electrode layer 102b is a metal nitride film, such as titanium nitride or nitride, which functions as a barrier layer. Tantalum, tungsten nitride, molybdenum nitride, chromium nitride, etc. are used.

[0035] The third electrode layer 102c is a nitrogen-containing In-Ga-Zn-O film or a nitrogen-containing In-Sn -O film, nitrogen-containing In-Ga-O film, nitrogen-containing In-Zn-O film, nitrogen-containing A Sn-O film, a nitrogen-containing In-O film, or a metal nitride film (InN, SnN, etc.) is used. As the third electrode layer 102c, these films have a work function of 5 electron volts, preferably 5.5 electron volts or higher, which can make the threshold voltage of the electrical characteristics of the transistor positive and realize a so-called normally-off switching element. This is different from a transistor using silicon. An n-type transistor using silicon makes the threshold positive by using an element that imparts p-type to the gate electrode or by doping a trace amount of an impurity element that imparts p-type into silicon. On the other hand, for a transistor using an In-Ga-Zn-O film as the semiconductor layer the threshold voltage can be made positive by using a gate electrode containing nitrogen. In this embodiment, an In-Ga-Zn-O film containing nitrogen is used. The film formation conditions are as follows: an oxide target (manufactured by Mitsui Kinzoku) with In2O 3:Ga2O3:ZnO = 2:2:1 [mole ratio] is used, the distance between the substrate and the target (also called the T-S distance) is 40 mm or more and 300 mm or less, the pressure is 0.4 to 0.6 Pa, the argon gas flow rate is 0 to 175 sccm, the nitrogen gas flow rate is 2

[0036] 5 to 200 sccm, the power is 1 kW to 5 kW, and the substrate temperature is 80°C or higher and less than 450°C. Also, since the resistance of the In-Ga-Zn-O film containing nitrogen decreases when heat treatment is performed, heat treatment may be performed to reduce the resistance if necessary. However, when aluminum is used as the first electrode layer 102a, the heat treatment is 380°C or lower, and when copper is used as the first electrode layer 102a the heat treatment is 450°C or lower. Note that the In-Ga-Zn-O film containing nitrogen is a polycrystal with c-axis orientation and has high crystallinity. Also, as a result of measuring a single film formed by sputtering with a nitrogen gas flow rate of 40 sccm, the In-Ga-Zn-O film containing nitrogen has a resistivity of about 10^-4 Ω·cm, which is lower than that of an In-Ga-Zn-O film without nitrogen doping. has a resistivity of about 10^-4 Ω·cm, which is lower than that of an In-Ga-Zn-O film without nitrogen doping. has a resistivity of about 10^-4 Ω·cm, which is lower than that of an In-Ga-Zn-O film without nitrogen doping. has a resistivity of about 10^-4 Ω·cm, which is lower than that of an In-Ga-Zn-O film without nitrogen doping. has a resistivity of about 10^-4 Ω·cm, which is lower than that of an In-Ga-Zn-O film without nitrogen doping. is a polycrystal with c-axis orientation and has high crystallinity. Also, as a result of measuring a single film formed by sputtering with a nitrogen gas flow rate of 40 sccm, the In-Ga-Zn-O film containing nitrogen has a resistivity of about 10^-4 Ω·cm, which is lower than that of an In-Ga-Zn-O film without nitrogen doping. The work function of is 5.6 electron volts.

[0037] In addition, a film with a thickness of 300 nm was formed on a quartz substrate, and the film was then cooled to 400° C. for 4 h under a nitrogen atmosphere. The nitrogen-containing In-Ga-Zn-O film of the sample after heat treatment at 50 °C for 1 hour Hall effect measurement (Hall effect device: ResiTest8300 series, Toyo Tech Co., Ltd.) The results are shown in Figure 9. The vertical axis of the graph in Figure 9 is the carrier concentration. The horizontal axis indicates the ratio of nitrogen gas to the total deposition gas. It can be seen from Fig. 9 that the carrier concentration increases as the proportion of nitrogen gas increases. In addition, the carrier type of the In-Ga-Zn-O film containing nitrogen was N-type.

[0038] In addition, the results of measuring a single film formed by sputtering with a nitrogen gas flow rate of 40 sccm were The work function of the nitrogen-containing In-O film is 5.4 eV. The nitrogen gas flow rate is 4 The results of measuring a single film formed by sputtering at 0 sccm showed that the In-S The work function of the nO film is 5.5 eV. The nitrogen gas flow rate is 40 sccm. The work of the nitrogen-containing In-Ga-O film was measured using a single sputtering method. The function is 5.4 eV. The sputtering rate is 40 sccm for nitrogen gas. As a result of measuring a single film formed by the annealing method, the work function of the nitrogen-containing In-Zn-O film was 5.5 The electron volts are shown in Fig. 1. The single film was formed by sputtering with a nitrogen gas flow rate of 40 sccm. Measurements showed that the work function of the nitrogen-containing Sn-O film was 5.1 eV.

[0039] Next, a gate insulating layer 103 covering the gate electrode layer is formed. The gate insulating layer 103 has a film thickness of 10 nm or more and 300 nm or less.

[0040] The gate insulating layer 103 is formed of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, gallium oxide, gallium zinc oxide (also called GZO), aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, or a mixed material thereof, using a single layer or a stacked layer by using a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed by a plasma CVD method using SiH4, oxygen, and nitrogen as film-forming gases.

[0041] Next, an oxide semiconductor film is formed on the gate insulating layer 103.

[0042] The oxide semiconductor film is formed using a sputtering method or the like, using a metal oxide target containing at least zinc, and having a film thickness of 5 nm or more and 5 0 μm or less obtained in an atmosphere of only oxygen or a mixed atmosphere of argon and oxygen. Representative examples of the metal oxide target include a quaternary metal oxide In-Sn-Ga-Zn-O-based metal oxide, a ternary metal oxide In-Ga-Zn- O-based metal oxide, In-Sn-Zn-O-based metal oxide, In-Al-Zn-O-based metal oxide, Sn-Ga-Zn-O-based metal oxide, Al-Ga-Zn-O-based metal oxide, Sn-A l-Zn-O-based metal oxide, and a binary metal oxide In-Zn-O-based metal oxide, S n-Zn-O-based metal oxide, etc. can be used as the target.

[0043] Also, in order to shift the threshold voltage of the transistor in the positive direction, oxidation The semiconductor film may contain a small amount of nitrogen to lower the Fermi level (E F ). However, when a small amount of nitrogen is contained in the oxide semiconductor film, the nitrogen concentration of the oxide semiconductor film shall be lower than the nitrogen concentration of the buffer layer formed later.

[0044] Also, when forming the oxide semiconductor film, by setting the pressure in the processing chamber of the sputtering apparatus to 0.4 Pa or less , it is possible to reduce the incorporation of impurities such as alkali metals and hydrogen into the film-forming surface and the film-formed object. Note that the hydrogen contained in the film-formed object may be contained not only as hydrogen atoms but also as hydrogen molecules, water, hydroxyl groups, or hydrides.

[0045] Also, when forming the oxide semiconductor film, the distance between the targets (T-S distance) shall be 40 mm or more and 300 mm or less (preferably 60 mm or more).

[0046] Also, when forming the oxide semiconductor film by sputtering, the temperature of the film-forming surface shall be 25 0 °C or higher, preferably equal to or lower than the upper limit temperature of the heat treatment of the substrate. 250 °C is the temperature that prevents the incorporation of impurities such as water and hydrogen into the film-formed object and releases the impurities into the gas phase in the chamber. Also, the upper limit of the temperature of the film-forming surface during film formation by sputtering shall be the upper limit temperature of the heat treatment of the substrate or the upper limit temperature of the film-formed object (the temperature at which the components during film formation change significantly when exceeding this temperature ).

[0047] Also, when forming the oxide semiconductor film, by setting the leak rate of the processing chamber of the sputtering apparatus to 1×1 0 -10 Pa·m 3 / second or less, it is possible to reduce the incorporation of impurities such as alkali metals and hydrides into the oxide semiconductor film during film formation by sputtering. ​​​​​​​ Also, by using an adsorption type vacuum pump (such as a cryopump, etc.) as the exhaust system, the backflow of impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrides from the exhaust system can be reduced.

[0048] It is preferable to continuously form the gate insulating layer 103 and the oxide semiconductor film without exposing them to the atmosphere. When forming the film continuously, each laminated interface can be formed without being contaminated by atmospheric components or contaminant impurity elements floating in the atmosphere.

[0049] After forming the oxide semiconductor film, if necessary, heat treatment (temperature range of 200 °C or higher and 450 °C or lower) can be performed in an atmosphere containing almost no hydrogen and moisture (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, for moisture, the dew point is -40 °C or lower, preferably -60 °C or lower), etc.). This heat treatment can also be called dehydration or dehydrogenation to desorb H, OH, etc. from the oxide semiconductor layer. When performing heat treatment by heating up in an inert atmosphere and then switching to an atmosphere containing oxygen halfway, or when performing heat treatment in an oxygen atmosphere, it can also be called oxidation treatment.

[0050] Next, a resist mask is formed on the oxide semiconductor film using a second photomask, and selectively etched to form an island-shaped oxide semiconductor layer 104. Then, the resist mask is removed.

[0051] Next, a buffer layer 105, a first conductive film 106a, a second conductive film 106b, and a third conductive film 106c are formed on the island-shaped oxide semiconductor layer 104. The cross-sectional view at this stage is shown in Fig. 1(A).

[0052] The buffer layer 105 can use an In-Ga-Zn-O film containing nitrogen, or an In-Sn -O film or the like.

[0053] The In-Ga-Zn-O film containing nitrogen is used for a part of the buffer layer 105 and the gate electrode layer, and has significantly different film characteristics from the In-Ga-Zn-O film used for the oxide semiconductor layer. In this specification, the film obtained by introducing oxygen gas into the chamber during film formation using a target for an In-Ga-Zn-O-based oxide semiconductor is called an In-Ga-Zn-O film.

[0054] FIG. 2(A) and FIG. 2(B) show the light transmittance of the actually formed In-Ga-Zn-O film and the In-Ga-Zn-O film containing nitrogen.

[0055] All the samples shown in FIG. 2(A) use the same target (oxide target (manufactured by Mitsui Kinzoku) with In2O3:Ga2O3:ZnO = 2 :2:2 [mole ratio]), with a T-S distance of 60 mm, a pressure of 0.4 Pa, a power of 500 W, a substrate temperature of 200 °C, and a film thickness of 100 nm is formed on a 0.5 mm thick quartz glass. The results of varying the conditions of the film-forming gas flow rate are shown in FIG. 2(A). Sample 1 has an argon gas flow rate of 35 sccm and a nitrogen gas flow rate of 5 sccm, Sample 2 has an argon gas flow rate of 20 sccm and a nitrogen gas flow rate of 20 sccm, Sample 3 has a nitrogen gas flow rate of 40 sccm, Sample 4 has an oxygen gas flow rate of 40 sccm Sample 5 has an oxygen gas flow rate of 30 sccm and a nitrogen gas flow rate of 10 sccm, Sample 6 has an oxygen gas flow rate of 20 sccm and a nitrogen gas flow rate of 20 sccm, and Sample 7 has an oxygen gas flow rate of 10 sccm and a nitrogen gas flow rate of 30 sccm.

[0056] Figure 2(B) shows the results of light transmittance with the substrate temperature at 400 °C during film formation. Figure 2(B ) All the samples shown are the same target (In2O3:Ga2O3:ZnO = 2:2:2 [mole ratio] oxide target (manufactured by Mitsui Kinzoku)) was used, the T-S distance was 60 mm, and the pressure was 0.4 Pa, the power was 500 W, and a 100-nm-thick film was formed on a 0.5-mm-thick quartz glass . Sample 1’ had an argon gas flow rate of 35 sccm and a nitrogen gas flow rate of 5 sccm , sample 3’ had a nitrogen gas flow rate of 40 sccm, sample 4’ had an oxygen gas flow rate of 4 0 sccm, and sample 6’ had an oxygen gas flow rate of 20 sccm and a nitrogen gas flow rate of 20 sc cm.

[0057] As shown in Figures 2(A) and 2(B), the In-Ga-Zn-O film obtained by introducing oxygen gas into the chamber during film formation is a film with high light transmittance and is almost transparent. On the other hand, the nitrogen-containing In-Ga-Zn- O film obtained by introducing nitrogen without introducing oxygen gas into the chamber during film formation is a brown film and has light-shielding properties.

[0058] Also, when these samples were each heat-treated at 450 °C for 1 hour in a nitrogen atmosphere, there was almost no change in the light transmittance. Also, a sample with the same film-forming conditions as sample 1 was measured by a thermal desorption spectrometer TDS (Thermal Desorption Spectros copy), and the results of the thermal desorption spectrum of H2O molecules desorbed from the film are shown in Figure 3 (A). The measurement conditions were a heating rate of about 30 °C / min, starting the measurement from 1×10 -8 (Pa), and during the measurement, the vacuum degree was about 1×10 -7 (Pa).

[0059] ​​​​Also, as Sample 8, with an oxygen gas flow rate of 15 sccm and a nitrogen gas flow rate of 30 sccm an In-Ga-Zn-O film (film thickness: 50 nm) obtained with a substrate temperature of 200 °C was subjected to TDS measurement and the results of the temperature-programmed desorption spectrum of H2O molecules desorbed from the film are shown in Fig. 3(B).

[0060] From Fig. 3(A) and Fig. 3(B), it can be said that the H2O content is almost the same at the same substrate temperature, and the thermal stability of both films is about the same. Also, although not shown here, the results of detecting N2 molecules by subjecting the same Sample 1 to TDS measurement and the results of detecting N2 molecules by subjecting the nitrogen-containing In-Ga-Zn-O film of Sample 1 to TDS measurement after heat treatment at 450 °C for 1 hour in a nitrogen atmosphere were almost the same.

[0061] Also, Sample 9 with a film thickness of 300 nm formed on a quartz substrate with a film formation condition of a substrate temperature of 400 °C and a nitrogen gas flow rate of 40 sccm and Sample 10 with a film thickness of 300 nm formed on a quartz substrate with a film formation condition of a substrate temperature of 400 °C and an oxygen gas flow rate of 40 sccm were each subjected to XRD measurement in the OUT OF PLANE, and the results are shown in Fig. 8(A) and Fig. 8(B). The nitrogen-containing In-Ga-Zn-O film (Sample 9) has high crystallinity immediately after film formation, and sharp peaks can be confirmed as shown in Fig. 8(A). Also, the In-Ga-Zn-O film (Sample 10) formed using only oxygen gas as the sputtering gas is found to have lower crystallinity than Sample 9. Thus, immediately after film formation, the In-Ga-Zn-O film and the nitrogen-containing In-Ga-Zn-O film are significantly different in film quality.

[0062] Next, on the third conductive film 106c, a resist mask 111 was formed using the third photomask ​​​​Perform the formation, selectively etch, and form the source electrode layers 108a to 108c or the drain electrode layers 109a to 109c. In this etching, the side surface of the resist mask 111 in the cross section and the side surface of the source electrode layers 108a to 108c or the side surface of the drain electrode layers 109a to 109c do not match Set the etching conditions.

[0063] Then, using the resist mask 111 as it is, selectively etch the buffer layer to form the first buffer layer 112a and the second buffer layer 112b. Note that the oxide semiconductor layer 107 having a concave portion is formed by the same etching process.

[0064] The cross-sectional view at this stage is shown in FIG. 1(B). The first buffer layer 112a having a cross-sectional shape protruding from the side surface of the source electrode layers 108a to 108c and the second buffer layer 112b having a cross-sectional shape protruding from the side surface of the drain electrode layers 109a to 109c are formed. Note that the etching order and the like are not limited as long as the same cross section as that in FIG. 1(B is obtained. ) is obtained.

[0065] After that, remove the resist mask 111.

[0066] Next, form the insulating layer 110. The insulating layer 110 functions as a passivation layer. The cross-sectional view at this stage is shown in FIG. 1(C).

[0067] The insulating layer 110 can be formed as a single layer or by stacking using the plasma CVD method, the sputtering method, or the like, using silicon oxide, nitrogen silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, zinc gallium oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, or a mixed material thereof. ​For example, a silicon oxynitride layer may be formed by plasma CVD using SiH4, oxygen, and nitrogen as the film-forming gas.

[0068] In this way, it is possible to fabricate the transistor shown in Fig. 1(C) using three photomasks. When fabricating the transistor shown in Fig. 1(C) as a switching element of the display device, a contact hole reaching the gate electrode layer or the drain electrode layer may be formed in the insulating layer 110, and a pixel electrode may be formed on the insulating layer 110. In this case, a fourth photomask for the contact hole and a fifth photomask for forming the pixel electrode are used, so a total of five photomasks are used.

[0069] The transistor has a first buffer layer 112a protruding from the side surfaces of the source electrode layers 108a to c and a second buffer layer 112b protruding from the side surfaces of the drain electrode layers 109a to c, and these buffer layers are structured to relieve electric field concentration.

[0070] Note that the length L in the channel length direction of the region of the buffer layer protruding from the side surface of the drain electrode layer (or the source electrode layer) can be appropriately adjusted according to etching conditions and the like. Generally, the length L in the channel length direction of the region of the buffer layer is the horizontal distance from the lower end of the drain electrode layers 109a to c (or the source electrode layers 108a to c) to the lower end of the second buffer layer 112b (or the first buffer layer 112a).

[0071] The resistivity of the tapered portion of the buffer layer, which is the electric field concentration relaxation region, depends on the thickness of the region and the length (L) in the channel length direction, but the implementer can appropriately select the material of the buffer layer and set the film thickness. ​​​​​​​​​​​​ , it may be adjusted to a desired resistivity by performing size design of the tapered portion or the like. At least the resistivity of the tapered portion of the buffer layer is set to a value lower than that of the channel formation region of the oxide semiconductor layer 107.

[0072] (Embodiment 2) In this embodiment, an example of manufacturing a transistor and a pixel electrode with a total of 4 photomasks, which is one less than that in Embodiment 1, will be described with reference to FIGS. 4 and 5. Since the manufacturing of the transistor is only partially different from that in Embodiment 1, detailed description of the same parts will be omitted here.

[0073] FIG. 4 is a top view showing a planar configuration of the pixel 310, and FIG. 5 is a cross-sectional view showing a stacked configuration of the pixel 310. Note that the dashed lines A1 - A2, B1 - B2, C1 - C2, D1 - D2 in FIG. 4 correspond to the cross-sections A1 - A2, B1 - B2, C1 - C2, D1 - D2 in FIGS. 5(A) to 5(D).

[0074] The transistor 311 shown in this embodiment has a shape in which the drain electrode layer 206b is surrounded by a U-shaped (C-shaped , U-shaped) source electrode layer 206a. By adopting such a shape, even if the area of the transistor is small, it is possible to secure a sufficient channel width, and it is possible to increase the amount of current (also referred to as on-current) flowing when the transistor is conducting.

[0075] The wiring 203 functions as a capacitive electrode or a capacitive wiring. In this embodiment, the wiring 203 and the drain electrode layer 206b are overlapped to form a capacitive element 313.

[0076] In addition, the semiconductor device described in this embodiment does not use the second photomask in Embodiment 1 for process simplification, and does not perform a photolithography process or an etching process for forming the island-shaped oxide semiconductor layer. As a result, the oxide semiconductor layer 205 remains in all of the pixel regions, resulting in a structure in which the wiring 212-i functions as a three-layer gate electrode layer, the wiring 216-j functions as one of the source electrode layer or the drain electrode layer,

[0077] and the wiring 216-j+1 functions as the other of the source electrode layer or the drain electrode layer, generating a parasitic transistor. Therefore, in this embodiment, a groove portion 230 from which the oxide semiconductor layer 205 is removed is provided in the pixel 310 to prevent the generation of the above-described parasitic transistor. By providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 212-i, generation of the parasitic transistor can be prevented. Further, by providing the groove portion 230 so as to cross both ends in the line width direction of the wiring 203, generation of other parasitic

[0078] transistors can be prevented. Note that a plurality of groove portions 230 may be provided on the wiring 212-i or on the wiring 203, respectively. Note that the groove portion 230 does not need to be provided in parallel with the wiring 216-j or the wiring 216-j+1, and may have a bent portion or a curved portion. Cross-section A1-A2 shows a stacked structure of the transistor 311 and the capacitor element 313. The transistor 311 is a transistor having a bottom gate structure. Cross- section B1-B2 shows a stacked structure from the wiring 216-j to the wiring 216-j+1 including the pixel electrode 210 and the groove portion 230. Further, cross-section shows the stacked structure. Further, the cross-section D1-D2 shows the stacked structure of the wiring 216-j+1, the intersection of the wiring 212-i, and the groove portion 230.

[0079] In the cross-section A1-A2 shown in FIG. 5(A), a base insulating layer 201 is formed on the substrate 200 , and a gate electrode layer 202 and a wiring 203 are formed on the base insulating layer 201. Further, a gate insulating layer 204 and an oxide semiconductor layer 205 are formed on the gate electrode layer 202 and the wiring 203. Further, buffer layers 312a, 312b, a source electrode layer 206a and a drain electrode layer 206b are formed on the oxide semiconductor layer 205. Further, in contact with a part of the oxide semiconductor layer 2 05, an insulating layer 207 is formed on the source electrode layer 206a and the drain electrode layer 206b. A pixel electrode 210 is formed on the insulating layer 207 and is electrically connected to the drain electrode layer 206b through a contact hole 208 formed in the insulating layer 207.

[0080] In the cross-section B1-B2 shown in FIG. 5(B), a base insulating layer 201 is formed on the substrate 200 , a gate insulating layer 204 is formed on the base insulating layer 201, and an oxide semiconductor layer 205 is formed on the gate insulating layer 204. Buffer layers 312a, 31 2c are formed on the oxide semiconductor layer 205, a wiring 216-j is formed on the buffer layer 312a, a wiring 216-j+1 is formed on the buffer layer 312 c, and an insulating layer 207 is formed on the oxide semiconductor layer 205, the buffer layers 312a, 312c, the wiring 216-j, and the wiring 216-j+1. Further, a pixel electrode 210 is formed on the insulating layer 207.

[0081] In the cross section C1-C2 shown in FIG. 5(C), an underlying insulating layer 201 is formed on a substrate 200 , and a wiring 212-i is formed on the underlying insulating layer 201. Further, on the wiring 212-i, a gate insulating layer 204 and an oxide semiconductor layer 205 are formed. Further, on the oxide semiconductor layer 2 05, a buffer layer 312a is formed, and a wiring 216-j is formed on the buffer layer 312a , and an insulating layer 207 is formed on the wiring 216-j.

[0082] In the cross section D1-D2 shown in FIG. 5(D), an underlying insulating layer 201 is formed on a substrate 200 , and a wiring 212-i is formed on the underlying insulating layer 201. The wiring 212-i has a three-layer structure and, in this embodiment, has a laminated structure of a copper film, a tungsten nitride film on the copper film, and an In-Ga-Zn-O film containing nitrogen on the tungsten nitride film . Further, on the wiring 212-i, a gate insulating layer 204 and an oxide semiconductor layer 205 are formed. Further, on the oxide semiconductor layer 2 05, a buffer layer 312c is formed, and a wiring 216-j+1 is formed on the buffer layer 312c, and an insulating layer 207 is formed on the wiring 216-j+1. In this embodiment, as the buffer layer 312c, an In-Sn-O film containing SiOx is used. Further, a part of the gate insulating layer 204, a part of the oxide semiconductor layer 205, and a part of the insulating layer 207 are removed to form a groove portion 230. The groove portion 230 is formed using the same photomask as that for forming a contact hole 208 formed in the insulating layer 207. Although not shown here, a contact hole reaching the gate electrode layer is also formed using the same photomask.

[0083] The formation of the groove portion 230 is performed using the same photomask as that for forming a contact hole 208 formed in the insulating layer 207. Further, although not shown here, a contact hole reaching the gate electrode layer is also formed using the same photomask.

[0084] ​​In addition, the oxide semiconductor layer 205 has sufficient translucency and does not pose a problem particularly in a transmissive liquid crystal display device even when it overlaps with the pixel electrode 210. For example, an In-Ga-Zn-O film obtained by introducing oxygen gas for film formation has high translucency as shown in FIGS. 2(A) and 2(B) and is suitable as the material of the oxide semiconductor layer 205. The semiconductor device described in this embodiment can be manufactured using a total of four photomasks: a first photomask for forming a gate electrode layer, a second photomask for forming a buffer layer, a source electrode layer, and a drain electrode layer, a third photomask for forming contact holes and grooves, and a fourth photomask for forming a pixel electrode. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. Further, as the liquid crystal layer, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal is heated and transitions from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet curable resin is added to improve the temperature range.

[0085] The semiconductor device described in this embodiment uses a total of four photomasks: a first photomask for forming a gate electrode layer, a buffer layer, a source electrode layer, and a drain electrode layer, a second photomask for forming contact holes and grooves, and a fourth photomask for forming a pixel electrode. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. The semiconductor device described in this embodiment can be manufactured using a total of four photomasks: a first photomask for forming a gate electrode layer, a buffer layer, a source electrode layer, and a drain electrode layer, a second photomask for forming contact holes and grooves, and a fourth photomask for forming a pixel electrode. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color.

[0086] When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color. When manufacturing a liquid crystal display device using the pixel including the transistor shown in FIGS. 4 and 5, an opposing substrate is bonded to the substrate 200, and a liquid crystal layer is provided therebetween. If the liquid crystal display device is a color filter type, a color filter and a black matrix are provided between the pixel electrode and the backlight. Also, if the liquid crystal display device is a field sequential type, a plurality of light sources (for example, R (red), G (green), B (blue)) presenting different colors are used, and a desired color is formed by time-division for each light presenting a specific color.

[0087] Further, as the liquid crystal layer, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal is heated and transitions from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet curable resin is added to improve the temperature range. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal is heated and transitions from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a chiral agent or an ultraviolet curable resin is added to improve the temperature range. The liquid crystal showing the blue phase and a chiral agent The liquid crystal composition containing a ral agent has a short response time of 10 μsec. or more and 100 μsec. or less and is optically isotropic, so alignment treatment is not required, and it is preferable because the viewing angle dependence is small .

[0088] When manufacturing an organic light-emitting display device using the transistors shown in FIGS. 4 and 5, two or more transistors are provided in a pixel, and an organic light-emitting element is formed with a pixel electrode electrically connected to at least one transistor as a cathode or an anode. In addition, since a partition wall made of an insulator is provided between adjacent pixel electrodes, one more photomask for patterning the partition wall is used , and an organic light-emitting display device can be manufactured with a total of five photomasks.

[0089] (Embodiment 3) Embodiment 1 and Embodiment 2 showed examples of bottom-gate type transistors, but here an example of manufacturing a top-gate type transistor is shown. In FIGS. 6(A), (B), (C) , the same reference numerals are used for the same parts as in FIGS. 1(A), 1(B), 1(C) for explanation .

[0090] In addition, in this embodiment, it is an example of manufacturing an oxide semiconductor layer by depositing it in two steps.

[0091] First, an oxide insulating film 160, which is an underlying insulating layer, is formed on a substrate 101.

[0092] The oxide insulating film 160 is formed using an oxide insulating film that releases a part of oxygen by heating . As the oxide insulating film that releases a part of oxygen by heating, it is preferable to use an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric ratio. The oxide insulating film that releases a part of oxygen by heating can diffuse oxygen into the crystalline oxide semiconductor film by heating . The oxide insulating film 160 is typically made of silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, hafnium oxide, yttrium oxide, etc. It can be formed with.

[0093] When the oxide insulating film 160 uses a Ga-Zn-O film or an α-Ga2O3 film having a hexagonal crystal structure, it is preferable because the crystal of the oxide semiconductor layer formed later and the crystal of the oxide insulating film 160, which is the underlying insulating layer, can be continuously aligned.

[0094] The oxide insulating film 160 is made to be 50 nm or more, preferably 200 nm or more and 500 nm or less. By increasing the thickness of the oxide insulating film 160, the amount of oxygen released from the oxide insulating film 160 can be increased, and the defects at the interface between the oxide insulating film 160 and the oxide semiconductor film formed later can be reduced due to the increase.

[0095] The oxide insulating film 160 is formed by a sputtering method, a CVD method, etc. Note that an oxide insulating film from which a part of oxygen is released by heating is preferably formed by using a sputtering method because it is easy to form.

[0096] Next, a first oxide semiconductor film having a film thickness of 1 nm or more and 10 nm or less is formed on the oxide insulating film 160.

[0097] In this embodiment, an oxide semiconductor target (In-Ga-Zn-O-based oxide semiconductor target (In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio])) is used, and the distance between the substrate and the target is 170 mm, the substrate temperature is 250 °C, the pressure is 0.4 Pa, and the direct current ​​​​​​​​(DC) Power supply: 0.5 kW, only oxygen, or form an oxide semiconductor film with a thickness of 5 nm in an argon and oxygen atmosphere for the first one.

[0098] Next, set the chamber atmosphere where the substrate is placed to nitrogen (dew point of -50°C or lower for moisture, preferably -60°C or lower for dew point), or dry air (dew point of -50°C or lower for moisture, preferably -60°C or lower for dew point), and perform the first heat treatment. The temperature of the first heat treatment is 35 0°C or higher and 750°C or lower. Also, the heating time of the first heat treatment is 1 minute or more and 24 hours or less to form the first crystalline oxide semiconductor layer 164 by the first heat treatment (refer to Fig. 6( A)).

[0099] Next, form a second oxide semiconductor film with a thickness greater than 10 nm on the first crystalline oxide semiconductor layer 164.

[0100] In this embodiment, use a target for oxide semiconductor (a target for In-Ga-Zn-O-based oxide semiconductor (In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio]) to form a second oxide semiconductor film with a thickness of 25 nm at a distance of 170 mm between the substrate and the target, a substrate temperature of 400°C, a pressure of 0.4 Pa, and a DC (DC) power supply of 0.5 kW, only oxygen, or in an argon and oxygen atmosphere. one.

[0101] Next, set the chamber atmosphere where the substrate is placed to nitrogen (dew point of -50°C or lower for moisture, preferably -60°C or lower for dew point), or dry air (dew point of -50°C or lower for moisture, preferably -60°C or lower for dew point), and perform the second heat treatment. The temperature of the second heat treatment is 35 0°C or higher and 750°C or lower. Also, the heating time of the second heat treatment is 1 minute or more and 24 hours or less Let it be so. The second crystalline oxide semiconductor layer 165 is formed by the second heat treatment (see Fig. 6( B)). In Fig. 6(B), the interface between the first crystalline oxide semiconductor layer 164 and the second crystalline oxide semiconductor layer 165 is indicated by a dotted line and is described as an oxide semiconductor stack, but there is no distinct interface, and it is illustrated for the sake of easy understanding.

[0102] The thus obtained first crystalline oxide semiconductor layer 164 and second crystalline oxide semiconductor layer 165 have a structure that is neither a single crystal structure nor an amorphous structure, and at least a part thereof is crystallized and has a c-axis orientation, which is a crystalline oxide semiconductor (also called C Axis Aligned Crys talline Oxide Semiconductor; CAAC-OS). )

[0103] Also, it is preferable to continuously perform the steps from the formation of the oxide insulating film 160 to the second heat treatment without exposing them to the atmosphere. Further, in order to promote the crystallization of the oxide semiconductor stack, when forming the first oxide semiconductor film or the second oxide semiconductor film, an oxygen gas cylinder containing a small amount of nitrogen or an argon gas cylinder containing a small amount of nitrogen may be introduced into the film formation chamber.

[0104] Next, the oxide semiconductor stack composed of the first crystalline oxide semiconductor layer 164 and the second crystalline oxide semiconductor layer 165 is processed to form an island-shaped oxide semiconductor stack.

[0105] The processing of the oxide semiconductor stack is performed by forming a mask with a desired shape on the oxide semiconductor stack using a first photomask and then etching the oxide semiconductor stack. It can be achieved. The above mask can be formed using methods such as photolithography. Alternatively, the mask may be formed using methods such as the inkjet method.

[0106] Note that the etching of the oxide semiconductor layer may be either dry etching or wet etching. Of course, these may be used in combination.

[0107] Next, a buffer layer, a first conductive film, a second conductive film, and a third conductive film are formed on the oxide semiconductor layer. The buffer layer, the first conductive film, the second conductive film, and the third conductive film are fabricated according to Embodiment Mode 1.

[0108] Next, a mask is formed on the third conductive film using a second photomask, and selective etching is performed to form the source electrode layers 108a - c or the drain electrode layers 109a - c. In this etching, the etching conditions are set such that the side surface of the resist mask does not match the side surface of the source electrode layers 108a - c or the side surface of the drain electrode layers 109a - c in cross section.

[0109] Then, using the resist mask as it is, the buffer layer is selectively etched to form the first buffer layer 112a and the second buffer layer 112b. After that, the resist mask is removed.

[0110] Next, a gate insulating layer 103 that covers the source electrode layers 108a - c or the drain electrode layers 109a - c and is in contact with the oxide semiconductor layer is formed. The gate insulating layer 103 is preferably formed using a Ga - Zn - O film or an α - Ga2O3 film having a hexagonal crystal structure because the crystal of the oxide semiconductor layer and the crystal of the gate insulating layer 103 can be continuously aligned.

[0111] Next, a third electrode layer 102c is formed on the gate insulating layer 103, and on top of that, a second electrode layer 102b is formed, and further on top of that, a first electrode layer 102a is formed. In this embodiment for the sake of correspondence with the stacked gate electrode layer in Fig. 1(A), the same materials are given the same names and will be described accordingly.

[0112] The third electrode layer 102c in contact with the gate insulating layer 103 is, as in Embodiment 1, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga -O film containing nitrogen, an In-Zn-O film containing nitrogen, an Sn-O film containing nitrogen, an In- O film containing nitrogen, a metal nitride film (such as InN, SnN), etc. are used.

[0113] In the above steps, a top-gate type transistor is formed (see Fig. 6(C)). The transistor has a first buffer layer 112a protruding from the side surfaces of the source electrode layers 108a to c and a second buffer layer 112b protruding from the side surfaces of the drain electrode layers 109a to c, and with these buffer layers, the structure is such that the electric field concentration is alleviated.

[0114] Note that the length L in the channel length direction of the region of the buffer layer protruding from the side surface of the drain electrode layer (or source electrode layer) can be appropriately adjusted according to etching conditions, etc. Generally the length L in the channel length direction of the region of the buffer layer is the horizontal distance from the lower end of the drain electrode layers 109a to c (or the source electrode layers 108a to c) to the lower end of the second buffer layer 112b (or the first buffer layer 112a).

[0115] The resistivity of the tapered portion of the buffer layer, which is an electric field concentration relaxation region, depends on the thickness of that region and the length (L) in the channel longitudinal direction. However, the implementer can appropriately adjust the resistivity to a desired value by selecting the material of the buffer layer, setting the film thickness , designing the size of the tapered portion, etc. At least the resistivity of the tapered portion of the buffer layer should be lower than that of the channel formation regions of the oxide semiconductor layer 166a and the oxide semiconductor layer 166b.

[0116] Note that the oxide semiconductor laminate obtained in this embodiment is not a single crystal throughout the laminate, but is a polycrystalline layer with a c-axis orientation perpendicular to the surface of the oxide semiconductor laminate and contains a plurality of crystals within the layer, but the respective a-b planes do not coincide.

[0117] Also, the buffer layer obtained in this embodiment is a polycrystal with a c-axis orientation perpendicular to the surface of the buffer layer and has higher crystallinity than the oxide semiconductor laminate.

[0118] Note that in this embodiment, an example of a top gate structure is shown, but it is not particularly limited, and a structure in which gate electrode layers are provided above and below with the oxide semiconductor laminate sandwiched therebetween may also be used.

[0119] Also, this embodiment can be freely combined with Embodiment 1 or Embodiment 2. For example, film formation is performed in two steps in this embodiment, and the oxide semiconductor laminate having a c-axis orientation can be used as the oxide semiconductor layer of Embodiment 1. Also, the oxide semiconductor laminate formed in two steps in this embodiment can be used as the oxide semiconductor layer of Embodiment 2, and a configuration in which the oxide semiconductor layer remains in all of the pixel regions may be used.

[0120] (Embodiment 4) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, television devices (also referred to as TVs or television receivers), monitors for computers, cameras such as digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. ) Examples of electronic devices equipped with the display device described in the above embodiment will be described.

[0121] FIG. 7(A) is a portable information terminal, which is composed of a main body 3001, a housing 3002, display units 3003a, 3003b, etc. The display unit 3003b is a panel having a touch input function, and by touching the keyboard button 3004 displayed on the display unit 3003b, screen operations and character input can be performed. Of course, the display unit 3003a may also be configured as a panel having a touch input function. By manufacturing a liquid crystal panel or an organic light emitting panel as a switching element of the semiconductor device shown in Embodiment 1 and applying it to the display units 3003a and 3003b, a highly reliable portable information terminal can be obtained.

[0122] FIG. 7(A) can have functions such as displaying various information (such as still images, moving images, text images, etc.), a calendar, date or time on the display unit, operating or editing the information displayed on the display unit, and controlling processing by various software (programs). Further, the back surface or side surface of the housing may be configured to include external connection terminals (such as earphone terminals, USB terminals, etc.) and a recording medium insertion part. ​​​​​​

[0123] Also, the portable information terminal shown in Fig. 7(A) may be configured to be able to wirelessly transmit and receive information. It is also possible to configure it to purchase and download desired book data, etc. from an e-book server wirelessly.

[0124] Also, in the portable information terminal shown in Fig. 7(A), one of the two display units 3003a and 3003b can be removed, and the figure in the case of removal is shown in Fig. 7(B). The display unit 3003a is also a panel with a touch input function, and when carrying it, further weight reduction can be achieved, and it can be operated with one hand holding the housing 3002 and the other hand, which is convenient.

[0125] Furthermore, the housing 3002 shown in Fig. 7(B) may be provided with an antenna, a microphone function, and a wireless function, and may be used as a mobile phone.

[0126] Fig. 7(C) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display video. Also, here, a configuration is shown in which the housing 9601 is supported by a stand 9605 incorporating a CPU. By applying the semiconductor device shown in Embodiment 1 to the display unit 9603, a highly reliable television device 9600 can be obtained.

[0127] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control operation device. Also, it is possible to configure the remote control operation device to be provided with a display unit for displaying information output from the remote control operation device.

[0128] ​​​​​​​​​​ Note that the television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can be connected to a communication network by wire or wirelessly via a modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0129] Also, the television device 9600 is provided with an external connection terminal 9604, a recording and playback unit 9602 for a storage medium, and an external memory slot. The external connection terminal 9604 can be connected to various cables such as a USB cable, enabling data communication with a personal computer or the like. In the recording and playback unit 9602 for a storage medium, a disk-shaped storage medium can be inserted, and data stored on the storage medium can be read and written to the storage medium. Also, images, videos, etc. stored in the external memory 9606 inserted into the external memory slot can

[0130] be projected onto the display unit 9603. As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other

[0131] 101 Substrate 102a - 102c Gate electrode layer 103 Gate insulating layer 104 Oxide semiconductor layer 105 Buffer layer 106a - 106c Conductive film 107 Oxide semiconductor layer 108a - 108c Source electrode layer 109a - 109c Drain electrode layer 110 Insulating layer 111 Resist mask 111 Post-resist mask 112a Buffer layer 112b Buffer layer 160 Oxide insulating film 164 Crystalline oxide semiconductor layer 165 Crystalline oxide semiconductor layer 166a, 166b Oxide semiconductor layer 200 Substrate 201 Underlying insulating layer 202 Gate electrode layer 203 Wiring 204 Gate insulating layer 205 Oxide semiconductor layer 206a Source electrode layer 206b Drain electrode layer 207 Insulating layer 208 Contact hole 210 Pixel electrode 212 Wiring 216 Wiring 230 Groove portion 310 Pixel 311 Transistor 312a Buffer layer 312b Buffer layer 312c Buffer layer 313 Capacitor element 3001 Body 3002 Housing 3003a Display section 3003b Display section 3004 Keyboard button 9600 Television apparatus 9601 Housing 9602 Memory medium playback / recording section 9603 Display section 9604 External connection terminal 9605 Stand 9606 External memory

Claims

1. A gate electrode layer, a gate insulating layer having a region on the gate electrode layer, an oxide semiconductor layer having a region overlapping the gate electrode layer via the gate insulating layer, a metal oxide layer having a region in contact with the oxide semiconductor layer, and an electrode having a region in contact with the metal oxide layer, wherein the electrode is electrically connected to the oxide semiconductor layer via the metal oxide layer, the metal oxide layer has a region overlapping the gate electrode layer via the oxide semiconductor layer in a region not overlapping the electrode, the metal oxide layer has indium, gallium, and zinc in a region overlapping the gate electrode layer, the oxide semiconductor layer has indium, gallium, and zinc in a region overlapping the gate electrode layer, the oxide semiconductor layer has crystals, the crystallinity of the metal oxide layer is higher than that of the oxide semiconductor layer, the metal oxide layer has a region c-axis oriented in a direction perpendicular or substantially perpendicular to the surface of the metal oxide layer, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the gate insulating layer is a laminate of silicon oxide and silicon nitride.

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