Substrate unit with support, substrate unit, semiconductor device, and manufacturing methods thereof

Abstract

To provide a substrate unit with a support, a substrate unit, a semiconductor device, and a manufacturing method thereof, which do not require a high-energy UV laser and hardly leave a peeling layer residue even after the support is peeled off.SOLUTION: In a substrate unit with a support, a peeling layer, a laser absorption layer that absorbs laser light, and a first wiring substrate are provided in this order, and a first electrode that can be bonded to at least one semiconductor element is provided on a first surface of the first wiring substrate, and a second electrode that can be bonded to a second wiring substrate is provided on a second surface of the first wiring substrate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a substrate unit with a support, a substrate unit, a semiconductor device, and manufacturing methods thereof.

Background Art

[0002] In recent years, as semiconductor devices have been advancing in high speed and high integration, for FC-BGA (Flip Chip-Ball Grid Array) substrates, there is a demand for reducing the pitch of bonding terminals with semiconductor elements and miniaturizing the wiring within the substrate. On the other hand, the bonding between the FC-BGA substrate and the motherboard is required to be performed with bonding terminals having substantially the same pitch as in the past. To cope with such reduction in the pitch of bonding terminals with semiconductor elements and miniaturization of the wiring within the FC-BGA substrate, several countermeasures have been studied. One of them is a method of creating a substrate for bonding semiconductor elements (silicon interposer) with fine wiring formed on a silicon substrate and bonding this to the FC-BGA substrate. Also, a method is disclosed in Patent Document 1 in which, without using a silicon interposer, the surface of the FC-BGA substrate is planarized by CMP (Chemical Mechanical Polishing) or the like, and fine wiring is formed on the FC-BGA substrate. Further, a method is disclosed in Patent Document 2 in which a fine wiring layer is formed on a support, this is mounted on the FC-BGA substrate, and then the support is peeled off to form a narrow pitch wiring substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] A silicon interposer is manufactured using a silicon wafer and equipment for pre-processes in semiconductor manufacturing. Since the silicon wafer has limitations in shape and size, the number of interposers that can be manufactured from a single wafer is small, and the manufacturing equipment is expensive, so the interposer is also expensive. In addition, since the silicon wafer is a semiconductor, there is a problem that the transmission characteristics deteriorate.

[0005] Also, in the method of planarizing the surface of the FC-BGA substrate and forming a fine wiring layer thereon, the deterioration of the transmission characteristics seen in the silicon interposer is small, but due to the manufacturing yield of the FC-BGA substrate itself and the high difficulty of forming the fine wiring formed on the FC-BGA substrate, the manufacturing yield of the fine wiring formation has become an issue. Furthermore, there are also issues in the mounting of semiconductor elements due to warping and distortion of the FC-BGA substrate.

[0006] On the other hand, in the method of forming a fine wiring layer on a support, mounting this on an FC-BGA substrate, or after forming a fine wiring layer on a support and integrating it with a semiconductor element, then peeling off the support, there were the following problems.

[0007] In the method of peeling off the support, a peeling layer is provided on the upper surface of the support, and the support is peeled off by irradiating the peeling layer with a laser. Since high-energy UV laser irradiation is required for peeling, there was a problem that a high-output laser device and repeated laser irradiation were required, and the load on the process became large. In addition, it was necessary to remove the peeling layer after peeling off the support, and there was a problem that a modified layer was likely to be formed due to laser irradiation, and residues were likely to occur on the surface of the wiring substrate.

[0008] Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a substrate unit with a support, a substrate unit, a semiconductor device, and manufacturing methods thereof that do not require a high-energy UV laser and are less likely to generate residues of the peeling layer even after peeling off the support.

Means for Solving the Problems

[0009] In order to solve the above problems, one aspect of the present invention provides a substrate unit with a support, a release layer, a laser absorption layer that absorbs laser light, and a first wiring substrate, which are provided in this order. On the first surface of the first wiring substrate, a first electrode capable of being joined to at least one semiconductor element is provided, and on the second surface of the first wiring substrate, a second electrode capable of being joined to a second wiring substrate is provided. and the peeling layer transmits 50% or more of the laser light It is a substrate unit with a support, characterized by the above.

[0010] Further, it is a substrate unit manufactured using the substrate unit with a support, characterized in that a second wiring substrate is joined to the second surface of the first wiring substrate, and the support is removed by laser irradiation.

[0011] Further, it is a semiconductor device manufactured using the substrate unit with a support, characterized in that on the first surface of the first wiring substrate in the substrate unit with a support, the first electrode and the semiconductor element are joined, and the support is removed by laser irradiation.

[0012] Further, another aspect of the present invention is A method for manufacturing a substrate unit with a support A step of forming a release layer and a laser absorption layer in this order on the upper surface of the support, a step of forming a seed layer on the laser absorption layer, a step of forming an electrode by an electrolytic plating layer on the seed layer, a step of repeatedly forming a resin layer and a conductor layer on the upper surface of the electrode to obtain a multilayer wiring, and a step of manufacturing a first wiring substrate by forming an electrode on the outermost surface of the multilayer wiring. It is a method for manufacturing a substrate unit with a support, characterized by including the above steps.

[0013] Further, a step of joining the substrate unit with a support manufactured using the method for manufacturing the substrate unit with a support to a second wiring substrate, and a step of peeling the support by peeling the release layer at the interface of the laser absorption layer by irradiating laser light. It is a method for manufacturing a substrate unit, characterized by including the above steps.

[0014] Also, a method for manufacturing a semiconductor device includes a step of bonding a semiconductor element to a substrate unit with a support, and a step of peeling the support by irradiating laser light to peel the peeling layer at the interface of the laser absorption layer.

Advantages of the Invention

[0015] According to the present invention, it is possible to provide a substrate unit with a support, a substrate unit, a semiconductor device, and a manufacturing method that do not require a high-energy UV laser and are less likely to generate residues of the peeling layer even after peeling the support.

[0016] Problems and effects other than those described above will be described in the following embodiments of the invention.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 7A

Figure 7B

Figure 8

Embodiments for Carrying Out the Invention

[0018] Embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0019] Also, the embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as the following. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

[0020] <First Embodiment> FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to the first embodiment of the present invention. In the present embodiment, the first wiring substrate is an interposer, and the second wiring substrate is an FC-BGA substrate.

[0021] A semiconductor device 25 according to an embodiment of the present invention includes a thin first wiring substrate (hereinafter, may be referred to as an "interposer") 1 provided with a fine wiring layer formed only of a build-up wiring layer in which a resin and wiring are laminated, on one surface of a second wiring substrate (hereinafter, may be referred to as an "FC-BGA substrate") 3. The first wiring substrate 1 and the second wiring substrate 3 are joined by joining electrodes such as solder bumps, copper posts (copper pillars), or gold bumps. The joined portion is referred to as an interposer-FC-BGA joint 19. Further, the gap between the first wiring substrate 1 and the second wiring substrate 3 is filled with an underfill 2 as an insulating adhesive member. Further, in the first wiring substrate 1, the surface on the side where the semiconductor element 4 is joined by a copper pillar or solder is defined as the first surface (the surface opposite to the second wiring substrate 3), and the portion where the semiconductor element 4 is joined is defined as a semiconductor element-interposer joint 21. The gap between the semiconductor element 4 and the first wiring substrate 1 is filled with an underfill 22.

[0022] The wiring width of the first wiring substrate (interposer) 1 is, for example, Line / Space = 1 / 1 to 5 / 5 μm, and the line width of the first wiring substrate (FC-BGA substrate) 1 is, for example, Line / Space = 8 / 8 to 25 / 25 μm. The wiring width of the first wiring substrate (interposer) 1 may be appropriately changed as long as it can be joined to the signal lines of at least one mounted semiconductor element 4.

[0023] Further, the insulating resin layer 12 (see FIG. 5B) used for the first wiring substrate (interposer) 1 is a photosensitive resin, and at least one of a photosensitive epoxy resin, polyimide, and polyamide is used. If it is possible to obtain a desired wiring width, the wiring formation method may appropriately select a process from methods such as Damascene and SAP: Semi Additive Process.

[0024] The underfill 2 is an adhesive material used to fix the first wiring board 1 and the second wiring board 3 and to seal the interposer-FC-BGA joint 19. As the underfill 2, for example, one kind of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a resin in which two or more of these resins are mixed, is added with silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide, etc. as a filler. The underfill 2 may be formed by filling a liquid resin.

[0025] The underfill 22 is an adhesive material used to fix the semiconductor element 4 and the first wiring board 1 and to seal the semiconductor element-interposer joint 21, and is composed of the same material as the underfill 2. Further, instead of the underfill 2 and / or the underfill 22 that utilize these capillary phenomena to fill the liquid resin after bonding, an anisotropic conductive film (ACF) that pre-arranges a sheet-like film before bonding and fills the space during bonding, a film-like bonding material (NCF), or a non-conductive paste (NCP) that pre-arranges a liquid resin before bonding and fills the space during bonding may be used.

[0026] The encapsulation resin 5 that encapsulates up to the side surface of the first wiring board 1 is a material different from the underfills 2 and 22, and is a resin in which one kind of epoxy resin, silicone resin, acrylic resin, urethane resin, polyester resin, oxetane resin, or two or more of these resins are mixed, added with silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide, etc. as a filler, and is formed by compression molding, transfer molding, etc. In FIG. 1, it encapsulates up to the side surface of the first wiring board 1, but if the semiconductor element 4 is encapsulated, the design can be changed as appropriate. For example, the side surface of the semiconductor element 4 may be encapsulated, but the side surface of the first wiring board 1 may not be encapsulated.

[0027] The individual intervals between the semiconductor element - interposer joints 21 are generally narrower than the individual intervals of the interposer - FC - BGA joints 19. Therefore, on the first wiring substrate 1, finer wiring is required on the first surface side where the semiconductor element 4 is joined than on the side joined to the FC - BGA substrate. For example, in order to support the current use of high - bandwidth memory (HBM), the wiring width on the first surface of the first wiring substrate 1 needs to be about 1 μm or more and 5 μm or less. For example, when the wiring width is 2 μm and the wiring height is 2 μm, and the film thickness of the insulating layer between the wirings is 2 μm, the thickness of one layer including the wiring is 4 μm, and two wiring layers are formed with this thickness. Further, when the electrode thickness of the joint between the first wiring substrate 1 and the second wiring substrate 3 and the joint between the first wiring substrate 1 and the semiconductor element 4 is 10 μm, the first wiring substrate 1 with a total thickness of about 28 μm is obtained.

[0028] FIG. 2 is a cross - sectional view showing the configuration of a substrate unit with a support according to an embodiment of the present invention. As described above, the thickness of the first wiring substrate 1 is as thin as about 28 μm in total, and it is difficult to join with the second wiring substrate 3 in its original state. Therefore, as shown in FIG. 2, it is effective to ensure rigidity using the support 6. Also, for forming wirings having a width and height of about 2 μm, a rigid support 6 with little deformation is advantageous. For the above reasons, as shown in FIG. 2, the first wiring substrate 1 is formed on the rigid support 6 via a release layer 7, a laser absorption layer 8, and a first seed layer 9. Note that layers other than the release layer 7, the laser absorption layer 8, and the first seed layer 9 may be provided on the support 6.

[0029] Next, taking the case of using the support 6, which is a rectangular plate - like member, as an example, it will be described with reference to FIGS. 3 and 4. FIG. 3 is a view showing a state where a release layer and a laser absorption layer are formed above the support, FIG. 3(a) shows a cross - sectional view showing a state where the release layer 7 and the laser absorption layer 8 are formed on the upper surface of the support 6, and FIG. 3(b) shows a plan view of the support 6, the release layer 7, and the laser absorption layer 8 viewed from above the support 6. FIG. 4 is a plan view showing a state where a plurality of second wiring substrates are placed above the support. On one surface of the support 6, a release layer 7 and a laser absorption layer 8 necessary for peeling the support 6 in a later process are formed.

[0030] The laser absorption layer 8 may be formed in the same shape as the planar shape of the release layer 7. However, as shown in FIGS. 3(a) and 3(b), the laser absorption layer 8 does not necessarily have to be formed at the end of the release layer 7. In addition, in the peripheral portion of the release layer 7 as shown in FIG. 3, the region where the laser absorption layer 8 is not formed may be obtained by a process of removing the laser absorption layer 8 in the peripheral portion of the release layer 7 after forming the laser absorption layer 8 on the entire upper surface of the release layer 7. As the process of removing the laser absorption layer 8, a protective film is formed in the peripheral portion of the release layer 7 before forming the laser absorption layer 8. After forming the laser absorption layer 8 on the release layer 7 and the upper surface of the protective film, the protective film is removed, and the laser absorption layer formed on the upper surface of the protective film is removed, so that the laser absorption layer in the peripheral portion of the release layer 7 may be removed.

[0031] Since the release layer 7 can be peeled off by using the heat generated when the laser absorption layer 8 absorbs the laser, it is preferable that the release layer 7 and the laser absorption layer 8 are in contact with each other. If there is a region where the laser absorption layer 8 is in contact with the support 6, peeling becomes difficult. Therefore, the laser absorption layer 8 is formed in a region inside the release layer 7 in a plan view. Further, as shown in FIG. 4, the plurality of first wiring boards 1 above the support 6 are placed in the inner region of the laser absorption layer 8, so that the first wiring board 1 can be peeled off from the support 6 with good yield.

[0032] In the present embodiment, as shown in FIG. 4, a plurality of first wiring boards 1 are placed above the support 6, and a board unit composed of the plurality of first wiring boards 1 is formed. The support 6 is described using a panel which is a rectangular plate-like member in the present embodiment. However, the support 6 may be, for example, a circular wafer.

[0033] Next, an example of the manufacturing process of the interposer (first wiring board 1) on the support 6 according to the first embodiment of the present invention will be described with reference to FIGS. 5A to 5C. FIGS. 5A to 5C are cross-sectional views showing an example of the manufacturing process of a substrate unit with a support according to an embodiment of the present invention.

[0034] First, as shown in FIG. 5A(a), a support 6 is prepared. Since the support 6 is to be peeled from the release layer 7 and the laser absorption layer 8 by irradiation with laser light, it is necessary to have translucency, and for example, glass can be used. Glass is excellent in rigidity and is suitable for forming a fine pattern on the first wiring board 1. Further, since glass has a small coefficient of thermal expansion (CTE) and is less likely to be distorted, it is excellent in ensuring pattern arrangement accuracy and flatness.

[0035] When glass is used as the support 6, the thickness of the glass is preferably large from the viewpoint of suppressing the occurrence of warping in the manufacturing process, for example, a thickness of 0.7 mm or more, preferably 1.1 mm or more. Further, the CTE of the glass is preferably 3 ppm or more and 15 ppm or less, and more preferably about 9 ppm from the viewpoint of the CTE of the second wiring board 3 and the semiconductor element 4.

[0036] Next, as shown in FIG. 5A(b), a release layer 7 and a laser absorption layer 8 necessary for peeling the support 6 in a later process are formed in this order on one surface of the support 6.

[0037] The release layer 7 can be selected from organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicon resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin. Further, the release layer 7 may be composed of a plurality of layers. For example, for the purpose of protecting the multilayer wiring layer formed on the support 6, a protective layer may be further provided on the release layer 7, and its configuration is not limited by this embodiment.

[0038] As a method for forming the release layer 7, when a liquid organic resin is used, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating method, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. When a film-like organic resin is used, lamination, vacuum lamination, vacuum pressing, etc. can be applied.

[0039] It is desirable that the thickness of these release layers 7 be 10 nm or more. When it is 10 nm or less, it is difficult to form the organic resin. The upper limit of the thickness is limited by the transmittance of the laser light. Since the laser light needs to pass through the release layer 7 from the support 6 side and irradiate the laser absorption layer 8, the release layer 7 preferably transmits 50% or more of the infrared laser light, and more preferably 80% or more from the viewpoint of being able to lower the laser output.

[0040] For the laser absorption layer 8, a material that absorbs infrared light can be selected, and it can be formed using an element selected from tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, silicon, an alloy material containing the element, or a compound material containing the element, etc.

[0041] As a method for forming the laser absorption layer 8, a vacuum evaporation method, a sputtering method, an ion plating method, an MBE method, a laser ablation method, a CVD method, etc. can be applied. It is desirable that the thickness of the laser absorption layer 8 be 1 nm or more and 500 nm or less. When it is 1 nm or less, it does not function as a continuous film and cannot absorb the laser. Also, when it is 500 nm or more, it is a layer to be removed after peeling the support, and the load on the process becomes high. Also, it is more preferably 5 nm or more and 100 nm or less. Also, considering the generation of heat due to absorption, the absorption rate of the infrared light is preferably 50% or more. For example, 500 nm of polyimide resin can be used as the release layer 7, 50 nm of titanium can be used as the laser absorption layer 8, and glass can be used for the support 6.

[0042] Next, the process of forming the first wiring substrate 1 on the upper surface of the release layer will be described with reference to the drawings after FIG. 5A(c).

[0043] First, in a vacuum, a first seed layer 9 is formed on the laser absorption layer 8. The first seed layer 9 acts as a power supply layer for electrolytic plating in wiring formation. The first seed layer 9 is formed, for example, by a sputtering method or a CVD method, and for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloys, etc. can be applied alone or in combination of a plurality. Considering the electrical characteristics, ease of manufacturing, and cost, it is preferable to sequentially form a titanium layer and then a copper layer by a sputtering method. The titanium layer is a layer that ensures the adhesion of the upper copper layer, and the copper layer mainly acts as a power supply layer for electrolytic plating. The total film thickness of the titanium and copper layers is preferably 1 μm or less as a power supply layer for electrolytic plating. For example, Ti: 50 nm, Cu: 300 nm can be used.

[0044] In order to ensure the adhesion between the laser absorption layer 8 and the first seed layer 9, titanium may be used as the same material. By using the same material, when removing the support 6 after peeling, it can be removed at once, so the process can be simplified.

[0045] Next, as shown in FIG. 5A(d), a first resist pattern 10 is formed on the first seed layer 9. The first resist pattern 10 can be formed by a known photolithography method.

[0046] Thereafter, as shown in FIG. 5A(e), after forming a conductor layer (first electrode) 11 by electrolytic plating, the first resist pattern 10 is removed. The conductor layer 11 becomes an electrode (bonding electrode) that can be joined to the semiconductor element 4. In this case, the thickness of the bonding electrode is preferably 5 μm or more.

[0047] In this way, on the first surface of the first wiring board 1, electrodes that can be joined to at least one semiconductor element are provided. Note that examples of the electrolytic plating method for forming the conductor layer 11 include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. Among these, electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity. From the viewpoints of circuit bonding reliability and manufacturing cost, the thickness of the electrolytic copper plating is preferably 1 μm or more and 30 μm or less. The first resist pattern 10 can be removed by a known stripping solution such as an alkaline solvent, for example.

[0048] Next, as shown in FIG. 5B(f), an insulating resin layer 12 is formed. The insulating resin layer 12 is formed such that the conductor layer 11 is embedded within the layer of the insulating resin layer 12. The insulating resin layer 12 can be formed, for example, by spin-coating a photosensitive epoxy resin. The photosensitive epoxy resin can be cured at a relatively low temperature and has little shrinkage due to curing after formation, so it is excellent for subsequent fine pattern formation.

[0049] The insulating resin layer 12 can be formed by spin-coating using a photosensitive epoxy resin, or can also be formed by subjecting an insulating resin film to compression curing with a vacuum laminator. In this case, an insulating film with good flatness can be formed. Additionally, for example, polyimide can also be used as the insulating resin.

[0050] Next, as shown in FIG. 5B(g), openings are formed in the insulating resin layer 12 by photolithography. The openings are formed so as to expose a part of the conductor layer 11. Plasma treatment may be performed on the openings for the purpose of removing residues during development.

[0051] Next, as shown in FIG. 5B(h), a second seed layer 13 is provided on the conductor layer 11 exposed by the opening of the insulating resin layer 12 and at least in the region where the conductor layer 15 described later is to be formed on the insulating resin layer 12. The configuration of the second seed layer 13 is the same as that of the first seed layer 9 described above, and the configuration and thickness can be changed as appropriate. For example, it is formed by sputtering with Ti: 50 nm and Cu: 300 nm.

[0052] Next, as shown in FIG. 5B(i), a second resist pattern 14 is patterned on the second seed layer 13, and a conductor layer (wiring layer) 15 is formed by electrolytic plating in the opening of the second resist pattern 14. The conductor layer 15 becomes a wiring layer inside the first wiring substrate 1 and is formed of, for example, copper. Then, as shown in FIG. 5B(j), the second resist pattern 14 is removed. Then, unnecessary portions of the second seed layer 13 are removed by etching.

[0053] Next, the steps from FIG. 5B(f) to FIG. 5B(j) are repeated to obtain a first wiring substrate 1 in which the conductor layer (wiring layer) 15 is multilayered as shown in FIG. 5B(k). Here, the conductor layer (second electrode) 16 formed on the outermost surface is an electrode for bonding to the second wiring substrate 3. In this case, the thickness of the bonding electrode is preferably 5 μm or more. In this way, an electrode capable of bonding to the second wiring substrate (FC - BGA substrate) 3 is provided on the second surface of the first wiring substrate 1.

[0054] Next, as shown in FIG. 5C(l), a outermost surface insulating resin layer 17 is formed on the first wiring substrate 1, and an opening for exposing at least a part of the conductor layer 16 is formed in the outermost surface insulating resin layer 17 by photolithography. The outermost surface insulating resin layer 17 is formed of, for example, a photosensitive epoxy resin. Note that the outermost surface insulating resin layer 17 may be made of the same material as the insulating resin layer 12.

[0055] Next, as shown in FIG. 5C(m), a surface treatment layer 18 may be provided to prevent oxidation of the surface of the conductor layer 16 and improve the wettability of the solder bumps. Electroless Ni / Pd / Au plating may be formed as the surface treatment layer 18. In addition, an OSP (Organic Soiderability Preservative, surface treatment with a water-soluble preflux) film may be formed on the surface treatment layer 18. Alternatively, electroless tin plating, electroless Ni / Au plating, etc. may be appropriately selected according to the application.

[0056] Next, as shown in FIG. 5C(n), after mounting a solder material on the surface treatment layer 18 and then melting and cooling it once to fix it, an interposer-FC-BGA joint 19a on the first wiring board 1 side composed of solder bumps or the like is obtained. Thereby, the substrate unit 23 with a support, which is the first wiring board (interposer) 1 formed on the support 6, is completed.

[0057] Subsequently, with reference to FIGS. 6A to 6E, an example of the bonding process between the first wiring board (interposer) 1 formed on the support 6 and the second wiring board (FC-BGA board) 3 will be described. FIGS. 6A to 6E are cross-sectional views showing an example of a method for manufacturing a substrate unit according to an embodiment of the present invention.

[0058] As shown in FIG. 6A, an interposer-FC-BGA joint 19b on the second wiring board 3 side composed of solder bumps or the like is designed in accordance with the interposer-FC-BGA joint 19a on the first wiring board 1 side. The first wiring board 1 formed on the support 6 is arranged with respect to the manufactured second wiring board 3. After bonding the first wiring board 1 and the second wiring board 3 formed on the support 6 as shown in FIG. 6B, underfill 2 is filled to fix the first wiring board 1 and the second wiring board 3 and seal the interposer-FC-BGA joint 19.

[0059] Next, as shown in FIG. 6C, laser light 20 is irradiated from the back surface of the support 6, that is, the surface opposite to the first wiring board 1 of the support 6, onto the laser absorption layer 8 formed at the interface with the release layer 7. Due to the heat generated by the laser absorption layer 8 absorbing the laser light 20, the release layer 7 decomposes, and the release layer 7 and the laser absorption layer 8 become in a separable state. Therefore, as shown in FIG. 6D, the support 6 can be removed.

[0060] Next, the laser absorption layer 8 and the first seed layer 9 are removed, and a substrate as shown in FIG. 6E can be obtained. For example, when titanium is used as the laser absorption layer 8, it can be dissolved and removed with an alkaline etching agent. At this time, if the first seed layer 9 is titanium, the first seed layer 9 can also be dissolved and removed simultaneously.

[0061] The remaining copper layer of the first seed layer 9 can be dissolved and removed with an acid-based etching agent. In this way, the first wiring board (interposer) 1 and the second wiring board (FC - BGA board) 3 are joined.

[0062] After that, in order to prevent oxidation and improve the wettability of the solder bumps, surface treatments such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, electroless Ni / Au plating, etc. may be performed on the conductor layer 11 exposed on the surface. Thus, the substrate unit 24 with the support removed is completed.

[0063] After that, the semiconductor element 4 is joined to the substrate unit 24 with the support removed, the underfill 22 is filled, the semiconductor element 4 and the first wiring board 1 are fixed, and the semiconductor element - interposer joint 21 is sealed. By sealing the semiconductor element 4 with the sealing resin 5, the semiconductor device 25 is completed.

[0064] <Second Embodiment> Next, a method for manufacturing a semiconductor device 26 in which a first wiring substrate 1 and a semiconductor element 4 are mounted on a second wiring substrate 3 according to the second embodiment will be described. The method for manufacturing the first wiring substrate 1 on the support 6 according to the second embodiment is similar to the method for manufacturing the first wiring substrate 1 on the support 6 according to the first embodiment. However, in the first embodiment, the first wiring substrate 1 is peeled off from the support 6, bonded to the second wiring substrate 3, and then the semiconductor element 4 is bonded. In contrast, in the second embodiment, after the semiconductor element 4 is bonded to the first wiring substrate 1 formed on the support 6, the first wiring substrate 1 and the semiconductor element 4 are peeled off from the support 6, and then the first wiring substrate 1 and the semiconductor element 4 are bonded to the second wiring substrate 3.

[0065] Therefore, in the first wiring substrate 1 in the first embodiment, the surface on the side opposite to the support 6 becomes the second surface of the first wiring substrate 1, and electrodes for bonding to the second wiring substrate 3 are provided on this second surface. The surface on the support 6 side becomes the first surface of the first wiring substrate 1, and electrodes for bonding to the semiconductor element 4 are provided on this surface. However, in the first wiring substrate 1 in the second embodiment, the surface on the side opposite to the support becomes the first surface of the first wiring substrate 1, and electrodes for bonding to the semiconductor element 4 are provided on this surface. The surface on the support side becomes the second surface of the first wiring substrate 1, and electrodes for bonding to the second wiring substrate 3 are provided on this surface.

[0066] Hereinafter, an example of the manufacturing process of the semiconductor device 26 according to the second embodiment of the present invention will be described with reference to FIGS. 7A, 7B, and 8. FIGS. 7A and 7B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 8 is a cross-sectional view showing an example of a semiconductor device according to an embodiment of the present invention.

[0067] As shown in FIG. 7A(a), on the surface of the first wiring substrate 1 opposite to the support 6, the semiconductor element 4 is bonded to the first wiring substrate 1 with copper pillars or solder. The bonded portion is referred to as a semiconductor element - interposer bonding portion 21.

[0068] Next, as shown in FIG. 7A(b), an underfill 22 is filled in the vicinity of the semiconductor element-interposer joint 21 to fix the semiconductor element 4 and the first wiring substrate 1 and to seal the semiconductor element-interposer joint 21.

[0069] Next, as shown in FIG. 7A(c), a sealing resin 5 for sealing the semiconductor element 4 is formed. The sealing resin 5 is made of a material different from the underfills 2 and 22, and is a resin in which one kind of epoxy resin, silicone resin, acrylic resin, urethane resin, polyester resin, oxetane resin, or a resin in which two or more of these resins are mixed is added with silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide, etc. as a filler, and is formed by compression molding, transfer molding, etc.

[0070] Next, the support 6 is peeled off. As shown in FIG. 7B(d), the laser light 20 is irradiated onto the laser absorption layer 8 to peel the first wiring substrate 1 on which the semiconductor element is mounted from the support 6. The laser light 20 is irradiated from the back surface of the support 6, that is, from the surface of the support 6 opposite to the semiconductor element 4, onto the laser absorption layer 8 formed at the interface with the support 6. Due to the heat generated by the laser absorption layer 8 absorbing the laser light 20, the release layer 7 is decomposed into a peelable state, and thus the support 6 can be removed as shown in FIG. 7B(e).

[0071] Next, the laser absorption layer 8 and the first seed layer 9 are removed. In the present embodiment, for example, titanium is used for the laser absorption layer 8, and in this case, the laser absorption layer 8 can be dissolved and removed with an alkaline etching agent. At this time, when the first seed layer 9 is made of titanium, the laser absorption layer 8 and the first seed layer 9 can be dissolved and removed simultaneously. The remaining copper layer of the first seed layer 9 can be dissolved and removed with an acid-based etching agent. In this way, a semiconductor device 26 in which the first wiring substrate (interposer) 1 and the semiconductor element 4 are joined as shown in FIG. 8 can be obtained.

[0072] Thereafter, in order to prevent oxidation and improve the wettability of solder bumps, surface treatment such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, electroless Ni / Au plating, etc. may be performed on the conductor layer 11 exposed on the surface to form the semiconductor device 26.

[0073] Thereafter, the semiconductor device 26 is bonded to the second wiring board (FC-BGA board) 3, filled with underfill 2, and the semiconductor device 26 and the second wiring board 3 are fixed and the interposer-FC-BGA joint 19 is sealed to complete the semiconductor device 25 integrated with the first wiring board 1.

[0074] As described above, in the method of forming a wiring board on a support via a release layer and peeling the wiring board from the support after the formation of the wiring board, the release layer and the laser absorption layer are provided in this order. As a result, it becomes possible to easily peel the wiring board, does not require a high-energy UV laser, and it is possible to provide a substrate unit with a support, a substrate unit, a semiconductor device, and a substrate unit with a support and a manufacturing method in which residues of the release layer are less likely to occur even after peeling of the support.

Example

[0075] <Comparative Experiment> Table 1 shows the comparative evaluation results of the presence or absence of formation of the laser absorption layer 8 and the release layer 7 on the upper surface of the support 6 as an effect confirmation in the present embodiment. As an evaluation of peeling of the laser absorption layer 8 and the release layer 7, after forming electrolytic copper plating upward, peeling was confirmed when laser light was irradiated from the support 6 side.

[0076] (Example) <Fabrication of Evaluation Substrate> As the support 6, a glass substrate (1.1 mm thick) was used. As the release layer 7 on the upper surface of the support 6, a polyimide resin was used, and the film thickness was adjusted to 500 nm, and the release layer was formed by spin coating. Ti was formed as the laser absorption layer 8 above the release layer 7 by sputtering. The film thicknesses of the laser absorption layer 8 were 20 nm, 50 nm, 100 nm, and 200 nm, and Examples 1 to 4 were respectively prepared. On the upper surface of the laser absorption layer 8, 300 nm of Cu was formed as the first seed layer 9 by sputtering, and electrolytic copper plating was formed thereon with a thickness of 20 μm. This evaluation substrate was used as an example. Next, a YAG laser (infrared laser) with a wavelength of 1064 nm and a solid-state UV laser (ultraviolet laser) with a wavelength of 355 nm were irradiated to evaluate the peeling of the support 6.

[0077] (Comparative Example 1) As Comparative Example 1, an evaluation substrate (with other configurations being the same as in the example) without forming the release layer 7 and the laser absorption layer 8 was fabricated, and a YAG laser (infrared laser) with a wavelength of 1064 nm and a solid-state UV laser (ultraviolet laser) with a wavelength of 355 nm were irradiated to evaluate the peeling of the support 6.

[0078] (Comparative Example 2) As Comparative Example 2, an evaluation substrate (with other configurations being the same as in the example) with the release layer 7 formed and the laser absorption layer 8 not formed was fabricated, and a YAG laser (infrared laser) with a wavelength of 1064 nm and a solid-state UV laser (ultraviolet laser) with a wavelength of 355 nm were irradiated to evaluate the peeling of the support 6.

[0079]

Table 1

[0080] In the examples, by irradiating with an infrared laser, peeling occurred at the interface between the release layer 7 and the laser absorption layer 8, and the support 6 could be removed. Also, the release layer 7 adhered to the support 6 side, and no residue of the release layer 7 was confirmed on the laser absorption layer 8 on the substrate side. On the other hand, in Comparative Example 1 and Comparative Example 2, peeling was impossible even when irradiated with an infrared laser.

[0081] In the examples, by irradiating with an ultraviolet laser, peeling occurred at the interface between the support 6 and the release layer 7, and the support 6 could be removed. However, the release layer 7 adhered to the laser absorption layer 8 on the substrate side and was confirmed as a residue. Also in Comparative Example 2, the support 6 could be removed by irradiating with an ultraviolet laser, but as in the examples, the release layer 7 adhered to the substrate side and was confirmed as a residue. On the other hand, in Comparative Example 1, peeling was not possible even when irradiated with an ultraviolet laser.

[0082] Consider the fact that peeling was possible only with an infrared laser in the examples. Since the laser absorption layer 8 absorbs the infrared laser, it is considered that peeling occurred at the interface between the release layer 7 and the laser absorption layer 8 due to the action of the heat generated by the absorption. Also, since the release layer 7 adheres to the support 6 side, a removal process is not required without remaining on the substrate side. On the other hand, in Comparative Examples 1 and 2, there is no layer that absorbs the infrared laser, and it is considered that peeling did not occur.

[0083] In the case of the ultraviolet laser, peeling was possible not only in the examples but also in Comparative Example 2. Since the release layer 7 absorbs the ultraviolet laser, in Comparative Example 2, it is considered that peeling occurred at the interface between the support 6 and the release layer 7 due to the action of the heat generated by the absorption. Also, in Comparative Example 2, since the release layer 7 adheres to the substrate side, the subsequent process that requires a removal process becomes complicated. On the other hand, in Comparative Example 1, there is no layer that absorbs the ultraviolet laser, and it is considered that peeling did not occur.

[0084] The above-described embodiments are examples, and of course, other specific detailed structures and the like can be appropriately changed.

Explanation of Reference Numerals

[0085] 1 First wiring board (interposer) 2, 22 Underfill 3 Second wiring board (FC - BGA board) 4 Semiconductor element 5 Encapsulating resin 6 Support 7 Release layer 8 Laser absorption layer 9 First seed layer 10 First resist pattern 13 Second seed layer 14 Second resist pattern 11, 15, 16 Conductor layer 12 Insulating resin layer 17 Outermost surface insulating resin layer 18 Surface treatment layer 19 Interposer - FC - BGA joint 19a Joint on the interposer side 19b Joint on the FC - BGA substrate side 20 Laser beam 21 Semiconductor element - interposer joint 23 Substrate unit with support 24 Substrate unit 25, 26 Semiconductor device

Claims

1. A substrate unit with a support, comprising a release layer, a laser absorption layer that absorbs laser light, and a first wiring substrate, which are provided in this order, wherein a first electrode capable of being joined to at least one semiconductor element is provided on a first surface of the first wiring substrate, and a second electrode capable of being joined to a second wiring substrate is provided on a second surface of the first wiring substrate, characterized in that the release layer transmits 50% or more of the laser light.

2. A substrate unit with a support, comprising a release layer, a laser absorption layer that absorbs laser light, and a first wiring substrate, which are provided in this order, wherein a first electrode capable of being joined to at least one semiconductor element is provided on a first surface of the first wiring substrate, and a second electrode capable of being joined to a second wiring substrate is provided on a second surface of the first wiring substrate, characterized in that the laser absorption layer is provided inside the release layer in a plan view.

3. A substrate unit with a support, comprising a release layer, a laser absorption layer that absorbs laser light, and a first wiring substrate, which are provided in this order, wherein a first electrode capable of being joined to at least one semiconductor element is provided on a first surface of the first wiring substrate, and a second electrode capable of being joined to a second wiring substrate is provided on a second surface of the first wiring substrate, characterized in that the laser absorption layer is made of metal and the release layer is made of an organic resin.

4. A substrate unit with a support, comprising a release layer, a laser absorption layer that absorbs laser light, and a first wiring substrate, which are provided in this order, wherein a first electrode capable of being joined to at least one semiconductor element is provided on a first surface of the first wiring substrate, and a second electrode capable of being joined to a second wiring substrate is provided on a second surface of the first wiring substrate, characterized in that the laser absorption layer is made of the same material as a part of an upper seed layer.

5. The substrate unit with a support according to any one of claims 1 to 4, characterized in that the laser absorption layer absorbs the laser light and peels off at the interface between the laser absorption layer and the release layer.

6. The substrate unit with a support according to any one of claims 1 to 5, characterized in that the laser light is infrared light.

7. A substrate unit manufactured using the substrate unit with a support according to any one of claims 1 to 6, The second wiring substrate is joined to the second surface of the first wiring substrate, and the substrate unit is characterized in that the support is removed by laser irradiation. **Claim 8** A semiconductor device manufactured using the substrate unit with a support according to any one of Claims 1 to 6, wherein a first electrode and the semiconductor element are joined on the first surface of the first wiring substrate in the substrate unit with a support, and the support is removed by laser irradiation. **Claim 9** A method for manufacturing a substrate unit with a support according to any one of Claims 1 to 6, comprising the steps of: forming a release layer and a laser absorption layer in this order on the upper surface of the support; forming a seed layer on the laser absorption layer; forming an electrode by an electrolytic plating layer on the seed layer; repeatedly forming a resin layer and a conductor layer on the upper surface of the electrode to obtain a multilayer wiring; and manufacturing a first wiring substrate by forming an electrode on the outermost surface of the multilayer wiring. **Claim 10** A method for manufacturing a substrate unit, comprising the steps of joining the substrate unit with a support manufactured using the method for manufacturing a substrate unit with a support according to Claim 9 to a second wiring substrate, and peeling the support by peeling the release layer at the interface of the laser absorption layer by irradiating laser light. **Claim 11** A method for manufacturing a semiconductor device, comprising the steps of joining a semiconductor element to the substrate unit with a support manufactured using the method for manufacturing a substrate unit with a support according to Claim 9, and peeling the support by irradiating laser light to peel the release layer at the interface of the laser absorption layer. **Claim 12** In the method for manufacturing a substrate unit according to Claim 10, the laser light is infrared light. **Claim 13** In the method for manufacturing a semiconductor device according to Claim 11, the laser light is infrared light.

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