Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor having a longer average operating time. A multilayer ceramic capacitor 1 according to the present invention comprises: a laminate 2 that is provided with an inner layer section 11 in which interior electrode layers 15 and interior dielectric layers 14 are laminated in an alternating manner, and two outer layer sections 22 which are respectively disposed on the two side surfaces of the inner layer section 11 in the lamination direction; and two exterior electrodes 3 that are respectively disposed on the end surfaces on the two sides of the laminate 2 in the lengthwise direction. The interior electrode layers 15 include: outermost interior electrode layers 150 closest to the outer layer sections 22; and inward interior electrode layers 153 other than the outermost interior electrode layers 150. At least one of the outer layer sections 22 includes a non-Ni-containing region 22A within 0.9 µm of the outermost interior electrode layer 150 closest to said outer layer section 22, and a Ni-containing region 22B separated by more than 0.9 µm from said outermost interior electrode layer 150. At least one of the outermost interior electrode layers 150 is thicker than the inward interior electrode layers 153 and varies little in terms of thickness.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] There is known a multilayer ceramic capacitor which is manufactured by alternately stacking a plurality of dielectric layers and a plurality of internal electrode layers, disposing outer layer portions on both sides in the stacking direction, and further firing. In recent years, such a multilayer ceramic capacitor has been required to be miniaturized and have a large capacitance. To achieve miniaturization and large capacitance, the internal electrode layer and the internal dielectric layer have been made thinner, the number of stacked layers has been increased, and regions such as outer layer portions other than the effective region sandwiched between the internal electrode layers have been minimized (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when the regions other than the effective region are minimized, the environmental resistance of the multilayer ceramic capacitor decreases, and the internal electrode disposed on the outermost side during firing is likely to deteriorate. As a result, the average operating time of the multilayer ceramic capacitor is shortened.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor with an improved average operating time.

Means for Solving the Problems

[0006] To solve the above problems, the present invention provides a laminate including an inner layer portion in which a plurality of internal electrode layers and internal dielectric layers are alternately laminated, and two outer layer portions disposed on both surfaces in the lamination direction of the inner layer portion, and two external electrodes disposed on end faces which are both surfaces on both sides in the length direction intersecting the lamination direction in the laminate. The internal electrode layer has an outermost internal electrode layer closest to each of the outer layer portions and an inner internal electrode layer other than the outermost internal electrode layer. At least one of the outer layer portions includes a Ni-free region within 0.9 μm from the outermost internal electrode layer closest to the outer layer portion and a Ni-containing region separated from the outermost internal electrode layer by more than 0.9 μm. At least one of the outermost internal electrode layers is thicker than the inner internal electrode layer and has a small thickness variation, thereby providing a multilayer ceramic capacitor.

Effects of the Invention

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor with an improved average operating time.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0009] (Multilayer Ceramic Capacitor 1) Hereinafter, the multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described. FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1 of the embodiment. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 in FIG. 1.

[0010] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided at both ends of the laminate 2. The laminate 2 includes an inner layer portion 11 in which an internal dielectric layer 14 and an internal electrode layer 15 are laminated.

[0011] (Dimensions of Multilayer Ceramic Capacitor 1) The dimensions of the multilayer ceramic capacitor 1 are, for example, the width direction W is 0.1 mm or more and 0.5 mm or less, the thickness direction is 0.1 mm or more and 0.5 mm or less, and the length direction L is 0.05 mm or more and 1.0 mm or less.

[0012] In the following description, as a term representing the orientation of the multilayer ceramic capacitor 1, in the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is defined as the length direction L. The direction in which the internal dielectric layer 14 and the internal electrode layer 15 are laminated is defined as the lamination direction T. The direction intersecting both the length direction L and the lamination direction T is defined as the width direction W. In the embodiment, the width direction W is orthogonal to both the length direction L and the lamination direction T. The multilayer ceramic capacitor 1 of the embodiment has a length direction L longer than the width direction W and the lamination direction T, but is not limited thereto, and the dimension in the length direction L may not be longer than the width direction W and the lamination direction T.

[0013] In the following description, among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T are defined as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W are defined as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L are defined as the first end surface C1 and the second end surface C2. When there is no need to particularly distinguish and describe the first main surface A1 and the second main surface A2, they are collectively referred to as the main surface A. When there is no need to particularly distinguish and describe the first side surface B1 and the second side surface B2, they are collectively referred to as the side surface B. When there is no need to particularly distinguish and describe the first end surface C1 and the second end surface C2, they are collectively referred to as the end surface C for description.

[0014] (Laminate 2) The laminate 2 includes a laminate chip 10 and side margin portions 21 disposed on both sides of the laminate chip 10 in the width direction W. The laminate chip 10 includes an inner layer portion 11 in which an internal dielectric layer 14 and an internal electrode layer 15 are laminated, a first outer layer portion 221 disposed on the first main surface A1 side of the inner layer portion 11 in the stacking direction T, and a second outer layer portion 222 disposed on the second main surface A2 side. When there is no need to particularly distinguish and describe the first outer layer portion 221 and the second outer layer portion 222, they are collectively referred to as the outer layer portion 22 for description.

[0015] The laminate 2 is substantially rectangular parallelepiped in shape, but it is preferable that the corners R1 and the ridge lines R2 are rounded. The corner R1 is a portion where the main surface A, the side surface B, and the end surface C intersect. The ridge line R2 is a portion where two surfaces of the laminate 2, that is, the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C intersect.

[0016] (Inner layer portion 11) The inner layer portion 11 is a portion where the internal dielectric layer 14 and the internal electrode layer 15 are alternately laminated along the stacking direction T. In the embodiment, both ends of the inner layer portion 11 in the stacking direction T are the internal electrode layers 15.

[0017] (Internal electrode layer 15) The internal electrode layer 15 contains, for example, Ni as a main component, and may further contain dielectric particles of the same composition system as the ceramics contained in the internal dielectric layer 14. Also, Sn may be disposed at the interface between the internal electrode layer 15 and the internal dielectric layer 14. In this case, Sn may be in a layered form or may be scattered. Further, Sn may be dissolved on the internal electrode layer 15 side or may be dissolved in the dielectric particles on the dielectric layer side.

[0018] The internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are alternately arranged.

[0019] The first internal electrode layer 15A includes a first facing portion 15Aa facing the second internal electrode layer 15B and a first lead-out portion 15Ab drawn from the first facing portion 15Aa toward the first end face C1 side. The end of the first lead-out portion 15Ab is exposed on the first end face C1 and is electrically connected to a first external electrode 3A described later. The second internal electrode layer 15B includes a second facing portion 15Ba facing the first internal electrode layer 15A and a second lead-out portion 15Bb drawn from the second facing portion 15Ba to the second end face C2. The end of the second lead-out portion 15Bb is electrically connected to a second external electrode 3B described later. The internal electrode layer 15 functions as a capacitor with charges accumulated between the first facing portion 15Aa of the first internal electrode layer 15A and the second facing portion 15Ba of the second internal electrode layer 15B with the internal dielectric layer 14 interposed therebetween.

[0020] As shown in FIG. 3, in the WT cross-section, which is a cross-section in the width direction W and the stacking direction T passing through the center of the laminate 2, the deviation d in the stacking direction T of the positions of the ends in the width direction W of two adjacent first internal electrode layers 15A and second internal electrode layers 15B above and below in the stacking direction T is preferably 5 μm or less, and more preferably 0.5 μm or less. That is, the ends in the width direction W of the first internal electrode layer 15A and the second internal electrode layer 15B adjacent to each other above and below in the stacking direction T are substantially at the same position in the width direction W, and the positions of the ends are aligned in the stacking direction T.

[0021] The number of the internal electrode layers 15 is preferably 10 or more and 1000 or less.

[0022] Also, the internal electrode layer 15 has a first outermost internal electrode layer 151 closest to the first outer layer portion 221, a second outermost internal electrode layer 152 closest to the second outer layer portion 222, and an inner internal electrode layer 153 other than the first outermost internal electrode layer 151 and the second outermost internal electrode layer 152. When it is not necessary to particularly distinguish and explain the first outermost internal electrode layer 151 and the second outermost internal electrode layer 152, they are collectively described as the outermost internal electrode layer 150.

[0023] (Inner internal electrode layer 153) The thickness of the inner internal electrode layer 153 is preferably 0.3 μm or more and 0.4 μm or less, and more preferably 0.3 μm or more and 0.35 μm or less. Also, the standard deviation / mean value indicating the thickness variation of the inner internal electrode layer 153 is 0.22 or more and 0.27 or less.

[0024] Note that the standard deviation / mean value indicating the thickness variation is obtained by the following formula. CV value = σ / Ave Ave: Average of thickness σ: Standard deviation of thickness Hereinafter, the standard deviation / mean value is shown as the CV value.

[0025] (Outermost internal electrode layer 150) At least one of the first outermost internal electrode layer 151 and the second outermost internal electrode layer 152 is thicker than the inner internal electrode layer 153. In the embodiment, both the first outermost internal electrode layer 151 and the second outermost internal electrode layer 152 are thicker than the inner internal electrode layer 153. The thickness of the outermost internal electrode layer 150 is preferably 0.4 μm or more and 0.5 μm or less, and more preferably 0.4 μm or more and 0.45 μm or less. Also, the CV value indicating the thickness variation of the outermost internal electrode layer 150 is smaller than that of the inner internal electrode layer 153 and is 0.09 or more and 0.17 or less.

[0026] (Method for measuring thickness) The method for measuring the thickness of the internal electrode layer 15, that is, the outermost internal electrode layer 150 and the inner internal electrode layer 153, is performed as follows, for example. First, an LT cross-section passing through the center of the multilayer ceramic capacitor 1 is polished to expose the inner layer portion 11. If necessary, the observation position is etched on the exposed cross-section to remove the conductor layer stretched by polishing.

[0027] FIG. 4 is an example of an enlarged image of the cross-section of the exposed inner layer portion 11. In the illustrated enlarged image, for example, a plurality of straight lines La, Lb, Lc, Ld, Le extending in the stacking direction T are drawn at equal intervals with a pitch S. The pitch S is preferably about 5 times or more and 10 times or less the thickness of the internal electrode layer 15 (the outermost internal electrode layer 150 or the inner internal electrode layer 153) to be measured. For example, when measuring the internal electrode layer 15 having a thickness of about 1 μm, the pitch S is set to 5 μm.

[0028] Next, on each of the five straight lines La, Lb, Lc, Ld, Le, the thicknesses da, db, dc, dd, de of the respective internal electrode layers 15 are measured. However, when the internal electrode layer 15 is missing on the straight lines La, Lb, Lc, Ld, Le and the inner dielectric layers 14 sandwiching the internal electrode layer 15 are connected, or when the enlarged view of the measurement position is unclear, a new straight line is drawn to measure the thickness of the internal electrode layer 15.

[0029] In the case of the inner internal electrode layer 153, when the number of stacked layers is less than 5, the thicknesses of all the inner internal electrode layers 153 are measured by the above method, and the average value is taken as the average thickness of the plurality of inner internal electrode layers 153. The thickness of the inner dielectric layer 14 can also be measured in the same manner as the inner internal electrode layer 153.

[0030] In the case of the outermost internal electrode layer 150, the thicknesses of the first outermost internal electrode layer 151 and the second outermost internal electrode layer 152 are measured separately. That is, the thicknesses da, db, dc, dd, de on each of the five straight lines La, Lb, Lc, Ld, Le of the first outermost internal electrode layer 151 are measured respectively, and the average of these is taken as the thickness of the first outermost internal electrode layer 151. The thicknesses da, db, dc, dd, de on each of the five straight lines La, Lb, Lc, Ld, Le of the second outermost internal electrode layer 152 are measured respectively, and the average of these is taken as the thickness of the second outermost internal electrode layer 152.

[0031] (Internal dielectric layer 14) The internal dielectric layer 14 is, for example, a dielectric ceramic containing Ba and Ti components and contains Si. Also, those obtained by adding components with a content less than the main components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. to these components may be used.

[0032] The total number of the internal dielectric layer 14 and the outer layer part 22 is preferably 100 or more and 2000 or less.

[0033] (Thickness of the internal dielectric layer 14) The internal dielectric layer 14 preferably has a thickness of 0.4 μm or more and 0.5 μm or less, and more preferably 0.4 μm or more and 0.45 μm or less. As described above, the thickness of the internal dielectric layer 14 can also be obtained by measuring the thicknesses Da, Db, Dc, Dd, De of each internal dielectric layer 14 on each of the five straight lines La, Lb, Lc, Ld, Le in the same manner as the internal electrode layer 15 and taking the average.

[0034] (Outer layer part 22) The outer layer part 22 is a dielectric layer located on both main surface A sides of the laminate 2 and located between the main surface A and the internal electrode layer 15 closest to the main surface A. As described above, the outer layer part 22 includes a first outer layer part 221 disposed on the first main surface A1 side in the stacking direction T of the inner layer part 11 and a second outer layer part 222 disposed on the second main surface A2 side.

[0035] The outer layer portion 22 contains Ba, Ti, and Ni. The mol% of Ni with respect to Ti in the outer layer portion 22 is preferably 0.4 mol% or more and 5.0 mol% or less. However, at least one of the first outer layer portion 221 and the second outer layer portion 222, and in the embodiment both outer layer portions 22, each include a Ni-free region 22A that contains almost no Ni within 0.9 μm from the outermost internal electrode layer 150 adjacent thereto. The region more than 0.9 μm away from the outermost internal electrode layer 150 is a Ni-containing region 22B that contains Ni. In the embodiment, the Ni-free region 22A may contain no Ni at all, or may contain a trace amount (0.2 mol% or less) of Ni as compared with the Ni-containing region 22B.

[0036] Furthermore, the outer layer portion 22 contains Mg and Mn. However, the amount of Mg is trace, and the mol% of Mg with respect to Ti ru m is preferably 0.001 mol% or more and 0.01 mol% or less. Also, the mol% of Mn with respect to Ti is preferably 0.05 mol% or more and 0.8 mol% or less.

[0037] (Side margin portion 21) The side margin portion 21 is disposed on both side surfaces B of the laminate chip 10, that is, on both side surfaces B of the outer layer portion 22 and the inner layer portion 11, and covers the side surfaces B of the outer layer portion 22 and the inner layer portion 11. The dielectric material of the side margin portion may be the same as that of the outer layer portion and the inner layer portion in the embodiment, but may also be different.

[0038] (Dielectric layer 20) In the present embodiment, the internal dielectric layer 14, the outer layer portion 22, and the side margin portion 21 are collectively referred to as the dielectric layer 20. The dielectric layer 20 includes a plurality of grains g. FIG. 5 is an enlarged view of the P portion surrounded by a circle in FIG. 3 and shows the grains g. The grains g are ceramic layers containing a perovskite-type compound containing Ba and Ti and other sub-components. The sub-components are at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y.

[0039] (Ni in grain g) At least the grains g in the outer layer portion 22 further contain Ni as a secondary component. Ni has the effect of hindering the growth of the grains g, and the grain g By containing Ni, during sintering described later, the grain growth of the grains g in the outer layer portion 22 is suppressed more as it goes to the outside. Since the grain growth of the grains g on the outside of the outer layer portion 22 is suppressed and the grain size becomes smaller, the interface becomes smooth. Therefore, the interface does not increase, and the thinnest part of the element thickness cannot be formed, so the reliability can be improved.

[0040] However, in the embodiment, the grains g in the Ni-containing region 22B contain Ni, but the grains g in the Ni-free region 22A do not contain Ni. This is because Ni present in the region that becomes the Ni-free region 22A during sintering is absorbed by the outermost internal electrode layer 150.

[0041] FIG. 6 is a diagram showing the dispersion state of Ni in one grain g included in the Ni-containing region 22B. In the embodiment, Ni is contained substantially uniformly inside one grain g included in the Ni-containing region 22B, and Ni is dissolved in the grain g. In this specification, substantially uniform means that the difference between the molar ratio (mol%) of Ni to Ti in the outer region g1 within about 10 nm from the outer periphery of the grain g and the molar ratio (mol%) of Ni to Ti in the central region g2 other than the outer region g1 in the grain g is ±20% or less.

[0042] However, the present invention is not limited to this. Ni may have a difference of more than ±20% between the molar ratio (mol%) of Ni to Ti in the outer region g1 within about 10 nm from the outer periphery of the grain g and the molar ratio (mol%) of Ni to Ti in the central region g2 other than the outer region g1 in the grain g. In the interior of one grain g included in the Ni-containing region 22B, Ni may be segregated and present, for example, in either the outer region g1 or the central region g2.

[0043] The measurement of the uniformity of Ni uses an image captured by TEM (transmission electron microscope) with a field of view of 1000 nm × 1000 nm and containing 100 or more grains g. At this time, measurements on irregularly shaped grains g are avoided, and grains g in which the outer region g1 and the central region g2 can be clearly distinguished are selected. In the selected grain g, Ni is detected, and the mol% of Ni with respect to Ti in the outer region g1 and the mol% of Ni with respect to Ti in the central region g2 are determined. In the embodiment, the difference between the mol% of Ni with respect to Ti in the outer region g1 and the mol% of Ni with respect to Ti in the central region g2 is ±20% or less. Note that in the grains g of the internal dielectric layer 14 and the side margin portion 21 other than the outer layer portion 22 in the dielectric layer 20, Ni may be uniform in the same manner as the outer layer portion 22, or different from the outer layer portion 22, Ni may be partially segregated, or Ni may not be contained.

[0044] (External electrode 3) The external electrode 3 includes a first external electrode 3A provided on the first end face C1 of the laminate 2 and a second external electrode 3B provided on the second end face C2 of the laminate 2. When there is no need to particularly distinguish between the first external electrode 3A and the second external electrode 3B for explanation, they are collectively described as the external electrode 3. The external electrode 3 covers not only the end face C but also a part of the main face A and the side face B on the end face C side.

[0045] As described above, the end of the first lead portion 15Ab of the first internal electrode layer 15A is exposed on the first end face C1 and is electrically connected to the first external electrode 3A. Also, the end of the second lead portion 15Bb of the second internal electrode layer 15B is exposed on the second end face C2 and is electrically connected to the second external electrode 3B. Thereby, between the first external electrode 3A and the second external electrode 3B, a structure is formed in which a plurality of capacitor elements are electrically connected in parallel.

[0046] In the embodiment, the external electrode 3 includes a base electrode layer 30 and a plating layer 31 disposed on the base electrode layer 30.

[0047] (Base electrode layer 30) The underlying electrode layer 30 includes at least one layer selected from a fired layer 30a, a conductive resin layer 30b, a thin film layer 30c, and the like. In the embodiment, it includes three layers: a fired layer 30a, a conductive resin layer 30b, and a thin film layer 30c.

[0048] (Fired layer 30a) The metal of the fired layer 30a includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The fired layer 30a may be a single layer or multiple layers. The fired layer 30a is formed by applying a conductive paste containing glass and metal to the laminate 2 and firing it. In the embodiment, the fired layer 30a is fired simultaneously with the internal electrode layer 15, but it is not limited to this, and it may be fired after firing the internal electrode layer 15.

[0049] (Conductive resin layer 30b) The conductive resin layer 30b includes conductive particles and a thermosetting resin in the embodiment. As specific examples of the thermosetting resin, various known thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin can be used. As the metal component, for example, Ag or metal powder with an Ag coating on the surface of base metal powder can be used. When forming the conductive resin layer 30b, it may be formed directly on the laminate 2 without forming the fired layer 30a. The conductive resin layer 30b may be a single layer or multiple layers.

[0050] Since the conductive resin layer 30b contains a thermosetting resin, it is, for example, more flexible than the fired layer 30a made of a plating film or a fired product of a conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical impact or impact caused by thermal cycling, the conductive resin layer 30b functions as a buffer layer, preventing cracks from occurring in the multilayer ceramic capacitor 1, easily absorbing piezoelectric vibration, and having an effect of suppressing "buzzing".

[0051] (Thin film layer 30c) The thin film layer 30c is a layer with a thickness of 1 μm or less formed by a thin film formation method such as sputtering or vapor deposition, on which metal particles are deposited.

[0052] (Plating layer 31) The plating layer 31 preferably includes plating of one metal selected from the group consisting of, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, and Ag-Pd alloy, or an alloy containing such a metal. The plating layer 31 is preferably formed of a plurality of layers. In an embodiment, the plating layer 31 includes a first plating layer 31a and a second plating layer 31b provided on the first plating layer 31a. In the embodiment, the first plating layer 31a is a Ni plating layer, and the second plating layer 31b is a Sn plating layer. The Ni plating layer 31 can prevent the base electrode layer 30 from being eroded by solder when mounting a ceramic electronic component. The Sn plating layer 31 can improve the wettability of the solder when mounting a ceramic electronic component, enabling easy mounting.

[0053] Also, the external electrode 3 does not include the base electrode layer 30 、me The plating layer 31 may be directly provided on the laminate 2. In this case, the internal electrode layer 15 and the plating layer 31 are directly connected. Also, in this case, a catalyst may be provided on the laminate 2 as a pretreatment.

[0054] In this case, the plating layer 31 preferably includes a first plating layer 31a and a second plating layer 31b provided on the first plating layer 31a. The first plating layer 31a and the second plating layer 31b preferably include plating of one metal selected from the group consisting of, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. And, for example, when Ni is used for the internal electrode layer 15, it is preferable to use Cu, which has good bonding properties with Ni, for the first plating layer 31a. Also, for the second plating layer 31b, it is preferable to use Sn or Au, which has good solder wettability, and for the first plating layer 31a, it is preferable to use Ni, which has solder barrier performance. The second plating layer 31b is formed as needed, and the external electrode 3 may be composed of only the first plating layer 31a. The second plating layer 31b may be provided as the outermost layer of the plating layer 31, or another plating layer may be provided on the second plating layer 31b. It is preferable that the plating layer 31 does not contain glass. Plating layer 3 1 of The metal ratio per unit volume is preferably 99% by volume or more.

[0055] (Method for manufacturing the multilayer ceramic capacitor 1) FIG. 7 is a flowchart for explaining the method for manufacturing the multilayer ceramic capacitor 1. FIG. 8 is a diagram for explaining the method for manufacturing the multilayer ceramic capacitor 1.

[0056] (Material sheet production step S1) First, ceramic powder containing Ba and Ti components, a binder, a solvent, and a ceramic slurry for the internal dielectric layer containing Si are prepared. The ceramic slurry for the internal dielectric layer is formed into a sheet shape on a carrier film using a die coater, a gravure coater, a microgravure coater, etc., thereby producing a ceramic green sheet 101 for the internal dielectric layer.

[0057] Subsequently, a conductor paste containing Ni is printed on the ceramic green sheet 101 for the internal dielectric layer by screen printing, inkjet printing, gravure printing, etc. so as to have a strip pattern, thereby forming a conductive pattern 102. As a result, a material sheet 103 is produced in which the conductive pattern 102 serving as the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101 for the internal dielectric layer that becomes the internal dielectric layer 14.

[0058] In addition, a ceramic slurry for the outer layer containing Ba, Ti, and Ni, similar to the ceramic slurry for the internal dielectric layer, a binder, and a solvent is prepared. The ceramic slurry for the outer layer is formed into a sheet on a carrier film using a die coater, a gravure coater, a micro gravure coater, or the like, thereby producing a ceramic green sheet 112 for the outer layer.

[0059] (Lamination step S2) Subsequently, a plurality of material sheets 103 are laminated. As shown in FIG. 8, a plurality of material sheets 103 are stacked such that the strip-shaped conductive patterns 102 face the same direction and the strip-shaped conductive patterns 102 are shifted by a half pitch in the width direction W between adjacent material sheets 103. Further, ceramic green sheets 112 for the outer layer, which will become the outer layers 22, are stacked on both sides of the plurality of laminated material sheets 103, respectively.

[0060] Next, the ceramic green sheet 112 for the outer layer and the plurality of stacked material sheets 103 are thermocompression bonded, thereby producing a mother block 110.

[0061] (Mother block cutting step S3) Subsequently, the mother block 110 is cut along the cutting line X shown in FIG. 8 corresponding to the dimensions of the stacked body chip 10 and a cutting line (not shown) intersecting the cutting line X. Thereby, a plurality of stacked body chips 10 are manufactured.

[0062] (Ceramic green sheet attachment step for side margin part S4) A ceramic green sheet for the side margin part containing a ceramic powder containing Ba and Ti components, a binder, and a solvent is prepared. The ceramic green sheet for the side margin part is applied to the surface of the carrier film and dried. Then, the ceramic green sheet for the side margin part and the side surface of the stacked body chip 10 are opposed to each other, pressed, and punched, whereby the ceramic green sheet for the side margin part is attached to the side surface of the stacked body chip 10.

[0063] (Sintering layer material coating step S5) The material of the sintering layer 30a of the base electrode layer 30 adheres to both end faces C of the laminated body chip 10 to which the ceramic green sheet for the side margin portion is attached.

[0064] (Firing step S6) Then, the laminated body chip 10 to which the material of the sintering layer 30a adheres is degreased under predetermined conditions in a nitrogen atmosphere, and then fired at a predetermined temperature in a nitrogen-hydrogen-steam mixed atmosphere and sintered to form the sintering layer 30a and the conductive resin layer 30b, resulting in the laminated body 2.

[0065] In this firing step S6, Ni present in the vicinity of each adjacent outermost internal electrode layer 150 in each outer layer portion 22 is absorbed by the outermost internal electrode layer 150. As a result, a Ni-free region 22A is formed within 0.9 μm from the adjacent outermost internal electrode layer 150 in the outer layer portion 22.

[0066] In addition, the outermost internal electrode layer 150 that has absorbed Ni existing within 0.9 μm from the adjacent outermost internal electrode layer 150 in the outer layer portion 22 becomes thicker than the inner internal electrode layer 153, and by absorbing Ni, the thickness uniformity of the outermost internal electrode layer 150 increases and the CV value decreases. The value of this CV value can be adjusted by adjusting the amount of Ni contained in the outer layer portion 22 and the like.

[0067] Here, during firing, the outermost internal electrode layer 150 is affected by heat and thus is more likely to deteriorate than the inner internal electrode layer 153. However, according to the embodiment, the inner internal electrode layer 153 has improved strength due to an increase in thickness and is less likely to be affected by heat deterioration. Furthermore, by increasing the thickness of the outermost internal electrode layer 150, heat transfer to the inner internal electrode layer 153 can be suppressed.

[0068] (Conductive resin layer step S7) Next, the material of the conductive resin layer 30b containing conductive particles and a thermosetting resin adheres onto the sintering layer 30a.

[0069] (Thin film layer formation step S8) Furthermore, on the material of the conductive resin layer 30b in the laminate 2, a thin film layer 30c which is a layer of 1 μm or less in which metal particles are deposited by a thin film formation method such as sputtering or vapor deposition is formed.

[0070] (Plating layer formation step S9) In the embodiment, as the plating layer 31, a first plating layer 31a which is a Ni plating layer and a second plating layer 31b which is a Sn plating on the first plating layer 31a are formed. Through the above steps, the multilayer ceramic capacitor 1 is manufactured.

[0071] (Examples) FIG. 9 is a table showing the results of measuring the mean time to failure (MTTF) of the multilayer ceramic capacitors 1 of Examples 1 to 21 according to the present invention and the multilayer ceramic capacitors 1 of Comparative Examples 1 to 4 different from the present invention. Hereinafter, the multilayer ceramic capacitors of the comparative examples will also be described using the same reference numerals as in the embodiment.

[0072] The mean time to failure is the average of the time until a failure occurs when a voltage of 5.1 V is applied between the external electrodes of the multilayer ceramic capacitor 1 in an environment of 150°C. A mean time to failure of 70 hours (hr) or more is considered a pass, and is indicated by ○ or ◎ in the determination results in the table of FIG. 9. A mean time to failure of less than 70 is considered a fail and is indicated by X.

[0073] For the multilayer ceramic capacitors 1 of the examples and the comparative examples, the thickness of the outermost internal electrode layer 150 is about 0.4 μm and the thickness of the inner internal electrode layer 153 is about 0.3 μm. And in the outer layer portion 22, within 0.9 μm from the adjacent outermost internal electrode layer 150 is the Ni-free region 22A, and the region more than 0.9 μm away from the outermost internal electrode layer 150 is the Ni-containing region 22B.

[0074] (Effect of CV value) In Examples 1 to 21 according to the embodiment, the CV value of the thickness of the outermost internal electrode layer 150 is smaller than that of the inner internal electrode layer 153. That is, the outermost internal electrode layer 150 has a smaller thickness variation than the inner internal electrode layer 153. On the other hand, in Comparative Examples 1 to 4, the CV value of the thickness of the outermost internal electrode layer 150 is larger than that of the inner internal electrode layer 153. That is, the outermost internal electrode layer 150 has a larger thickness variation than the inner internal electrode layer 153.

[0075] As shown in the table, in all of Examples 1 to 21, the average operation time is 70 hours (hr) or more. On the other hand, in all of Comparative Examples 1-4, the average operation time is less than 70 hours.

[0076] In particular, when comparing Example 15 and Comparative Example 2, the Mg content with respect to Ti is 1.000 mol% in both cases, and the Mn content with respect to Ti is 0.6 mol% in both cases. However, in Example 15, the Ni content with respect to Ti is 1.5 mol%, the CV value of the outermost internal electrode layer 150 is 0.19, which is smaller than 0.24 of the inner internal electrode layer 153. In this Example 15, the average operation time is 73 hours. On the other hand, in Comparative Example 2, the Ni content with respect to Ti is 0.2 mol%, the CV value of the outermost internal electrode layer 150 is 0.28, which is larger than 0.24 of the inner internal electrode layer 153. In this Comparative Example 2, the average operation time is 35 hours.

[0077] That is, it can be seen that in Example 15, compared with Comparative Example 2, although the conditions other than the Ni content with respect to Ti are the same, by increasing the Ni content with respect to Ti and reducing the CV value of the outermost internal electrode layer 150, the average operation time has become longer.

[0078] According to Examples 1 to 21 according to the embodiment above, since the CV value of the thickness of the outermost internal electrode layer 150 is smaller than that of the inner internal electrode layer 153, compared with the case where the CV value of the thickness of the outermost internal electrode layer 150 is larger than that of the inner internal electrode layer 153 as in Comparative Examples 1-4, the average operating time can be lengthened, and the average operating time can be made 70 hours or more which is the passing line.

[0079] (Preferred range of CV value of thickness of outermost internal electrode layer 150) Also, in Examples 2 to 9, Examples 11 to 14, and Examples 16 to 21 where the CV value of the thickness of the outermost internal electrode layer 150 is 0.09 or more and 0.17 or less, the average operating time is 78 hours or more. On the other hand, in Examples 1, 10, and 15 where the CV value of the thickness of the outermost internal electrode layer 150 is 0.19 or more, the average operating time is 75 hours or less.

[0080] From the above, it can be seen that the CV value of the thickness of the outermost internal electrode layer 150 is more preferably 0.09 or more and 0.17 or less.

[0081] (Preferred range of Mg content with respect to Ti) Also, in Examples 4, 10, 11, 12, 13, 14, and 15 according to the embodiment, the Ni content with respect to Ti is 1.5 mol% in all cases, and the Mn content with respect to Ti is 0.6 mol% in all cases and is equal.

[0082] However, in Example 10, the Mg content with respect to Ti is below the analysis limit, and the average operation time is 74 hours. In Example 4, the Mg content with respect to Ti is 0.001 mol%, and the average operation time is 105 hours. In Example 11, the Mg content with respect to Ti is 0.005 mol%, and the average operation time is 100 hours. In Example 12, the Mg content with respect to Ti is 0.010 mol%, and the average operation time is 101 hours. In Example 13, the Mg content with respect to Ti is 0.050 mol%, and the average operation time is 81 hours. In Example 14, the Mg content with respect to Ti is 0.500 mol%, and the average operation time is 78 hours. In Example 15, the Mg content with respect to Ti is 0.100 mol%, and the average operation time is 72 hours.

[0083] That is, when the Mg content with respect to Ti is in the range of 0.001 mol% or more and 0.01 mol% or less as in Examples 4, 11, and 12, the average operation time is 100 hours or more. On the other hand, in Example 10 where the Mg content with respect to Ti is less than 0.001 mol%, or in Examples 13, 14, and 15 where the Mg content with respect to Ti is more than 0.01 mol%, the average operation time is 81 hours or less.

[0084] From the above, it can be seen that the Mg content with respect to Ti is preferably 0.001 mol% or more and 0.01 mol% or less.

[0085] (Preferred range of Ni content with respect to Ti) Also, in Examples 2, 3, 4, 5, 6, 7, and 9 according to the embodiment, the Mg content with respect to Ti is 0.001 mol% in all cases, and the Ni content with respect to Ti is 0.60 mol%, which is the same.

[0086] However, in Example 2, the Ni content with respect to Ti is 0.04 mol%, and the average operation time is 95 hours. In Example 3, the Ni content with respect to Ti is 1.0 mol%, and the average operation time is 99 hours. In Example 4, the Ni content with respect to Ti is 1.5 mol%, and the average operation time is 105 hours. In Example 5, the Ni content with respect to Ti is 2.0 mol%, and the average operation time is 102 hours. In Example 6, the Ni content with respect to Ti is 3.5 mol%, and the average operation time is 99 hours. In Example 7, the Ni content with respect to Ti is 5.0 mol%, and the average operation time is 98 hours. In Example 9, the Ni content with respect to Ti is 10.0 mol%, and the average operation time is 78 hours.

[0087] That is, when the Ni content with respect to Ti is in the range of 0.4 mol% or more and 5.0 mol% or less in Examples 2, 3, 4, 5, 6, and 7, the average operation time is 95 hours or more. In contrast, in Example 9 where the Ni content with respect to Ti is more than 5.0 mol%, the average operation time is 78 hours.

[0088] From the above, it can be seen that the Ni content with respect to Ti is preferably 0.4 mol% or more and 5.0 mol% or less.

[0089] (Preferred range of Mn content with respect to Ti) Also, in Examples 16, 17, 18, 19, 20, and 21, the Ni content with respect to Ti is 1.5 mol% in all cases, and the Mg content with respect to Ti is 0.001 mol% and is the same.

[0090] However, in Example 21, the Mn content relative to Ti is 0.03 mol%, and the average operating time is 78 hours. In Example 20, the Mn content relative to Ti is 0.05 mol%, and the average operating time is 95 hours. In Example 19, the Mn content relative to Ti is 0.20 mol%, and the average operating time is 97 hours. In Example 18, the Mn content relative to Ti is 0.40 mol%, and the average operating time is 108 hours. In Example 17, the Mn content relative to Ti is 0.80 mol%, and the average operating time is 113 hours. In Example 16, the Mn content relative to Ti is 1.00 mol%, and the average operating time is 80 hours.

[0091] That is, when the Mn content relative to Ti is in the range of 0.05 mol% or more and 0.80 mol% or less as in Examples 19, 18, and 17, the average operating time is 95 hours or more. On the other hand, in Example 21 where the Mn content relative to Ti is 0.03 mol%, or 1.00 in Example 16 where it is 1.00 mol%, the average operating time is 80 hours or less.

[0092] From the above, it can be seen that the Mn content relative to Ti is preferably 0.05 mol% or more and 0.80 mol% or less.

[0093] (Effect) As described above, according to the multilayer ceramic capacitor 1 of the embodiment, at least one of the outer layer portions 22 includes a Ni-free region 22A within 0.9 μm from the outermost internal electrode layer 150 closest to the outer layer portion 22 and a Ni-containing region 22B separated from the outermost internal electrode layer 150 by more than 0.9 μm. At least one of the outermost internal electrode layers 150 is thicker than the inner internal electrode layer 153 and has a small thickness variation. Thereby, the average operating time can be lengthened.

[0094] In the multilayer ceramic capacitor 1 of the embodiment, by setting the mol% of Ni relative to Ti to 0.4 mol% or more and 5.0 mol% or less, the average operating time can be further lengthened.

[0095] Furthermore, in the multilayer ceramic capacitor 1 of the embodiment, by setting the mol% of Mg with respect to Ti to 0.001 mol% or more and 0.01 mol% or less, the mean time between failures can be further extended.

[0096] Also, in the multilayer ceramic capacitor 1 of the embodiment, by setting the mol% of Mn with respect to Ti to 0.05 mol% or above 0.80 mol% below more, the mean time between failures can be further extended.

[0097] As described above, the embodiments of the present invention have been described, but the present invention is not limited to these embodiments and can be variously modified within the scope of the gist thereof.

Description of Reference Numerals

[0098] g grain g1 outer region g2 central region 1 multilayer ceramic capacitor 2 laminate 3 external electrode 10 laminate chip 11 inner layer portion 14 internal dielectric layer 15 internal electrode layer 150 outermost internal electrode layer 151 first outermost internal electrode layer 152 second outermost internal electrode layer 153 inner internal electrode layer 20 dielectric layer 21 side margin portion 22 outer layer portion 22A Ni-free region 22B Ni-containing region 30 underlayer electrode layer 31 plating layer

Claims

1. A laminate including an inner layer portion in which a plurality of layers of internal electrode layers and internal dielectric layers are alternately laminated, and two outer layer portions respectively disposed on both surfaces of the inner layer portion in the lamination direction; Two external electrodes respectively disposed on end faces which are both surfaces of the laminate in the longitudinal direction intersecting the lamination direction; The internal electrode layer has an outermost internal electrode layer closest to each of the outer layer portions and an inner internal electrode layer other than the outermost internal electrode layer; At least one of the outer layer portions includes a Ni-free region within 0.9 μm from the outermost internal electrode layer closest to the outer layer portion and a Ni-containing region separated from the outermost internal electrode layer by more than 0.9 μm; At least one of the outermost internal electrode layers is thicker than the inner internal electrode layer and has a small thickness variation; A multilayer ceramic capacitor.

2. The outer layer portion contains Ti and Ni, and the molar ratio of Ni to Ti is 0.4 mol% or more and 5.0 mol% or less; The multilayer ceramic capacitor according to Claim 1.

3. The outer layer portion includes a plurality of grains, and each of the grains has: The difference between the molar ratio of Ni to Ti in the central region other than the outer region of the grain and the molar ratio of Ni to Ti in the outer region within 10 nm from the outside of the grain is ±20% or less. The multilayer ceramic capacitor according to Claim 2.

4. The standard deviation / mean value of the thickness of the outermost internal electrode layer is 0.09 or more and 0.17 or less; The multilayer ceramic capacitor according to Claim 1.

5. The outer layer portion contains Ti and Mg, and the molar ratio of Mg to Ti is 0.001 mol or more and 0.01 mol or less; The multilayer ceramic capacitor according to Claim 3.

6. The outer layer portion contains Ti and Mn, and the molar ratio of Mn to Ti is 0.05 mol% or more and 0.80 mol% or less; The multilayer ceramic capacitor according to any one of Claims 1 to 5.

7. The thickness of the internal dielectric layer is 0.4 μm or more and 0.5 μm or less; The multilayer ceramic capacitor according to any one of Claims 1 to 5.

8. The thickness of the internal dielectric layer is 0.4 μm or more and 0.45 μm or less; The multilayer ceramic capacitor according to any one of Claims 1 to 5.

9. The thickness of the inner internal electrode layer is 0.3 μm or more and 0.4 μm or less; The multilayer ceramic capacitor according to any one of claims 1 to 5.

10. The thickness of the inner internal electrode layer is 0.3 μm or more and 0.35 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 5.

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