Communication system, communication method, and program

Abstract

To provide a communication system capable of enhancing a rate of occurrence of data discard by synchronizing clocks to be used for transmission / reception.SOLUTION: A communication system includes: one or more clock extraction sections each for generating a clock synchronized to transmitted data by performing clock extraction from a head bit of data transmitted from each of one or more devices for transmission / reception through lines to a device for control; one or more clock frequency division sections for dividing frequencies of clocks synchronized to the transmitted data and outputting frequency divided clocks; a frequency divided clock selection section for selecting a frequency divided clock corresponding to any one line and outputting the selected frequency divided clock; an asynchronous clock frequency division section for generating a frequency divided asynchronous clock; a phase synchronization section for generating and outputting a reference clock synchronized to the selected frequency divided clock on the basis of the selected frequency divided clock and the frequency divided asynchronous clock; and a reference clock multiplication section for multiplying the reference clock and outputting the multiplied clock.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a communication system, a communication method, and a program.

Background Art

[0002] Regarding the synchronization of clocks in a network, the following documents can be cited.

[0003] Patent Document 1 relates to a slave synchronization method that does not affect the slave synchronization of other lines when a failure occurs in one of a plurality of lines.

[0004] Patent Document 2 relates to a transceiver module that can inexpensively realize the needs in the case of high-speed and short-distance communication.

[0005] Patent Document 3 relates to a network device used to realize a synchronization network on Ethernet (registered trademark).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] The following analysis is provided by the inventor of the present invention.

[0008] In an XFI interface for 10GBASE-X used in a router or the like, at a connection portion between a control device such as a CPU and a communication device such as an Ethernet (registered trademark) transceiver, bit errors may occur during data capture, and packets may not be recognized properly, resulting in the packets being discarded by the receiving device. In such cases, the expected communication quality may not be obtained.

[0009] An object of the present invention is to provide a communication system, a communication method, and a program that contribute to making it possible to improve the occurrence rate of data discard by synchronizing the clocks used for transmission and reception.

Means for Solving the Problem

[0010] According to a first aspect of the present invention, for a control device, clock extraction is performed from the leading bit of data transmitted from each of one or more transmission / reception devices via each line, and one or more clock extraction units that respectively generate clocks synchronized with the transmitted data; one or more clock division units that divide each of the clocks synchronized with the transmitted data and output each divided clock; a divided clock selection unit that selects a divided clock corresponding to any one line from one or more of the divided clocks and outputs the selected divided clock; an asynchronous clock division unit that divides an asynchronous clock and generates a divided asynchronous clock; a phase synchronization unit that generates and outputs a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock; a reference clock multiplication unit that multiplies the reference clock and outputs one or more multiplied clocks A communication system including the above can be provided.

[0011] According to a second aspect of the present invention, a computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit, performs clock extraction from the leading bits of data transmitted from each of one or more transmitting and receiving devices via each line to a control device, and generates clocks synchronized with the transmitted data, respectively, in one or more clock extraction steps; divides each of the clocks synchronized with the transmitted data, and outputs respective divided clocks, in one or more clock division steps; selects a divided clock corresponding to any one line from one or more of the divided clocks, and outputs the selected divided clock, in a divided clock selection step; divides an asynchronous clock, and generates a divided asynchronous clock, in an asynchronous clock division step; generates and outputs a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock, in a phase synchronization step; multiplies the reference clock, and outputs one or more multiplied clocks, in a reference clock multiplication step A communication method including the above can be provided. This method is associated with a specific machine, namely, a computer that performs the communication method.

[0012] According to a third aspect of the present invention, in a computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit, perform clock extraction from the leading bits of data transmitted from each of one or more transmitting and receiving devices via each line to a control device, and generate clocks synchronized with the transmitted data, respectively, in one or more clock extraction processes; divide each of the clocks synchronized with the transmitted data, and output respective divided clocks, in one or more clock division processes; A frequency division clock selection process that selects a frequency division clock corresponding to any one line from the one or more frequency division clocks and outputs the selected frequency division clock, An asynchronous clock division process that divides an asynchronous clock and generates a divided asynchronous clock, A phase synchronization process that generates and outputs a reference clock synchronized with the selected frequency division clock based on the selected frequency division clock and the divided asynchronous clock, A reference clock multiplication process that multiplies the reference clock and outputs one or more multiplied clocks A program that causes the above to be executed can be provided.

[0013] These programs can be recorded on a computer-readable storage medium. The storage medium can be a non-transient one such as a semiconductor memory, a hard disk, a magnetic recording medium, an optical recording medium, etc. The present invention can also be embodied as a computer program product.

Effects of the Invention

[0014] According to the present invention, it is possible to provide a communication system, a communication method, and a program that contribute to making it possible to improve the data discard rate by synchronizing the clocks used for transmission and reception.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0016] First, an overview of an embodiment of the present invention will be described with reference to the drawings. Note that the reference numerals in the drawings appended to this overview are for convenience and are appended to each element as an example to assist understanding, and are not intended to limit the present invention to the illustrated embodiments. Also, the connection lines between the blocks in the drawings and the like referred to in the following description include both bidirectional and unidirectional ones. The one-way arrow schematically shows the flow of the main signal (data) and does not exclude bidirectionality.

[0017] FIG. 1 is a diagram showing an example of the configuration of a communication system according to an embodiment of the present invention. Referring to FIG. 1, the communication system 100 includes one or more clock extraction units 1201 to 120n and a clock generation unit 130. The clock generation unit 130 includes one or more clock division units 1401 to 140n, a divided clock selection unit 150, an asynchronous clock division unit 160, a phase synchronization unit 170, and a reference clock multiplication unit 180.

[0018] The transmission / reception device 1101 is connected to the control device 190 by lines 1011 and 1021, the transmission / reception device 110n is connected to the control device 190 by lines 101n and 102n, the clock extraction unit 1201 acquires the data 101 transmitted on the line 1011, and the clock extraction unit 120n acquires the data 10n transmitted on the line 101n.

[0019] The clock extraction units 1201 to 120n extract clocks from the leading bits of the data 101 to 10n transmitted from each of the one or more transmission / reception devices 1101 to 110n to the control device 190 via the respective lines 1011 to 101n, and generate clocks 211 to 21n synchronized with the transmitted data 101 to 10n. The lines 1011 to 101n and the lines 1021 to 102n are, for example, a plurality of Ethernet (registered trademark) lines used in a router or the like.

[0020] One or more clock division units 1401 to 140n of the clock generation unit 130 divide each of the clocks 211 to 21n synchronized with the transmitted data, and output the respective divided clocks.

[0021] The divided clock selection unit 150 of the clock generation unit 130 selects a divided clock corresponding to any one of the lines 1011 to 101n from the one or more divided clocks, and outputs the selected divided clock.

[0022] The asynchronous clock division unit 160 of the clock generation unit 130 divides the asynchronous clock and generates a divided asynchronous clock.

[0023] The phase synchronization unit 170 of the clock generation unit 130 generates and outputs a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock.

[0024] The reference clock multiplication unit 180 of the clock generation unit 130 multiplies the reference clock and outputs one or more multiplied clocks.

[0025] The reference clock multiplication unit 180 of the clock generation unit 130 supplies the multiplied clocks used by the transmission / reception devices 1101 to 110n and the control device 190 for transmission / reception to the transmission / reception devices 1101 to 110n and the control device 190.

[0026] As described above, according to one embodiment of the present invention, it is possible to generate a multiplied clock used for transmission and reception by a transmission / reception device and a control device synchronized with the transmitted data.

[0027] Also, according to one embodiment of the present invention, it is possible to supply to each device a clock of any frequency synchronized with the data transmitted on an arbitrary line or a clock of an arbitrary independent frequency.

[0028] Further, according to one embodiment of the present invention, by operating the functions related to data transmission and reception on the lines within the device based on a synchronized clock, it is possible to improve the occurrence rate of data discard due to reduction of bit errors.

[0029] Therefore, according to one embodiment of the present invention, it is possible to provide a communication system, a communication method, and a program that contribute to making it possible to improve the occurrence rate of data discard by synchronizing the clocks used for transmission and reception.

[0030] [First Embodiment] Next, the communication system according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a diagram showing an example of the configuration of the communication system according to the first embodiment of the present invention. Further, FIG. 3 is a diagram showing an example of the configuration of the clock generation unit of the communication system according to the first embodiment of the present invention. In FIGS. 2 and 3, components denoted by the same reference numerals as in FIG. 1 represent the same components.

[0031] Referring to FIG. 2, the communication system 100 includes clock extraction units 1201 to 120n and a clock generation unit 130. Referring to FIG. 3, the clock generation unit 130 includes clock division units 1401 to 140n, a divided clock selection unit 150, an asynchronous clock division unit 160, a phase synchronization unit 170, and a reference clock multiplication unit 180.

[0032] The clock extraction units 1201 to 120n extract clocks respectively from the leading bits of the data 101 to 10n transmitted from each of the one or more transmission / reception devices 1101 to 110n to the control device 190 via the respective lines 1011 to 101n, generate clocks 211 to 21n synchronized with the transmitted data 101 to 10n, and supply them to the clock generation unit 130. The lines 1011 to 101n and the lines 1021 to 102n are, for example, a plurality of Ethernet (registered trademark) lines used in a router or the like. The clock extraction reference clocks (clocks serving as references for clock extraction) 201 to 20n are supplied from the clock generation unit 130 to the clock extraction units 1201 to 120n. For example, in the case of a 10GBASE-X XFI interface, both the clocks 211 to 21n synchronized with the transmitted data and the clock extraction reference clocks 201 to 20n are 156.25 MHz. That is, the clock extraction units 1201 to 1201n for each of the lines 1011 to 101n transmit the clocks 211 to 21n synchronized with the transmitted data, which are extracted and generated respectively based on the clock extraction reference clocks 201 to 20n, to the clock generation unit 130.

[0033] Referring to FIG. 3, the clocks 211 to 21n synchronized with the transmitted data generated by the clock extraction units 1201 to 120n described in FIG. 2 are supplied to the clock division units 1401 to 140n of the clock generation unit 130, and the clock division units 1401 to 140n generate divided clocks 311 to 31n with a frequency of 6.25 MHz by dividing, for example, by 25.

[0034] From among the divided clocks 311 to 31n respectively divided by the clock division units 1401 to 140n, the divided clock selection unit 150 selects a divided clock 151 selected for any one of the lines.

[0035] Also, an asynchronous clock 200 generally supplied from a crystal oscillator or the like is divided by the asynchronous clock division unit 160 to generate an asynchronous divided clock 161 of 6.25 MHz.

[0036] The divided clock 151 selected by the divided clock selection unit 150 and the asynchronous divided clock 161 divided by the asynchronous clock division unit 160 are input to the phase synchronization unit 170. The phase synchronization circuit (PLL) in the phase synchronization unit 170 uses the asynchronous divided clock 161 divided by the asynchronous clock division unit 160 to generate a reference clock 171 synchronized with the selected divided clock 151 corresponding to the selected line.

[0037] The phase synchronization unit 170 may be configured by, for example, a digital phase-locked loop (DPLL). The processing of the DPLL adjusts the phase from the asynchronous divided clock 161 divided by the asynchronous clock division unit 160 to generate a clock with the same phase as the divided clock 151 selected by the divided clock selection unit 150, and outputs the generated clock as the reference clock 171. As another processing of the DPLL, multiple-phase clocks with different multiplied phases are generated from the asynchronous divided clock 161 divided by the asynchronous clock division unit 160, and for the divided clock 151 selected by the divided clock selection unit 150, an optimally phase-multiplied clock, such as a multiplied clock with the closest phase, is selected, and the selected phase-multiplied clock is divided and output as the reference clock 171.

[0038] In the reference clock multiplication unit 180, the reference clocks 201 to 20n for clock extraction supplied to the clock extraction units 1201 to 120n, the clocks 301 to 30n input to the transmission / reception devices 1101 to 110n for each communication, and the clock 400 input to the control device 190 are multiplied to the required frequencies from the reference clock 171 output by the phase synchronization unit 170 and then generated and output. At this time, the reference clocks 201, 202, 20n for clock extraction, the clocks 301, 302, 30n input to the transmission / reception devices 1101 to 110n, the clock 400 input to the control device 190, and other necessary clocks generally become clocks with frequencies that can be generated by multiplying the 6.25 MHz reference clock 171.

[0039] As described above, according to the first embodiment of the present invention, it is possible to generate a multiplied clock used for transmission and reception by the transmission / reception device and the control device in synchronization with the transmitted data. Therefore, according to the first embodiment of the present invention, by synchronizing the clocks used for transmission and reception, it is possible to contribute to improving the occurrence rate of data discard, and a communication system, a communication method, and a program can be provided.

[0040] [Second Embodiment] Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing an example of the configuration of a clock extraction unit of a communication system according to the second embodiment of the present invention. FIG. 5 is a diagram showing an example of the operation of the clock extraction unit of the communication system according to the second embodiment of the present invention. In FIG. 4, components denoted by the same reference numerals as those in FIGS. 1 to 3 represent the same components.

[0041] Referring to FIG. 4, the clock extraction unit 1201 includes a 66-fold multiplication unit 401 that generates a multiplied clock 501 obtained by multiplying the clock extraction reference clock 201 by 66, and a clock recovery unit 402 that takes the multiplied clock 501 and the data 101 transmitted from the transmission / reception device 1101 on the line 1011 as inputs, and outputs a clock 211 synchronized with the transmitted data extracted and generated therefrom. The clock 211 synchronized with the transmitted data is sent to a clock division unit 1401 that divides it by 66 to generate a divided clock 311, and the divided clock 311 is generated.

[0042] Next, an example of the operation of the clock extraction unit 1201 according to the second embodiment of the present invention will be described. The portion surrounded by the broken line 600 in FIG. 5 shows the operation of clock recovery. Referring to FIG. 5, there are shown a reference clock 201 for clock extraction, a multiplied clock 501 obtained by multiplying the reference clock for clock extraction, data (received data of the clock extraction unit 1201) 101 transmitted from the transmission / reception device 1101 via the line 1011, a clock 211 synchronized with the transmitted data, which is extracted and generated by the clock recovery unit 402 based on the multiplied clock 501, and a divided clock 311 obtained by dividing the clock 211 synchronized with the transmitted data by 66 by the clock division unit 1401.

[0043] The clock recovery unit 402 extracts and generates a clock 211 synchronized with the transmitted data 101 from the multiplied clock 501 obtained by multiplying the reference clock 201 for clock extraction. Examples of the operation of clock recovery include, for example, performing phase adjustment on the multiplied clock 501 to generate a clock having the same phase with respect to the transmitted data 101 and outputting the generated clock as the clock 211 synchronized with the transmitted data 101. Also, there are methods such as generating multi-phase clocks having different phases from the multiplied clock 501 obtained by multiplying the reference clock and selecting an optimal-phase clock, such as the clock having the closest phase, with respect to the transmitted data 101 and outputting it as the clock 211 synchronized with the transmitted data.

[0044] As described above, according to the second embodiment of the present invention, the clock extraction unit 1201 can be configured to extract, from the leading bits of the data transmitted via each line, clocks synchronized with the transmitted data, respectively.

[0045] [Third Embodiment] Next, the third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a diagram showing an example of the configuration of the clock generation unit 130 of the communication system according to the third embodiment of the present invention. In FIG. 6, components denoted by the same reference numerals as those in FIGS. 1 to 3 represent the same components.

[0046] In the third embodiment of the present invention, an embodiment is described in which a phase-locked loop (PLL) is configured by an asynchronous clock divider section 160 and a phase synchronization section 170.

[0047] Referring to FIG. 6, the phase synchronization section 170 includes a phase comparator 601 that compares the phase of the divided clock 151 selected by the divided clock selection section 150 with the phase of the asynchronous clock 200 divided by the asynchronous clock divider section 160, a low-pass filter (LPF) 602 that receives the output of the phase comparator 601, and a voltage-controlled oscillator 603, such as a VCXO (voltage-controlled crystal oscillator), that receives the output of the low-pass filter 602. The output of the voltage-controlled oscillator 603 is supplied as the asynchronous clock 200 to the asynchronous clock divider section 160, and the divided asynchronous clock 200 is output as the reference clock 171. The asynchronous clock 200 is a clock obtained by dividing the output of the voltage-controlled oscillator 603, which is asynchronous with the selected divided clock 151, by the asynchronous clock divider section 160 at the start of operation of the PLL. However, when the PLL becomes phase-synchronized with the selected divided clock 151, the reference clock 171 becomes a clock that is phase-synchronized with the selected divided clock 151.

[0048] As described above, according to the third embodiment of the present invention, the phase synchronization section 170 of the third embodiment, which is different from the operation of the phase synchronization section 170 described in the first embodiment, can be configured.

[0049] Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiments, and further modifications, substitutions, and adjustments can be made without departing from the basic technical idea of the present invention. For example, the network configuration shown in each drawing, the configuration of each element, and the expression form of the message are examples for helping the understanding of the present invention and are not limited to the configurations shown in these drawings. Also, "A and / or B" is used to mean at least one of A or B.

[0050] Also, the procedures shown in the above-described first to third embodiments can be realized by a program that causes a computer (9000 in FIG. 7) functioning as the communication system of the present invention to realize the functions of the communication system. Such a computer is exemplified by a configuration including a CPU (Central Processing Unit) 9010, a communication interface 9020, a memory 9030, and an auxiliary storage device 9040 in FIG. 7. That is, the CPU 9010 in FIG. 7 may execute a control program for the communication system and perform update processing of each calculation parameter held in the auxiliary storage device 9040 or the like.

[0051] The memory 9030 is a RAM (Random Access Memory), a ROM (Read Only Memory), or the like.

[0052] That is, each part (processing means, function) of the communication system shown in the above-described first to third embodiments can be realized by a computer program that causes the processor of the above computer to execute each of the above-described processes using the hardware thereof.

[0053] Finally, the preferred forms of the present invention will be summarized. [First Form] (Refer to the communication system according to the above first viewpoint) [Second Form] In the communication system described in the first form, it is preferable that the clock extraction unit performs clock data recovery based on the multiplied clock output from the reference clock multiplication unit. [Third Form] In the communication system described in the first form, it is preferable that the phase synchronization unit is a digital phase-locked loop (DPLL). [Fourth Form] In the communication system according to the first aspect, the phase synchronization unit includes a phase comparator that compares the phase of the selected divided clock and the divided asynchronous clock, a low-pass filter that receives the output of the phase comparator, and a voltage-controlled oscillator that receives the output of the low-pass filter. The output of the voltage-controlled oscillator is supplied as the asynchronous clock to the asynchronous clock division unit, and the divided asynchronous clock is output as the reference clock. This is preferable. [Fifth Aspect] In the communication system according to the first aspect, it is preferable that the reference clock multiplication unit supplies the multiplied clock used by the transmission / reception device and the control device for transmission / reception to the transmission / reception device and the control device. [Sixth Aspect] In the communication system according to the first aspect, it is preferable that the line is an Ethernet (registered trademark) line. [Seventh Aspect] (Refer to the communication method according to the second perspective above) [Eighth Aspect] In the communication method according to the seventh aspect, it is preferable that the computer performs clock data recovery based on the multiplied clock in the clock extraction step. [Ninth Aspect] (Refer to the program according to the third perspective above) [Tenth Aspect] In the program according to the ninth aspect, it is preferable that the computer is caused to perform clock data recovery based on the multiplied clock in the clock extraction process. Note that the seventh and ninth aspects can be developed into the third to sixth aspects in the same manner as the first aspect.

[0054] Incidentally, each disclosure of the above patent documents is incorporated herein by reference. Within the scope of the entire disclosure of the present invention (including the claims), further modifications and adjustments of the embodiments or examples can be made based on the basic technical idea. Also, within the scope of the disclosure of the present invention, various combinations or selections of various disclosure elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. That is, the present invention naturally includes all the disclosures including the claims, and various modifications and corrections that could be made by those skilled in the art according to the technical idea. In particular, regarding the numerical ranges described in this document, any numerical value or small range included within the range should be construed as being specifically described even in the absence of separate description. Furthermore, each disclosure item of the above-cited documents, as necessary and in accordance with the spirit of the present invention, is also considered to be included in the disclosure of the present application as a part of the disclosure of the present invention, and can be used in combination with the description items in this document, either in part or in whole.

Explanation of Signs

[0055] 100 Communication system 101~10n Transmitted data 1011, 1012, 101n, 1021, 1022, 102n Lines 1101, 1102, 110n Transceiver devices 130 Clock generation unit 1201, 1202, 120n Clock extraction units 1401, 1402, 140n Clock division units 150 Divided clock selection unit 151 Selected divided clock 160 Asynchronous clock division unit 161 Asynchronous divided clock 170 Phase synchronization unit 171 Reference clock 180 Reference clock multiplier unit 190 Control device 200 Asynchronous clock 201, 202, 20n Reference clocks for clock extraction Clocks synchronized with the transmitted data 211, 212, 21n Clocks 301, 302, 30n, 400 Divided clocks 311, 312, 31n 66-times multiplier section 401 Clock recovery section 402 Multiplied clock 501 Phase comparator 601 Low-pass filter (LPF) 602 Voltage-controlled oscillator 603 Computer 9000 CPU 9010 Communication interface 9020 Memory 9030 Auxiliary storage device 9040

Claims

1. For a control device, one or more clock extraction units that perform clock extraction from the leading bits of data transmitted via each line from each of one or more transmission / reception devices and generate clocks synchronized with the transmitted data respectively; One or more clock division units that divide each of the clocks synchronized with the transmitted data and output each divided clock; A divided clock selection unit that selects a divided clock corresponding to any one line from one or more of the divided clocks and outputs the selected divided clock; An asynchronous clock division unit that divides an asynchronous clock and generates a divided asynchronous clock; A phase synchronization unit that generates and outputs a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock, generates multi-phase clocks with different phases multiplied from the divided asynchronous clock, selects the clock having the closest phase to the selected divided clock, and divides the selected clock having the closest phase to output the reference clock; the phase synchronization unit; A reference clock multiplication unit that multiplies the reference clock and outputs one or more multiplied clocks A communication system including the above.

2. The communication system according to claim 1, wherein the clock extraction unit performs clock data recovery based on the multiplied clock output by the reference clock multiplication unit.

3. The communication system according to claim 1, wherein the phase synchronization unit is a digital phase-locked loop (DPLL).

4. The communication system according to claim 1, wherein the reference clock multiplication unit supplies the multiplied clock used by the transmission / reception device and the control device for transmission / reception to the transmission / reception device and the control device.

5. The communication system according to claim 1, wherein the line is an Ethernet (registered trademark) line.

6. A computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit For a control device, perform clock extraction from the leading bits of data transmitted via each line from each of one or more transmission / reception devices, and generate clocks synchronized with the transmitted data, respectively, in one or more clock extraction steps; divide each of the clocks synchronized with the transmitted data, and output each divided clock, in one or more clock division steps; select, from one or more of the divided clocks, a divided clock corresponding to any one line, and output the selected divided clock, in a divided clock selection step; divide an asynchronous clock, and generate a divided asynchronous clock, in an asynchronous clock division step; a phase synchronization step of generating and outputting a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock, generating multi-phase clocks with different phases multiplied from the divided asynchronous clock, selecting the clock having the closest phase with respect to the selected divided clock, and dividing the selected clock having the closest phase to output the reference clock; multiply the reference clock to output one or more multiplied clocks, in a reference clock multiplication step A communication method including the above steps.

7. The communication method according to claim 6, wherein the computer performs clock data recovery based on the multiplied clock in the clock extraction step.

8. In a computer including one or more clock extraction units, one or more clock division units, a divided clock selection unit, an asynchronous clock division unit, a phase synchronization unit, and a reference clock multiplication unit, for a control device, perform clock extraction from the leading bits of data transmitted via each line from each of one or more transmission / reception devices, and generate clocks synchronized with the transmitted data, respectively, in one or more clock extraction processes; divide each of the clocks synchronized with the transmitted data, and output each divided clock, in one or more clock division processes; select, from one or more of the divided clocks, a divided clock corresponding to any one line, and output the selected divided clock, in a divided clock selection process; divide an asynchronous clock, and generate a divided asynchronous clock, in an asynchronous clock division process; A phase synchronization process that generates and outputs a reference clock synchronized with the selected divided clock based on the selected divided clock and the divided asynchronous clock, the process generating multi-phase clocks with different phases multiplied from the divided asynchronous clock, selecting, for the selected divided clock, the clock having the closest phase, dividing the selected clock having the closest phase, and outputting the divided clock as the reference clock; A reference clock multiplication process that multiplies the reference clock and outputs one or more multiplied clocks A program for causing the execution thereof.

9. The program according to claim 8, wherein, in the clock extraction process, the computer is caused to perform clock data recovery based on the multiplied clock.

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