Clock recovery circuit, error rate measurement device, and error rate measurement method

Abstract

To provide a clock recovery circuit, an error rate measurement device, and an error rate measurement method, capable of reproducing a half rate clock while assuring tolerance against a wide loop band and frequency deviation due to SSC modulation.SOLUTION: A clock recovery circuit 1 includes: a VCO part 80 for outputting an output signal at a frequency according to a control voltage; a phase comparison part 20 for respectively differential-outputting an error signal with a pulse width according to a phase difference between the output signal or divided signal of the output signal of the VCO part 80 and a data signal, and a reference signal with a pulse width according to the data signal; a differential amplification part 40 for subtracting a half of differential amplitude of the reference signal from the differential amplitude of the error signal; an amplification part 50 for amplifying the output of the differential amplification part 40; a loop filter part 60 for smoothing the output of the amplification part 50 and error-amplifying the smoothed output of the amplification part 50; and a pre-tune part 70 for outputting a control voltage, obtained by adding a pre-tune voltage to the output of the loop filter part 60, to the VCO part 80.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a clock recovery circuit, an error rate measurement device, and an error rate measurement method, and particularly relates to a clock recovery circuit, an error rate measurement device, and an error rate measurement method for reproducing a half-rate clock from a data signal modulated by a spread-spectrum clock.

Background Art

[0002] The PCI Express (registered trademark) (Peripheral Component Interconnect Express) standard has been increasing its data rate with each generation. In Gen5, it is 32 Gbit / s in NRZ (Non Return to Zero), and in Gen6, it is 32 Gbaud (i.e., 64 Gbit / s) in PAM4 (Pulse Amplitude Modulation 4).

[0003] In recent years, due to the spread of IoT (Internet of Things) and cloud computing, communication systems have come to handle huge amounts of data, and the interfaces of various communication devices constituting the communication system have been evolving towards higher speeds and serial transmissions. For example, in the standards of high-speed serial buses such as USB (registered trademark) (Universal Serial Bus) and PCI Express, SSC modulation using a spread-spectrum clock (SSC) that spreads the spectrum of the reference signal is adopted as a measure for electromagnetic compatibility (EMC).

[0004] The SSC-modulated data signal is generated at a timing synchronized with a reference clock frequency-swept by an SSC modulation wave having a predetermined modulation frequency. For example, the SSC modulation wave of the PCI Express standard has a waveform shape of a triangular wave with a period of 33 kHz as shown in FIG. 15.

[0005] By the way, as one of the indexes for evaluating the quality of signals in communication devices, the bit error rate (BER), which is defined as the comparison between the number of bit errors that occur in the received data and the total number of received data, is known.

[0006] In recent years, many of the various communication devices that make up a communication system do not transmit a clock for synchronization and only transmit data signals. Conventional error rate measurement devices for measuring BER are equipped with a clock recovery circuit that regenerates a clock from the received data signal. Conventionally, various clock recovery circuits have been proposed (see, for example, Patent Documents 1 to 9 and Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Non-Patent Documents

[0008]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] However, conventional clock recovery circuits such as those disclosed in Patent Documents 1 to 9 and Non-Patent Document 1 do not have a wide loop bandwidth that can support various standards or tolerance for a large frequency offset of about 5000 ppm, for example. For this reason, these clock recovery circuits have a problem that they cannot be applied to error rate measurement devices that are required to support various standards including the PCI Express standard.

[0010] The present invention has been made to solve such conventional problems, and an object thereof is to provide a clock recovery circuit, an error rate measurement device, and an error rate measurement method that can reproduce a half-rate clock while ensuring a wide loop bandwidth and tolerance for frequency offset due to SSC modulation.

Means for Solving the Problems

[0011] In order to solve the above problems, a clock recovery circuit according to the present invention is a clock recovery circuit (1) that reproduces a half-rate clock having a frequency that is half of a data signal SSC-modulated at a predetermined SSC modulation frequency, including: a voltage-controlled oscillator (80) that outputs an output signal having a frequency corresponding to an input control voltage; a phase comparator (20) that differentially outputs an error signal having a pulse width corresponding to a phase difference between a clock signal, which is a divided signal obtained by dividing the output signal of the voltage-controlled oscillator or the frequency of the output signal, and the data signal, and a reference signal having a pulse width corresponding to the data signal; a differential amplifier (40) that subtracts half of the differential amplitude of the reference signal differentially output by the phase comparator from the differential amplitude of the error signal differentially output by the phase comparator; an amplifier (50) that amplifies the output of the differential amplifier; a loop filter unit (60) that smoothes the output of the amplifier and error-amplifies the smoothed output of the amplifier with reference to a predetermined reference voltage; and a pre-tuning unit (70) that outputs the control voltage obtained by adding a predetermined pre-tuning voltage to the output of the loop filter unit to the voltage-controlled oscillator. The phase comparator includes: a first latch circuit (23) that latches the data signal in synchronization with a positive-phase signal of the clock signal; a second latch circuit (24) that latches the data signal in synchronization with a negative-phase signal of the clock signal; a third latch circuit (25) that latches the output of the first latch circuit in synchronization with the negative-phase signal of the clock signal; a fourth latch circuit (26) that latches the output of the second latch circuit in synchronization with the positive-phase signal of the clock signal; a first exclusive OR circuit (27) that outputs an exclusive OR of the output of the first latch circuit and the output of the second latch circuit; a second exclusive OR circuit (28) that outputs an exclusive OR of the output of the third latch circuit and the output of the fourth latch circuit; a first differential amplifier (29) that amplifies the output of the first exclusive OR circuit and differentially outputs the error signal; and a second differential amplifier (30) that amplifies the output of the second exclusive OR circuit and differentially outputs the reference signal. The half-rate clock is the clock signal when the clock recovery circuit is locked.

[0012] With this configuration, the clock recovery circuit according to the present invention can reproduce the half-rate clock by ensuring a sufficient loop gain, thereby ensuring a wide loop bandwidth and resistance to frequency offset due to SSC modulation. For example, the clock recovery circuit 1 according to the present invention can cope with a maximum frequency offset of 5300 ppm of the SSC modulation of the PCI Express standard.

[0013] In addition, the clock recovery circuit according to the present invention can dispense with a reference clock, a PFD (Phase Frequency Detector), a charge pump, etc., and can ensure fast and stable lock performance. In particular, the clock recovery circuit according to the present invention is characterized in that it can reproduce the half-rate clock with a simple circuit configuration by not including a charge pump.

[0014] Note that the data rates of Gen1 / 2 of the PCI Express standard are 2.5 / 5 Gbit / s, which are 2 times and 2 times of 2.5 Gbit / s respectively. 0 times and 2 1 times. Therefore, when the output signal from a VCO (Voltage-Controlled Oscillator) with an oscillation frequency in the 5 GHz band is divided by 2 or 4 by a frequency divider in the clock recovery circuit according to the present invention, the number of VCOs included in the voltage-controlled oscillation unit can be reduced, thereby realizing cost reduction and efficiency improvement.

[0015] In addition, the data rates of Gen3 / 4 / 5 / 6 of the PCI Express standard are 8 / 16 / 32 Gbit / s and 32 Gbaud, which are 2 times, 2 times, 2 times, and 2 times of 8 Gbit / s respectively. Therefore, when the output signal (without frequency division) from a VCO with an oscillation frequency in the 16 GHz band is output as it is, or divided by 2 or 4 by a frequency divider and then output in the clock recovery circuit according to the present invention, the number of VCOs included in the voltage-controlled oscillation unit can be reduced, thereby realizing cost reduction and efficiency improvement. 0 times and 2 1 times and 2 2 times.

[0016] Also, in the clock recovery circuit according to the present invention, the differential amplification unit has a third differential amplifier (41), and an output terminal of the third differential amplifier is connected to an inverting input terminal of the third differential amplifier via a first resistor (R1) and is connected to an input side of the amplification unit. A non-inverting input terminal of the third differential amplifier is grounded via a second resistor (R2), an inverted signal of the reference signal is input to the non-inverting input terminal via a third resistor (R3), a non-inverted signal of the error signal is input to the non-inverting input terminal via a fourth resistor (R4), an inverted signal of the error signal is input to the inverting input terminal via a fifth resistor (R5), a non-inverted signal of the reference signal is input to the inverting input terminal via a sixth resistor (R6), resistance values of the first resistor, the second resistor, the fourth resistor, and the fifth resistor are all equal, and resistance values of the third resistor and the sixth resistor are twice resistance values of the first resistor, the second resistor, the fourth resistor, and the fifth resistor. This may be a configuration characterized thereby.

[0017] With this configuration, in the clock recovery circuit according to the present invention, one differential amplification unit can perform differential voltage calculation for subtracting a reference signal shown in Non-Patent Document 1 from an error signal with a half gain, avoiding a dead zone (non-linear region) in a phase comparison unit, and making it easier to lock, thereby improving circuit efficiency.

[0018] Also, the clock recovery circuit according to the present invention may be configured to further include a frequency counter unit (100) that counts a frequency of the clock signal.

[0019] With this configuration, the clock recovery circuit according to the present invention can output information for determining whether a lock state of the clock recovery circuit is in a locked state, an unlocked state, or a pseudo-locked state.

[0020] Further, the clock recovery circuit according to the present invention may be configured to further include a switching unit (52, 53, 64 to 67) that switches the gain of the amplification unit and the constant of the loop filter unit. Further, the switching unit may be configured to switch including a ninth resistor (R9) and a first capacitor (C1) that constitute a low-pass filter included in the loop filter unit.

[0021] With this configuration, the clock recovery circuit according to the present invention can change the loop bandwidth characteristics by selectively switching the loop gain and the loop filter constant.

[0022] Further, the error rate measuring device according to the present invention includes a signal receiving unit (153) that receives a data signal SSC-modulated at a predetermined SSC modulation frequency, and an error rate calculation unit (155) that calculates the bit error rate of the bit string data constituting the data signal received by the signal receiving unit. The error rate measuring device (150) is characterized in that the signal receiving unit has the clock recovery circuit according to claim 1 or claim 2, and extracts the bit string data constituting the data signal at the rising and falling timings of the half-rate clock reproduced from the data signal by the clock recovery circuit.

[0023] With this configuration, the error rate measuring device according to the present invention can receive the SSC-modulated data signal transmitted from the object to be measured and reproduce the half-rate clock from the data signal using any of the above clock recovery circuits. Further, the error rate measuring device according to the present invention can extract the bit string data constituting the data signal at the rising and falling timings of the reproduced half-rate clock and measure the BER of this bit string data.

[0024] In addition, the error rate measurement method according to the present invention includes a signal reception step (S2, S3) of receiving a data signal SSC-modulated at a predetermined SSC modulation frequency, and an error rate calculation step (S4) of calculating a bit error rate of bit string data constituting the data signal received in the signal reception step. The signal reception step is configured to extract the bit string data constituting the data signal at the rising and falling timings of the half-rate clock reproduced from the data signal by the clock recovery circuit according to claim 1 or claim 2.

Effect of the Invention

[0025] The present invention provides a clock recovery circuit, an error rate measurement device, and an error rate measurement method that can reproduce a half-rate clock while ensuring a wide loop bandwidth and resistance to frequency deviation due to SSC modulation.

Brief Description of the Drawings

[0026]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0027] Hereinafter, embodiments of a clock recovery circuit, an error rate measurement device, and an error rate measurement method according to the present invention will be described with reference to the drawings.

[0028] (First Embodiment) The clock recovery circuit 1 according to the first embodiment of the present invention shown in FIG. 1 can reproduce a half-rate clock having a frequency that is 1 / 2 of the frequency of a data signal SSC-modulated at a predetermined SSC modulation frequency and a half-rate clock having a frequency that is 1 / 2 of the frequency of a normal data signal that is not SSC-modulated. Hereinafter, mainly, the case where the data signal is an SSC-modulated signal will be described.

[0029] The SSC modulation frequency is defined for each communication standard and is, for example, a frequency in the range of 30 to 33 kHz. The half-rate clock reproduced from the SSC-modulated data signal by the clock recovery circuit 1 is a clock that is SSC-modulated in the same manner as the data signal, and as shown in FIG. 2, depending on the frequency deviation of the SSC modulation and the SSC modulation frequency, the interval of the rising (or falling) edge of the pulse and the pulse width have changed.

[0030] The data signal input to the clock recovery circuit 1 is a single-ended signal or a differential signal. Also, the half-rate clock of the data signal is a single clock or a differential clock having a frequency that is 1 / 2 of the frequency of the data signal. For example, in the case of a data signal of Gen5 of the PCI Express standard with a data rate of 32 Gbit / s, the frequency of the half-rate clock is 16 GHz.

[0031] As shown in FIG. 1, the clock recovery circuit 1 includes a limiting amplifier unit 10, a phase comparison unit 20, a differential amplifier unit 40, an amplifier unit 50, a loop filter unit 60, a pre-tune unit 70, a voltage controlled oscillator unit (hereinafter, also referred to as "VCO unit") 80, a frequency divider unit 90, a frequency counter unit 100, and a control unit 110.

[0032] The limiting amplifier section 10 is an amplifier that uses a saturated region of input-output characteristics and amplifies with a predetermined amplitude as a limit. That is, the limiting amplifier section 10 is configured to improve the input sensitivity of the data signal by shaping and amplifying the input data signal. Further, when the data signal is a PAM4 signal, the limiting amplifier section 10 converts the input PAM4 signal into a NRZ-equivalent signal having voltages of logic levels "0" and "1" in the voltage range of the center (Most Significant Bit: MSB) of the eye pattern and outputs it. That is, by passing the data signal through the limiting amplifier section 10, the clock recovery circuit 1 can handle both NRZ signals and PAM4 signals.

[0033] As shown in FIG. 3, the phase comparison section 20 includes a first input differential amplifier 21, a second input differential amplifier 22, a first latch circuit 23, a second latch circuit 24, a third latch circuit 25, a fourth latch circuit 26, a first exclusive OR (EXOR) circuit 27, a second EXOR circuit 28, a first output differential amplifier 29, and a second output differential amplifier 30.

[0034] These latch circuits 23 to 26, EXOR circuits 27 and 28, and differential amplifiers 29 and 30 are integrated, for example, as a monolithic microwave integrated circuit (MMIC) using an InP HBT (Heterojunction Bipolar Transistor) process.

[0035] The first input differential amplifier 21 is a differential buffer amplifier having a differential input and a single-ended output, and is configured to amplify the data signal and output it to the first latch circuit 23 and the second latch circuit 24. When the data signal is a single-ended signal, only the positive-phase signal or the inverted-phase signal of the data signal is input to the first input differential amplifier 21. On the other hand, when the data signal is a differential signal, the positive-phase signal and the inverted-phase signal of the data signal are differentially input to the first input differential amplifier 21.

[0036] The second input differential amplifier 22 is a differential buffer amplifier having differential inputs and outputs, and amplifies a divided signal from a division unit 90 described later or an output signal (without division) from a VCO unit 80 described later, and outputs differential outputs to a first latch circuit 23 and a second latch circuit 24.

[0037] Hereinafter, the divided signal from the division unit 90 and the output signal from the VCO unit 80 are collectively referred to as a "clock signal". The clock signal at the time of locking of the clock recovery circuit 1 is a single clock or a half-rate clock of a differential clock synchronized with the data signal.

[0038] When the clock signal is a single-ended signal, only the positive-phase signal or the inverted-phase signal of the clock signal is input to the second input differential amplifier 22. On the other hand, when the clock signal is a differential signal, the positive-phase signal and the inverted-phase signal of the clock signal are differentially input to the second input differential amplifier 22.

[0039] The first latch circuit 23 is a D flip-flop that latches the data signal output from the first input differential amplifier 21 in synchronization with the positive-phase signal of the clock signal output from the second input differential amplifier 22.

[0040] The second latch circuit 24 is a D flip-flop that latches the data signal output from the first input differential amplifier 21 in synchronization with the inverted-phase signal of the clock signal output from the second input differential amplifier 22.

[0041] The third latch circuit 25 is a D flip-flop that latches the output of the first latch circuit 23 in synchronization with the inverted-phase signal of the clock signal output from the second input differential amplifier 22.

[0042] The fourth latch circuit 26 is a D flip-flop that latches the output of the second latch circuit 24 in synchronization with the positive-phase signal of the clock signal output from the second input differential amplifier 22.

[0043] The first EXOR circuit 27 is configured to output the exclusive OR of the outputs of the first latch circuit 23 and the second latch circuit 24.

[0044] The second EXOR circuit 28 is configured to output the exclusive OR of the outputs of the third latch circuit 25 and the fourth latch circuit 26.

[0045] The first output differential amplifier 29 is a high-speed CML (Current Mode Logic) differential buffer amplifier with a single-ended input and a differential output. It amplifies the output of the first EXOR circuit 27 and differentially outputs an error signal as shown by the solid line in FIG. 4. Here, the error signal is a differential signal having a pulse width with a duty ratio corresponding to the phase difference between the data signal and the clock signal. The differential output of the first output differential amplifier 29 has, for example, an H level of 0V and an L level of -0.5V.

[0046] The second output differential amplifier 30 is a high-speed CML differential buffer amplifier with a single-ended input and a differential output. It amplifies the output of the second EXOR circuit 28 and differentially outputs a reference signal as shown by the dashed line in FIG. 4. Here, the reference signal is a differential signal having a pulse width corresponding to the data signal. The differential output of the second output differential amplifier 30 has, for example, an H level of 0V and an L level of -0.5V.

[0047] Note that the phase comparison unit 20 differs from the configuration of the half-rate linear phase detector of the clock recovery circuit disclosed in Non-Patent Document 1 in that the outputs of the error signal and the reference signal are high-speed CML differential outputs.

[0048] Generally, the higher the operating speed of the phase detector, the lower the output amplitude in order to secure the bandwidth, and there is a problem that the phase detection voltage sensitivity (phase sensitivity) decreases. The phase comparison unit 20 outputs two differential signals, namely, the positive-phase error signal (hereinafter also referred to as "positive-phase error signal EP") of the error signal and the negative-phase error signal (hereinafter also referred to as "negative-phase error signal EN") of the error signal, and the positive-phase reference signal (hereinafter also referred to as "positive-phase reference signal RP") of the reference signal and the negative-phase reference signal (hereinafter also referred to as "negative-phase reference signal RN") of the reference signal, so as to increase the phase sensitivity.

[0049] Hereinafter, the operation of the phase comparison unit 20 will be described. Here, it is assumed that the data signal input to the phase comparison unit 20 is a toggling pattern obtained by SSC modulating a 1-bit serial data in which "0" and "1" are alternately repeated. Also, it is assumed that the clock signal input to the phase comparison unit 20 is an SSC-modulated clock having the same period as the above-described toggling pattern.

[0050] At this time, while shifting the phase of the clock signal with respect to the data signal, when the DC average voltages of the positive-phase error signal EP and the positive-phase reference signal RP are respectively measured, as shown in FIG. 5, a characteristic in which the voltage changes in units of 1UI (Unit Interval) according to the phase difference between the data signal and the clock signal is obtained. The same characteristic is obtained for the negative-phase error signal EN and the negative-phase reference signal RN.

[0051] The phase comparison unit 20 is preferably operated at an operating point corresponding to the vicinity of the center of a portion where the slopes of the characteristics of the DC average voltages of the positive-phase error signal EP and the negative-phase error signal EN are gentle and the linearity is good (for example, the region surrounded by the broken-line ellipse in FIG. 5).

[0052] As shown in FIG. 6, the differential amplifier unit 40 includes a third differential amplifier 41, an ADC 42, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

[0053] The third differential amplifier 41 is an amplifier with differential input and single-ended output, and is a high-speed operational amplifier that differentially amplifies the signals input to the inverting input terminal (-) and the non-inverting input terminal (+) and outputs them to the amplification unit 50.

[0054] The output terminal of the third differential amplifier 41 is connected to the inverting input terminal of the third differential amplifier 41 via the first resistor R1 and is also connected to the input side of the amplification unit 50. The non-inverting input terminal of the third differential amplifier 41 is grounded via the second resistor R2.

[0055] The in-phase reference signal RN is input to the non-inverting input terminal of the third differential amplifier 41 via the third resistor R3. The positive-phase error signal EP is input to the non-inverting input terminal of the third differential amplifier 41 via the fourth resistor R4. The in-phase error signal EN is input to the inverting input terminal of the third differential amplifier 41 via the fifth resistor R5. The positive-phase reference signal RP is input to the inverting input terminal of the third differential amplifier 41 via the sixth resistor R6.

[0056] Here, the resistance values of the first resistor R1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5 are all equal. If this resistance value is R, the resistance values of the third resistor R3 and the sixth resistor R6 are 2×R, which is twice that of R.

[0057] That is, the output voltage V of the differential amplification unit 40 is obtained by subtracting half of the differential amplitude represented by the difference between the voltage V_RP of the positive-phase reference signal RP and the voltage V_RN of the in-phase reference signal RN from the differential amplitude represented by the difference between the voltage V_EP of the positive-phase error signal EP and the voltage V_EN of the in-phase error signal EN, as shown in the following formula (1).

[0058] V = (V_EP - V_EN) - (V_RP - V_RN) × 0.5 (1)

[0059] As shown in formula (1), by differentially amplifying the positive-phase error signal EP and the in-phase error signal EN and the positive-phase reference signal RP and the in-phase reference signal RN respectively by the differential amplification unit 40 and performing voltage calculation, the phase sensitivity of the phase comparison unit 20 can be theoretically doubled.

[0060] Also, through the operation of Expression (1) in the differential amplification unit 40, the clock recovery circuit 1 can reproduce the half-rate clock of the data signal while avoiding the dead zone that occurs near the inflection points of the positive-phase error signal EP and the negative-phase error signal EN in the phase comparison unit 20. Furthermore, it can be confirmed by, for example, circuit simulation that the noise generated by the level transition of the data signal can be reduced through the operation of Expression (1) in the differential amplification unit 40.

[0061] The ADC 42 converts the output signal of the third differential amplifier 41 from an analog signal into digital data and outputs the digital data of the output signal of the third differential amplifier 41 to the control unit 110. The control unit 110 obtains information on the operating point voltage of the phase comparison unit 20 from the digital data of the output signal of the differential amplification unit 40 captured by the ADC 42, and determines whether the phase comparison unit 20 is operating at an optimal operating point. Thus, for example, the reference voltage Vref set in the loop filter unit 60 described later can be optimized.

[0062] As shown in FIG. 7, the amplification unit 50 includes a fourth differential amplifier 51, a seventh resistor R7, and an eighth resistor R8.

[0063] The fourth differential amplifier 51 is a high-speed operational amplifier having differential inputs and a single-ended output. The non-inverting input terminal (+) of the fourth differential amplifier 51 is grounded. The fourth differential amplifier 51 amplifies the signal input to the non-inverting input terminal (-) and outputs it to the loop filter unit 60.

[0064] The output terminal of the fourth differential amplifier 51 is connected to the inverting input terminal of the fourth differential amplifier 51 via the seventh resistor R7 and is also connected to the input side of the loop filter unit 60. The output signal of the third differential amplifier 41 is input to the non-inverting input terminal of the fourth differential amplifier 51 via the eighth resistor R8.

[0065] The amplifier section 50 further compensates for the phase sensitivity of the phase comparison section 20 by amplifying the output of the differential amplifier section 40. As a result, the loop gain for obtaining the desired loop bandwidth and SSC modulation tolerance of the clock recovery circuit 1 is improved. If the clock recovery circuit 1 does not include the amplifier section 50, it is difficult to ensure a wide loop bandwidth and SSC modulation tolerance. The gain of the amplifier section 50 is determined by the resistance values of the seventh resistor R7 and the eighth resistor R8.

[0066] Although FIG. 7 shows an example in which the amplifier section 50 constitutes an inverting amplifier, the present invention is not limited thereto. Whether these amplifiers perform inverting amplification or non-inverting amplification, including the differential amplifiers in the subsequent loop filter section 60 and pre-tuning section 70, may be appropriately set according to the voltage control polarity of the VCO section 80. With the same idea, the polarity of the differential signal input to the front-stage differential amplifier section 40 may be appropriately switched.

[0067] The loop filter section 60 serves as both a low-pass filter that smoothes the output of the amplifier section 50 and an error amplifier that error-amplifies the smoothed output of the amplifier section 50 with reference to a predetermined reference voltage Vref.

[0068] As shown in FIG. 8, the loop filter section 60 includes an error amplifier 61, a DAC 62, an ADC 63, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a first capacitor C1, and a second capacitor C2.

[0069] The error amplifier 61 is an amplifier having differential inputs and a single-ended output, and is, for example, a low-noise operational amplifier commonly used in a PLL (Phase Locked Loop). The error amplifier 61 error-amplifies the signals input to the inverting input terminal (-) and the non-inverting input terminal (+) respectively and outputs them to the pre-tuning section 70.

[0070] The output signal of the amplifier section 50 is input to the inverting input terminal of the error amplifier 61 via a low-pass filter composed of the ninth resistor R9 and the first capacitor C1 and the eleventh resistor R11.

[0071] The output terminal of the error amplifier 61 is connected to the inverting input terminal of the error amplifier 61 via the second capacitor C2 and the tenth resistor R10, and is also connected to the input side of the pre-tuning unit 70.

[0072] The DAC 62 is configured to convert a digital value of a predetermined reference voltage Vref into an analog voltage signal and input it to the non-inverting input terminal of the error amplifier 61. The reference voltage Vref is theoretically about half of the voltage change range of the voltage obtained by multiplying the gain of the amplification unit 50 by the formula (1). For example, the value of the reference voltage Vref determined from the characteristics of the error signal and the positive-phase signal of the reference signal is obtained by subtracting half (about -0.125V) of the DC average voltage of the corresponding positive-phase reference signal RP from the voltage value (about -0.25V) near the center of the characteristics of the DC average voltage of the positive-phase error signal EP (see FIG. 5), and then multiplying by the gain of the amplification unit 50. That is, the reference voltage Vref plays a role in determining the operating point at the phase comparison unit 20 at the time of locking. Further, the output signal of the amplification unit 50 is error-amplified by the error amplifier 61 with the reference voltage Vref as a reference, and the clock recovery circuit 1 locks.

[0073] Actually, since the differential signal of the error signal and the reference signal is input to the differential amplification unit 40, the offset voltages of the positive-phase error signal EP and the positive-phase reference signal RP, and the offset voltages of the negative-phase error signal EN and the negative-phase reference signal RN are canceled out by the differential amplification in the differential amplification unit 40, and the theoretical reference voltage Vref becomes 0V.

[0074] In particular, since the frequency offset of the SSC modulation of the PCI Express standard is as large as about 5000 ppm, if an appropriate reference voltage Vref is not set to optimize the operating point of the phase comparison unit 20, the phase comparison unit 20 will deviate from the phase detection range (the area surrounded by the broken-line ellipse in FIG. 5) where it operates linearly. In this case, the clock recovery circuit 1 cannot follow the frequency offset of the data signal, and the spectrum of the reproduced half-rate clock is distorted and phase jumps occur.

[0075] Actually, when the clock recovery circuit 1 locks, it is desirable to perform optimization adjustment of the reference voltage Vref so that synchronization between the half-rate clock reproduced by the clock recovery circuit 1 and the data signal can be achieved in a desired loop bandwidth. Whether synchronization between the half-rate clock and the data signal is achieved in the desired loop bandwidth can be confirmed, for example, by whether the frequency measured by the frequency counter unit 100 described later is within the desired data rate range.

[0076] The ADC 63 converts the output signal of the error amplifier 61 from an analog signal into digital data and outputs the digital data of the output signal of the error amplifier 61 to the control unit 110. Since the output signal of the error amplifier 61 is equivalent to the output signal of the phase detector by the PLL, the control unit 110 can obtain modulation profile waveform information of SSC modulation such as the waveform shape of the triangular wave from the digital data of the output signal of the loop filter unit 60 captured by the ADC 63 and can display the modulation profile waveform information on a display device (not shown) as necessary. The modulation profile waveform information includes, for example, information such as the amplitude, period, and slope of the waveform of the triangular wave of SSC modulation.

[0077] For example, the control unit 110 may control the reference voltage Vref output from the DAC 62 based on the degree of coincidence between known information such as the frequency offset, period, and slope of the SSC modulation of the data signal input to the clock recovery circuit 1 and the modulation profile waveform information output from the ADC 63. Thereby, the operating point of the phase comparison unit 20 can be optimized.

[0078] The error amplifier 61 of the loop filter unit 60 configured in this way amplifies the error between the voltage of the output signal from the amplification unit 50 and the reference voltage Vref.

[0079] As an application example, since the reference voltage Vref determines the operating point of the phase comparator 20, it is also possible to operate the clock recovery circuit 1 as a simple variable delay element by changing the reference voltage Vref.

[0080] The loop bandwidth of the clock recovery circuit 1 can be set by the gain setting of the amplifier section 50, the ratio of the resistance values of the 11th resistor R11 and the 10th resistor R10 of the loop filter section 60, and the capacitance value of the second capacitor C2. The loop bandwidth of the clock recovery circuit 1 is, for example, about several MHz to a dozen or so MHz. The resistance value of the 9th resistor R9 and the capacitance value of the first capacitor C1 may be set according to the desired loop characteristics in the high frequency range.

[0081] There is a trade-off relationship between the width of the loop bandwidth of the clock recovery circuit 1 and the smallness of the peaking in the frequency characteristics of the loop bandwidth. Further, an appropriate gain of the amplifier section 50 is determined by the relationship between the GB product (Gain Band width product) and the loop bandwidth. That is, when the gain of the amplifier section 50 is increased, the loop bandwidth becomes wider, but the bandwidth of the fourth differential amplifier 51 which is an operational amplifier becomes narrower due to the influence of the GB product. Therefore, the peaking of the loop bandwidth increases overall considering the balance between the loop bandwidth and the operational amplifier bandwidth. When the peaking becomes significant, the loop finally becomes unstable and the clock recovery circuit 1 cannot lock. Therefore, it is necessary to balance the loop bandwidth and the gain of the amplifier section 50. That is, the limit of the loop bandwidth is related to the GB product, and it is necessary to make the loop bandwidth narrower than the bandwidth of the fourth differential amplifier 51.

[0082] In the clock recovery circuit 1 for the error rate measurement device, it is necessary to widen the loop bandwidth within a range where peaking hardly occurs in the frequency characteristics of the loop bandwidth in consideration of the jitter tolerance characteristics. Fig. 9 shows the jitter transfer characteristics of the clock recovery circuit 1 when the data rate of the data signal is 5 Gbit / s and the loop bandwidth is about 9 MHz. Peaking of about 0.5 dB is observed from 1 MHz to 4 MHz, but it can be said that the influence of the jitter increase of the clock signal on the error rate measurement is not significant with this level of peaking.

[0083] In the clock recovery circuit 1 of this embodiment, since the amplification unit 50 is arranged in front of the loop filter unit 60, the influence of noise increase associated with the amplification by the amplification unit 50 is mitigated by the low-pass filter composed of the ninth resistor R9 and the first capacitor C1 of the loop filter unit 60.

[0084] FIG. 10(a) shows the spectrum of the half-rate clock reproduced by the clock recovery circuit 1 of this embodiment in which the amplification unit 50 is arranged in front of the loop filter unit 60. On the other hand, FIG. 10(b) shows the spectrum of the half-rate clock reproduced by the configuration of the comparative example in which the amplification unit 50 is arranged behind the loop filter unit 60. In both cases, the input data signal has a data rate of 5 Gbit / s, an SSC modulation frequency of 33 kHz, and a frequency offset of 5300 ppm.

[0085] From the spectra of FIGS. 10(a) and (b), it can be seen that by arranging the amplification unit 50 in front of the loop filter unit 60, the C / N ratio (Carrier to Noise ratio) can be improved as compared with the case where the amplification unit 50 is arranged behind the loop filter unit 60.

[0086] Some conventional clock recovery circuits employ a method in which a PLL equipped with a PFD and a charge pump is used in combination with a reference clock, locked to the reference clock in advance, and then the loop is switched after bringing the oscillation frequency of the VCO close to the target frequency.

[0087] On the other hand, since the clock recovery circuit 1 of this embodiment does not employ the above method, it is provided with a pre-tuning unit 70 that brings the control voltage of the VCO unit 80 close to a value that realizes the target frequency in advance.

[0088] The pre-tuning unit 70 is configured to output to the VCO unit 80 a control voltage obtained by adding a pre-determined pre-tuning voltage Vpt to the output of the loop filter unit 60.

[0089] As shown in FIG. 11, the pre-tuning unit 70 includes a fifth differential amplifier 71, a DAC 72, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14.

[0090] The fifth differential amplifier 71 is an amplifier having a differential input and a single-ended output, and is, for example, a low-noise operational amplifier commonly used in a PLL. The fifth differential amplifier 71 differentially amplifies the signals input to the inverting input terminal (-) and the non-inverting input terminal (+) respectively and outputs them to the VCO unit 80.

[0091] The output signal of the loop filter unit 60 is input to the inverting input terminal of the fifth differential amplifier 71 via the thirteenth resistor R13.

[0092] The output terminal of the fifth differential amplifier 71 is connected to the inverting input terminal of the fifth differential amplifier 71 via the twelfth resistor R12 and is also connected to the input side of the VCO unit 80 via the fourteenth resistor R14.

[0093] The DAC 72 converts the digital value of a predetermined pre-tuning voltage Vpt into an analog voltage signal and inputs it to the non-inverting input terminal of the fifth differential amplifier 71.

[0094] The fifth differential amplifier 71 sets the twelfth resistor R12 and the thirteenth resistor R13 to the same resistance value to minimize noise, serves as an inverting buffer with a gain of -1, and adds the pre-tuning voltage Vpt from the DAC 72 with an offset. The fourteenth resistor R14 is inserted to prevent oscillation of the fifth differential amplifier 71.

[0095] When the output voltage of the pre-tuning unit 70 is input as a control voltage, the VCO unit 80 outputs an output signal having a frequency corresponding to this control voltage to the subsequent frequency division unit 90. The VCO unit 80 may include, for example, a plurality of VCOs (not shown) having different oscillation frequencies.

[0096] When using a plurality of VCOs, since the frequency control terminals of the VCOs are usually of high impedance, the configuration may be such that the frequency control terminals are connected to the plurality of VCOs simultaneously or switched and selected by an analog switch or the like. Also, when the capacitance added to the frequency control terminals of the VCOs due to simultaneous connection of a plurality of them cannot be ignored in terms of the performance of the loop bandwidth, there is also a method of branching the circuit from the pre-tuning unit 70 or the loop filter unit 60, paralleling them, and connecting them to each VCO.

[0097] The frequency division unit 90 is composed of, for example, a programmable frequency divider and is configured to output a frequency-divided signal obtained by dividing the frequency of the output signal of the VCO unit 80. The frequency-divided signal is a single-ended signal or a differential signal. The frequency-divided signal at the time of lock of the clock recovery circuit 1 becomes a half-rate clock of a single clock or a differential clock synchronized with the data signal.

[0098] For example, the VCO unit 80 has one VCO with an oscillation frequency in the 5 GHz band for Gen1 / 2 of the PCI Express standard with a data rate of 2.5 / 5 Gbit / s. That is, the clock recovery circuit 1 generates a half-rate clock in a desired frequency range by dividing the output signal from the VCO with an oscillation frequency in the 5 GHz band by 2 or 4 by the frequency division unit 90 and outputting it.

[0099] Also, the VCO unit 80 has one VCO with an oscillation frequency in the 16 GHz band for Gen3 / 4 / 5 / 6 of the PCI Express standard with a data rate of 8 / 16 / 32 Gbit / s and 32 Gbaud. That is, the clock recovery circuit 1 outputs the output signal from the VCO with an oscillation frequency in the 16 GHz band as it is (without frequency division), or generates a half-rate clock in a desired frequency range by dividing the output signal from the VCO with an oscillation frequency in the 16 GHz band by 2 or 4 by the frequency division unit 90 and outputting it.

[0100] That is, in order to support all of Gen1 / 2 / 3 / 4 / 5 / 6 of the PCI Express standard, the VCO unit 80 may be provided with, for example, two types of VCOs or a VCO capable of oscillating two types of frequencies. Also, for the selection of whether to divide the output signal from the VCO or not, and for the selection of two types of VCOs, an externally provided selector or the like may be used. Note that there are also products on the market in which a divider is integrated in the VCO.

[0101] However, since the loop gain also changes as the division ratio of the division unit 90 changes as described above, it is desirable to switch the gain of the amplification unit 50 and the constants of the loop filter unit 60 to optimize the loop bandwidth characteristics at each desired data rate.

[0102] For example, the loop bandwidth characteristics can be changed by selectively switching the gain of the amplification unit 50 and the constants of the loop filter unit 60 with a switching unit such as an analog switch.

[0103] FIG. 12(a) shows an example in which the amplification unit 50 has two switching units 52 and 53. The switching unit 52 is configured to selectively switch two resistors R7a and R7b having different resistance values instead of one seventh resistor R7. The switching unit 53 is configured to selectively switch two resistors R8a and R8b having different resistance values instead of one eighth resistor R8.

[0104] FIG. 12(b) shows an example in which the loop filter unit 60 has four switching units 64, 65, 66, and 67. The switching unit 64 is configured to selectively switch two resistors R11a and R11b having different resistance values instead of one eleventh resistor R11. The switching unit 65 is configured to selectively switch two sets of a resistor R10a and a capacitor C2a and a resistor R10b and a capacitor C2b having different resistance values and capacitance values instead of one set of a tenth resistor R10 and a second capacitor C2.

[0105] The switching unit 66 is configured to selectively switch between two resistors R9a and R9b having different resistance values instead of one ninth resistor R9. The switching unit 67 is configured to selectively switch between capacitors C1a and C1b having different capacitance values instead of one first capacitor C1.

[0106] Note that the number of resistors or capacitors that each switching unit can switch is not limited to two as described above, and may be any number of three or more. Also, the loop filter unit 60 may have only the switching units 64 and 65 among the above four switching units.

[0107] The control unit 110 has, for example, a correction table that defines the optimum setting values of the gain of the amplifier unit 50 and the constants of the loop filter unit 60 for each data rate of the data signal, and can quickly switch each switching unit according to the desired data rate.

[0108] The frequency counter unit 100 is configured to count the frequency of the clock signal.

[0109] The pre-tuning voltage Vpt is set by the control unit 110 so that the frequency measured by the frequency counter unit 100 is slightly higher than half the frequency of the data signal when the clock recovery circuit 1 is unlocked. For example, the pre-tuning voltage Vpt is set to a value such that the control voltage output from the pre-tuning unit 70 becomes a voltage corresponding to the desired free-running frequency of the VCO unit 80 when the clock recovery circuit 1 is unlocked. Note that the upper limit of the frequency at which the clock recovery circuit 1 can lock is the value obtained by dividing the free-running frequency of the VCO unit 80 at the time of unlocking by the division ratio of the frequency division unit 90.

[0110] When there is a large difference between the frequency corresponding to the data rate of the data signal and the frequency measured by the frequency counter unit 100 at the time of unlock, a pseudo-lock may occur in which the clock recovery circuit 1 locks to a frequency slightly different from the target frequency. The pseudo-lock is considered to occur due to the frequency components of the pattern of the data signal. The optimum values of the reference voltage Vref and the pre-tuning voltage Vpt that can avoid the pseudo-lock may differ depending on the presence or absence of SSC modulation of the data signal. Also, if the target frequency and the free-running frequency at the time of unlock are too far apart, the lock time of the clock recovery circuit 1 will become long, so the free-running frequency needs to be determined in consideration of the desired lock time.

[0111] Conversely, when the difference between the frequency corresponding to the data rate of the data signal and the frequency measured by the frequency counter unit 100 at the time of unlock is small, for example, when a part of the frequency transition due to SSC modulation exceeds the free-running frequency at which unlock occurs, unlock occurs at a part of the transition frequency, and there may be adverse effects such as CW-like spurious signals being superimposed near the free-running frequency of the spectrum of the half-rate clock. Therefore, the frequency corresponding to the data rate of the data signal and the frequency measured by the frequency counter unit 100 at the time of unlock need to be separated to a certain extent so as not to cause adverse effects as much as possible in consideration of the lock time.

[0112] For this reason, the control unit 110 may have a table that defines the reference voltage Vref and the pre-tuning voltage Vpt for each data rate of the data signal, whether the data signal is SSC-modulated or not. Note that the reference voltage Vref and the pre-tuning voltage Vpt are constant values for each data rate, regardless of the locked or unlocked state of the clock recovery circuit 1.

[0113] In the PCI Express specification, the data rate changes sequentially from Gen1 towards the desired Gen number, and the maximum allowable time during the data rate change is defined. Therefore, it is necessary to change the settings of each part of the clock recovery circuit 1 within the maximum allowable time and then lock the clock recovery circuit 1. After configuring a table with predefined setting values, by the control unit 110 controlling the pre-tune voltage Vpt and the reference voltage Vref, the lock time of the clock recovery circuit 1 can be shortened, and the change of the data rate from Gen1 to the desired Gen number can be smoothly implemented.

[0114] The locked state of the clock recovery circuit 1, that is, which state of lock, unlock, or pseudo-lock has occurred, can be reliably determined mainly by whether the frequency measured by the frequency counter unit 100 is within the desired data rate range. When it is determined to be in a pseudo-lock state, for example, there is also a method of controlling the reference voltage Vref and the pre-tune voltage Vpt to once enter the unlock state and then return to the optimal setting to prompt correct locking. Or there is also a method of turning off and then turning on the output of the limiting amplifier unit 10 where the data signal is input.

[0115] Also, as described above, the information on the operating point voltage of the phase comparison unit 20 obtained from the ADC42 of the differential amplifier unit 40 and the modulation profile waveform information obtained from the ADC63 of the loop filter unit 60 can also be used as reference information for the locked state of the clock recovery circuit 1.

[0116] The control unit 110 is composed of a microcomputer or a personal computer including, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), etc., and is configured to control the operations of the above-mentioned respective parts constituting the clock recovery circuit 1.

[0117] As described above, in the clock recovery circuit 1 according to the present embodiment, the phase comparator 20 that operates at high speed differentially outputs an error signal and a reference signal, and the subsequent differential amplifier 40 subtracts half of the differential amplitude of the reference signal from the differential amplitude of the error signal. Further, the amplifier 50 amplifies the output of the differential amplifier 40 at the front stage of the loop filter 60, and the loop filter 60 error-amplifies while smoothing the output of the amplifier 50, thereby suppressing an increase in noise associated with the amplification of the amplifier 50 while maximizing the loop gain.

[0118] With these configurations, the clock recovery circuit 1 according to the present embodiment can reproduce a half-rate clock by ensuring a sufficient loop gain, thereby ensuring a wide loop bandwidth and tolerance to frequency deviation due to SSC modulation. For example, the clock recovery circuit 1 according to the present embodiment can handle a maximum frequency deviation amount of 5300 ppm of SSC modulation in the PCI Express standard.

[0119] Also, in the clock recovery circuit 1 according to the present embodiment, the pre-tune unit 70 outputs a control voltage obtained by adding the pre-tune voltage Vpt to the output of the loop filter 60 to the VCO unit 80. With this configuration, the clock recovery circuit 1 according to the present embodiment can eliminate the need for a reference clock, PFD, charge pump, etc., and can ensure fast and stable lock performance. In particular, the clock recovery circuit 1 according to the present embodiment is characterized in that it can reproduce a half-rate clock with a simple circuit configuration by not including a charge pump.

[0120] Also, when the clock recovery circuit 1 according to the present embodiment divides the output signal from a VCO with an oscillation frequency in the 5 GHz band by 2 or 4 by the frequency divider 90, or outputs the output signal (without frequency division) from a VCO with an oscillation frequency in the 16 GHz band as it is, or divides it by 2 or 4 by the frequency divider 90 and outputs it, the number of VCOs included in the VCO unit 80 can be reduced, thereby reducing costs and improving efficiency.

[0121] That is, in order to support all of Gen1 / 2 / 3 / 4 / 5 / 6 of the PCI Express standard, the VCO section 80 may be provided with, for example, two types of VCOs or a VCO that can oscillate at two types of frequencies. Also, for the selection of whether to divide the output signal from the VCO or not, and for the selection of two types of VCOs, an externally provided selector or the like may be used.

[0122] Also, in the differential amplification section 40 of the clock recovery circuit 1 according to the present embodiment, the resistance values of the third resistor R3 and the sixth resistor R6 are twice the resistance values of the first resistor R1, the second resistor R2, the fourth resistor R4, and the fifth resistor R5.

[0123] With this configuration, the clock recovery circuit 1 according to the present embodiment can perform a differential voltage operation for avoiding the dead zone in the phase comparison section 20 by the differential amplification section 40 having one high-speed operational amplifier, and can improve the circuit efficiency.

[0124] Also, since the clock recovery circuit 1 according to the present embodiment includes a frequency counter section 100 that counts the frequency of the clock signal, it can output information for determining whether the lock state of the clock recovery circuit 1 is in a locked, unlocked, or pseudo-locked state.

[0125] Also, the clock recovery circuit 1 according to the present embodiment may include switching sections 52 and 53 that switch the gain of the amplification section 50, and switching sections 64 and 65 that switch the constants of the loop filter section 60.

[0126] With this configuration, the clock recovery circuit 1 according to the present embodiment can change the loop band characteristics by selectively switching the loop gain and the loop filter constants.

[0127] Also, since the VCO section 80 of the clock recovery circuit 1 according to the present embodiment includes a plurality of VCOs, and the frequency division section 90 divides the output signal of the VCO section 80 at a plurality of frequency division ratios, it can support data signals at a plurality of data rates.

[0128] (Second Embodiment) Next, an error rate measurement apparatus and an error rate measurement method according to a second embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. Also, the description of the same operations as those in the first embodiment will be omitted as appropriate.

[0129] As shown in FIG. 13, an error rate measurement apparatus 150 according to the second embodiment measures the error rate of a data signal transmitted from a device under test (DUT) 200, and includes a data storage unit 151, a signal transmission unit 152, a signal reception unit 153, a synchronization detection unit 154, an error rate calculation unit 155, a display unit 156, and a control unit 157.

[0130] The DUT 200 outputs a data signal that is SSC-modulated at a predetermined SSC modulation frequency or a normal data signal that is not SSC-modulated. Examples of the standards corresponding to the DUT 200 include PCI Express Gen1 to 6, USB3.1 to 4, DP1.4 to 2, and the like. Hereinafter, mainly, the case where the data signal is an SSC-modulated signal will be described.

[0131] The data storage unit 151 is configured by a memory such as a RAM, and stores in advance reference bit string data. Here, the bit string data is data corresponding to K levels from a 0 level to a K−1 level that a PAM signal composed of a multi-value K (K is an integer of 2 or more) of 2 values or more can take. For example, the bit string data of a PAM4 signal, which is a 4-value PAM signal, consists of combinations of bits of "00", "01", "10", and "11".

[0132] The signal transmission unit 152 SSC-modulates the bit string data read from the data storage unit 151 at a predetermined SSC modulation frequency to generate a test signal, and transmits the generated test signal to the DUT 200. At this time, the DUT 200 receives the test signal transmitted from the signal transmission unit 152, and transmits the received test signal to the signal reception unit 153 as a data signal. That is, the DUT 200 transmits a PAM signal of K value SSC-modulated at a predetermined SSC modulation frequency as a data signal.

[0133] The signal reception unit 153 receives the data signal SSC-modulated at a predetermined SSC modulation frequency transmitted from the DUT 200, and outputs the bit string data of the received data signal to the synchronous detection unit 154. It has the clock recovery circuit 1 of the first embodiment and the bit string data extraction unit 158.

[0134] The clock recovery circuit 1 regenerates a half-rate clock from the data signal transmitted from the DUT 200.

[0135] The bit string data extraction unit 158 extracts the bit string data constituting the data signal transmitted from the DUT 200 at the rising and falling timings of the half-rate clock regenerated from the data signal by the clock recovery circuit 1. For example, the bit string data extraction unit 158 has at least one 0 / 1 discriminator, and by inputting the half-rate clock from the clock recovery circuit 1 to each 0 / 1 discriminator, the level of the data signal transmitted from the DUT 200 can be determined at the rising and falling timings of the half-rate clock. Note that the half-rate clock output from the clock recovery circuit 1 may be used as an operation clock not only in the bit string data extraction unit 158 but also in each part constituting the error rate measurement device 150.

[0136] The synchronization detection unit 154 is configured to synchronize the bit sequence data read from the data storage unit 151 with the bit sequence data of the data signal extracted by the bit sequence data extraction unit 158. Then, the synchronization detection unit 154 outputs the bit sequence data of the data signal for which synchronization has been achieved to the error rate calculation unit 155.

[0137] The error rate calculation unit 155 sequentially compares the bit sequence data constituting the data signal output from the synchronization detection unit 154 with the bit sequence data stored in the data storage unit 151 to detect the error bits of the bit sequence data constituting the data signal and calculate the BER of the bit sequence data constituting the data signal.

[0138] The display unit 156 is composed of a display device such as an LCD (Liquid Crystal Display) or a CRT (Cathode Ray Tube), and displays various display contents such as the BER of the bit sequence data calculated by the error rate calculation unit 155 according to the display control signal output from the control unit 157.

[0139] The control unit 157 is configured in the same manner as the control unit 110 in the first embodiment, and controls the operations of the above-described units constituting the error rate measurement device 150. Note that the control unit 157 in the present embodiment may also serve as the control unit 110 in the first embodiment.

[0140] Hereinafter, an example of the processing of the error rate measurement method using the error rate measurement device 150 of the present embodiment will be described with reference to the flowchart of FIG. 14. Note that descriptions overlapping with the description of the configuration of the error rate measurement device 150 described above will be omitted as appropriate.

[0141] First, the signal transmission unit 152 SSC-modulates the bit sequence data read from the data storage unit 151 at a predetermined SSC modulation frequency to generate a test signal, and transmits the generated test signal to the DUT 200 (step S1).

[0142] Next, the clock recovery circuit 1 receives the data signal SSC-modulated at a predetermined SSC modulation frequency from the DUT 200 and reproduces a half-rate clock (signal reception step S2).

[0143] Next, the bit string data extraction unit 158 extracts the bit string data constituting the data signal at the rising and falling timings of the half-rate clock reproduced from the data signal by the clock recovery circuit 1 (signal reception step S3).

[0144] Next, the error rate calculation unit 155 calculates the BER of the bit string data constituting the data signal extracted in step S3 (error rate calculation step S4).

[0145] As described above, the error rate measurement device 150 according to the present embodiment can receive the SSC-modulated data signal transmitted from the DUT 200 and reproduce a half-rate clock from the data signal using the clock recovery circuit 1 of the first embodiment. Further, the error rate measurement device 150 according to the present embodiment can extract the bit string data constituting the data signal at the rising and falling timings of the reproduced half-rate clock and measure the BER of this bit string data.

Explanation of Reference Numerals

[0146] 1 Clock recovery circuit 20 Phase comparison unit 23 First latch circuit 24 Second latch circuit 25 Third latch circuit 26 Fourth latch circuit 27 First EXOR circuit (first exclusive OR circuit) 28 Second EXOR circuit (second exclusive OR circuit) 29 First output differential amplifier (first differential amplifier) 30 Second output differential amplifier (second differential amplifier) 40 Differential amplification unit 41 Third differential amplifier 50 Amplification unit 52, 53, 64 - 67 Switching Unit 60 Loop Filter Unit 70 Pre - tuning Unit 80 VCO Unit (Voltage - Controlled Oscillator Unit) 90 Frequency Division Unit 100 Frequency Counter Unit 150 Error Rate Measurement Device 151 Data Storage Unit 152 Signal Transmission Unit 153 Signal Reception Unit 154 Synchronization Detection Unit 155 Error Rate Calculation Unit 158 Bit - string Data Extraction Unit 200 DUT R1 First Resistor R2 Second Resistor R3 Third Resistor R4 Fourth Resistor R5 Fifth Resistor R6 Sixth Resistor

Claims

1. A clock recovery circuit (1) for reproducing a half-rate clock having a frequency that is half the frequency of a data signal SSC-modulated at a predetermined SSC modulation frequency, comprising: A voltage-controlled oscillator (80) that outputs an output signal having a frequency corresponding to an input control voltage; A phase comparison unit (20) that differentially outputs an error signal having a pulse width corresponding to a phase difference between a clock signal, which is an output signal of the voltage-controlled oscillator or a divided signal obtained by dividing the frequency of the output signal, and the data signal, and a reference signal having a pulse width corresponding to the data signal; A differential amplifier unit (40) that subtracts half of the differential amplitude of the reference signal differentially output by the phase comparison unit from the differential amplitude of the error signal differentially output by the phase comparison unit; An amplifier unit (50) that amplifies the output of the differential amplifier unit; A loop filter unit (60) that smoothes the output of the amplifier unit and error-amplifies the smoothed output of the amplifier unit with respect to a predetermined reference voltage; A pre-tuning unit (70) that adds a predetermined pre-tuning voltage to the output of the loop filter unit and outputs the obtained control voltage to the voltage-controlled oscillator, wherein the phase comparison unit includes: A first latch circuit (23) that latches the data signal in synchronization with the positive-phase signal of the clock signal; A second latch circuit (24) that latches the data signal in synchronization with the negative-phase signal of the clock signal; A third latch circuit (25) that latches the output of the first latch circuit in synchronization with the negative-phase signal of the clock signal; A fourth latch circuit (26) that latches the output of the second latch circuit in synchronization with the positive-phase signal of the clock signal; A first exclusive OR circuit (27) that outputs the exclusive OR of the output of the first latch circuit and the output of the second latch circuit; A second exclusive OR circuit (28) that outputs the exclusive OR of the output of the third latch circuit and the output of the fourth latch circuit; A first differential amplifier (29) that amplifies the output of the first exclusive OR circuit and differentially outputs the error signal; A second differential amplifier (30) that amplifies the output of the second exclusive OR circuit and differentially outputs the reference signal, and the half-rate clock is the clock signal when the clock recovery circuit is locked. A clock recovery circuit characterized by this.

2. The differential amplifier unit has a third differential amplifier (41). The output terminal of the third differential amplifier is connected to the inverting input terminal of the third differential amplifier via a first resistor (R1) and is also connected to the input side of the amplification unit. The non-inverting input terminal of the third differential amplifier is grounded via a second resistor (R2). The inverted signal of the reference signal is input to the non-inverting input terminal via a third resistor (R3). The non-inverting signal of the error signal is input to the non-inverting input terminal via a fourth resistor (R4). The inverted signal of the error signal is input to the inverting input terminal via a fifth resistor (R5). The non-inverted signal of the reference signal is input to the inverting input terminal via a sixth resistor (R6). The resistance values of the first resistor, the second resistor, the fourth resistor, and the fifth resistor are all equal. The clock recovery circuit according to claim 1, wherein the resistance values of the third resistor and the sixth resistor are twice the resistance values of the first resistor, the second resistor, the fourth resistor, and the fifth resistor.

3. The clock recovery circuit according to claim 1 or claim 2, further comprising a frequency counter unit (100) that counts the frequency of the clock signal.

4. The clock recovery circuit according to claim 1 or claim 2, further comprising a switching unit (52, 53, 64 to 67) that switches the gain of the amplification unit and the constants of the loop filter unit.

5. An error rate measurement device (150) comprising a signal reception unit (153) that receives a data signal SSC-modulated at a predetermined SSC modulation frequency, and an error rate calculation unit (155) that calculates the bit error rate of the bit string data constituting the data signal received by the signal reception unit. The signal reception unit has the clock recovery circuit according to claim 1 or claim 2, and extracts the bit string data constituting the data signal at the rising and falling timings of the half-rate clock reproduced from the data signal by the clock recovery circuit. An error rate measurement device characterized by this.

6. An error rate measurement method including a signal reception step (S2, S3) of receiving a data signal SSC-modulated at a predetermined SSC modulation frequency, and an error rate calculation step (S4) of calculating the bit error rate of the bit string data constituting the data signal received in the signal reception step. ​ ​ The signal reception step extracts the bit string data constituting the data signal at the rising and falling timing of the half-rate clock reproduced from the data signal by the clock recovery circuit according to claim 1 or claim 2, and is an error rate measurement method characterized by this.

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