Substrate and mounting substrate

Abstract

To provide a substrate which can inhibit melted solder alloy from flowing from one major surface side and reaching the other major surface side through a through hole, and to provide a mounted substrate.SOLUTION: A substrate includes: a base material having a major surface; a conductor pattern disposed on the major surface and having a center pad part; and a first annular wall. The substrate is formed with a through hole which penetrates through the substrate in a thickness direction and is located at a position overlapping with the center pad part in a plan view. The first annular wall is disposed on the center pad part so as to enclose a periphery of the through hole in the plan view.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a substrate and a mounting substrate.

Background Art

[0002] For example, Japanese Patent Application Laid-Open No. 2016-18846 (Patent Document 1) describes a semiconductor package. The semiconductor package described in Patent Document 1 is a QFN (Quad Flat Non-leaded) package. From the back surface of the semiconductor package of Patent Document 1, a central electrode and a plurality of peripheral electrodes are exposed. The central electrode is at the center of the back surface. The peripheral electrodes are around the central electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The semiconductor package described in Patent Document 1 is mounted on a substrate. The substrate has, for example, a base material, a conductor pattern, and a solder resist. The base material has a first main surface and a second main surface that is the opposite surface of the first main surface. The conductor pattern is disposed on the first main surface and has a central pad, a plurality of peripheral pads, and wiring. The peripheral pads are around the central pad. The wiring connects the outer peripheral edge of the central pad and the peripheral pads. The solder resist is disposed on the first main surface so as to cover the conductor pattern. The solder resist is formed with a first opening that exposes the central pad and a plurality of second openings that expose the peripheral pads.

[0005] The semiconductor package described in Patent Document 1 is mounted on the substrate by joining the central electrode to the central pad with a solder alloy and joining the peripheral electrodes to the peripheral pads with a solder alloy.

[0006] For the bonding between the central electrode and the central pad and the bonding between the peripheral electrode and the peripheral pad, cream solder is used. Cream solder is a paste obtained by mixing flux, an organic solvent, and powder of a solder alloy. When the powder of the solder alloy in the cream solder is melted, the flux and the organic solvent volatilize, so that through-holes are formed in the base material at positions overlapping the central pad in plan view. However, the melted solder alloy may reach the second main surface side through the through-holes.

[0007] When the melted solder alloy solidifies on the second main surface side, the metal mask used when printing cream solder on the pad disposed on the second surface comes into contact with the solidified solder alloy, and the printing of the cream solder on the second main surface becomes unstable.

[0008] The present invention has been made in view of the problems of the prior art as described above. More specifically, the present invention provides a substrate and a mounting substrate capable of suppressing the melted solder alloy from reaching from one main surface side to the other main surface side through the through-holes.

Means for Solving the Problems

[0009] The substrate of the present invention includes a base material having a main surface, a conductor pattern disposed on the main surface and having a central pad portion, and a first annular wall. The substrate has through-holes that penetrate the substrate in the thickness direction and are located at positions overlapping the central pad portion in plan view. The first annular wall is disposed on the central pad portion so as to surround the periphery of the through-hole in plan view.

[0010] The above-described substrate may further include a solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening exposing the central pad portion. The first annular wall may be formed of the same material as the solder resist.

[0011] The above-described substrate may further include a second annular wall disposed on the first annular wall. The second annular wall may be formed of a material different from that of the first annular wall.

[0012] In the above-described substrate, the second annular wall may be formed of a resin ink colored in a color different from that of the solder resist.

[0013] In the above-described substrate, the conductor pattern may further have a peripheral pad portion around the central pad portion. The solder resist may further be formed with a second opening for exposing the peripheral pad portion. In the above-described substrate, the through hole may be a vent hole.

[0014] The mounting substrate of the present invention includes the above-described substrate, a semiconductor package having a back surface, and a solder alloy. The semiconductor package has, on the back surface, a central electrode facing the central pad portion and peripheral electrodes around the central electrode and facing the peripheral pad portions. The solder alloy joins the central electrode and a portion of the central pad portion outside the first annular wall in plan view, and also joins the peripheral electrodes and the peripheral pad portions.

[0015] In the above-described mounting substrate, the semiconductor package may be a QFN package.

Advantages of the Invention

[0016] According to the substrate and the mounting substrate of the present invention, it is possible to suppress the molten solder alloy from reaching from one main surface side to the other main surface side through the through hole.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0018] Details of embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and duplicate descriptions will not be repeated.

[0019] (First Embodiment) The substrate according to the first embodiment will be described. In the following, the substrate according to the first embodiment is referred to as the substrate 100.

[0020] <Configuration of Substrate 100> The configuration of the substrate 100 will be described below.

[0021] FIG. 1 is a plan view of the substrate 100. FIG. 2 is a cross-sectional view taken along II-II in FIG. 1. As shown in FIGS. 1 and 2, the substrate 100 has a base material 10, a conductor pattern 20, a solder resist 30, and a first annular wall 40.

[0022] The base material 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are end faces in the thickness direction of the base material 10. The second main surface 10b is the opposite surface of the first main surface 10a. The base material 10 is formed of an electrically insulating material. The base material 10 is formed of, for example, glass epoxy. However, the electrically insulating material used for the base material 10 is not limited thereto.

[0023] The conductor pattern 20 is disposed on the first main surface 10a. The conductor pattern 20 is formed of an electrically conductive material. The conductor pattern 20 is formed of, for example, copper. However, the electrically conductive material used for the conductor pattern 20 is not limited thereto.

[0024] The conductor pattern 20 has a central pad 21 and a plurality of peripheral pads 22. The central pad 21 is, for example, rectangular in plan view. More specifically, the central pad 21 is square in plan view. The peripheral pads 22 are disposed around the central pad 21. The peripheral pads 22 are, for example, rectangular in plan view. More specifically, the peripheral pads 22 are rectangular in plan view. The peripheral pads 22 are spaced apart from the outer peripheral edge (outer peripheral edge 21a) of the central pad 21. The short side of the peripheral pad 22 in plan view faces the outer peripheral edge 21a with a gap therebetween. A plurality of peripheral pads 22 facing one side of the outer peripheral edge 21a are arranged in a row along the direction of the one side.

[0025] A part of the plurality of peripheral pads 22 (referred to as peripheral pad 22a) is connected to the outer peripheral edge 21a by a wiring 23.

[0026] A through hole 100a is formed in the substrate 100. The through hole 100a penetrates the substrate 100 in the thickness direction. The through hole 100a is formed at a position overlapping the central pad 21 in plan view. The through hole 100a is, for example, circular in plan view.

[0027] The base material 10 has a through hole 10c formed therein. The through hole 10c penetrates the base material 10 in the thickness direction. On the inner wall surface of the through hole 10c, a conductor layer 24 is disposed. The conductor layer 24 is connected to the central pad 21. The conductor layer 24 is also disposed on the second main surface 10b around the through hole 10c. The conductor layer 24 is formed of an electrically conductive material (for example, copper). In this case, the hole surrounded by the conductor layer 24 becomes the through hole 100a. When the conductor layer 24 is not formed, the through hole 10c becomes the through hole 100a.

[0028] The solder resist 30 is disposed on the first main surface 10a so as to cover the conductor pattern 20. The solder resist 30 is also disposed on the second main surface 10b. The solder resist 30 covers a conductor pattern (not shown) disposed on the second main surface 10b. The solder resist 30 is formed of an electrically insulating material. The solder resist 30 is formed of, for example, an epoxy resin. However, the electrically insulating material used for the solder resist 30 is not limited to this. The solder resist 30 may be colored.

[0029] The solder resist 30 has a first opening 31 and a plurality of second openings 32 formed therein. The first opening 31 and the second openings 32 penetrate the solder resist 30 in the thickness direction. The central pad 21 is exposed from the first opening 31. The peripheral pads 22 are exposed from the second openings 32.

[0030] The first opening 31 is rectangular in plan view. More specifically, the first opening 31 is square in plan view. The first opening 31 is, for example, outside the outer peripheral edge 21a in plan view. The second openings 32 are rectangular in plan view. More specifically, the second openings 32 are rectangular in plan view.

[0031] The first annular wall 40 is disposed on the central pad 21. The first annular wall 40 surrounds the through hole 100a in a plan view. The first annular wall 40 is preferably annular. The inner peripheral edge of the first annular wall 40 may reach the edge of the through hole 100a or may be spaced apart from the edge of the through hole 100a. Let the width of the first annular wall 40 be width W1. The width W1 is the distance between the inner peripheral edge and the outer peripheral edge of the first annular wall 40. Let the width of the central pad 21 be width W2. The width W2 is preferably at least 6 times the width W1.

[0032] The first annular wall 40 is formed of, for example, the same material as the solder resist 30. The thickness of the first annular wall 40 is the same as, for example, the thickness of the solder resist 30. That is, the solder resist 30 and the first annular wall 40 are formed by, for example, the same process. The solder resist 30 and the first annular wall 40 are formed, for example, by attaching a dry film of the constituent material of the solder resist 30 onto the first main surface 10a and then developing and exposing the attached dry film for patterning. Note that instead of attaching the dry film, a liquid constituent material of the solder resist 30 may be applied.

[0033] <Configuration of the mounting substrate 200> The configuration of the mounting substrate 200 will be described below.

[0034] FIG. 3 is a cross-sectional view of the mounting substrate 200. As shown in FIG. 3, the mounting substrate 200 has a substrate 100 and a semiconductor package 300.

[0035] The semiconductor package 300 is, for example, a QFN package. However, the semiconductor package 300 is not limited thereto. The semiconductor package 300 may be, for example, an LGA (Lead Grid Array) package. The semiconductor package 300 has a lead frame 310, a semiconductor chip 320, bonding wires 330, and a sealing resin 340.

[0036] The lead frame 310 has a die pad portion 311 and a plurality of lead portions 312. The plurality of lead portions 312 are arranged around the die pad portion 311. The lead frame 310 is formed of an electrically conductive material. The lead frame 310 is formed of, for example, a copper alloy. However, the electrically conductive material used for the lead frame 310 is not limited to this.

[0037] The semiconductor chip 320 has a front surface 320a and a back surface 320b. The front surface 320a and the back surface 320b are end faces in the thickness direction of the semiconductor chip 320. The back surface 320b is the opposite surface of the front surface 320a. The semiconductor chip 320 is arranged on the die pad portion 311. More specifically, the back surface 320b is connected to the die pad portion 311 by a solder alloy (not shown), a conductive adhesive (not shown), etc. Although not shown, bonding pads are formed on the front surface 320a.

[0038] The bonding wire 330 is connected to the bonding pad of the semiconductor chip 320 at one end and is connected to the lead portion 312 at the other end. The bonding wire 330 is formed of an electrically conductive material such as gold or copper. The encapsulating resin 340 encapsulates the lead frame 310, the semiconductor chip 320, and the bonding wire 330. The encapsulating resin 340 is formed of, for example, an epoxy resin. However, the resin material used for the encapsulating resin 340 is not limited to this.

[0039] The semiconductor package 300 has a front surface 300a and a back surface 300b. The front surface 300a and the back surface 300b are end faces in the thickness direction of the semiconductor package 300. FIG. 4 is a bottom view of the semiconductor package 300. As shown in FIG. 4, the die pad portion 311 and the lead portion 312 are exposed from the encapsulating resin 340 on the back surface 300b. The die pad portion 311 and the lead portion 312 exposed from the encapsulating resin 340 on the back surface 300b respectively become the central electrode 300c and the peripheral electrode 300d of the semiconductor package 300. The peripheral electrode 300d is arranged around the central electrode 300c.

[0040] As shown in FIG. 3, the semiconductor package 300 is mounted on the substrate 100. More specifically, the solder alloy 210 joins the central pad 21 and the central electrode 300c and also joins the peripheral pad 22 and the peripheral electrode 300d. The solder alloy 210 is formed of, for example, a tin alloy.

[0041] In mounting the semiconductor package 300 on the substrate 100, first, cream solder is applied on the central pad 21 and the peripheral pad 22. The cream solder is applied, for example, near the four corners in a plan view of the central pad 21 exposed from the first opening 31.

[0042] Second, the semiconductor package 300 is mounted on the substrate 100. At this time, the central pad 21 faces the central electrode 300c with the cream solder intervening therebetween, and the peripheral pad 22 faces the peripheral electrode 300d with the cream solder intervening therebetween. When the semiconductor package 300 is mounted on the substrate 100, the cream solder applied on the central pad 21 is spread.

[0043] Thirdly, the substrate 100 on which the semiconductor package 300 is mounted is loaded into a reflow furnace. As a result, the solder alloy 210 melts and spreads by wetting between the central pad 21 and the central electrode 300c and between the peripheral pad 22 and the peripheral electrode 300d, and the joining between the central pad 21 and the central electrode 300c and the joining between the peripheral pad 22 and the peripheral electrode 300d are performed. As described above, the semiconductor package 300 is mounted on the substrate 100, and the mounted substrate 200 is obtained.

[0044] In addition, the gas generated when the flux and the organic solvent volatilize from the cream solder is discharged through the through-hole 100a. That is, the through-hole 100a is a gas vent hole during reflow.

[0045] <Effect of the substrate 100> Hereinafter, the effect of the substrate 100 will be described while comparing it with the substrate according to the comparative example. The substrate according to the comparative example is referred to as substrate 100A.

[0046] FIG. 5 is a plan view of the substrate 100A. As shown in FIG. 5, the substrate 100A has a base material 10 (not shown in FIG. 5), a conductor pattern 20, and a solder resist 30. In the substrate 100A, the conductor pattern 20 has a central pad 21, a plurality of peripheral pads 22, and a wiring 23. In this regard, the configuration of the substrate 100A is common to the configuration of the substrate 100.

[0047] The substrate 100A does not have the first annular wall 40. In this regard, the configuration of the substrate 100A is different from the configuration of the substrate 100.

[0048] In the substrate 100A, since there is no first annular wall 40, when the semiconductor package 300 is mounted, the molten solder alloy 210 on the central pad 21 spreads not only on the central pad 21 but also on the conductor layer 24. As a result, the molten solder alloy 210 on the central pad 21 reaches the second main surface 10b side and solidifies on the second main surface 10b side.

[0049] After components are mounted on the first major surface 10a side including the mounting of the semiconductor package 300, in order to mount components on the second major surface 10b side, using a metal mask, the cream solder is applied onto pads of the conductor pattern disposed on the second major surface 10b. However, when the semiconductor package 300 is mounted, it reaches the second major surface 10b side through the through hole 100a, and the solder alloy 210 solidified on the second major surface 10b side comes into contact with the above-mentioned metal mask. Therefore, the application of the cream solder onto the pads of the conductor pattern disposed on the second major surface 10b is unstable.

[0050] On the other hand, in the substrate 100, since the first annular wall 40 is disposed on the central pad 21 so as to surround the through hole 100a, when the semiconductor package 300 is mounted, the wetting spread of the molten solder alloy 210 onto the conductor layer 24 on the central pad 21 is blocked by the first annular wall 40. Therefore, according to the substrate 100, the reaching of the molten solder alloy 210 from the first major surface 10a side to the second major surface 10b side is suppressed.

[0051] When the first annular wall 40 is formed of the same material as the solder resist 30, the first annular wall 40 and the solder resist 30 can be formed in the same process. Therefore, in this case, without adding a new process, the reaching of the molten solder alloy 210 from the first major surface 10a side to the second major surface 10b side is suppressed.

[0052] (Second Embodiment) A substrate according to the second embodiment will be described. Hereinafter, the substrate according to the second embodiment will be referred to as the substrate 100B. Here, mainly the differences from the substrate 100 will be described, and overlapping descriptions will not be repeated.

[0053] <Configuration of Substrate 100B> The configuration of the substrate 100B will be described below.

[0054] FIG. 6 is a plan view of the substrate 100B. FIG. 7 is a cross-sectional view taken along VII-VII in FIG. 6. As shown in FIGS. 6 and 7, the substrate 100B has a base material 10, a conductor pattern 20, a solder resist 30, and a first annular wall 40. In this regard, the configuration of the substrate 100B is common to the configuration of the substrate 100.

[0055] The substrate 100B further has a second annular wall 50. In this regard, the configuration of the substrate 100B is different from the configuration of the substrate 100.

[0056] The second annular wall 50 is annular in plan view. More specifically, the second annular wall 50 is annular in plan view. The second annular wall 50 is disposed on the first annular wall 40. The second annular wall 50 is formed of a material different from that of the first annular wall 40. In other words, the second annular wall 50 is formed of a material different from that of the solder resist 30.

[0057] The second annular wall 50 is formed of, for example, resin ink. The resin ink is, for example, silk ink. This resin ink is preferably colored in a color different from that of the solder resist 30. For example, when the solder resist 30 (the first annular wall 40) is colored green, the second annular wall 50 is formed of resin ink colored white.

[0058] Although not shown, characters are drawn on the solder resist 30 with the same resin ink as that used for the second annular wall 50. This character indicates, for example, information necessary when mounting components on the substrate 100B and information regarding the handling of the substrate 100B.

[0059] <Effect of the substrate 100B> The effect of the substrate 100B will be described below.

[0060] In the substrate 100B, since the second annular wall 50 is disposed on the first annular wall 40, when the semiconductor package 300 is mounted, a structure that prevents the spread of wetting of the solder alloy 210 on the conductor layer 24 on the central pad 21 is increased. Therefore, according to the substrate 100B, the reaching of the molten solder alloy 210 from the first main surface 10a side to the second main surface 10b side is further suppressed.

[0061] Also, in the manufacturing process of the substrate 100B, characters for displaying various information on the solder resist 30 are drawn using a resin ink colored in a color different from that of the solder resist 30. In the substrate 100B, since the second annular wall 50 is formed using the same ink as the resin ink used for drawing the above characters, the second annular wall 50 can be formed within this process, and there is no need to add a new process for forming the second annular wall 50.

[0062] As described above, the embodiments of the present invention have been described, but the above embodiments can be variously modified. Also, the scope of the present invention is not limited to the above embodiments. The scope of the present invention is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Explanation of Reference Numerals

[0063] 10 Base material, 10a First main surface, 10b Second main surface, 10c Through hole, 20 Conductor pattern, 21 Central pad, 21a Outer peripheral edge, 22, 22a Peripheral pad, 23 Wiring, 24 Conductor layer, 30 Solder resist, 31 First opening, 32 Second opening, 40 First annular wall, 50 Second annular wall, 100, 100A, 100B Substrate, 100a Through hole, 200 Mounting substrate, 210 Solder alloy, 300 Semiconductor package, 300a, 320a Surface, 300b, 320b Back surface, 300c Central electrode, 300d Peripheral electrode, 310 Lead frame, 311 Die pad portion, 312 Lead portion, 320 Semiconductor chip, 320a Surface, 320b Back surface, 330 Bonding wire, 340 Sealing resin, W1, W2 Width.

Claims

1. A substrate comprising: a base material having a main surface; a conductor pattern disposed on the main surface and having a central pad portion; and a first annular wall; wherein a through hole is formed in the substrate, penetrating the substrate in the thickness direction and overlapping the central pad portion in a plan view; the first annular wall is disposed on the central pad portion so as to surround the periphery of the through hole in a plan view; the substrate further comprises a solder resist disposed on the main surface so as to cover the conductor pattern and having a first opening for exposing the central pad portion; the first annular wall is formed of the same material as the solder resist; the substrate further comprises a second annular wall disposed on the first annular wall; the second annular wall is formed of a material different from that of the first annular wall.

2. The substrate according to claim 1, wherein the second annular wall is formed of a resin ink colored in a color different from that of the solder resist.

3. The conductor pattern further has a peripheral pad portion around the central pad portion; the substrate according to claim 1 or claim 2, wherein the solder resist further has a second opening for exposing the peripheral pad portion.

4. The substrate according to any one of claims 1 to 3, wherein the through hole is a vent hole.

5. A mounting substrate comprising: the substrate according to claim 3; a semiconductor package having a bottom surface; and a solder alloy, wherein the semiconductor package has a central electrode facing the central pad portion and a peripheral electrode surrounding the central electrode and facing the peripheral pad portion on the bottom surface, and the solder alloy joins the central electrode and a portion of the central pad portion outside the first annular wall in a plan view, and joins the peripheral electrode and the peripheral pad portion.

6. The mounting substrate according to claim 5, wherein the semiconductor package is a QFN package.

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