Reduction of Readout Errors in Quantum Computing

Abstract

A system for reducing errors in a quantum program is provided. The system may include a processor that executes computer-executable components stored in a memory. The computer-executable components include a compilation component that causes encoding one or more quantum bits at a time according to a cyclic repeat code after an operation on the quantum bits and before readout.

Description

Technical Field

[0001] One or more embodiments of the present invention relate to reducing readout errors in quantum computing.

[0002] A quantum computer is constructed from quantum devices coupled to an environment that can decohere and relax the quantum information contained in the quantum devices. Thus, such devices can be affected by external noise. As a result, the quantum processor formed by the quantum devices can be noisy, and there can be errors in the quantum computing using the quantum processor. Such noise or errors can exist regardless of the architecture of the quantum devices.

[0003] Readout errors can occur from quantum measurements of the quantum devices used in quantum computing after the quantum devices are operated according to the operations defining the quantum computing. Thus, improved techniques for reducing readout errors may be desired.

Summary of the Invention

Means for Solving the Problems

[0004] The following presents a summary for providing a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later.

[0005] According to one embodiment, a system is provided. The system includes a processor that executes computer-executable components stored in a memory. The computer-executable components include a compile component that encodes one or more qubits according to a cyclic repetition code at once after an operation on the one or more qubits and before readout. Thus, the measurement that defines readout is the only operation acting on the encoded qubit state, but all other operations that describe the preparation of the joint state of one or more qubits can be implemented without encoding. Thus, by using a cyclic repetition code to encode one or more qubits, readout errors in quantum computing including the encoded qubits can be reduced.

[0006] Further, or in another embodiment, the computer-executable components also include a branch identification component that identifies a first chain of ancillary qubits coupled to a particular qubit among the one or more qubits, a second chain of ancillary qubits coupled to the particular qubit, and a flag qubit that joins the first chain of ancillary qubits and the second chain of ancillary qubits. Encoding of the one or more qubits includes encoding the particular qubit by encoding the first chain of ancillary qubits using iterative encoding and encoding the second chain of ancillary qubits using iterative encoding.

[0007] According to another embodiment, a computer-implemented method is provided. The computer-implemented method includes a step of encoding one or more qubits according to a cyclic repetition code at once after an operation on the one or more qubits and before readout by a processor.

[0008] According to a further embodiment, a computer program product for reducing readout errors in quantum computing is provided. The computer program product includes a computer-readable storage medium having program instructions embodied therein. The program instructions are further executable by a processor to cause the processor to encode one or more qubits using a cyclic repetition code once, after operations on a plurality of qubits and before readout.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0031] Embodiments of the present disclosure address the problem of reducing readout errors in quantum computing. To that end, embodiments of the present disclosure utilize an exemplary form of quantum repetition code that exploits redundancy to protect quantum information from the effects of noise. Specifically, embodiments of the present disclosure cause one or several qubit devices to be encoded in their respective states according to cyclic repetition encoding. These encoded states are encoded all at once before readout after operations on one or more qubit devices have been performed. Thus, the measurement that defines readout is the only operation acting on the encoded qubit state, while all other operations that define quantum computing can be implemented without encoding. Cyclic repetition encoding utilizes a closed-loop chain of qubit devices. The qubit devices within such a chain are identified for encoding. That qubit device is called the root qubit. First and second chains of ancillary qubit devices are identified within the closed-loop chain. Each of these chains of ancillary qubit devices is coupled to the root qubit. Another qubit device, called a flag qubit, is also identified. The flag qubit is added to the first and second chains of ancillary qubits.

[0032] A series of controlled NOT (CNOT) gates define iterative encodings in each of the first and second chains of the ancillary qubits. The CNOT gates also couple a qubit device at the end of the first chain of the ancillary qubits. Another CNOT gate further couples the flag qubit to a qubit device at the end of the second chain of the ancillary qubits. In both cases, the flag qubit is the target of such a CNOT gate. Thus, together with the respective couplings to the flag qubits of both chains of the ancillary qubits, the iterative encodings of those chains constitute a cyclic iterative encoding. By measuring the single qubit state of the flag qubit, the quality of the encoding can be detected. With an error-free encoding, a majority vote evaluation can be performed that provides a result with reduced errors with respect to the single qubit state of the root qubit.

[0033] The exemplary cyclic iterative encoding described herein can be applied to various types of quantum computing. From the results of quantum computing of electronic structures and time propagation of model Hamiltonians, it has been revealed that the cyclic iterative encoding brings higher accuracy compared to general techniques for readout error reduction.

[0034] Exemplary embodiments of the present disclosure can provide several advantages compared to general techniques for reducing read errors, such as read calibration matrices, non-cyclic repetition codes, and small-scale stabilizer codes. As an example, embodiments of the present disclosure avoid imposing constraints on the quantum circuits to be encoded and can be utilized to encode the single-qubit states of an arbitrary number of qubit devices. In stark contrast, general stabilizer codes can only encode the single-qubit states of two-qubit devices and are applicable to a limited set of logical gates. As another example, by reducing read errors, embodiments of the present disclosure can result in more accurate estimates from quantum computations. As a result, the embodiments described herein can be used to address chemical accuracy and better estimate the dynamics of expected values and physical observables. In that regard, embodiments of the present disclosure are applicable not only to variational algorithms, but also to simulations involving measurements of observables in specific wave functions generated by quantum circuits. As yet another example, embodiments of the present disclosure do not grow exponentially, in stark contrast to the reduction of classical post-measurement read errors. Thus, a cyclic repetition encoding of many qubits can be implemented, resulting in reduced read errors and improved accuracy of quantum computations that utilize the encoded qubits associated therewith.

[0035] Some exemplary embodiments of the present disclosure are described by way of example with reference to qubit devices and quantum circuits only. However, the present disclosure is not limited thereto. In fact, the principles of the present disclosure can be applied to any representation of quantum computing and any type of quantum device (such as high-dimensional particle devices) used in physical implementations of quantum computers. Further, by way of example only, the improvements brought about by the cyclic iteration strength of the present disclosure are shown for quantum computing of electronic structure calculations and time propagation of model Hamiltonians. Further, the principles of the present disclosure are not limited to these types of quantum computing. In fact, the cyclic iteration encoding of the present disclosure can be widely applied to quantum computing in a wide range of fields such as physics, chemistry, materials science, cyber security, bioinformatics, and the like.

[0036] Referring to the drawings, FIG. 1 shows a non-limiting example of an operating environment 100 for reducing readout errors in quantum computing according to one or more embodiments described herein. The operating environment 100 includes a user device 110 (e.g., a classical computer) operably coupled to a compiler system 120. The user device 110 can send data defining a quantum program 112 to the compiler system 120 for compilation. The quantum program 112 can define one or several quantum algorithms. Thus, the quantum program 112 can include a group of quantum circuits 114 representing at least a part of the quantum program 112. The group of quantum circuits 114 includes one or more quantum circuits. In some cases, the group of quantum circuits 114 includes a specific quantum circuit representing a quantum algorithm (such as a variational quantum algorithm) included in the quantum program 112.

[0037] Each quantum circuit within the group of quantum circuits 114 can include one or several of various quantum gates. These quantum gates include, among many other gates, for example, Pauli gates representing Pauli operators (e.g., X gate or Y gate); Hadamard gate; rotation gate (e.g., R zgates and phase shift gates); controlled phase shift gates; CNOT gates; Toffoli (or controlled-controlled-NOT) gates: swap gates; Fredkin gates may be included. The data defining the quantum program 112 may include, in some embodiments, first data defining one or several first quantum gates constituting the first quantum circuit of the quantum circuit group 114. The data defining the quantum program 112 may also include second data defining one or several second quantum gates constituting the second quantum circuit of the quantum circuit group 114. Further, or in some embodiments, instead of defining specific quantum gates, the data defining the quantum program 112 may include first data defining one or several general unitary matrices U constituting at least one of the quantum circuit groups 114.

[0038] The compiler system 120 can receive the data defining the quantum program 112. In some embodiments, as shown in FIG. 2, the compiler system 120 may include an intake component 210 capable of receiving the data defining the quantum program 112. As further shown in FIG. 2, the compiler system 120 may also include other components, one or several processors 260, and one or several memory devices 270 (referred to as memory 270). The processor 260 and the memory 270 can be electrically, optically, and / or communicatively connected to each other.

[0039] Returning to the reference of FIG. 1, the compiler system 120 can then compile the quantum program 112 for execution on the quantum hardware 130. In some embodiments, the quantum hardware 130 embodies or includes a cloud-based quantum computer. In other embodiments, the quantum hardware 130 embodies or includes a local quantum computer. Regardless of its spatial footprint, the quantum hardware 130 can include a plurality of qubit devices 140 arranged in a particular layout. The qubit device can be one of several types of solid state devices. Each qubit device of the qubit devices 140 is coupled to an environment that decoheres and relaxes the quantum information contained in the qubit device. Thus, the quantum hardware 130 can be noisy. By way of example only, the qubit device can be a Josephson junction device, a semiconductor quantum dot, or a defect in a semiconductor material (such as holes in Si and Ge). In other embodiments, the qubit device can include atomic qubits built within an ion trap. For example, the atomic qubits can be embodied with calcium ions, ytterbium ions, or similar ions. In one embodiment, the quantum hardware 130 includes a plurality of qubit devices 124 each embodied with a transmon.

[0040] In some cases, a particular layout of the plurality of qubit devices 140 can exhibit a honeycomb connectivity. Such a layout includes one or several chains of qubit devices that form a closed loop chain. Thus, the qubit devices within such a chain are said to have a cyclic connectivity. The schematic 300 of FIG. 3 schematically shows a closed loop chain of qubit devices. In some cases, a particular layout of the plurality of qubit devices 140 can exhibit a connectivity that supports several closed loop chains of qubits. Each of these several closed loop chains of qubits can enable encoding of the qubits according to the cyclic iterative encoding described herein.

[0041] Referring further to FIG. 1, the compiler system 120 can utilize the cyclic connection of the quantum bit devices included in the quantum bit device 140 during the compilation of the quantum program 112. Specifically, the compiler system 120 can encode one or more quantum bits in a closed-loop chain according to cyclic repetition (CR) encoding.

[0042] The main cause of inaccuracies that affect the read operation in the quantum hardware 130 can be represented by bit flips in the computational basis. Therefore, the compiler system 120 can implement an iterative encoding scheme that is specifically designed to detect and correct that form of read error. Specifically, for a general state

Number

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[0043] The above mapping represents a repetitive encoding, where n rep Stabilizer {Z0Z1;Z1Z2,…,Zn rep-1 Z nrep}, where Z i is the Pauli σ applied to qubit device i z This is a quantum gate. The root qubit is associated with index i=0. State

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number

[0044] Compiler system 120 can implement cyclic iterative encoding at once after operations on one or more qubits and before quantum measurement (referred to as readout). That is, these measurements are the only operations acting on the encoded state. All other operations that describe the preparation of the joint state of one or more root qubits can be implemented without encoding. Such other operations represent at least a part of a specific quantum computation and can generally be represented by a unitary U acting on one or more root qubits that are encoded. Therefore, one or more second unitaries may follow that unitary, and each unitary represents an operation related to the cyclic iterative encoding of each of the root qubits to be encoded. Further, in some embodiments, each of the one or more second unitaries has the structure of the same encoding operation. Therefore, the same encoding unitary can be used to encode each qubit within a set of multiple encoded qubits. Therefore, each of the multiple root qubits can be encoded individually, resulting in a cyclic iterative encoding of the multiple root qubits.

[0045] As an illustration, FIG. 4A shows a schematic quantum circuit 400 showing the temporal relationship between a unitary 410 represented by U that represents a one-qubit computation and a second unitary 420 represented by U that represents an operation related to the cyclic iterative encoding of the root qubit q. The measurement value is schematically shown as a dial icon on the right side of FIG. 4A. エンコーディング As another illustration, FIG. 4B shows a schematic quantum circuit 450 showing the temporal relationship between a unitary 460 represented by U that represents a two-qubit computation and two unitaries each representing an operation related to the cyclic iterative encoding of its respective root qubit. U

[0046] (0) エンコーディング ​The first unitary 470, indicated by , encodes the first root qubit q0 by operating on two first iterative branches A0 and B0 and the flag qubit f0. The iterative branch A0 includes auxiliary qubits indicated by a01, a02, …, a0 N-1 , and a0 N . The iterative branch B0 includes auxiliary qubits indicated by b01, b02, …, b0 N-1 , and b0 N . The second unitary 470, indicated by U (1) エンコーディング , encodes the second root qubit q1 by operating on two iterative branches A1 and B1 and the flag qubit f1. The iterative branch A1 includes auxiliary qubits indicated by a11, a12, …, a1 N-1 , and a1 N . The iterative branch B1 includes auxiliary qubits indicated by b11, b12, …, b1 N-1 , and b1 N . Thus, the root qubits q0 and q1 are encoded individually (e.g., independently of each other) and in parallel. Further, U (0) エンコーディング and U (1) エンコーディング have the same encoding operation structure. After encoding q0 and q1 individually, if there is a cyclic connection in the layout of the qubits including q0 and q1, each of these encoded qubits can be placed in the network of encoded qubits. The measurement value is also schematically shown as a dial icon on the right side of FIG. 4B in this case.

[0047] The cyclic iterative encoding can be performed, for example, by applying n rep CNOT gates targeting n rep auxiliary qubits. Finally, in some embodiments, the compiler system 120 has each set being n repIt may include a branch discrimination component 220 (FIG. 2) that can identify two sets of auxiliary qubits having qubit devices. Each of these sets constitutes an iterative branch. The branch discrimination component 220 can also identify another qubit device connected to both the root qubit (e.g., q in FIG. 3) and both sets of auxiliary qubit devices. The other qubit device functions as a flag qubit (denoted by f in the schematic 350 of FIG. 3).

[0048] As described above, the unitary U エンコーディング represents a cyclic iterative encoding. The unitary U エンコーディング acts on an auxiliary register corresponding to the first and second iterative branches respectively defined by the first and second sets of auxiliary qubits to map each root qubit to its encoded version. That unitary U エンコーディング can be applied to encode each qubit within a set of a plurality of qubits to be encoded. As described above, in the case of two qubits, U (0) エンコーディング (FIG. 4B) is the same as U エンコーディング , and U (1) エンコーディング (FIG. 4B) is also the same as U エンコーディング .

[0049] In some cases, U エンコーディング includes an arrangement of CNOT operations that define the encoding. Such an arrangement can correspond to a series of CNOT operations targeting the auxiliary qubits sequentially (see FIG. 2 for an example). The compiler system 120 can configure U エンコーディング . For this purpose, in some embodiments, the compiler system 120 may include a compile component 230 that can receive data defining the first iterative branch, the second iterative branch, the flag qubit, and the root qubit. In some cases, such data can be received from the branch discrimination component 220. In other cases, the compile component 220 can load such data from the layout 272. Then, the compile component 230 uses the received data to configure Uエンコーディング can be configured.

[0050] In cyclic iterative encoding, the first iterative branch and the second iterative branch utilize a split iterative layout connected by a flag qubit initialized in the state |0>. Each of the first iterative branch and the second iterative branch has the same number of qubit devices (n rep as described above), is connected to the flag qubit by a CNOT gate, and in both cases the flag qubit is the target. The flag qubit is denoted by f in the schematic 350 of FIG. 3. Since cyclic iterative encoding depends on the iterative branches of auxiliary qubits, it may be less sensitive to error propagation compared to iterative encoding using a single chain of 2N auxiliary qubits. Furthermore, many of the CNOT gates of U エンコーディング can be executed in parallel, thus reducing the depth of the effective encoding circuit.

[0051] FIG. 5A shows a non-limiting example of U エンコーディング according to the aspects described herein. The unitary 510 implements U エンコーディング . The unitary 510 includes a first sequence of CNOT gates operating on each auxiliary qubit of the first iterative branch. The unitary 510 also includes a second sequence of CNOT gates operating on each auxiliary qubit of the second iterative branch. As shown in FIG. 5A, the first sequence of CNOT gates includes a first CNOT gate 520(1) that couples a root qubit and a1, where the root qubit is the control and a1 is the target; a second CNOT gate 520(2) that couples a1 and a2, where a1 is the control and a2 is the target; a N-1 is the control, and a N is the target, a N-1 and a NContinue in the same way up to the CNOT gate 520(N) that combines them (shown as a broken CNOT gate). Further, the second sequence of CNOT gates includes a first CNOT gate 540(1) that combines the root qubit and b1, where the root qubit is the control and b1 is the target; a second CNOT gate 540(2) that combines b1 and b2, where b1 is the control and b2 is the target; b N-1 is the control, and b N is the target, b N-1 and b N Continue in the same way up to the CNOT gate 540(N) that combines them (shown as a broken CNOT gate). Since the iterative encoding is a cyclic iterative encoding, the CNOT gate 530 combines the flag qubit with the auxiliary qubit a N where a N is the control and the flag qubit is the target. Further, the CNOT gate 550 also combines the flag qubit with the auxiliary qubit b N where b N is the control and the flag qubit is the target.

[0052] In FIG. 5A, a second iterative branch is used after the first iterative branch in the cyclic iterative encoding, but the present disclosure is not limited thereto. In fact, one of the advantages of cyclic iterative encoding is the parallel execution of the CNOT gates of the first iterative branch and the CNOT gates of the second iterative branch. In such a scenario, for example, the CNOT gate 520(2) and the CNOT gate 540(2) are aligned in FIG. 5A.

[0053] FIG. 5B shows a schematic quantum circuit 560 showing the temporal relationship between a unitary 562 represented by U that represents a two-qubit computation and two unitaries each representing an operation related to the cyclic iterative encoding of their respective root qubits q0 and q1. The two unitaries include U (0) エンコーディング and U(1) エンコーディング is included. The unitary 565 is U (0) エンコーディング to embody. The unitary 565 includes a first sequence of CNOT gates operating on each of the auxiliary qubits of the first iterative branch A0. The unitary 565 also includes a second sequence of CNOT gates operating on each of the auxiliary qubits of the second iterative branch B0. As described above, each of these branches is coupled to the root qubit q0. As shown in FIG. 5B, the first sequence of CNOT gates includes a first CNOT gate 570(1) that couples the root qubit q0 and a01, where the root qubit is the control and a01 is the target; a0 N-1 is the control, and a0 N is the target, a0 N-1 and a0 N continuously continues to the CNOT gate 570(N) that couples and a0 N-1 is the control, and b0 N is the target, b0 N-1 and b0 N continuously continues to the CNOT gate 576(N) that couples and b0 N is the control, and the flag qubit f0 is the target, the auxiliary qubit a0 N couples the flag qubit f0. Further, the CNOT gate 574 also couples the flag qubit f0 to the auxiliary qubit b0 N is the control, and the flag qubit is the target, b0 N where N

[0054] The unitary 590 is U (1) エンコーディングImplement. The arithmetic structure of the unitary 590 is the same as that of the unitary 565. Specifically, the unitary 590 includes a first sequence of CNOT gates that operate on each auxiliary qubit of the first iterative branch A1. The unitary 590 also includes a second sequence of CNOT gates that operate on each auxiliary qubit of the second iterative branch B1. As described above, each of these branches is coupled to the root qubit q1. As shown in Figure 5B, the first sequence of CNOT gates includes a first CNOT gate 580(1) that couples the root qubit q1 and a11, where the root qubit is the control and a11 is the target; a1 N-1 is the control, and a1 N is the target, and continues continuously up to the CNOT gate 580(N) that couples a1 N-1 and a1 N . Further, the second sequence of CNOT gates includes a first CNOT gate 586(1) that couples the root qubit q1 and b11, where the root qubit is the control and b11 is the target; b1 N-1 is the control, and b1 N is the target, and continues continuously up to the CNOT gate 586(N) that couples b1 N-1 and b1 N . Since the iterative encoding is cyclic iterative encoding, the CNOT gate 582 couples the flag qubit f1 to the auxiliary qubit a1 N , where a1 N is the control and the flag qubit f1 is the target. Further, the CNOT gate 574 also couples the flag qubit f1 to the auxiliary qubit b1 N , where b1 N is the control and the flag qubit is the target.

[0055] As described above, U (0) エンコーディング and U (1) エンコーディングThey have the same structure of encoding operation. Therefore, the unitary 590 and the unitary 565 have the same structure of encoding operation and can thus be called symmetric to each other. Also in this case, in FIG. 5B, the second iterative branches B0 and B1 are used after the first iterative branches A0 and A1 in each cyclic iterative encoding, but the present disclosure is not limited thereto. As described above, one of the advantages of cyclic iterative encoding is the parallel execution of the CNOT gates of the first iterative branch and the CNOT gates of the second iterative branch. In that regard, the unitary 565 and the unitary 590 can be implemented simultaneously, and as a result, the root qubits q0 and the root qubit q1 are cyclically iteratively encoded in parallel and independently of each other.

[0056] Similar to the general case, the initial non-encoded state of the root qubit is

Number

[0057] When there is no error during the split iterative encoding, the state after U エンコーディング is

Number

Number

[0058] In the case of a quantum bit device 140 arranged in a layout including multiple replicas of a closed loop chain of qubits, or an arrangement having a cyclic connection (see FIG. 3 for an example), the multiple root qubits corresponding to each replica can be encoded in parallel with each other individually (e.g., independently of each other). The cyclic iterative encoding of multiple qubits can be performed in parallel with each other for each of the multiple qubits, so the cyclic iterative encoding is scalable. Each of these encoded root qubits and the associated closed loop chain of qubits can be utilized in multi-qubit quantum computing using the quantum bit device 140.

[0059] U エンコーディング After one or more instances of [[]] are configured for one or more qubits respectively, the compiler system 120 can generate a compiled version of the quantum program 112. The compiled version includes the CR iterative unitary 128 (e.g., U エンコーディングincludes one or several compiled quantum circuits 124. The compiler system 120 can execute the compiled version of the quantum program 112. Executing the compiled version of the quantum program 112 may include sending one or more compiled quantum circuits 124 for execution by the quantum hardware 130. Executing one or more compiled quantum circuits 124 includes executing the operations in the quantum computation defined by the quantum program 112, and, after the execution of the operations on one or more qubits and before reading, executing the encoding of one or more qubits according to the cyclic repetition code at one time. Further, executing the compiled version of the quantum program 112 also includes causing all qubit devices represented within the compiled quantum circuit 124 to be measured in the computational basis. In other words, part of the execution of the compiled version of the quantum program 112 includes measuring all qubit devices utilized in the quantum computation defined by the quantum program 112 and the second qubit devices utilized in the cyclic repetition encoding. In some embodiments, the compiler system 120 can include a monitoring component 240 (FIG. 2) that causes such all qubit devices to be measured in the computational basis.

[0060] The compiler system 120 can receive the readout data obtained from those measurements and then perform a majority vote evaluation to restore the measured values of the root qubits. More specifically, through the majority vote evaluation applied in the post-processing stage of the result bit string, the readout results with reduced errors can be restored for individual root qubits. In particular, any bit string b0b1…bn obtained as a result of the quantum measurement in the computational basis rep is decoded as 0 or 1 according to which of the two values appears more in the n rep +1 output bits. (n repIf a bit value less than 2 in ( + 1) is inverted by noise, the decoding is successful. For this purpose, the compiler system 120 can receive read data from the root qubit, the flag qubit, and the auxiliary qubit. Then, the compiler system 120 can perform a majority-based evaluation using the received read data. In some embodiments, as shown in FIG. 2, the compiler system 120 may include an evaluation component 250 that can receive read data and hold the read data in the memory 270. The read data can be held in one or several records 276 (referred to as read data 276). Then, the evaluation component 250 can execute the majority-based procedure described above.

[0061] There are several layouts of the qubit device 140 (FIG. 1) that can include a group of multiple qubit devices with cyclic connections. Quantum computing using such layouts can utilize the cyclic iterative encoding described herein. For illustrative purposes only, FIG. 6A shows a non-limiting example of a layout 600 of the qubit device 140 according to one or more embodiments described herein. In layout 600, twenty qubit devices are arranged in a geometric shape showing many closed-loop chains of qubit devices. Each of the twenty qubit devices is assigned an index numbered from 0 to 19. In one example, the twenty qubit devices are implemented with twenty transmons.

[0062] FIG. 6B shows a non-limiting example of a closed-loop chain 650 present in the layout 600 shown in FIG. 6A. The closed-loop chain 650 includes four auxiliary qubit devices (e.g., auxiliary qubits) divided into two branches that can use a first iterative branch including a1 and a2 and a second iterative branch including b1 and b2 as iterative branches. Each of the branches is coupled to the root qubit at one end and further coupled to the flag qubit at the other end. A replica of the closed-loop chain 650 is also present in the layout 600 of FIG. 6A. Both closed-loop chains of qubit devices can be utilized in two-qubit quantum computing. An example of the closed-loop chain 650 includes qubit devices 11 and 16 as the first iterative branch; qubit devices 18 and 13 as the second iterative branch; qubit device 17 as the flag qubit; and qubit device 12 as the root qubit. In that case, the replica includes qubit devices 1 and 6 as the first iterative branch; qubit devices 8 and 3 as the second iterative branch; qubit device 2 as the flag qubit; and qubit device 7 as the root qubit. The aforementioned numbers representing the qubit devices correspond to the respective indexes shown in FIG. 6A.

[0063] Merely as another illustration, FIG. 7A shows a non-limiting example of a layout 700 of a qubit device 140. In the layout 700, 65 qubit devices are arranged in a geometric shape showing many closed-loop chains of qubit devices. Each of the 65 qubit devices is assigned an index numbered from 0 to 64. In one example, the 65 qubit devices are embodied by 65 transmon devices.

[0064] Figure 7B shows a non-limiting example of a closed-loop chain 750 present in the layout 700 shown in Figure 7A. The closed-loop chain 750 includes 10 auxiliary qubit devices divided into two branches that can use a first repeating branch including a1, a2, a3, a4, and a5 and a second repeating branch including b1, b2, b3, b4, and b5 as repeating branches. Each of the branches is coupled to a root qubit at one end and further coupled to a flag qubit at the other end. An example of the closed-loop chain 750 includes qubit devices 32, 31, 39, 45, 46 as the first repeating branch; qubit devices 48, 49, 40, 35, and 34 as the second repeating branch; qubit device 33 as the root qubit; and qubit device 47 as the flag qubit. The foregoing numbers representing qubit devices correspond to the respective indices shown in Figure 7A.

[0065] Replicas of the layout 750 can be used for the cyclic repeated encoding of two qubits. For this purpose, as an example, Figure 7C shows two closed-loop chains that can be used for such encoding, a first closed-loop chain including qubit devices 33, 32, 31, 39, 45, 46, 47, 48, 49, 40, 35, and a second closed-loop chain including qubit devices 34, and 19, 20, 21, 12, 8, 7, 6, 5, 4, 11, 17, and 18. The second closed-loop chain is coupled to the first closed-loop chain by qubit device 25. In this arrangement, the encoded root qubits are qubit device 19 and qubit device 33, and the flag qubits are qubit device 47 and qubit device 6. The auxiliary qubits are represented by white circles. The foregoing numbers representing qubit devices correspond to the respective indices shown in Figure 7A.

[0066] FIG. 8 is a block diagram of a non-limiting example of a compiler system 120 for read error reduction in quantum programs / computations according to one or more embodiments described herein. As shown in FIG. 8, compiler system 120 may include one or several processors 810 and one or several memory devices 830 (referred to as memory 830). In some embodiments, processor 810 may be disposed within a single computing device (e.g., a blade server device or another type of server device). In other embodiments, processor 810 may be distributed across two or more computing devices (e.g., multiple blade server devices or other types of server devices).

[0067] Processor 810 can be operably coupled to memory 830, for example, via one or several communication interfaces 820. Communication interface 820 may be suitable for a particular arrangement (local or distributed) of processor 810. In some embodiments, communication interface 820 may include one or more bus architectures such as an Ethernet-based industrial bus, a Controller Area Network (CAN) bus, a Modbus, other types of field bus architectures, or the like. Further, or in other embodiments, the communication interface may include a wireless network and / or a wired network each having its own footprint.

[0068] Memory 830 can hold or otherwise store machine-accessible components (e.g., computer-readable and / or computer-executable components) and data according to the present disclosure. Thus, in some embodiments, machine-accessible instructions (e.g., computer-readable instructions and / or computer-executable instructions) embody or otherwise configure each of the machine-accessible components within memory 830. The machine-accessible instructions can be encoded within memory 830 and arranged to form each of the machine-accessible components. The machine-accessible instructions can be constructed (e.g., linked and compiled) and held in a computer-executable form within memory 830 or within one or several other machine-accessible non-transitory storage media. Specifically, as shown in FIG. 8, in some embodiments, the machine-accessible components include an intake component 210, a branch identification component 220, a compilation component 230, a monitoring component 240, and an evaluation component 250. Memory 830 can also include data (not shown in FIG. 8) that enables the various functions described herein. In some embodiments, compilation component 230 can include one or a combination of branch identification component 220, monitoring component 240, and evaluation component 250. As shown in FIG. 9, memory 930 can hold layout 272 and read data 276.

[0069] Machine-accessible components can be accessed and executed by at least one of processors 810, either individually or in a particular combination. In response to execution, each of the machine-accessible components can provide the functions described herein in connection with reducing read errors in quantum computing. Thus, by executing the computer-accessible components held in memory 830, compiler system 120 can be operated in accordance with the aspects described herein. More specifically, at least one of processors 810 can, by executing machine-accessible components, cause compiler system 120 to encode one or more qubit devices (e.g., qubit devices or high-dimensional particle devices) using cyclic repetition codes, and during compilation of a quantum program executed on quantum hardware including qubit devices in accordance with aspects of the present disclosure, encoding unitary U can be added to a sequence of quantum gates corresponding to each of the qubit devices. エンコーディング be added.

[0070] Although not shown in FIG. 8, compiler system 120 can also include other types of computing resources that can enable or otherwise facilitate execution of machine-accessible components held in memory 830. These computing resources include, for example, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Tensor Processing Unit (TPU), memory, disk space, receive bandwidth and / or transmit bandwidth, an interface (such as an I / O interface); a controller device; a power source; and the like. For example, memory 830 can also include a programming interface (such as an API); an operating system; software for configuring and / or controlling a virtualized environment; firmware; and the like.

[0071] The cyclic iterative encoding of the present disclosure is applicable to quantum computing using quantum hardware 130 (FIG. 1) having a cyclic connection. These quantum computations can include, for example, electronic structure calculations and simulations of the time propagation of a model Hamiltonian. Other types of quantum computations in chemistry and physics can also be implemented. It should be noted that the present disclosure is not limited to these types of quantum computations. In fact, the cyclic iterative encoding of the present disclosure can generally be applied to any quantum computation.

[0072] Using a noisy quantum computer enables, for example, the efficient implementation of quantum computations of the electronic structure properties of compounds. In some cases, such computations may rely on adaptive quantum circuits. For example, the Variational Quantum Eigensolver (VQE) algorithm approximates the electronic ground state and the corresponding energy expectation value <(|H|(> depending on the quantum resources. Here, H is the electronic molecular Hamiltonian describing the compound, and |(> is a hypothesized parameterized wave function encoded on a qubit register.

[0073] As described above, the cyclic iterative encoding of the present disclosure can reduce readout errors. Therefore, by implementing the VQE algorithm using the quantum hardware 130, the effect of such encoding on the readout of the energy expectation value can be analyzed. As an illustration, the VQE algorithm has been implemented for the model systems HeH + and H2. For this purpose, for HeH + , the perturbation to the Hartree-Fock (HF) ground state determinant is prepared using the two-qubit quantum circuit 900 shown in FIG. 9. Here, a, b, c are variational parameters.

Number

[0074] In an embodiment where the quantum bit device 140 includes a quantum bit layout 700 (FIG. 7A), the quantum circuit 900 was executed on the quantum bit device 140. The quantum circuit 900 was executed both when using cyclic iterative encoding and when not using cyclic iterative encoding. The results of the quantum calculations at each interatomic distance are shown in Table 1010. The same two quantum bit devices (labeled simply q J and q K in FIG. 9 for naming purposes) were used for the calculations without cyclic iterative encoding (labeled "uncoded" in FIGS. 10 and 11) and as the root quantum bits for the calculations using (4 + 1 + 1) quantum bit cyclic iterative encoding. Thus, the gate errors during the state preparation stage are consistent, and the results can only differ in the quality of the readout measurement. Therefore, the effect of cyclic iterative encoding for reducing readout errors is emphasized. As shown in FIG. 10, by including cyclic iterative encoding in the quantum calculation, in this example, the total error (defined as the difference from the reference energy value) is reduced by an average of about 43% compared to the non-encoded quantum calculation. The reference energy value is shown as the solid line trace 1015 (labeled "exact") and is obtained using an Unrestricted Hartree-Fock (UHF) classical calculation.

[0075] Regarding the electronic structure of H2, a (10 + 1 + 1) quantum bit quantum chemistry experiment was executed on the quantum layout 700 (FIG. 7A), and a single quantum bit VQE calculation was performed. In such a calculation, the reduction of two quantum bits to the quantum bit Hamiltonian obtained by parity mapping is utilized, and the two quantum bit Hamiltonian including |01> and |10> as the ground state and the excited state respectively

Number

Number

[0076] In these calculations, numerically optimized hypothesized parameters for noise-free simulations are used as samples of energy estimates that exceed the results of the reference HF. The results of the calculations are shown in Chart 1110 of FIG. 11. As shown in FIG. 11, the improved effect of the cyclic iterative encoding can be clearly seen in Chart 1110 and Chart 1120 of this additional example. The reference energy value is shown as the solid line trace 1115 (labeled "exact") and is obtained using UHF classical calculations.

[0077] To show the performance of the cyclic iterative encoding described herein on deeper circuits, a digital quantum simulation of the two-spin transverse-field Ising model can be implemented. Such an Ising model is represented by the following Hamiltonian.

Number

Number

Number

[0078] FIG. 13 shows the results of implementing the case of n = 5 on a quantum processor having the qubit layout 600 shown in FIG. 6A. The results show the time evolution of the total spin component along the z direction. [Number] Similar to the electronic structure calculations described above, the same pair of qubit devices (indexes 7 and 12 of the qubit layout 600) are used both as root qubits in non-encoded calculations and in 4+1+1 cyclic iterative encoding. The results of such non-encoded calculations are labeled "non-encoded" in FIG. 13. Another pair of qubit devices (indexes 15 and 16 of the qubit layout 600) is also used in non-encoded calculations as reference calculations because the qubit devices of that pair show the calibration data with the lowest readout error. Such reference results are labeled "non-encoded (A)" in FIG. 13. As shown in this additional example, the results of quantum calculations using cyclic iterative encoding are superior to both non-encoded quantum calculations.

[0079] FIG. 14 is a flowchart of a non-limiting example of a computer-implemented method 1400 for reducing read errors in quantum programs / computations according to one or more embodiments of the present disclosure. As described above, reduction of read errors can be achieved using cyclic repetition encoding. Although described with reference to a qubit device, the exemplary method 1400 can be implemented for other types of quantum devices such as high-dimensional particle devices. A computing system can at least partially implement the computer-implemented method 1400. Implementing the computer-implemented method 1400 can include, for example, compiling or executing, or both, one or several blocks included in the computer-implemented method 1400. A computing system can include one or several processors, one or several memory devices, other types of computing resources (such as communication interfaces, bus architectures, etc.), combinations thereof, or other similar resources, and / or can be operably coupled thereto. In some embodiments, the computing system can be embodied within or configure the compiler system 120 according to various embodiments described herein.

[0080] In block 1410, the computing system can configure a quantum computation to be executed within a quantum processor. Finally, the computing system can receive, via the capture component 210, data defining, for example, a quantum program including one or several quantum circuits. The quantum program defines the quantum computation.

[0081] In block 1420, the computing system can configure one or more encoding unitaries using each closed-loop chain of a qubit device (e.g., qubit device 140 (FIG. 1)) within the quantum processor. The one or more unitaries can be configured, for example, by the compilation component 230. Each encoding unitary of the one or more encoding unitaries (U エンコーディング) defines the cyclic iterative encoding of a qubit device involved in quantum computing. As described above, the encoded qubit device is called a root qubit. For example, in a two-qubit computation, one or more of the constituent unitaries can be U (0) エンコーディング and U (1) エンコーディング as shown in FIG. 5B.

[0082] In block 1430, the computing system can execute quantum computing within the quantum processor. The compilation component 230 (FIG. 2) can execute quantum computing.

[0083] In block 1440, the computing system can perform cyclic iterative encoding on one or more qubit devices (root qubits) within the quantum processor using one or more encoding unitaries. The compilation component 230 (FIG. 2) can execute quantum computing. Performing cyclic iterative encoding includes, for example, converting an operation defined by one or more unitaries into a pulse schedule and, further, applying a component scheduled to perform cyclic iterative encoding to one or some of the components of the quantum hardware 130. In some cases, such a conversion can be performed by the computing system via the compilation component 230, for example. In other cases, the conversion can be performed by the quantum hardware 130.

[0084] In block 1450, the computing system can measure the qubit devices involved in quantum computing and other qubit devices within the closed-loop chain. Those other qubit devices include auxiliary qubits and flag qubits. The monitoring component 240 can cause such measurements, for example.

[0085] In block 1460, the computing system can determine that a flag bit corresponding to the cyclic iterative encoding of a particular qubit device (e.g., a particular routed qubit) is in a state indicating an error-free encoding. The monitoring component 240 can cause such measurements, for example.

[0086] In block 1470, the computing system can perform a majority-based evaluation using data from the measurements. Such an evaluation can provide a single-qubit state with reduced readout error for a particular qubit. The evaluation component 250 can perform a majority-based evaluation, for example.

[0087] To provide context for various aspects of the disclosed subject matter, FIG. 15 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 15 illustrates a block diagram of an exemplary, non-limiting operating environment that can facilitate one or more embodiments described herein. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. A suitable operating environment 1500 for implementing various aspects of the present disclosure may include a computer 1512. The computer 1512 can also include a processing unit 1514, a system memory 1516, and a system bus 1518. The system bus 1518 can operably couple system components including, but not limited to, the system memory 1516 to the processing unit 1514. The processing unit 1514 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures can also be used as the processing unit 1514. The system bus 1518 can use any of a variety of available bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, and / or, without limitation, an Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire, and Small Computer System Interface (SCSI), including a local bus that incorporates any of the above bus architectures. The system memory 1516 can also include volatile memory 1520 and non-volatile memory 1522. A basic input / output system (BIOS), including basic routines for transferring information between elements within the computer 1512, such as during startup, can be stored in the non-volatile memory 1522.By way of example, and not limitation, non-volatile memory 1522 can include, but is not limited to, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 1520 can also include random access memory (RAM) that functions as an external cache memory. By way of example, and not limitation, RAM can be available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct rambus RAM (DRRAM), direct rambus dynamic RAM (DRDRAM), and rambus dynamic RAM.

[0088] Computer 1512 can also include removable / non-removable, volatile / non-volatile computer storage media. FIG. 15 shows, for example, disk storage 1524. Disk storage 1524 can also include devices such as, but not limited to, magnetic disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 1524 can also include storage media separately or in combination with other storage media including, but not limited to, optical disk drives such as compact disk ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives) or digital versatile disk ROM drives (DVD-ROM). A removable or non-removable interface such as interface 1526 can be used to facilitate connection of disk storage 1524 to system bus 1518. FIG. 15 also shows software that can function as an intermediary between the user and the basic computer resources described in the appropriate operating environment 1500. Such software can also include, for example, operating system 1528. The operating system 1528 stored on disk storage 1524 functions to control and allocate the resources of computer 1512. System applications 1530 can utilize the resource management by operating system 1528 via program modules 1532 and program data 1534 stored in either system memory 1516 or disk storage 1524, for example. It should be understood that the present disclosure can be implemented with various operating systems or combinations of operating systems. The user inputs commands or information into computer 1512 via one or more input devices 1536.Input device 1536 can include, but is not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite broadcast receiving antenna, scanner, television tuner card, digital camera, digital video camera, webcam, and the like. These and other input devices can be connected to processing unit 1514 through system bus 1518 via one or more interface ports 1538. One or more interface ports 1538 can include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). One or more output devices 1540 can use some of the same type of ports as input device 1536. Thus, for example, a USB port can be used to provide input to computer 1512 and output information from computer 1512 to output device 1540. Output adapter 1542 can be provided to indicate that among output devices 1540, there are some output devices 1540 such as monitors, speakers, and printers that require a dedicated adapter. Output adapter 1542 can include, by way of example and not limitation, video cards and sound cards that provide connection means between output device 1540 and system bus 1518. Note that other devices and / or systems of devices can provide both input and output functions, such as one or more remote computers 1544.

[0089] Computer 1512 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 1544. Remote computer 1544 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer device or other common network node and the like, and can further typically include many or all of the elements described in relation to computer 1512. For simplicity, only memory storage device 1546 is shown with remote computer 1544. Remote computer 1544 is logically connected to computer 1512 through network interface 1548 and can then be physically connected via communication connection 1550. Further, operations can be distributed across multiple (local and remote) systems. Network interface 1548 can include wired and / or wireless communication networks such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies can include fiber distributed data interface (FDDI), copper distributed data interface (CDDI), Ethernet (registered trademark), token ring and the like. WAN technologies can include, but are not limited to, point-to-point links, circuit-switched networks such as integrated services digital network (ISDN (registered trademark)) and variations thereof, packet-switched networks, and digital subscriber line (DSL). One or more communication connections 1550 refer to the hardware / software used to connect network interface 1548 to system bus 1518. Communication connection 1550 is shown inside computer 1512 for illustrative clarity, but can also be external to computer 1512. The hardware / software for connecting to network interface 1548 can also include internal and external technologies such as modems, cable modems and DSL modems, ISDN (registered trademark) adapters, and Ethernet (registered trademark) cards, including modems that typically include ordinary telephone grade modems, for illustrative purposes only.

[0090] In some embodiments, various embodiments of the compiler system 120 described herein can be associated with a cloud computing environment. For example, the compiler system 120 can be included in a cloud computing environment 1650 included in an operating environment 1600 shown in FIG. 16, and / or one or more functional abstraction layers described herein with reference to FIG. 17 (e.g., hardware and software layers 1760, virtualization layer 1770, management layer 1780, and / or workload layer 1790).

[0091] Although this disclosure includes a detailed description of cloud computing, it should be understood that the implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the present invention can be implemented in combination with any other type of computing environment, now known or later developed.

[0092] Cloud computing is a service delivery model that enables convenient on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0093] The characteristics are as follows.

[0094] On-demand self-service: A cloud consumer can provision computing capabilities, such as server time and network storage, automatically as needed, without the need for human interaction with the service provider.

[0095] Broad network access: The capabilities are available over the network and accessed through a standard mechanism that facilitates use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, PDAs).

[0096] Resource pooling: The provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically assigned and reassigned according to demand. Consumers generally have a sense of location independence in that they have no control or knowledge of the exact location of the provided resources but can specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0097] Rapid elasticity: Capabilities can be provisioned quickly and elastically, and in some cases, automatically, scaled out rapidly, released quickly, and scaled in rapidly. To the consumer, the capabilities available for provisioning often appear limitless and can be purchased in any quantity at any time.

[0098] Measured service: The cloud system automatically controls and optimizes resource use by leveraging measurement capabilities at an appropriate level of abstraction for the type of service (e.g., storage, processing, bandwidth, active user accounts). Monitoring, controlling, and reporting resource usage can provide transparency to both the provider and the consumer of the services used.

[0099] The service model is as follows.

[0100] Software as a Service (SaaS): The ability provided to consumers is to use the provider's applications running on cloud infrastructure. The applications are accessible from various client devices via a client interface such as a web browser (e.g., web-based email). Consumers can except for limited user-specific application configurations, do not manage or control the underlying cloud infrastructure including the network, servers, operating systems, storage, and even individual application features.

[0101] Platform as a Service (PaaS): The ability provided to consumers is to deploy applications created or acquired by consumers using programming languages and tools supported by the provider onto the cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure including the network, servers, operating systems, storage, but control the deployed applications and, in some cases, the configuration of the application hosting environment.

[0102] Infrastructure as a Service (IaaS): The ability provided to consumers is to provision processing, storage, network, and other basic computing resources on which consumers can deploy and run any software that may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but control the operating systems, storage, deployed applications, and in some cases, limit the control of selected networking components (e.g., host firewalls).

[0103] The deployment model is as follows.

[0104] Private Cloud: The cloud infrastructure is operated solely for an organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0105] Community Cloud: The cloud infrastructure is shared by multiple organizations and supports a specific community with shared concerns (e.g., mission, security requirements, policies, compliance considerations). It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0106] Public Cloud: The cloud infrastructure is made available to the general public or large industry groups and is owned by an organization that sells cloud services.

[0107] Hybrid Cloud: The cloud infrastructure remains a single entity but is a composition of two or more clouds (private, community, or public) joined by standardized or proprietary technologies (e.g., cloud bursting for load distribution between clouds) that enable data and application portability.

[0108] The cloud computing environment is service-oriented, emphasizing statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0109] Referring now to FIG. 16, an exemplary cloud computing environment 1650 is shown. As shown, cloud computing environment 1650 includes one or more cloud computing nodes 1610 that may be communicatively coupled to local computing devices used by cloud consumers such as, for example, a personal digital assistant (PDA (registered trademark)) or cellular telephone 1654A, a desktop computer 1654B, a laptop computer 1654C, and / or an automotive computer system 1654N. Although not shown in FIG. 16, cloud computing nodes 1610 may further include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, and / or another quantum platform) to which local computing devices used by cloud consumers may communicate. Nodes 1610 may communicate with one another. They may be grouped (not shown) physically or virtually into one or more networks such as the aforementioned private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof. Thereby, cloud computing environment 1650 can provide infrastructure, platform, and / or software as a service such that cloud consumers need not maintain resources on local computing devices. The types of computing devices 1654A - N shown in FIG. 16 are intended only as examples, and it will be understood that cloud computing nodes 1610 and cloud computing environment 1650 can communicate with any type of computerized device via any type of network and / or network addressable connection (e.g., using a web browser).

[0110] Referring now to FIG. 17, a set of functional abstraction layers provided by the cloud computing environment 1650 (FIG. 16) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 17 are for illustrative purposes only and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided.

[0111] The hardware and software layer 1760 includes hardware and software components. Examples of hardware components include mainframe 1761, RISC (Reduced Instruction Set Computer) architecture-based server 1762, server 1763, blade server 1764, storage device 1765, and network and networking components 1766. In some embodiments, the software components include network application server software 1767, database software 1768, quantum platform routing software (not shown in FIG. 17), and / or quantum software (not shown in FIG. 17).

[0112] The virtualization layer 1770 provides an abstraction layer that can provide the following examples of virtual entities: virtual server 1771, virtual storage 1772, virtual network 1773 including a virtual private network, virtual applications and operating systems 1774, and virtual clients 1775.

[0113] In one example, the management layer 1780 may provide the functions described below. Resource provisioning 1781 provides for the dynamic procurement of computing resources and other resources utilized to execute tasks within a cloud computing environment. Metering and pricing 1782 provides for cost tracking when resources are utilized within a cloud computing environment and for charging or billing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides for authentication of cloud consumers and tasks and for protection of data and other resources. The user portal 1783 provides access to the cloud computing environment for consumers and system administrators. Service level management 1784 provides for the allocation and management of cloud computing resources such that required service levels are met. Planning and fulfillment of service level agreements (SLAs) 1785 provides for the advance preparation and procurement of cloud computing resources for which future requirements are anticipated in accordance with an SLA.

[0114] The workload layer 1790 provides examples of functions that a cloud computing environment may utilize. Non-limiting examples of workloads and functions that may be provided from this layer include mapping and navigation 1791, software development and lifecycle management 1792, virtual classroom education delivery 1793, data analytics processing 1794, transaction processing 1795, and vulnerability risk assessment software 1796.

[0115] Embodiments of the present invention may be a system, method, apparatus, and / or computer program product at any possible level of integration of technical details. The computer program product may include a computer-readable storage medium (or media) having thereon computer-readable program instructions for causing a processor to execute aspects of the present invention.

[0116] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile discs (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium as used herein should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0117] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices or to an external computer or an external storage device via a network, such as, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on a computer-readable storage medium within each respective computing / processing device.

[0118] Computer-readable program instructions for performing the operations of various aspects of the present invention may be source code or object code written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, integrated circuit configuration data, or object-oriented programming languages such as Smalltalk®, C++, or the like, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions for customizing the electronic circuit to perform aspects of the present invention.

[0119] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0120] These computer-readable program instructions are provided to a general-purpose computer, a special-purpose computer processor, or other programmable data processing apparatus, generating a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium containing the instructions therein comprises a manufacture including instructions for implementing the aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0121] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0122] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or combinations of dedicated hardware and computer instructions.

[0123] The subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on one or more computers, and those skilled in the art will recognize that the present disclosure can also be combined with other program modules or implemented in combination. In general, program modules include routines, programs, components, data structures, etc. that perform specific tasks and / or implement specific abstract data types. Further, those skilled in the art will understand that the computer-implemented methods of the present invention can be implemented in other computer system configurations including single-processor or multi-processor computer systems, minicomputing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs (registered trademarks), telephones), microprocessor-based or programmable household appliances or industrial electronic devices, and the like. The illustrated aspects can also be implemented in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. However, at least some aspects, if not all, of the present disclosure can be implemented on a stand-alone computer. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0124] As used in this application, the terms "component", "system", "platform", "interface", and the like can refer to and / or include a computer-related entity or an entity related to an operating machine with one or more specific functions. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a server and the server can be components. One or more components can exist within a process and / or an execution thread, and a component can be localized on one computer and / or distributed between two or more computers. In another example, each component can be executable from various computer-readable media having various data structures stored thereon. A component can communicate through local and / or remote processes according to, for example, signals having one or more data packets (e.g., data from one component that interacts with another component via signals across a network such as a local system, a distributed system, and / or the Internet). As another example, a component can be a device having specific functionality provided by mechanical parts operated by an electrical or electronic circuit and operated by software or a firmware application executed by a processor. In such a case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a component can be a device that provides specific functionality through electronic components without mechanical parts, and the electronic components can include a processor or other means for executing software or firmware that at least partially provides the functionality of the electronic components. In one aspect, a component can emulate an electronic component via a virtual machine, for example, within a cloud computing system.

[0125] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, "X uses A or B" is satisfied if X uses A, if X uses B, or if X uses both A and B. Further, the articles "a" and "an" used in the specification of the subject matter and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or it is clear from the context that they refer to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean that they function as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Further, any aspect or design described herein as "example" and / or "exemplary" should not necessarily be construed as more preferable or advantageous than other aspects or designs, nor does it mean excluding equivalent exemplary structures and techniques known to those skilled in the art.

[0126] As used in the specification of the subject matter, the term "processor" can refer to substantially any computing processing unit or device having, but not limited to, a single-core processor, a single processor with software multithreading execution capabilities, a multi-core processor, a multi-core processor with software multithreading execution capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Further, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a processor can utilize, but not limited to, nanoscale architectures such as molecular and quantum dot-based transistors, switches, gates, etc. for optimization of area usage or improvement of the performance of user equipment. A processor can also be implemented as a combination of computing processing units.

[0127] In the present disclosure, terms such as "store", "storage", "data store", "data storage", "database", "repository", and substantially any other information storage component related to the operation and function of a component are used to refer to an entity embodied in a "memory component", "memory", or a component that includes a memory. It should be understood that the memory and / or memory components described herein can be either volatile memory or non-volatile memory, or can include both volatile memory and non-volatile memory. By way of example and not limitation, non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include, for example, RAM that can function as an external cache memory. By way of example and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), sync link DRAM (SLDRAM), direct rambus RAM (DRRAM), direct rambus dynamic RAM (DRDRAM), and rambus dynamic RAM (RDRAM). Further, the memory components of the systems or computer-implemented methods disclosed herein are not limited to and are intended to include these and any other suitable types of memory.

[0128] What has been described above includes merely examples of a system, a computer program product, and a computer-implemented method. Of course, for the purpose of describing the present disclosure, it is impossible to describe all possible combinations of components, products, and / or computer-implemented methods. However, those skilled in the art can recognize that many more combinations and permutations of the present disclosure are possible. Further, in the detailed description, claims, appendices, and drawings, to the extent that the terms "includes", "has", "possesses", and similar terms are used, such terms are construed as "comprising" when used as transitional words in the claims, and are intended to be inclusive in the same manner as the term "comprising".

[0129] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been chosen in order to best explain the principles of the embodiments, the practical application, or a technical improvement beyond the technology found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

Claims

1. A processor that executes computer-executable components stored in a memory, the computer-executable components having a compile component that, after an operation on one or more qubits and before reading, encodes the one or more qubits according to a cyclic repetition code at once A system comprising.

2. The computer-executable components further comprise a branch identification component that identifies a first chain of auxiliary qubits coupled to a particular qubit among the one or more qubits, a second chain of auxiliary qubits coupled to the particular qubit, and a flag qubit that joins the first chain of the auxiliary qubits and the second chain of the auxiliary qubits, and encoding the one or more qubits comprises encoding the first chain of the auxiliary qubits using iterative encoding; and encoding the second chain of the auxiliary qubits using the iterative encoding Encoding the specific qubit, the system according to claim 1.

3. The one or more qubits have a plurality of qubits, and encoding comprises cyclic iterative encoding of a first qubit among the plurality of qubits and a second qubit among the plurality of qubits in parallel and independently of each other, the system according to claim 1 or 2.

4. The quantum hardware further comprises a monitoring component that measures the state of the flag qubit, the state representing one of incorrect encoding or error-free encoding of the particular qubit, the system according to claim 2.

5. A controlled NOT (CNOT) gate couples the flag qubit and the auxiliary qubit at the end of the first chain of the auxiliary qubits, and a second CNOT couples the flag qubit to the auxiliary qubit at the end of the second chain of the auxiliary qubits, the system according to claim 2.

6. The particular qubit, the first chain of the auxiliary qubits, the second chain of the auxiliary qubits, and the flag qubit are arranged in a layout having a cyclic connection, the system according to claim 2.

7. The system according to any one of claims 1 to 6, wherein the one or more qubits are included in a qubit layout showing a kagome connectivity.

8. The system according to any one of claims 1 to 7, wherein the one or more qubits constitute a quantum processor of one of a cloud-based quantum computer or a local quantum computer.

9. A computer-implemented method comprising, after an operation on one or more qubits and before readout, encoding the one or more qubits according to a cyclic repetition code at once by a processor.

10. The processor further comprises identifying a first chain of auxiliary qubits coupled to a specific qubit among the one or more qubits, a second chain of auxiliary qubits coupled to the specific qubit, and a flag qubit joining the first chain of the auxiliary qubits and the second chain of the auxiliary qubits, wherein the step of encoding the one or more qubits is encoding the first chain of the auxiliary qubits according to iterative encoding; and encoding the second chain of the auxiliary qubits according to iterative encoding to encode the specific qubit. The computer-implemented method according to claim 9.

11. The one or more qubits have a plurality of qubits, and the step of encoding the one or more qubits has a step of encoding a first qubit among the plurality of qubits and a second qubit among the plurality of qubits in parallel and independently of each other. The computer-implemented method according to claim 9 or 10.

12. The processor further comprises a step of causing a quantum hardware to measure a state of the flag qubit, the state representing one of an incorrect encoding or a correct encoding of the specific qubit. The computer-implemented method according to claim 10.

13. The computer-implemented method according to any one of claims 9 to 12, further comprising applying, by the processor, a step of encoding the one or more qubits in a quantum calculation of time propagation of a quantum observable quantity.

14. The computer-implemented method according to any one of claims 9 to 13, further comprising applying, by the processor, a step of encoding the one or more qubits in a variational quantum algorithm.

15. The computer-implemented method according to claim 10, wherein the specific qubit, the first chain of auxiliary qubits, the second chain of auxiliary qubits, and the flag qubit are arranged in a layout having a cyclic connection.

16. A computer program for reducing a readout error in quantum computing, the computer program comprising program instructions, the program instructions causing a processor to, after an operation on a plurality of qubits and before readout, encode one or more qubits according to a cyclic repetition code at once such that the computer program is executable by the processor.

17. The program instructions are further executable by the processor to cause the processor to identify a first chain of auxiliary qubits coupled to a specific qubit among the one or more qubits, a second chain of auxiliary qubits coupled to the specific qubit, and a flag qubit that joins the first chain of auxiliary qubits and the second chain of auxiliary qubits, and encoding the one or more qubits is encoding the first chain of auxiliary qubits using iterative encoding; and encoding the second chain of auxiliary qubits using the iterative encoding to encode the specific qubit, the computer program according to claim 16.

18. The one or more qubits have a plurality of qubits, and encoding the one or more qubits comprises encoding a first qubit among the plurality of qubits and a second qubit among the plurality of qubits in parallel. The computer program according to claim 16 or 17.

19. The program instructions are further executable by the processor to cause the processor to cause the quantum hardware to measure the state of the flag qubit, and the state represents one of an incorrect encoding or a correct encoding of the plurality of qubits. The computer program according to claim 17.

20. The specific qubit, the first chain of auxiliary qubits, the second chain of auxiliary qubits, and the flag qubit are arranged in a layout having a circular connection. The computer program according to claim 17.

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