Semiconductor device and method of manufacturing the same

Abstract

An embodiment of the present application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device may include a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and the thickness of the first dielectric layer in a first region is greater than the thickness of the first dielectric layer in a second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate. The second gate structure is formed on the side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first region and the second region. In this way, the capacitance between the second gate structure and the drain is reduced and the capacitance between the field plate and the channel is increased, thereby reducing the parasitic capacitance of the device and improving the gain characteristics of the device at high frequencies.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more particularly, to semiconductor devices and methods of manufacturing the same.

Background Art

[0002] In some applications, radio frequency devices are required to have good gain characteristics at high frequencies. For example, third-generation compound semiconductor materials represented by gallium nitride (GaN) and silicon carbide (SiC) have attracted wide attention due to their excellent material properties. Gallium nitride-based devices are widely used in the field of radio frequency devices because of advantages such as high mobility, strong breakdown resistance, and excellent heat dissipation. However, gallium nitride-based radio frequency devices have high exponential requirements for high-frequency gain characteristics.

[0003] The gain characteristics of radio frequency devices at high frequencies mainly depend on whether the parasitic capacitors of the radio frequency devices can perform efficient and high-speed charging and discharging operations based on signals in a high-frequency operating state. Therefore, without changing another design structure of the radio frequency device, by reducing the capacitance value of the parasitic capacitor, the gain characteristics of the radio frequency device at high frequencies can be effectively improved. Currently, the parasitic capacitance of radio frequency devices can be adjusted by changing the thickness or dielectric constant of the dielectric layer. However, in this adjustment method, other adverse effects such as electrostatic breakdown are likely to occur.

Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor device and a method of manufacturing the same. By adjusting the structure of the semiconductor device, the parasitic capacitance of the radio frequency device can be reduced, and the gain characteristics of the radio frequency device at high frequencies can be improved.

[0005] According to a first aspect, an embodiment of the present application provides a semiconductor device including a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and the thickness of the first dielectric layer in a first region is greater than the thickness of the first dielectric layer in a second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate, and the second gate structure is formed on the side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and disposed in both the first region and the second region. In this way, compared with the capacitance in a semiconductor device having a first dielectric layer with an equal thickness, in this semiconductor device, since the thickness of the first dielectric layer in the first region is large, the capacitance between the second gate structure and the drain is reduced, and since the thickness of the first dielectric layer in the second region is small, the capacitance between the field plate and the channel increases. Therefore, the parasitic capacitance of the semiconductor device is reduced, and the gain characteristics of the semiconductor device at high frequencies are improved. In addition, with this design, the electric field stress inside the device can be further adjusted. Since the thickness of the first dielectric layer in the first region is large, the electric field peak in the second gate structure is weakened, and the overall robustness of the device is improved.

[0006] In some possible implementations, the semiconductor device further includes a source and a drain located on the substrate. The gate is located between the source and the drain. The field plate faces, in a direction perpendicular to the surface of the substrate, the portion of the gate facing the drain and extends to the drain. The portion of the field plate located in the second region is electrically connected to the source.

[0007] In this embodiment of the present application, the semiconductor device may further include a source and a drain. The field plate is connected to the source and extends to the drain to modulate the electric field and capacitance distribution between the source and the drain, thereby implementing a specific indicator of high-frequency gain.

[0008] In some possible implementations, the first dielectric layer includes a first sub-film layer and a second sub-film layer.

[0009] The first sub-film layer covers the substrate, and the second sub-film layer is located in a first region on the first sub-film layer, or the first sub-film layer is located on the substrate and in the first region, and the second sub-film layer covers the first sub-film layer and the substrate that is within a second region and outside the first sub-film layer.

[0010] In this embodiment of the present application, the first dielectric layer may include a multilayer structure, where the first region is thick. Thus, the thickness of the first dielectric layer in the first region is greater than the thickness of the first dielectric layer in the second region. In this way, the parasitic capacitance of the semiconductor device is reduced, and the gain characteristics of the semiconductor device at high frequencies are improved.

[0011] In some possible implementations, the material of at least one of the first sub-film layer and the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0012] In this embodiment of the present application, in order to better control the dielectric constant of the first dielectric layer, the materials of the first sub-film layer and the second sub-film layer may be set.

[0013] In some possible implementation forms, the substrate includes a base and an epitaxial layer. The epitaxial layer is disposed facing the gate. The material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire. The epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride.

[0014] In this embodiment of the present application, the substrate may include a base and an epitaxial layer, and the epitaxial layer can be used as a functional layer so that the semiconductor device has a personalized function.

[0015] In some possible implementation forms, the material of the gate and / or the field plate is at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, and copper.

[0016] In this embodiment of the present application, in order to achieve better conductivity of the gate and the field plate, the materials of the gate and the field plate can be set.

[0017] In some possible implementation forms, the material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0018] In this embodiment of the present application, in order to achieve better insulation of the second dielectric layer, the material of the second dielectric layer can be set.

[0019] According to a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including: providing a substrate; Forming a first dielectric layer and a gate on a substrate, wherein the gate is located on the substrate and in a first region, the thickness of the first dielectric layer in the first region being greater than the thickness of the first dielectric layer in a second region outside the first region, the gate including a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate, the first gate structure penetrating the first dielectric layer in a direction perpendicular to the surface of the substrate, and the second gate structure being formed on the side of the first dielectric layer away from the substrate and covering a part of the first dielectric layer; Forming a second dielectric layer covering the gate and the first dielectric layer; and Forming a field plate on the second dielectric layer, the field plate being disposed in both the first region and the second region.

[0020] In some possible implementation forms, a source and a drain are further formed on the substrate, the gate is located between the source and the drain, the field plate faces the portion of the gate facing the drain and extends to the drain in a direction perpendicular to the surface of the substrate, and the portion of the field plate located in the second region is electrically connected to the source.

[0021] In some possible implementation forms, the first dielectric layer includes a first sub-film layer and a second sub-film layer, and the step of forming the first dielectric layer and the gate on the substrate includes: Sequentially forming a first sub-film layer and a second sub-material layer on the substrate; Etching the second sub-material layer and the first sub-film layer in the first region to obtain a first via; Forming a first gate structure located inside the first via and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer; and A step of etching and removing a second sub-material layer outside the second gate structure by using the second gate structure as a mask, wherein the second sub-material layer located in the first region is used as a second sub-film layer.

[0022] In this embodiment of the present application, by using the first sub-film layer as an etching stop layer and the second gate structure as a hard self-aligned mask, the second sub-material layer can be etched without adding sequential photolithography processes. Thereby, the cost can be reduced.

[0023] In some possible implementations, the step of forming a first dielectric layer and a gate on a substrate includes the following: A step of forming a first dielectric layer on the substrate; A step of etching the first dielectric layer in the first region to obtain a second via; A step of forming a first gate structure located inside the second via and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer; and A step of thinning the first dielectric layer in a second region outside the first region to form the first dielectric layer.

[0024] In this embodiment of the present application, by using the second gate structure as a hard self-aligned mask, the second sub-material layer can be etched without adding sequential photolithography processes. Thereby, the cost can be reduced.

[0025] In some possible implementations, the first dielectric layer includes a first sub-film layer and a second sub-film layer, and the step of forming a first dielectric layer and a gate on a substrate includes the following: A step of forming a first sub-material layer on the substrate; A step of removing the first sub-material layer in a second region outside the first region and using the first sub-material layer located in the first region as the first sub-film layer; Forming a first sub-film layer and a second sub-film layer covering the substrate; Etching the second sub-film layer and the first sub-film layer in the first region to obtain a third via; and Forming a first gate structure located inside the third via and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer.

[0026] In this embodiment of the present application, first, the first sub-film layer in the first region may be formed, and then, the second sub-film layer is covered to obtain a flat second sub-film layer.

[0027] In some possible implementations, the first dielectric layer includes the first sub-film layer and the second sub-film layer, and the step of forming the first dielectric layer and the gate on the substrate includes the following: Forming a first sub-film layer in a first region on the substrate by using a two-layer photoresist patterning process; Forming a first sub-film layer and a second sub-film layer covering the substrate; Etching the second sub-film layer and the first sub-film layer in the first region to obtain a third via; and Forming a first gate structure located inside the third via and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer.

[0028] In this embodiment of the present application, in order to help obtain the second sub-film layer accurately located under the second gate structure, first, the first sub-film layer may be formed, and then, the second sub-film layer located in the first region and on the first sub-film layer is formed.

[0029] In some possible implementation forms, the material of the first sub-film layer and / or the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0030] In some possible implementation forms, the substrate includes a base and an epitaxial layer. The material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire, and the epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride.

[0031] In some possible implementation forms, the material of the gate and / or the field plate is at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, and copper.

[0032] In some possible implementation forms, the material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0033] According to a third aspect, an embodiment of the present application provides an electronic device including a circuit board and a semiconductor device connected to the circuit board and provided in the first aspect of the present application.

[0034] From the above technical solutions, it can be seen that the embodiments of the present application have the following advantages:

[0035] Embodiments of the present application provide a semiconductor device and a method of manufacturing the same. The semiconductor device may include a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and the thickness of the first dielectric layer in a first region is greater than the thickness of the first dielectric layer in a second region outside the first region. The gate is located on the substrate and in the first region, and the gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate, and the second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and disposed in both the first region and the second region. In this way, compared with a semiconductor device having a first dielectric layer of equal thickness, in this semiconductor device, since the thickness of the first dielectric layer in the first region is large, the capacitance between the second gate structure and the drain is reduced, and since the thickness of the first dielectric layer in the second region is small, the capacitance between the field plate and the channel increases, so the parasitic capacitance of the semiconductor device is reduced and the gain characteristics of the semiconductor device at high frequencies are improved. In addition, with this design, the electric field stress inside the device can be further adjusted. Since the thickness of the first dielectric layer in the first region is large, the electric field peak in the second gate structure is weakened, and the overall robustness of the device is improved.

Brief Description of the Drawings

[0036] For a clear understanding of specific implementations of the present application, the following briefly describes the accompanying drawings for explaining specific implementations of the present application. It is obvious that the accompanying drawings merely show some embodiments of the present application.

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Embodiments for Carrying Out the Invention

[0037] Embodiments of the present application provide a semiconductor device and a method for manufacturing the same. By adjusting the structure of the semiconductor device, the parasitic capacitance of the radio frequency device can be reduced, and the gain characteristics of the radio frequency device at high frequencies can be improved.

[0038] In the specification, claims, and appended drawings of this application, terms such as "first", "second", "third", "fourth", etc. (if any) are for the purpose of distinguishing similar objects and do not necessarily indicate a particular order or sequence. Data called in such a way is interchangeable in appropriate circumstances. Thus, it should be understood that the embodiments described in this specification can be implemented in an order other than the order exemplified or described in this specification. Further, the terms "include", "contain" and any other variations mean covering non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units is not necessarily limited to the explicitly listed steps or units, and may include other steps or units not explicitly listed or that are specific to such a process, method, product, or device.

[0039] This application will be described in detail with reference to schematic diagrams. For ease of explanation, when embodiments of this application are described, the cross-sectional views of the device structure are not partially enlarged according to a general ratio. The schematic diagrams are merely examples and should not limit the protection scope of this application in this specification. In addition, during actual manufacturing, a three-dimensional space of length, width, and depth should be included.

[0040] Currently, in some scenarios, radio frequency devices are required to have good gain characteristics at high frequencies. The gain characteristics of radio frequency devices at high frequencies mainly depend on whether the parasitic capacitors of the radio frequency devices can perform efficient and high-speed charging and discharging operations based on signals in the high-frequency operating state. Therefore, without changing another design structure of the radio frequency device, by reducing the capacitance value of the parasitic capacitor, the gain characteristics of the radio frequency device at high frequencies can be effectively improved.

[0041] FIG. 1 is a schematic diagram of the structure of a radio frequency device according to an embodiment of the present application. The radio frequency device includes a substrate 100, a first dielectric layer 210 on the substrate 100, a gate 220 penetrating the first dielectric layer 210 and covering a part of the first dielectric layer 210, a second dielectric layer 230 covering the gate 220 and the first dielectric layer 210, and a field plate 240 located on the second dielectric layer 230. The substrate 100 includes a source 101 and a drain 102. The field plate 240 is located on the side of the gate 220 facing the drain 102, extends above the gate 220, and the field plate 240 is connected to the source 101. Factors determining the parasitic capacitance of the radio frequency device include a parasitic capacitance C1 between the bottom of the gate 220 and the drain 102, a parasitic capacitance C2 between the portion of the gate 220 located on the first dielectric layer 210 and the drain 102, and a parasitic capacitance C3 between the field plate 204 and the channel under the gate 220. In order to reduce the overall parasitic capacitance of the radio frequency device, it is necessary to reduce C1 and C2 and increase C3. The parasitic capacitances C1, C2, and C3 can be adjusted by changing the thickness or dielectric constant of the dielectric layer. However, the inventors have found through research that this adjustment method is likely to cause other adverse effects, such as electrostatic breakdown.

[0042] Specifically, when the thickness of the first dielectric layer 210 is increased and the dielectric constant of the first dielectric layer 210 is reduced, the parasitic capacitance C2 between the portion of the gate 220 located on the first dielectric layer 210 and the drain 102 can be reduced, and the parasitic capacitance C3 between the field plate 240 and the channel can also be reduced, but the overall parasitic capacitance of the device cannot be reduced. However, when the thickness of the second dielectric layer 230 is decreased and the dielectric constant of the second dielectric layer 230 is increased, the parasitic capacitance C3 between the field plate 240 and the channel increases, and there is also a possibility of causing deterioration of the breakdown voltage characteristics between the gate 220 and the field plate 240.

[0043] FIG. 2 is a schematic diagram of a lateral electric field stress distribution according to an embodiment of the present application. The horizontal coordinate is the position along the surface of the substrate, and the vertical coordinate is the electric field stress at each position in the high-voltage reverse bias stress state. The first electric field peak is at the bottom of the gate and may correspond to the end close to the drain 102. The second electric field peak is at the upper part of the first dielectric layer 210 and may correspond to the end close to the drain 102. The third electric field peak may correspond to the end of the field plate 140 close to the drain 102. As can be seen from the figure, the second electric field peak is the highest. Therefore, under continuous high electric field stress, when the thickness of the first dielectric layer 210 is small, the first dielectric layer 110 under the gate and at the position corresponding to the electric field peak is susceptible to time dependent dielectric breakdown (TDDB) and has a high reliability risk. Therefore, in order to improve the reliability of the device, it is necessary to reduce C2.

[0044] Based on the above technical problems, embodiments of the present application provide a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and the thickness of the first dielectric layer in the first region is greater than the thickness of the first dielectric layer in the second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate, and the second gate structure is formed on the side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and is disposed in both the first region and the second region. In this way, compared with the capacitance in a semiconductor device having a first dielectric layer of equal thickness, in this semiconductor device, since the thickness of the first dielectric layer in the first region is large, the capacitance between the second gate structure and the drain is reduced, and since the thickness of the first dielectric layer in the second region is small, the capacitance between the field plate and the channel increases. Therefore, the parasitic capacitance of the semiconductor device is reduced, and the gain characteristics of the semiconductor device at high frequencies are improved. In addition, with this design, the electric field stress inside the device can be further adjusted. Since the thickness of the first dielectric layer in the first region is large, the electric field peak in the second gate structure is weakened, and the overall robustness of the device is improved.

[0045] To make the above objects, features, and advantages of the present application clearer and easier to understand, the following will describe specific implementation forms of the present application in detail with reference to the accompanying drawings.

[0046] FIG. 3A, FIG. 3B, and FIG. 3C are schematic diagrams of the structure of a semiconductor device according to an embodiment of the present application. The semiconductor structure includes a substrate 100, a gate 120, a first dielectric layer 110, a second dielectric layer 130, and a field plate 140.

[0047] In this embodiment of the present application, the substrate 100 can be designed based on various device requirements. Specifically, the substrate 100 can include a base and an epitaxial layer. The epitaxial layer is formed on the surface of the base and is disposed toward the gate 120. The base can be one or more of a semiconductor substrate, such as gallium nitride (GaN), aluminum nitride (AlN), silicon (Si), silicon carbide (SiC), and sapphire. The base may provide a support function for the semiconductor device or may form part of the functional layer of the semiconductor device. The epitaxial layer can be a film layer obtained by epitaxial growth on the base and is usually a functional layer constituting the semiconductor device, and can be, for example, one or more of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), and scandium aluminum nitride (ScAlN). The materials of the base and the epitaxial layer may be the same or different. The silicon carbide substrate can have a single crystal structure and can have multiple structure types, such as 4H-silicon carbide, 6H-silicon carbide, and 3C-silicon carbide.

[0048] For example, when the semiconductor device is a high-electron-mobility transistor (HEMT) device based on gallium nitride, the base can be a silicon carbide material, and the epitaxial layer can include gallium nitride and aluminum gallium nitride. Gallium nitride and aluminum gallium nitride form a heterostructure to generate a two-dimensional electron gas, and the formed semiconductor device can operate by using the two-dimensional electron gas generated by the heterostructure. Of course, the semiconductor device in this embodiment of the present application can alternatively be another radio frequency device, and the base and the epitaxial layer can also be designed correspondingly.

[0049] The substrate 100 has a first dielectric layer 110, and the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the first dielectric layer 110 in the second region outside the first region. The first region is a region on the substrate and includes a space defined by the surface of the substrate and a plurality of straight lines perpendicular to the surface of the substrate. The first region is a region used to form a gate and may be a central region of the region where the source and drain are located. The first region may be larger than the region where the gate is located or may be equal to the region where the gate is located. Refer to FIGS. 3A, 3B, and 3C. The central dashed box represents the first region 1001, and the dashed boxes on both sides of the first region 1001 represent the second region 1002. Since FIGS. 3A, 3B, and 3C are cross-sectional views, the second region 1002 may actually be located on both sides of the first region 1001 or may form a ring region surrounding the first region 1001, for example, a circular ring region or a polygonal ring region.

[0050] In this embodiment of the present application, the first dielectric layer 110 may be a plurality of stacked layers of films or may be an integrated structure of one layer of film. The one layer of film may contain a plurality of materials or may contain one material.

[0051] Specifically, the first dielectric layer 110 may have an integrated structure, and the first dielectric layer 110 in the second region outside the first region is thinned by etching so that the first dielectric layer 110 has a small thickness. Please refer to FIG. 3A. In the thinning process, the sidewall at the boundary between the first region and the second region may not be strictly steep, and the sidewall may be located in the first region. The first region may be equal to the region where the gate 120 is located, or may be slightly larger than the region where the gate 120 is located. The thickness range of the first dielectric layer 110 in the first region may be 40 nm to 1000 nm, and the thickness range of the first dielectric layer 110 in the second region outside the first region may be 20 nm to 500 nm. The material of the first dielectric layer 110 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0052] Specifically, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. Referring to FIG. 3B, the first sub-film layer 112 is located in a first region on the substrate 100, and the second sub-film layer 113 covers the first sub-film layer 112 and the substrate 100 in a second region outside the first sub-film layer 112. Thus, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the first dielectric layer 110 in a second region outside the first region is the thickness of the first sub-film layer 112. Specifically, the portion of the second sub-film layer 113 that covers the sidewall of the first sub-film layer 112 is located in the first region and may define a large thickness of the first region. In this case, the size of the first sub-film layer 112 in the direction along the surface of the substrate is smaller than the size of the first region in the direction along the surface of the substrate. In this case, the first region may be larger than the region where the gate is located, the thickness range of the first sub-film layer 112 may be 20 nm to 500 nm, the material of the first sub-film layer 112 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The thickness range of the second sub-film layer 113 may be 20 nm to 500 nm, and the material of the second sub-film layer 113 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0053] Specifically, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. Refer to FIG. 3C. The first sub-film layer 112 covers the substrate 100, and the second sub-film layer 113 is located in a first region on the first sub-film layer 112. Thus, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the first dielectric layer 110 in a second region outside the first region is the thickness of the second sub-film layer 113, and the second sub-film layer 113 may have sidewalls that are not strictly steep enough. In this case, the sidewalls may be located in the first region. The thickness range of the first sub-film layer 112 may be 20 nm to 500 nm, and the material of the first sub-film layer 112 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The thickness range of the second sub-film layer 113 may be 20 nm to 500 nm, and the material of the second sub-film layer 113 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0054] A gate 120 is formed in the first region. The gate 120 includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates a first dielectric layer 110 on the substrate 100. Since the gate 120 is located in the first region, the first gate structure penetrates a thicker portion of the first dielectric layer 110. The second gate structure is formed on the first dielectric layer 110 (upward in FIGS. 3A, 3B, and 3C). Specifically, the second gate structure is formed on the side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer. In this case, the size of the second gate structure in the direction parallel to the surface of the substrate is larger than the size of the first gate structure in the direction parallel to the surface of the substrate. In other words, the first gate structure and the second gate structure can form a T-shaped structure. The first gate structure is connected to the substrate 100, and the second gate structure helps to maintain the balance of the electric field and capacitance inside the device. In addition, a gate dielectric layer may be further formed under the gate 120, and the gate dielectric layer is formed between the epitaxial layer and the first gate structure.

[0055] The substrate 100 may further include a source 101 and a drain 102. The source 101 and the drain 102 are located on both sides of the gate 120 respectively. The channel region is included between the source 101 and the drain 102. The channel region is used to form a conductive channel when the device operates. The first region is located above the channel region, and the gate 120 is also located above the channel region. The gate 120 may have excellent conductivity, and the material of the gate 120 may be at least one of nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), and copper (Cu). A parasitic capacitor C1 exists between the first gate structure in the gate 120 and the drain 102, and the parasitic capacitor C1 is related to the size of the first gate structure. A parasitic capacitor C2 exists between the second gate structure in the gate 120 and the drain 102, and the parasitic capacitor C2 is related to the thickness and dielectric constant of the first dielectric layer 110 under the second gate structure.

[0056] The second dielectric layer 130 may cover the gate 120 and the first dielectric layer 110. The second dielectric layer 130 may protect the gate 120 or may be used as an isolation layer. The material of the second dielectric layer 130 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide, and the thickness range of the second dielectric layer 130 may be from 20 nm to 500 nm.

[0057] The field plate 140 is located on the second dielectric layer 130. The field plate 140 faces the drain-facing portion of the gate in the direction perpendicular to the surface of the substrate and may extend to the drain. In other words, the field plate 140 is located on the drain-facing side of the second gate structure and may extend above the second gate structure (upward in FIGS. 3A, 3B, and 3C). The portion of the field plate 140 located in the second region is electrically connected to the source 101 (see the field plate 140 on the source 101 in FIGS. 3A, 3B, and 3C, where the field plate 140 on the source 101 is an integrated structure with the field plate 140 above the gate 120), and is configured to modulate the electric field and capacitance distribution between the source and the drain to implement a specific indicator of the high-frequency gain. The material of the field plate 140 is at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. The material of the field plate 140 and the material of the gate 120 may be the same or different. The thickness range of the field plate 140 is from 20 nm to 1500 nm. When the device operates, there is a parasitic capacitor C3 between the field plate 140 and the conductive channel under the field plate 140. This parasitic capacitor affects the overall parasitic capacitor of the device and is related to the thickness and dielectric constant of the first dielectric layer 110 under the field plate 140 and the thickness and dielectric constant of the second dielectric layer 130 under the field plate 140.

[0058] In this embodiment of the present application, the first dielectric layer 110 is thicker in the first region and thinner in the second region outside the first region. Specifically, the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the first dielectric layer 110 in the second region outside the first region. In this way, without affecting the parasitic capacitance C3 between the field plate 140 and the conductive channel, the capacitance C2 between the second gate structure and the drain 102 can be reduced. Therefore, the overall parasitic capacitance of the device can be effectively reduced. In addition, since the thickness of the first dielectric layer 110 in the first region is large, the potential and electric field distribution at the end of the gate 120 close to the drain 102 are adjusted, and the electric field stress at the position where the TDDB failure is likely to occur is effectively weakened, so that the overall robustness of the device can be improved.

[0059] FIG. 4 is a schematic diagram of another lateral electric field stress distribution according to an embodiment of the present application. The horizontal coordinate is the position along the surface of the substrate, and the vertical coordinate is the electric field stress at each position in the high-voltage reverse bias stress state. The first electric field peak may correspond to the end of the first gate structure close to the drain 102, the second electric field peak may correspond to the end of the second gate structure close to the drain 102, the third electric field peak may correspond to the end of the bottom layer of the field plate 140 close to the gate 120, and the fourth electric field peak may correspond to the end of the bottom layer of the field plate 140 close to the drain. It can be seen from the figure that the second electric field peak is weakened, and as a result, the risk of TDDB failure is reduced.

[0060] One embodiment of the present application provides a semiconductor device including a substrate, a gate, a second dielectric layer, and a field plate. The substrate has a first dielectric layer, and the thickness of the first dielectric layer in a first region is greater than the thickness of the first dielectric layer in a second region outside the first region. The gate is located on the substrate and in the first region, and the gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate, and the second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and disposed in both the first region and the second region. In this way, compared with the capacitance in a semiconductor device having a first dielectric layer of equal thickness, in this semiconductor device, since the thickness of the first dielectric layer in the first region is large, the capacitance between the second gate structure and the drain is reduced, and since the thickness of the first dielectric layer in the second region is small, the capacitance between the field plate and the channel increases. Therefore, the parasitic capacitance of the semiconductor device is reduced, and the gain characteristics of the semiconductor device at high frequencies are improved. In addition, with this design, the electric field stress inside the device can be further adjusted. Since the thickness of the first dielectric layer in the first region is large, the electric field peak in the second gate structure is weakened, and the overall robustness of the device is improved.

[0061] Based on the semiconductor device provided in the embodiment of the present application, one embodiment of the present application further provides a method for manufacturing a semiconductor device. FIG. 5 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. This method may include the following steps.

[0062] S101: Provide a substrate 100. Refer to FIG. 6.

[0063] In this embodiment of the present application, the substrate 100 can be designed based on various device requirements. Specifically, the substrate 100 can include a base and an epitaxial layer. The epitaxial layer is formed on the surface of the base and is disposed toward the gate 120. The base can be one or more of semiconductor substrates such as GaN, AlN, Si, SiC, and sapphire. The base may provide a support function for the semiconductor device or may constitute a part of the functional layer of the semiconductor device. The epitaxial layer can be a film layer obtained by epitaxial growth on the base and is usually a functional layer constituting the semiconductor device and can be one or more of, for example, GaN, AlGaN, InAlN, AlN, and ScAlN. The materials of the base and the epitaxial layer may be the same or different. The silicon carbide substrate can have a single crystal structure and can have a plurality of structure types such as 4H-silicon carbide, 6H-silicon carbide, and 3C-silicon carbide.

[0064] In the gate last process, the source and the drain can be formed before the gate 120, and the substrate 100 can further include a source 101 and a drain 102. A channel region is included between the source 101 and the drain 102. The channel region is used to form a conductive channel when the device operates. The source 101 and the drain 102 can be obtained by doping the substrate 100.

[0065] S102: Form a first dielectric layer on the substrate 100 and form a gate 120 in a first region on the substrate 100. Here, the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the first dielectric layer 110 in a second region outside the first region, and the gate 120 includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. Please refer to FIGS. 7-10, FIGS. 12-15, and FIGS. 17-22.

[0066] In this embodiment of the present application, a first dielectric layer 110 may be formed on a substrate 100, and the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the first dielectric layer 110 in a second region outside the first region. The first region may be a region used to form a gate and may be a central region of a region where a source and a drain are located. The first region may be larger than the region where the gate is located or may be equal to the region where the gate is located. The first dielectric layer 110 may be formed before the gate 120 or may be formed in the process of forming the gate 120.

[0067] In this embodiment of the present application, a gate 120 is formed in the first region. The gate 120 includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer 110 on the substrate 100. Since the gate 120 is located in the first region, the first gate structure penetrates the thicker portion of the first dielectric layer 110. The second gate structure is formed on the first dielectric layer 110 (upward in FIGS. 3A, 3B, and 3C). In this case, the size of the second gate structure in the direction parallel to the surface of the substrate is larger than the size of the first gate structure in the direction parallel to the surface of the substrate. In other words, the first gate structure and the second gate structure may form a T-shaped structure. A gate dielectric layer may be further formed under the gate 120, and the gate dielectric layer is formed between the epitaxial layer and the first gate structure. The gate 120 may have excellent conductivity, and the material of the gate 120 may be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. There is a parasitic capacitor C1 between the first gate structure in the gate 120 and the drain 102, and the parasitic capacitor is related to the size of the first gate structure. There is a parasitic capacitor C2 between the second gate structure in the gate 120 and the drain 102, and the parasitic capacitor C2 is related to the thickness and dielectric constant of the first dielectric layer 110 under the second gate structure.

[0068] In this embodiment of the present application, the first dielectric layer 110 is thicker in the first region and thinner in the second region outside the first region. Specifically, the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the first dielectric layer 110 in the second region outside the first region. In this way, the capacitance between the second gate structure and the drain 102 can be reduced without affecting the parasitic capacitances at other positions. Therefore, the overall parasitic capacitance of the device can be effectively reduced. In addition, since the thickness of the first dielectric layer 110 in the first region is large, the potential and electric field distribution at the end of the gate 120 close to the drain 102 can be adjusted to effectively weaken the electric field stress at the position where TDDB failure is likely to occur, and the overall robustness of the device can be improved.

[0069] In this embodiment of the present application, the first dielectric layer 110 may be a plurality of stacked films or an integrated structure of a single-layer film. The single-layer film may contain a plurality of materials or a single material.

[0070] In a possible method of forming the first dielectric layer 110 and the gate 120, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. In this case, first, the first sub-film layer 112 and the second sub-material layer 113' are continuously deposited on the substrate 100. Refer to FIG. 7. The thickness range of the first sub-film layer 112 can be 20 nm to 500 nm, and the material of the first sub-film layer 112 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The thickness range of the second sub-material layer 113' can be 20 nm to 500 nm, and the material of the second sub-material layer 113' can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The first sub-film layer 112 and the second sub-material layer 113' can have different refractive indices, densities, and etching resistances. The first sub-film layer 112 and the second sub-material layer 113' may be the same material or different materials. When the first sub-film layer 112 and the second sub-material layer 113' have the same material layer, the first sub-film layer 112 and the second sub-material layer 113' have different deposition temperatures, whereby the first sub-film layer 112 and the second sub-material layer 113' have different refractive indices, densities, and etching resistances.

[0071] Next, the second sub-material layer 113' and the first sub-film layer 112 in the first region can be etched to obtain the first via 119. Refer to FIG. 8. The second sub-material layer 113' and the first sub-film layer 112 can be etched by using a photolithography process. The etching method can be anisotropic dry etching or wet etching. The first via 119 is located in the first region and exposes the substrate 100 within the first region. When the gate dielectric layer is formed on the substrate 100, the first via 119 can expose the gate dielectric layer.

[0072] Next, a first gate structure located inside the first via 119 and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer are formed to obtain a gate 120. Refer to FIG. 9. The first gate structure and the second gate structure can be formed by deposition and etching. Specifically, a conductor material can be deposited to fill the first via 119 and cover the first via 119. The thickness range of the conductor material can be 20 nm to 1500 nm, and the conductor material can be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. Then, the conductor material outside the first region can be removed to form the gate 120 located in the conductor region.

[0073] Next, by using the second gate structure as a mask, the second sub-material layer 113' outside the second gate structure can be etched and removed. Here, the second sub-material layer 113' located in the first region is used as the second sub-film layer 113. Refer to FIG. 10. Since there is an etching resistance difference between the first sub-film layer 112 and the second sub-material layer, the first sub-film layer 112 is used as an etching stop layer, and the second sub-material layer 113' is etched by using the second gate structure as a hard self-aligned mask to obtain the second sub-film layer 113. The etched surface remains at the position between the first sub-film layer 112 and the second sub-material layer 113', the etched thickness is the thickness of the second sub-material layer 113', and the etching method can be anisotropic dry etching or wet etching. Since the second gate structure can be used as a mask, there is no need to add a sequential photolithography process, and costs can be saved. It is obvious that the etching of the second sub-material layer 113' may alternatively be performed by using a photolithography process before the first gate structure and the second gate structure are formed. Details are not described herein.

[0074] In other words, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. The first sub-film layer 112 covers the substrate 100, and the second sub-film layer 113 is located in a first region on the first sub-film layer 112. Thus, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the first dielectric layer 110 in a second region outside the first region is the thickness of the second sub-film layer 113. The material of the first sub-film layer 112 and / or the second sub-film layer 113 is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0075] In another possible method of forming the first dielectric layer 110 and the gate 120, first, a first dielectric layer 115 may be deposited on the substrate 100. Refer to FIG. 12. The thickness range of the first dielectric layer 115 may be from 40 nm to 1000 nm, and the material of the first dielectric layer 115 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0076] Next, the first dielectric layer 115 in the first region can be etched to obtain a second via 116. Refer to FIG. 13. The first dielectric layer 115 can be etched by using a photolithography process. The etching method can be anisotropic dry etching or wet etching. The second via 116 is located in the first region and exposes the substrate 100 within the first region. When the gate dielectric layer is formed on the substrate 100, the second via 116 can expose the gate dielectric layer.

[0077] Next, a first gate structure located inside the second via 116 and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer can be formed to form the gate 120. Refer to FIG. 14. The first gate structure and the second gate structure can be formed by deposition and etching. Specifically, a conductor material can be deposited to fill the second via 116 and cover the second via 116. The thickness range of the conductor material can be 20 nm to 1500 nm, and the conductor material can be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. Next, the conductor material outside the first region can be removed to form the gate 120 located in the conductor region.

[0078] Next, the first dielectric layer 115 outside the first region may be etched to remove a portion having a specific thickness within the second region outside the first region of the first dielectric layer 115. That is, the first dielectric layer 115 within the second region is thinned to form the first dielectric layer 110. Refer to FIG. 15. In the etching process, the second gate structure is used as a hard self-aligned mask, and the etched thickness can be controlled by using the etching rate and the etching duration, the thickness range can be 20 nm to 500 nm, and the etching method can be anisotropic dry etching or wet etching. Since the first dielectric layer 110 in the second region outside the first region is thinned by etching, the thickness of the first dielectric layer 110 in the second region is thin. Specifically, the thickness of the first dielectric layer 110 in the first region is the deposited thickness of the first dielectric layer 115, the thickness range of the first dielectric layer 110 in the first region can be 40 nm to 1000 nm, and the thickness range of the first dielectric layer 110 in the second region outside the first region can be 20 nm to 500 nm. Since the second gate structure can be used as a mask, there is no need to add a sequential photolithography process. Thereby, the cost can be reduced. It is obvious that the etching of the first dielectric layer 115 in the second region outside the first region may alternatively be performed by using a photolithography process before the first gate structure and the second gate structure are formed. Details are not described in this specification.

[0079] In yet another possible method of forming the first dielectric layer 110 and the gate 120, the first dielectric layer includes a first sub-film layer 112 and a second sub-film layer 113. In this case, a first sub-material layer 111 is deposited on the substrate 100. Refer to FIG. 17. Next, the first sub-material layer 111 in the second region outside the first region is removed, and the first in the first region 1The sub-material layer 111 is used as the first sub-film layer 112. Refer to FIG. 19. The thickness range of the first sub-material layer 111 is 20 nm to 500 nm, and the material of the first sub-material layer 111 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The first sub-material layer 111 can be etched by using a photolithography process. The etching method can be anisotropic dry etching or wet etching.

[0080] Next, a second sub-film layer 113 covering the first sub-film layer 112 and the substrate 100 can be formed. Refer to FIG. 20. The second sub-film layer 113 can be formed by deposition. The thickness range of the second sub-film layer 113 can be 20 nm to 500 nm, and the material of the second sub-film layer 113 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The second sub-film layer 113 can cover the upper surface and side walls of the first sub-film layer 112, as well as the substrate 100 outside the first sub-film layer 112.

[0081] Next, the second sub-film layer 113 and the first sub-film layer 112 in the first region can be etched to obtain a third via 114. Refer to FIG. 21. The second sub-film layer 113 and the first sub-film layer 112 can be etched by using a photolithography process. The etching method can be anisotropic dry etching or wet etching. The third via 114 is disposed in the first region to expose the substrate 100 in the first region. When the gate dielectric layer is formed on the substrate 100, the third via 114 can expose the gate dielectric layer.

[0082] Next, a first gate structure located inside the third via 114 and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer may be formed to form the gate 120. Refer to FIG. 22. The first gate structure and the second gate structure may be formed by deposition and etching. Specifically, a conductor material may be deposited to fill and cover the third via 114. The thickness range of the conductor material may be from 20 nm to 1500 nm, and the conductor material may be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. Then, the conductor material outside the first region may be removed to form the gate 120 located in the conductor region.

[0083] In yet another possible method of forming the first dielectric layer 110 and the gate 120, the first dielectric layer includes a first sub-film layer 112 and a second sub-film layer 113. The first sub-film layer 112 may be formed on the substrate 100 in the first region by using a two-layer photoresist patterning process. The two-layer photoresist pattern has a large opening and includes a first photoresist 103 located in the lower layer and a second photoresist 104 having a small opening and located in the upper layer. Thus, the position of the first sub-film layer 112 is defined by using the openings in the two-layer photoresist. Refer to FIG. 18. Then, the first sub-film layer 112 may be formed in the openings by using a deposition process. It is clear that a dielectric material is also formed on the photoresist layer during deposition. Refer to FIG. 18. The thickness range of the first sub-film layer 112 may be from 20 nm to 500 nm, and the material of the first sub-film layer 112 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. Then, the two-layer photoresist 103 / 104 and the dielectric material on the two-layer photoresist 103 / 104 may be removed by dry etching or wet etching. Refer to FIG. 19. Then, the first sub-film layer 112 may be cleaned by dry treatment and / or wet treatment.

[0084] Next, a second sub-film layer 113 covering the first sub-film layer 112 and the substrate 100 may be formed. Etch the second sub-film layer 113 and the first sub-film layer 112 in the first region to obtain a third via 114, and form a first gate structure inside the third via 114 and a second gate structure connected to the first gate structure and covering a part of the first dielectric layer. For the formation of the second sub-film layer 113, the formation of the third via, and the formation of the first gate structure and the second gate structure, refer to the foregoing method and FIGS. 20, 21, and 22. Details will not be described again in this specification.

[0085] In other words, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. The first sub-film layer 112 is located in a first region on the substrate 100, and the second sub-film layer 113 covers the first sub-film layer 112 and the substrate 100 in a second region outside the first sub-film layer 112. Thus, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the first dielectric layer 110 in a second region outside the first region is the thickness of the first sub-film layer 112.

[0086] S103: Form a second dielectric layer 130 covering the gate 120 and the first dielectric layer 110. Refer to FIGS. 11, 16, and 23.

[0087] After the gate 120 is formed, a second dielectric layer 130 covering the gate 120 and the first dielectric layer 110 may be formed. The second dielectric layer 130 may protect the gate 120 or be used as a separation layer. The second dielectric layer 130 may be formed by deposition, the material of the second dielectric layer 130 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide, and the thickness range of the second dielectric layer 130 may be 20 nm to 500 nm.

[0088] In the gate-first process, after the second dielectric layer 130 is formed, the second dielectric layer 130 and the first dielectric layer 110 may be etched to expose the source and drain regions of the substrate 100, thereby forming the source 101 and the drain 102.

[0089] S104: Form the field plate 140 on the second dielectric layer 130. Please refer to FIG. 1, FIGS. 3A-3C, and FIG. 4.

[0090] After the second dielectric layer 130 is formed, the field plate 140 may be formed on the second dielectric layer 130. The field plate 140 faces the drain-facing portion of the gate in a direction perpendicular to the surface of the substrate and may extend to the drain. In other words, the field plate 140 is located on the drain-facing side of the second gate structure and may extend above (upward in FIGS. 3A, 3B, and 3C) the second gate structure. The portion of the field plate 140 located in the second region is electrically connected to the source 101 (refer to the field plate 140 on the source 101 in FIGS. 3A, 3B, and 3C, where the field plate 140 on the source 101 is an integrated structure with the field plate 140 above the gate 120), and is configured to modulate the electric field and capacitance distribution between the source and the drain to implement a specific indicator of high-frequency gain. The material of the field plate 140 is at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. The material of the field plate 140 and the material of the gate 120 may be the same or different. The thickness range of the field plate 140 is 20 nm to 1500 nm. When the device operates, there is a parasitic capacitor C3 between the field plate 140 and the conductive channel under the field plate 140. This parasitic capacitor affects the overall parasitic capacitor of the device and is related to the thickness and dielectric constant of the first dielectric layer 110 under the field plate 140, as well as the thickness and dielectric constant of the second dielectric layer 130 under the field plate 140.

[0091] Since the thickness of the region of the first dielectric layer 110 under the second gate structure is greater than the thickness of the first dielectric layer 110 in the second region outside the second gate structure, the capacitance between the second gate structure and the drain 102 can be reduced without affecting the parasitic capacitance between the field plate 140 and the channel. Therefore, the parasitic capacitance of the entire device can be effectively reduced.

[0092] One embodiment of the present application provides a method for manufacturing a semiconductor device. The method includes providing a substrate, and forming a first dielectric layer and a gate on the substrate. The thickness of the first dielectric layer in the first region is greater than the thickness of the first dielectric layer in the second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate. The first gate structure penetrates the first dielectric layer in a direction perpendicular to the surface of the substrate. The second gate structure is formed on the side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer. Then, forming a second dielectric layer covering the gate and the first dielectric layer, and forming a field plate on the second dielectric layer. The field plate is disposed in both the first region and the second region. In this way, compared with the capacitance in a semiconductor device having a first dielectric layer with an equal thickness, in this semiconductor device, since the thickness of the first dielectric layer in the first region is large, the capacitance between the second gate structure and the drain is reduced, and since the thickness of the first dielectric layer in the second region is small, the capacitance between the field plate and the channel increases. Therefore, the parasitic capacitance of the semiconductor device is reduced, and the gain characteristics of the semiconductor device at high frequencies are improved. In addition, with this design, the electric field stress inside the device can be further readjusted. Since the thickness of the first dielectric layer in the first region is large, the electric field peak in the second gate structure is weakened, and the overall robustness of the device is improved.

[0093] Based on the semiconductor device provided in the embodiments of the present application, one embodiment of the present application further provides an electronic device. The electronic device includes a circuit board and a semiconductor device connected to the circuit board. The semiconductor device can be any semiconductor device provided in the foregoing specification. The circuit board can be a printed circuit board (PCB). It is obvious that the circuit board can alternatively be a flexible circuit board (FPC) or the like. The circuit board is not limited in this embodiment. Optionally, the electronic device is different types of user equipment or terminal devices such as a computer, a mobile phone, a tablet computer, a wearable device, and an in-vehicle device. Alternatively, the electronic device can be a network device such as a base station.

[0094] Optionally, the electronic device further includes a package substrate. The package substrate is fixed to the printed circuit board (PCB) by using solder balls, and the semiconductor device is fixed to the package substrate by using solder balls.

[0095] Another aspect of the present application further provides a non-transitory computer-readable storage medium for use with a computer. The computer has software for creating an integrated circuit. The computer-readable storage medium stores one or more computer-readable data structures. The one or more computer-readable data structures have optical mask data for manufacturing the integrated circuit provided in any one of the figures provided in the foregoing specification.

[0096] All embodiments in this specification are described progressively. For the same or similar parts in the embodiments, please refer to these embodiments. Each embodiment focuses on the differences from other embodiments.

[0097] The above is a specific implementation form of this application. It should be understood that the foregoing embodiments are only intended to explain the technical solutions of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still make modifications to the technical solutions described in the foregoing embodiments without departing from the scope of the technical solutions of the embodiments of this application, or make equivalent substitutions for some of its technical features.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first dielectric layer and a gate on the substrate, wherein the gate is located on the substrate and in a first region, the thickness of the first dielectric layer in the first region is greater than the thickness of the first dielectric layer in a second region outside the first region, the gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the surface of the substrate, the first gate structure penetrates the first dielectric layer in the direction perpendicular to the surface of the substrate, the second gate structure is formed on the side of the first dielectric layer away from the substrate and covers a part of the first dielectric layer; forming a second dielectric layer covering the gate and the first dielectric layer; forming a field plate on the second dielectric layer, wherein the field plate is disposed in both the first region and the second region; the first dielectric layer includes a first sub-film layer and a second sub-film layer, and the step of forming the first dielectric layer and the gate on the substrate includes: sequentially forming the first sub-film layer and a second sub-material layer on the substrate; etching the second sub-material layer and the first sub-film layer in the first region to obtain a first via; forming the first gate structure located inside the first via and the second gate structure connected to the first gate structure and covering the part of the first dielectric layer; etching and removing the second sub-material layer outside the second gate structure by using the second gate structure as a mask, wherein the second sub-material layer located in the first region is used as the second sub-film layer; A method comprising the above steps.

2. A source and a drain are further formed on the substrate, the gate is located between the source and the drain, the field plate faces the portion of the gate facing the drain in a direction perpendicular to the surface of the substrate and extends to the drain, and the portion of the field plate located in the second region is electrically connected to the source. The method according to claim 1.

3. The step of forming the first dielectric layer and the gate on the substrate comprises: forming a first dielectric layer on the substrate; etching the first dielectric layer in the first region to obtain a second via; forming the first gate structure located inside the second via and a second gate structure connected to the first gate structure and covering the part of the first dielectric layer; thinning the first dielectric layer in the second region outside the first region to form the first dielectric layer The method according to claim 1 or 2.

4. The first dielectric layer includes a first sub-film layer and a second sub-film layer, and the step of forming the first dielectric layer and the gate on the substrate comprises: forming a first sub-material layer on the substrate; removing the first sub-material layer in the second region outside the first region and using the first sub-material layer located in the first region as the first sub-film layer; forming a second sub-film layer covering the first sub-film layer and the substrate; etching the second sub-film layer and the first sub-film layer in the first region to obtain a third via; forming the first gate structure located inside the third via and a second gate structure connected to the first gate structure and covering the part of the first dielectric layer The method according to claim 1 or 2.

5. The first dielectric layer includes a first sub-film layer and a second sub-film layer, and the step of forming the first dielectric layer and the gate on the substrate comprises: forming the first sub-film layer in the first region on the substrate by using a two-layer photoresist patterning process; forming a second sub-film layer covering the first sub-film layer and the substrate; etching the second sub-film layer and the first sub-film layer in the first region to obtain a third via; forming the first gate structure located inside the third via and a second gate structure connected to the first gate structure and covering the part of the first dielectric layer The method according to claim 1 or 2.

6. The material of the first sub-film layer and / or the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide, according to the method described in any one of claims 1, 4, and 5.

7. The substrate includes a base and an epitaxial layer. The material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire. The epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride, according to the method described in any one of claims 1 to 6.

8. The material of the gate and / or the field plate is at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, and copper, according to the method described in any one of claims 1 to 7.

9. The material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide, according to the method described in any one of claims 1 to 8.

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