Method for manufacturing a superconducting integrated circuit

Abstract

A method of forming a superconducting integrated circuit is discussed that includes depositing a first superconducting metal layer over at least a portion of a substrate, depositing a dielectric layer over a first region of the first superconducting metal layer, patterning the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and to form an opening, and depositing a second superconducting metal layer at an ambient temperature below the melting point of the second superconducting metal layer, whereby the second superconducting metal layer fills the opening and is in conductive contact with at least a portion of the first region of the first superconducting metal layer.

Description

Technical Field

[0001] Field The present disclosure generally relates to methods for manufacturing superconducting integrated circuits, and more particularly, to systems and methods for forming components of superconducting integrated circuits from aluminum.

Background Art

[0002] Background Quantum Devices A quantum device is a structure in which quantum mechanical effects are observable. Quantum devices include circuits in which current transport within the circuit is governed by quantum mechanical effects. Such devices include spintronics and superconducting circuits. Both spin and superconductivity are quantum mechanical phenomena. Quantum devices can be used in measuring instruments, calculators, etc.

[0003] Quantum Computing A quantum computer is a system that directly utilizes at least one quantum mechanical phenomenon (e.g., superposition, tunneling, and entanglement) to perform data operations. The unit of a quantum computer is a qubit. A quantum computer can achieve speedup for specific classes of computational problems (e.g., computational problems that simulate quantum physics).

[0004] Superconducting Processors A quantum processor can take the form of a superconducting processor. However, a superconducting processor may include processors that are not for quantum computing. For example, some implementations of superconducting processors may not focus on quantum effects such as quantum tunneling, superposition, and entanglement, but rather may operate by emphasizing another principle, such as the principle governing the operation of a classical computer processor, etc. However, such implementations of superconducting "classical" processors may still have certain advantages. Superconducting classical processors may be able to have a faster switching speed and shorter calculation time than non-superconducting processors due to their physical characteristics as they are, so it may be more realistic to solve certain problems with superconducting classical processors. The systems and methods of the present invention are particularly suitable for use in the manufacture of both superconducting quantum processors and superconducting classical processors.

[0005] Superconducting qubit A superconducting qubit is a type of superconducting quantum device that can be included in a superconducting integrated circuit. Superconducting qubits are classified into several categories according to the physical characteristics used to encode information. For example, superconducting qubits are classified into charge devices, flux devices, and phase devices. Charge devices store and manipulate information in the charged state of the device. Flux devices store and manipulate information in variables related to the magnetic flux passing through a part of the device. Phase devices store and manipulate information in variables related to the difference in the superconducting phase between two regions of the device. Recently, hybrid devices that use two or more of the degrees of freedom of charge, flux, and phase have been developed. Superconducting qubits generally include at least one Josephson junction. A Josephson junction is a small interruption in a superconducting current path that would otherwise be continuous and is typically realized by a thin insulating barrier sandwiched between two superconducting electrodes. Thus, a Josephson junction can be formed as a three-layer structure. Details of superconducting qubits are described, for example, in U.S. Patent Nos. 7,876,248, 8,035,540, and 8,098,179.

[0006] Manufacture of integrated circuits In this application, an integrated circuit is also referred to as a chip, and a superconducting integrated circuit is also referred to as a superconducting chip in this application.

[0007] Conventionally, the manufacture of superconducting integrated circuits has not been carried out in state-of-the-art semiconductor manufacturing facilities. This is presumably because there is a concern that some of the materials used in superconducting integrated circuits can contaminate semiconductor facilities. For example, gold may be used as a resistor in a superconducting circuit, but gold can potentially contaminate the manufacturing tools used in the manufacture of complementary metal-oxide-semiconductor (CMOS) wafers in semiconductor facilities.

[0008] The manufacture of superconductors has typically been carried out in a research environment where standard industrial techniques can be optimized for superconducting circuit production. The manufacture of superconducting integrated circuits has often been carried out using tools previously used in the manufacture of semiconductor chips or semiconductor integrated circuits. Due to problems specific to superconducting circuits, not all semiconductor processes and semiconductor technologies can necessarily be transferred to the manufacture of superconducting chips. Converting semiconductor processes and semiconductor technologies for use in the manufacture of superconducting chips and circuits often requires changes and fine-tuning. Such changes and adjustments are typically not obvious and may require many experiments. The problems and challenges faced by the semiconductor industry are not necessarily relevant to the superconducting industry. Similarly, problems and challenges related to the superconducting industry are often little or no problem in standard semiconductor manufacturing.

[0009] Even a small amount of impurities in a superconducting chip can potentially impair the functionality of the superconducting chip or cause noise that can degrade it. Noise can also potentially impair or degrade the functionality of individual devices (e.g., superconducting qubits). Since noise is a serious problem for the operation of a quantum computer, it is necessary to take measures to reduce noise as much as possible.

[0010] The above examples of the prior art and the limitations related thereto are illustrative and not exclusive. Those skilled in the art will recognize other limitations of the prior art upon reading this specification and studying the drawings. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0011] Brief Summary In one aspect, a method of forming a superconducting integrated circuit for a quantum processor is provided. The method includes depositing a first superconducting metal to form a first superconducting metal layer that covers at least a portion of a substrate, the first superconducting metal layer including an upper surface having a first region; depositing a dielectric layer to cover the first region of the first superconducting metal layer; patterning the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening; and depositing a second superconducting metal at an ambient temperature lower than the melting point of the second superconducting metal, whereby the second superconducting metal fills the opening and forms a connection that makes conductive contact with at least a portion of the first region of the first superconducting metal layer, and forms a second superconducting metal layer that covers the dielectric layer and the connection.

[0012] According to another aspect, the method may further include depositing an adhesive layer along at least the side surfaces of the opening such that the adhesive layer is aligned, planarizing the first superconducting metal layer, and planarizing the second superconducting metal layer. Planarizing the second superconducting metal layer may include chemical mechanical polishing (CMP). Patterning the dielectric layer to form the opening may include patterning the dielectric layer to form an opening having a dimension greater than 0.1 micron. Depositing the second superconducting metal may include depositing aluminum. Depositing the second superconducting metal at an ambient temperature lower than the melting point of the second superconducting metal may include depositing at an ambient temperature lower than 650° C. or at an ambient temperature of 100° C. to 520° C. Depositing the second superconducting metal at an ambient temperature lower than the melting point of the second superconducting metal may include depositing a first portion at an ambient temperature of 100° C. to 300° C. and depositing a second portion at an ambient temperature of 450° C. to 650° C. Depositing the second superconducting metal may include depositing aluminum by physical vapor deposition (PVD). Depositing the first superconducting metal includes depositing aluminum.

[0013] According to another aspect, depositing the first superconducting metal may include depositing a first wiring layer, and depositing the second superconducting metal may include depositing vias and a second wiring layer. The method may further include, after depositing the first superconducting metal layer, patterning the first superconducting metal layer to form additional openings, depositing an additional dielectric layer to fill the additional openings, and depositing a dielectric layer to cover a first region of the first superconducting metal layer and the upper surface of the additional dielectric layer. Before patterning the first superconducting metal layer, the method may further include depositing a polish stop layer on at least a portion of the first superconducting metal layer, and patterning the first superconducting metal layer may further include patterning the first superconducting metal layer and the polish stop layer. After depositing the additional dielectric layer to fill the additional openings, the method may further include planarizing the additional dielectric layer to have an upper surface at the same height as the upper surface of the polish stop layer, and removing the polish stop layer. The method may further include depositing a second polish stop layer on at least a portion of the second superconducting metal layer, patterning the second polish stop layer and the second superconducting metal layer to form a third opening, and depositing a third dielectric layer to fill the third opening. The method may further include depositing a superconducting barrier layer covering the second superconducting metal layer, and patterning the second superconducting metal layer and the superconducting barrier layer.

[0014] According to one aspect, a method of forming a superconducting integrated circuit for a quantum processor is provided. The method includes depositing a first superconducting metal at a first ambient temperature lower than the melting point of the first superconducting metal, whereby the first superconducting metal fills an opening in a first dielectric layer to form a first connection portion that makes conductive contact with a conductive layer beneath the first dielectric layer, and forming a first superconducting metal layer covering the first dielectric layer and the first connection portion; depositing the first superconducting metal at a second ambient temperature lower than the melting point of the first superconducting metal, whereby the first superconducting metal aligns along an opening in a second dielectric layer and forms an adhesive layer covering the second dielectric layer; and depositing the first superconducting metal at a third ambient temperature lower than the melting point of the first superconducting metal and higher than the second ambient temperature to form a filling layer covering the adhesive layer, whereby the adhesive layer and the filling layer fill the opening in the second dielectric layer to form a second connection portion that makes conductive contact with a conductive layer beneath the second dielectric layer, and form a second superconducting metal layer covering the second dielectric layer and the first connection portion.

[0015] According to another aspect, depositing the first superconducting metal at an ambient temperature lower than the melting point of the first superconducting metal may include depositing at an ambient temperature of 100°C to 300°C, depositing the first superconducting metal at a second ambient temperature lower than the melting point of the first superconducting metal may include depositing at an ambient temperature of 100°C to 300°C, and depositing the first superconducting metal at a third ambient temperature lower than the melting point of the first superconducting metal may include depositing at an ambient temperature of 450°C to 650°C.

[0016] According to one aspect, a superconducting integrated circuit includes a substrate, a first metal layer including a first metal that becomes superconducting below a first critical temperature, the first metal layer covering at least a portion of the substrate and including an upper surface having a first region, a dielectric layer covering at least a portion of the first metal layer, the dielectric layer exposing at least a portion of the first region of the first metal layer and including an opening having a side surface defined by the dielectric layer and a bottom surface defined by at least the exposed portion of the first region of the first metal layer, a second metal layer including a second metal that becomes superconducting below a second critical temperature, the second metal layer arranged along at least the side surface of the opening and including an adhesive layer, and a third metal layer including the second metal, the third metal layer covering at least a portion of the dielectric layer, filling the opening, and making conductive contact with at least a portion of the first region of the first metal layer, and can be summarized as such.

[0017] According to another aspect, the second metal may include aluminum. The first metal may include aluminum. The opening may have a dimension (e.g., a horizontal dimension, a diameter) of 0.1 micron or more. The first metal layer may include a first wiring layer, and the second and third metal layers may include vias and a second wiring layer. The interface (e.g., the transition region) between the second metal layer and the third metal layer may be distinguishable (e.g., by evaluating particles with a microscope (e.g., measuring the particle size)), which is because, for example, the particle sizes are different as a result of depositing the materials forming the layers at different temperatures at different timings (e.g., sequentially).

[0018] In another aspect, as would be recognized by those skilled in the art, each of the above features may be combined with each other in any suitable combination.

[0019] Brief Description of Some of the Drawings In the drawings, like reference numerals identify like elements or acts. The sizes and relative positions of elements within the drawings are not necessarily drawn to scale accurately. For example, the shapes and angles of various elements are not necessarily drawn to scale accurately, and some of these elements may be arbitrarily enlarged and arranged to make the drawings easier to understand. Further, a particular shape of an element being drawn does not necessarily convey any information regarding the actual shape of that particular element, and may be selected only for ease of recognition within the drawings.

Brief Description of the Drawings

[0020]

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DETAILED DESCRIPTION OF THE INVENTION

[0021] Detailed Description In the following description, specific details are set forth in order to provide a thorough understanding of various implementations of the disclosure. However, as will be understood by those skilled in the art, the implementations may be practiced without one or more of these specific details, or in other ways, components, materials, etc. In other instances, well-known structures related to computer systems, server computers, and / or communication networks are not shown or described in detail to avoid unnecessarily obscuring the description of the implementations.

[0022] Throughout this specification and the following claims, unless otherwise stated, the word "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., it does not exclude the addition of unrecited elements or method acts).

[0023] References to "one implementation" or "an implementation" throughout this specification mean that a particular feature, structure, or characteristic described in connection with that implementation is included in at least one implementation. Thus, the appearances of the phrases "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0024] In this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the word "or" is generally used in the sense of "and / or" unless the context clearly dictates otherwise.

[0025] The headings given in this specification and the abstract of the disclosure are for convenience only and do not explain the scope or meaning of the implementations.

[0026] The various implementations described herein provide systems and methods for manufacturing superconducting integrated circuits. As noted above, in the art, the manufacture of superconducting integrated circuits tends to be carried out in a research environment outside of state-of-the-art semiconductor manufacturing facilities, and even when the manufacture of superconducting integrated circuits is typically carried out using many of the same tools and techniques previously used in the semiconductor manufacturing industry, there is that tendency. Due to problems specific to superconducting circuits, generally, semiconductor processes and semiconductor technologies need to be modified for use in the manufacture of superconducting chips and circuits. Such modifications are typically not obvious and may require some experimentation.

[0027] A superconducting material is a material in which a transition to superconducting behavior occurs at a critical temperature T c . This material is in a non-superconducting state at temperatures higher than T c but behaves as a superconductor at temperatures lower than T c . The critical temperature is also referred to as the transition temperature in this application. A superconducting integrated circuit can be cooled by a cryogenic refrigerator. The cryogenic refrigerator can be, for example, a dilution refrigerator and / or a cryocooler, such as a pulse tube cryocooler, which is also referred to as a pulse tube refrigerator in this application. A superconducting integrated circuit can be cooled to a temperature below 1K. In some implementations, the superconducting integrated circuit is cooled to a temperature below 20mK. In some implementations, the superconducting integrated circuit and the cryogenic refrigerator are elements of a superconducting computer.

[0028] In some embodiments, the superconducting computer is a superconducting quantum computer. Superconducting integrated circuits that use multiple superconducting layers often require superconducting interconnections between the layers. These interconnections are called "vias". Hinode et al., Physica C 426-432 (2005) 1533-1540 discusses some of the problems specific to superconducting vias. In multilayer superconducting integrated circuits, successive layers of conductive wiring are typically separated from each other by an interlayer dielectric ("ILD"). The ILD structurally supports the entire circuit while electrically insulating adjacent conductive layers. The thickness of the ILD determines the distance between two adjacent conductive layers in the circuit, which affects, among other things, the inductive and capacitive coupling between adjacent conductive layers.

[0029] FIG. 1A shows a cross-sectional view of a portion of a superconducting integrated circuit 100a, which includes a substrate 102 and a first superconducting metal layer 104, where the first superconducting metal layer 104 is formed by depositing a first superconducting metal so as to directly or indirectly cover at least a portion of the substrate 102. Naturally, the metal layer 104 can be formed to directly or indirectly cover the substrate 102. In this specification, directly covering the substrate means that the layer is formed directly on the substrate without interposing another layer between it and the substrate. Indirectly covering the substrate means that the layer is formed on at least a portion of the substrate with at least one other layer interposed between it and the substrate. The substrate 102 can be formed of silicon, sapphire, quartz, silicon dioxide, or any other suitable material. The first superconducting metal layer 104 can be aluminum, niobium, or another suitable superconducting metal. Throughout this specification, unless the context indicates otherwise, particularly when it should be understood in another meaning, terms such as "deposit", "deposited", "deposition", etc. are generally used to include any method of depositing a material, and such methods include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced PVD, plasma-enhanced CVD, and atomic layer deposition (ALD). The first superconducting metal layer can be planarized (e.g., by chemical mechanical planarization), which will be discussed in more detail later with reference to FIGS. 10A and 10B.

[0030] FIG. 1B is a cross-sectional view of a portion of the superconducting integrated circuit 100a of FIG. 1A after a dielectric layer 106 has been deposited to form a superconducting integrated circuit 100b. The dielectric layer 106 is deposited covering at least a first region of the upper surface 108 of the first superconducting metal layer 104. Naturally, the dielectric layer 106 can cover all or only a specific region of the upper surface 108. In some implementations, the dielectric material 106 can be, for example, SiO2, SiN, or any other suitable dielectric material known in the art. The deposition of the dielectric layer 106 can be performed, for example, by CVD, PVD, ALD, or a similar process. The dielectric layer 106 can be planarized, if necessary, to smooth the surface.

[0031] FIG. 1C is a cross-sectional view of a portion of the superconducting integrated circuit 100b of FIG. 1B after a patterning step for forming the superconducting integrated circuit 100c. The dielectric layer 106 is patterned to expose at least a portion of a first region of the first superconducting metal layer, and an aperture, recess, or opening 110 (collectively referred to herein as the opening 110) is formed. The opening 110 can have dimensions greater than 0.3 microns, for example, the dimensions of the opening can be 0.3 to 0.7 microns or the like. In another implementation, the opening 110 can have dimensions of 0.1 to 1 micron for the opening. In another implementation, the opening 110 can have dimensions of 0.1 to 10 microns for the opening. Of course, the opening 110 can be circular, elliptical, square, rectangular, or any other shape required by the implementation. The dimensions of the opening 110 can be the diameter or the width, and generally mean the minimum horizontal dimension of the opening 110 to be filled. For example, in an implementation where the opening 110 is a rectangle with a width of 0.3 microns and a length of 2 microns, the dimension considered is 0.3 microns for the width.

[0032] Figures 1D - 1H are cross - sectional views of a portion of the superconducting integrated circuit 100c of FIG. 1C during the deposition and reflow process of the second superconducting metal 112. The second superconducting metal 112 is deposited at an ambient temperature lower than the melting point of the second superconducting metal layer 112, whereby the second superconducting metal 112 fills the opening 110 to form the connection portion 114, and the connection portion 114 makes conductive contact with at least a portion of the first region of the first superconducting metal layer 104. The second superconducting metal 112 further forms a second superconducting metal layer 116 that covers the dielectric layer 106 and the connection portion 114. In some implementations, the second superconducting metal layer 112 is deposited by PVD in the form of a continuous thin layer, whereby it reflows at the ambient temperature to fill the opening 110 with little or no void or cavity. The second superconducting metal 112 can be aluminum, and aluminum is deposited in layers by PVD at an ambient temperature lower than 650 °C (e.g., between 100 °C and 520 °C). The second superconducting metal 112 is deposited at a sufficiently high ambient temperature such that the metal has sufficient mobility to completely fill the opening 110 and form a second superconducting metal layer 116 having a thickness as shown in FIG. H. The second superconducting metal layer 116 has an upper surface 118h. In some implementations, the upper surface 118h can have sufficient flatness such that additional layers can be formed directly on the upper surface 118h after deposition.

[0033] Figures 1I and 1J are cross - sectional views of a portion of the superconducting integrated circuit 100h of FIG. 1H after an optional planarization step. Planarizing the second superconducting metal layer 112 can include using chemical - mechanical polishing (CMP) to form a flat or nearly flat upper surface 118. As shown in FIG. 1I, the upper surface 118i can be at a certain thickness above the dielectric layer 106, or as shown in FIG. 1J, the upper surface 118j can be at the same height as the upper surface of the dielectric layer 106. In some implementations, the second superconducting metal layer 112 can be patterned. Next, the upper surface 118 can receive additional layers in order to form additional elements of the superconducting integrated circuit.

[0034] FIG. 2A is a partial cross-sectional view of a superconducting integrated circuit 200a, which includes a first superconducting metal layer 202 and a deposition and polish stop layer 204 deposited on at least a portion of the first superconducting metal layer 202. The first superconducting metal layer 202 and the polish stop layer 204 are patterned to form an opening 206. In some implementations, the polish stop layer 204 may not be included, and the first superconducting metal layer 202 may be patterned after deposition to form the opening 206. In some implementations, the first superconducting metal layer 202 may be aluminum and may be deposited as a metal film. In some implementations, the polish stop layer 204 may be a sacrificial film and may be silicon nitride. Patterning the first superconducting metal layer 202 and the deposition and polish stop layer 204 may include masking and etching these two layers. In some implementations, this may include RIE.

[0035] FIG. 2B is a partial cross-sectional view of the superconducting integrated circuit 200a after a dielectric layer 208 is deposited and planarized within the opening 206 to form a superconducting integrated circuit 200b. The dielectric layer 208 may be planarized such that the upper surface of the dielectric layer 208 is at the same height as the upper surface of the polish stop layer 204. In some implementations, planarization may include CMP. In some implementations, such as those where the polish stop layer 204 is not included, the dielectric layer 208 may be deposited to fill the opening 206 and cover an area of the upper surface of the first superconducting metal layer 202 and the upper surface of the dielectric layer 208 within the opening 206, as shown in FIG. 2D. In some implementations, the dielectric layer 208 may be silicon dioxide or another insulating interlayer dielectric material.

[0036] FIG. 2C is a partial cross-sectional view of the superconducting integrated circuit 200b after the polish stop layer 204 is removed to form a superconducting integrated circuit 200c.

[0037] FIG. 2D is a cross-sectional view of a portion of superconducting integrated circuit 200c after the second dielectric layer 210 has been deposited and patterned to form superconducting integrated circuit 200d. Patterning the second dielectric layer 210 may include masking and etching (such as RIE).

[0038] FIG. 2E is a cross-sectional view of a portion of superconducting integrated circuit 200d after the second metal layer 212 has been deposited to form superconducting integrated circuit 200e. The temperature at which the second metal layer 212 may be deposited is lower than the melting point of the second superconducting metal, but is high enough such that the second superconducting metal layer 212 reflows to fill the openings formed in the second dielectric layer 210 as shown, and at the same time forms a layer that covers the second dielectric layer 210 and the connections within the openings. In some implementations, the second metal layer 212 may be aluminum and the temperature may be less than 650°C. In some implementations, the upper surface of the second metal layer 212 may be polished for planarization of the upper surface and selection of the thickness of the second metal layer 212.

[0039] FIG. 2F is a cross-sectional view of a portion of superconducting integrated circuit 200e after the second polishing stop layer 214 has been deposited on at least a portion of the second superconducting metal layer 212 to form superconducting integrated circuit 200f. In some implementations, the polishing stop layer 214 may be a sacrificial film and may be silicon nitride.

[0040] FIG. 2G is a cross-sectional view of a portion of superconducting integrated circuit 200f after the second metal layer 212 and the polishing stop layer 214 have been patterned to form the opening 216. In some implementations, a third dielectric layer may be deposited to fill the third opening 216. Patterning the second metal layer 212 and the polishing stop layer 214 may include masking and etching (such as RIE). The patterning may stop where the material of the dielectric layer 208 is present.

[0041] In some implementations, additional components may be formed by operations similar to those shown in FIGS. 2A - 2G.

[0042] Of course, the implementation forms described with respect to FIGS. 1A-1J and FIGS. 2A-2G are configuration examples, and the methods 600 and 700 described below can be used to form superconducting integrated circuits having various shapes and configurations.

[0043] In the exemplary implementation form of FIG. 3A, the superconducting integrated circuit 300a has a substrate 302 and a first superconducting metal layer 304 covering at least a part of the substrate 302. The dielectric layer 306 is deposited to cover a region of the first superconducting metal layer 304. In some implementation forms, the dielectric layer 306 can be deposited over the entire upper surface of the first superconducting metal layer 304, and then the dielectric layer 306 can be patterned so that at least a part of the upper surface of the first superconducting metal layer 304 is exposed. In this implementation form of the superconducting integrated circuit 300, angled sidewalls 308 are defined by patterning the dielectric layer 306. The second superconducting metal layer 310 is deposited at an ambient temperature lower than the melting point of the second superconducting metal layer 310, whereby the second superconducting metal layer 310 fills the opening defined by the angled sidewalls 308 to form an angled superconducting via 312 and a layer over the dielectric layer 306 and the angled superconducting via 312. The superconducting via 312 makes conductive contact with the exposed surface of the first superconducting metal layer 304. The first and second superconducting metal layers 304 and 310 can be formed of the same superconducting metal (e.g., aluminum).

[0044] In some implementations, the material of the second superconducting metal layer 310 may be difficult to adhere to the materials of the dielectric layer 306 and the first superconducting metal layer 304. As a result, the second superconducting metal may separate from the surface, leaving behind voids and non-uniform deposition in layer 310. A superconducting adhesion layer may be included to reduce or eliminate the separation of the second superconducting metal from the surface. The superconducting adhesion layer is formed from a material that is more easily adhered to by the superconducting metal layer 304 and the dielectric layer 306, and the second superconducting metal layer 310 adheres more easily to this superconducting adhesion layer. FIG. 3B is a cross-sectional view of one implementation of an angled superconducting via having a superconducting adhesion layer 314. Of course, any of the manufacturing processes described herein can be modified to include depositing an adhesion layer along the sides or sides and bottom of the opening prior to depositing the superconducting metal. The adhesion layer may be formed of a titanium-based material in some implementations, such as pure titanium, titanium nitride, or titanium tungsten. Other superconducting materials may also be used.

[0045] Figures 4A and 4B are exemplary implementations of superconducting vias with alternative angles within superconducting integrated circuits 400a and 400b. Substrate 402 has a first superconducting metal layer 404 deposited thereon, and the first superconducting metal layer 404 is patterned to cover only a portion of the substrate 402. A dielectric layer 406 is deposited to cover the substrate 402 and the first superconducting metal layer 404, and then the dielectric layer 406 can be patterned so that a portion of the upper surface of the first superconducting metal layer 404 is exposed. A second superconducting metal layer 408 is deposited on the dielectric layer 406 and the first superconducting metal layer 404 at an ambient temperature lower than the melting point of the second superconducting metal layer 408, whereby the second superconducting metal layer 408 fills the opening in the dielectric layer 406, makes conductive contact with the first superconducting metal layer 404, and simultaneously forms a covering layer. The upper surface of the covering layer of the second superconducting metal layer 408 can be planarized and smoothed. In the implementation of Figure 4A, the second superconducting metal layer 408 is planarized until it reaches a certain thickness. Figure 4B is a cross-sectional view after planarization of an alternative implementation of the angled superconducting via of Figure 4A, and the second superconducting metal layer 408 is planarized so that its upper surface is at the same height as the upper surface of the dielectric layer 406. In this implementation, an additional metal layer can be deposited on the second superconducting metal layer 408 and the dielectric layer 406, and the second superconducting metal layer 408 can form an electrical connection between the first superconducting metal layer 404 and the additionally deposited metal layer.

[0046] Of course, each of the above-described features of the superconducting integrated circuit can be combined as needed for a given application. For example, the implementations of FIGS. 4A and 4B have angled vias with a patterned first superconducting metal layer. In another implementation, the patterned first superconducting metal layer can be used with vias having straight sidewalls, such as in the exemplary implementations of FIGS. 5A and 5B. FIGS. 5A and 5B illustrate one implementation with straight superconducting vias within superconducting integrated circuits 500a and 500b. A first superconducting metal layer 504 is deposited so as to directly or indirectly cover at least a portion of a substrate 502, and then the first superconducting metal layer 504 is patterned to define individual superconducting metal components. A dielectric layer 506 is deposited to cover the substrate 502 and the upper surface of the first superconducting metal layer 504, and the dielectric layer 506 is patterned to expose at least a portion of the upper surface of the first superconducting metal layer 504 and to form an opening 508, resulting in the superconducting integrated circuit 500a. FIG. 5B is a cross-sectional view of the superconducting integrated circuit 500a after a second superconducting metal layer 510 has been deposited at an ambient temperature lower than the melting point of the second superconducting metal layer 510 to form the superconducting integrated circuit 500b. The second superconducting metal layer 510 fills the opening 508 and makes conductive contact with at least a portion of the upper surface of the first superconducting metal layer 504 to form a covering layer. The second superconducting metal layer 510 can then be planarized and / or patterned, and additional layers can be deposited. Of course, a similar implementation can be formed on another layer covering the substrate of the superconducting integrated circuit.

[0047] FIG. 6 is a flowchart showing a method 600 of forming a superconducting integrated circuit for a quantum processor according to the system and method of the present invention. The method 600 can be used, for example, to form the components of the superconducting integrated circuit of FIGS. 1A-1J. The method 600 includes operations 602-608, but in other implementations, certain operations can be omitted, additional operations can be added, and / or the operations can be performed in a different order. The method 600 can be performed, for example, by an integrated circuit manufacturing facility when the manufacturing process is initiated.

[0048] In 602, the first superconducting metal layer is deposited so as to directly or indirectly cover at least a part of the substrate. In some implementation forms, the first superconducting metal can be aluminum. Aluminum can be deposited directly on the substrate or on an intervening layer of an integrated circuit, for example, on a dielectric layer or on another metal layer. The deposition of aluminum can be carried out by a standard deposition process such as chemical vapor deposition or physical vapor deposition. In some implementation forms, the upper surface of aluminum can be planarized by a chemical mechanical planarization process.

[0049] In 604, a dielectric layer is deposited so as to cover a first region on the upper surface of the first superconducting metal layer. The dielectric material can include a non-oxide dielectric such as silicon nitride and can be deposited by any deposition process including CVD, PVD, and / or ALD.

[0050] In 606, the dielectric layer is patterned so as to expose at least a part of the first region of the first superconducting metal layer and to form an opening. The opening can have a dimension greater than 0.3 microns, for example, 0.3 to 0.7 microns. In another implementation form, the opening can have a dimension of 0.1 to 1 micron or 0.1 to 10 microns. As described above, the dimension of the opening can be the diameter or the width and generally means the minimum horizontal dimension of the opening to be filled.

[0051] In 608, the second superconducting metal layer is deposited at an ambient temperature lower than the melting point of the second superconducting metal layer, whereby the second superconducting metal layer fills the opening and makes conductive contact with at least a part of the first region of the first superconducting metal layer. In some implementation forms, the second superconducting metal can be aluminum. In an implementation form where both the first and second metal layers are aluminum, an aluminum / aluminum interface can be formed. The deposition can be carried out at a temperature below 650 °C, for example, at a temperature of 100 °C to 520 °C. The deposition can include depositing aluminum on each layer by physical vapor deposition (PVD) and controlling the temperature so as to enable aluminum to reflow within the opening.

[0052] After operation 608, the method may end or another manufacturing operation may be performed. For example, after the second superconducting metal layer is deposited, it may be planarized, for example, by chemical mechanical polishing (CMP). The method may also be restarted to form another component within the quantum processor.

[0053] FIG. 7 is a flowchart showing one implementation of method 600 of FIG. 6 according to the system and method of the present invention. Method 700 of FIG. 7 may be used, for example, to form the components of the superconducting integrated circuit of FIGS. 2A-2G. Method 700 includes operations 702-724, but in other implementations, certain operations may be omitted, additional operations may be added, and / or each operation may be performed in a different order. Operations 704, 710, 712, 720, and 722 are optional and require an optional polish stop layer. Method 700 may be performed, for example, by an integrated circuit manufacturing facility when the manufacturing process is initiated.

[0054] At 702, a first superconducting metal layer is deposited. The first superconducting metal layer may be deposited as a metal film by techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced PVD, plasma-enhanced CVD, and atomic layer deposition (ALD). In some implementations, the first superconducting metal layer may be aluminum.

[0055] At 704, an optional polish stop layer may be deposited on at least a portion of the first superconducting metal layer before patterning the first superconducting metal layer. The polish stop layer may act as a sacrificial film in subsequent operations and may be, for example, silicon nitride.

[0056] At 706, the first superconducting metal layer is patterned to form openings. In implementations where a polish stop layer is deposited, both the first superconducting metal layer and the polish stop are patterned. Patterning may include subtractive patterning such as masking and etching. In some implementations, patterning may be performed by reactive ion etching (RIE).

[0057] At 708, a dielectric layer may be deposited to fill the opening of the first superconducting metal layer. The dielectric layer may be, for example, silicon dioxide.

[0058] At 710, the dielectric layer is planarized so that the upper surface of the dielectric layer is at the same height as the upper surface of the polish stop layer. In some implementations, the dielectric may be planarized by CMP.

[0059] At 712, the polish stop layer may be removed. In some implementations, the polish stop layer may be removed by RIE.

[0060] At 714, another dielectric layer may be deposited. In some implementations, this dielectric material may be the same as the dielectric deposited at 708. In some implementations, the dielectric may be silicon dioxide. In some implementations, operations 708 and 714 may be performed together, for example, in a deposition technique that does not use a polish stop layer. The dielectric layer is deposited such that at the same time as the upper surface of the dielectric layer is deposited, it covers at least a first region of the upper surface of the first superconducting metal layer.

[0061] At 716, the dielectric layer is patterned to expose at least a portion of the first region of the first superconducting metal layer and to form an opening. In some implementations, patterning may include masking and etching techniques (such as RIE). In some implementations, the dielectric layer may be patterned to form an opening with a dimension greater than 0.3 microns, for example, an opening with a dimension of 0.3 - 0.7 microns. In another implementation, the opening may have a dimension of 0.1 - 1 micron or 0.1 - 10 microns. This dimension may be the diameter or width and generally means the minimum horizontal dimension of the opening to be filled.

[0062] In 718, the second superconducting metal layer is deposited at an ambient temperature lower than the melting point of the second superconducting metal layer, whereby the second superconducting metal layer fills the opening of the dielectric layer and makes conductive contact with at least a portion of the first region of the first superconducting metal layer. This temperature can be selected such that the material of the second metal layer flows sufficiently to fill the via opening formed in the dielectric layer. In some implementations, deposition can be performed on a plurality of metal thin film layers deposited by a method such as PVD, and those metal thin film layers are formed to flow into the opening. In some implementations, the second superconducting metal layer can be aluminum. In an implementation where the second superconducting metal layer is aluminum, the deposition can be performed at a temperature below 650 °C, for example, at a temperature of 100 °C to 520 °C.

[0063] In 720, the second superconducting metal layer is optionally polished to smooth the upper surface of the second superconducting metal layer. In some implementations, polishing can reduce the second metal layer to the required thickness. Operation 720 can include planarizing the second superconducting metal layer (e.g., by chemical mechanical polishing (CMP)).

[0064] In 722, a second polishing stop layer can be optionally deposited on at least a portion of the second superconducting metal layer. In some implementations, the polishing stop layer can act as a sacrificial film in subsequent operations and can be, for example, silicon nitride.

[0065] In 724, the second superconducting metal layer is patterned to form features of the superconducting integrated circuit (e.g., superconducting vias). In an implementation where a polishing stop layer is deposited on the second superconducting metal layer, both the first superconducting metal layer and the polishing stop are patterned. Patterning can include subtractive patterning such as masking and etching. In some implementations, patterning can be performed by reactive ion etching (RIE). In some implementations, the second polishing stop layer and the second superconducting metal layer are patterned to form at least one third opening, and then the third opening can be filled by depositing a third dielectric layer.

[0066] After 724, the method may be repeated, i.e., other components of the superconducting integrated circuit may be formed. The method may end, for example, end until restarted again to form a new superconducting integrated circuit. Of course, method 700 may be included in a larger manufacturing method, there may be any number of preceding manufacturing operations before operation 702, and there may be any number of subsequent manufacturing operations after operation 724.

[0067] FIG. 8 shows a computing system 800 including a digital computer 802. The exemplary digital computer 802 includes one or more digital processors 806 that can be used to perform classical digital processing tasks. The digital computer 802 may further include at least one system memory 822 and at least one system bus 820, and the system bus 820 couples various system components including the system memory 822 to the digital processor 806. The system memory 822 may store a series of modules 824.

[0068] The digital processor 806 can be any logic processing unit or circuit (e.g., an integrated circuit), for example, one or more central processing units (“CPUs”), graphics processing units (“GPUs”), digital signal processors (“DSPs”), application specific integrated circuits (“ASICs”), programmable gate arrays (“FPGAs”), programmable logic controllers (“PLCs”), etc., and / or combinations thereof.

[0069] In some implementations, computing system 800 may include an analog computer 804, which may include one or more quantum processors 826. The quantum processor 826 may be at least one superconducting integrated circuit, which may include microwave-sensitive components within a microwave shielding layer, components fabricated from a low-noise dielectric, and other components fabricated using the systems and methods described in this application. The quantum processor 826 may include at least one integrated circuit fabricated using the methods described in more detail herein. The digital computer 802 may communicate with the analog computer 804 (e.g., via controller 818). The analog computer 804 may perform certain calculations in response to instructions from the digital computer 802. This will be described in more detail herein.

[0070] The digital computer 802 may include a user input / output subsystem 808. In some implementations, the user input / output subsystem includes one or more user input / output components, such as a display 810, a mouse 812, and / or a keyboard 814.

[0071] The system bus 820 may employ any known bus structure or bus architecture, including a memory bus having a memory controller, a peripheral bus, and a local bus. The system memory 822 may include non-volatile memory such as read-only memory (“ROM”), static random access memory (“SRAM”), flash NAND, and volatile memory such as random access memory (“RAM”) (not shown).

[0072] The digital computer 802 may also include other non-transitory computer-readable or processor-readable storage media or non-volatile memory 816. The non-volatile memory 816 can take various forms, such as a hard disk drive that reads and writes to a hard disk (e.g., a magnetic disk), an optical disk drive that reads and writes to a removable optical disk, and / or a solid-state drive (SSD) that reads and writes to solid-state media (e.g., NAND-based flash memory). The non-volatile memory 816 can communicate with the digital processor via a system bus 820 and can include a suitable interface or controller 818 coupled to the system bus 820. The non-volatile memory 816 can operate as a long-term storage device for processor-readable or computer-readable instructions, data structures, or other data (sometimes called program modules) for the digital computer 802.

[0073] While the digital computer 802 has been described as utilizing a hard disk, an optical disk, and / or solid-state storage media, as will be understood by those skilled in the art, other types of non-transitory and non-volatile computer-readable media are also available. As will be understood by those skilled in the art, some computer architectures utilize both non-transitory volatile memory and non-transitory non-volatile memory. For example, data in volatile memory can be cached in non-volatile memory. Or, a solid-state disk can provide non-volatile memory using integrated circuits.

[0074] Various processor-readable or computer-readable instructions, data structures, or other data may be stored in the system memory 822. For example, the system memory 822 may store instructions for communicating with a remote client and scheduling the use of resources including resources on the digital computer 802 and the analog computer 804. Also, for example, the system memory 822 may store at least one of processor-executable instructions or data that cause a processor to execute various algorithms when executed by at least one processor. In some implementations, the system memory 822 may store processor-readable or computer-readable calculation instructions and / or data for performing pre-processing, co-processing, and post-processing on the analog computer 804. The system memory 822 may store a series of analog computer interface instructions for interacting with the analog computer 804.

[0075] The analog computer 804 may include at least one analog processor (e.g., the quantum processor 826). The analog computer 804 may be provided in an isolated environment, for example, in an isolated environment that protects the internal components of a quantum computer from heat, magnetic fields, and other external noise. The isolated environment may include a refrigerator (e.g., a dilution refrigerator) operable to cool the analog processor to cryogenic temperatures (e.g., below about 1K).

[0076] The analog computer 804 may include programmable elements (e.g., qubits, couplers, and other devices). The qubits may be read out via a readout system 828. The readout results may be sent to other computer-readable or processor-readable instructions of the digital computer 802. The qubits may be controlled by a qubit control system 830. The qubit control system 830 may include an on-chip digital-to-analog converter (DAC) and an analog line operable to apply a bias to a target device. The couplers that couple the qubits may be controlled by a coupler control system 832. The coupler control system 832 may include tuning elements such as an on-chip DAC and an analog line. The qubit control system 830 and the coupler control system 832 may be used to implement the quantum annealing schedule described herein on the analog processor 804. The programmable elements may be included in a quantum processor 826 in the form of an integrated circuit. The qubits and couplers may be disposed in a layer of the integrated circuit that includes a first material. Other devices (e.g., the readout control system 828) may be disposed in other layers of the integrated circuit that include a second material.

[0077] Of course, the methods described herein may be used to form various components of a superconducting integrated circuit. In the implementations shown in FIGS. 9A and 9B, the methods may be combined with a dual-damascene process. FIG. 9A shows an exemplary implementation of a superconducting integrated circuit 900a patterned to form an opening 908. A first superconducting metal layer 904 is deposited so as to directly or indirectly cover at least a portion of a substrate 902, and then the first superconducting metal layer 904 is patterned to define individual superconducting metal components. A dielectric layer 906 is deposited to cover the substrate 902 and the upper surface of the first superconducting metal layer 904, exposing at least a portion of the upper surface of the first superconducting metal layer 904, and the dielectric layer 906 is patterned to form an opening 908, thereby obtaining the superconducting integrated circuit 900a.

[0078] FIG. 9B is a cross-sectional view of a superconducting integrated circuit 900a after a second superconducting metal layer 910 is deposited at an ambient temperature lower than the melting point of the second superconducting metal layer 910 to form a superconducting integrated circuit 900b. The second superconducting metal layer 910 fills the opening 908 and makes conductive contact with at least a portion of the upper surface of the first superconducting metal layer 904. The second superconducting metal layer 910 may be planarized and / or patterned after deposition, and additional layers may be deposited. In the exemplary implementation of FIG. 9B, the first superconducting metal layer 904 is the first wiring layer, and the second superconducting metal layer 910 constitutes both superconducting vias 912 and a second wiring layer 914.

[0079] FIG. 10A is a cross-sectional view of a portion of a superconducting integrated circuit 1000a after a metal layer 1004 is deposited so as to directly or indirectly cover at least a portion of a substrate 1002.

[0080] FIG. 10B is a cross-sectional view of a superconducting integrated circuit 1000a after a first superconducting metal layer 1004 is planarized and a dielectric layer 1006 is deposited and patterned to form a superconducting integrated circuit 1000b. As described above, the planarization of the first superconducting metal layer 1004 may include CMP. The dielectric layer 1006 is deposited on the surface 1008 of the first superconducting metal layer 1004 and patterned to form an opening 1010.

[0081] As described above, in some combinations of materials, the second superconducting metal may not adhere easily or surely to the material of the first superconducting layer and / or the dielectric layer. In some implementations, it may be advantageous to provide an adhesion layer or seed layer for the second superconducting material. This layer is deposited at a lower ambient temperature than the remainder of the second superconducting material forming the layer, and the ambient temperature is lower than the melting point of both the second superconducting metals. In some implementations, such as when the second superconducting metal is aluminum, as the deposition temperature increases, the grain size of aluminum increases, and as a result, the adhesion problem between materials may increase. In some implementations, it may be advantageous to deposit the first adhesion layer or seed layer of aluminum at a low temperature and then at a higher temperature. Aluminum at a low temperature can adhere easily to the metal layer and the dielectric layer, and aluminum at a high temperature can adhere easily to aluminum at a low temperature.

[0082] FIG. 10C is a cross-sectional view of the superconducting integrated circuit 1000b after low-temperature reflow deposition of the first portion 1012a for forming the superconducting integrated circuit 1000c. In some implementations, the first portion 1012a can be aluminum deposited at an ambient temperature of 100°C to 300°C.

[0083] FIG. 10D is a cross-sectional view of the superconducting integrated circuit 1000c during high-temperature reflow deposition of the second portion 1012b for forming the superconducting integrated circuit 1000d. In some implementations, the second portion 1012b can be aluminum deposited at an ambient temperature of 450°C to 650°C. The first portion 1012a and the second portion 1012b are collectively referred to herein as the second superconducting metal layer 1012.

[0084] FIG. 10E is a cross-sectional view of superconducting integrated circuit 1000d after high temperature reflow deposition is complete and the second metal layer has been polished to form superconducting integrated circuit 1000e. In some implementations, as a result of forming the first portion 1012a and the second portion 1012b at different ambient temperatures, an interface 1022 (e.g., a transition region) between the first portion 1012a and the second portion 1012b is distinguishable. For example, in some implementations, the grain size of aluminum in one region or layer (e.g., the first portion 1012a) may differ from the grain size of aluminum in another region or layer (e.g., the second portion 1012b) based on the ambient temperature at which the aluminum constituting each region or layer was deposited, resulting in a distinguishable interface of the transition between different aluminum grain sizes, which is detectable by appropriate means. Of course, this interface may include a finite mixing region (e.g., a transition region) between the first portion 1012a and the second portion 1012b.

[0085] In some implementations, the chemistry used to pattern the metal layer can cause metal contamination, which can in turn have adverse effects such as noise on the processor during use. In one implementation, aluminum is contaminated by the chemistry of fluorine-containing etching, which can generate noise for the processor. To reduce or eliminate this contamination, a passivation layer can be applied to the metal layer prior to the patterning operation, thereby preventing the upper surface of the metal from being exposed to potential contamination. The superconducting barrier layer or passivation layer is deposited covering the second superconducting metal layer, and the second superconducting metal layer and the superconducting barrier layer are patterned together.

[0086] FIG. 10F is a cross-sectional view of superconducting integrated circuit 1000e after passivation layer 1016 has been deposited to form superconducting integrated circuit 1000f.

[0087] FIG. 10G is a cross-sectional view of a superconducting integrated circuit 1000f after a second superconducting metal layer 1012 (composed of 1012a and 1012b) and a passivation layer 1016 are patterned to form a superconducting integrated circuit 1000g.

[0088] FIG. 10H is a cross-sectional view of a superconducting integrated circuit 1000g after the passivation layer 1016 is removed to form a superconducting integrated circuit 1000h.

[0089] Referring to FIGS. 1A - 1J, in some implementations, the described operations can be performed at a relatively low and uniform ambient temperature, for example, an ambient temperature such as 100°C to 300°C. In contrast, referring to FIGS. 10A - 10H, in another implementation, the described operations can be performed at two different temperatures, one being a relatively low ambient temperature, for example, 100°C to 300°C, and one being a relatively high ambient temperature but still lower than the melting point of the relevant superconducting metal, for example, 450°C to 650°C. In some implementations, both temperature ranges can be used in separate parts of the circuit.

[0090] FIG. 10I is a cross-sectional view of a portion of a superconducting integrated circuit 1000i having both high-temperature and low-temperature superconducting metal layers. FIG. 10I shows a connection and wiring layer 1018 (the connection communicates with the metal layer 1004) formed by a two-temperature process and a connection and wiring layer 1020 (the connection communicates with the connection and wiring layer 1018) formed by a one-temperature process. Of course, the order of components 1018 and 1020 can be reversed in another implementation, or components 1018 and 1020 can be formed in separate parts of the superconducting integrated circuit and may not communicate directly with each other.

[0091] FIG. 11 is a flowchart showing a method 1100 of forming a superconducting integrated circuit for a quantum processor according to the system and method of the present invention. Method 1100 can be used, for example, to form the components of the superconducting integrated circuit of FIGS. 10A - 10I. Method 1100 includes operations 1102 - 1118, but in other implementations, certain operations may be omitted, additional operations may be added, and / or the operations may be performed in a different order. Method 1100 can be performed, for example, by an integrated circuit manufacturing facility when a manufacturing process is initiated.

[0092] At 1102, a first dielectric layer can be deposited, for example, on top of a superconducting metal layer as described above.

[0093] At 1104, the first dielectric layer can be patterned to form an opening, which can be done, for example, to expose the surface of the underlying superconducting metal layer.

[0094] At 1106, a first superconducting metal is deposited at a first ambient temperature lower than the melting point of the first superconducting metal, whereby the first superconducting metal fills the opening of the first dielectric layer and forms a first connection portion that makes electrical contact with the conductive layer beneath the first dielectric layer, and forms a first superconducting metal layer that covers the first dielectric layer and the first connection portion.

[0095] At 1108, the first superconducting metal layer is optionally planarized, which is done, for example, by a chemical mechanical planarization process.

[0096] At 1110, the first superconducting metal layer is optionally patterned to form, for example, wiring.

[0097] At 1112, a first superconducting metal is deposited at a second ambient temperature lower than the melting point of the first superconducting metal, whereby the first superconducting metal aligns along the opening of the second dielectric layer and forms an adhesive layer that covers the second dielectric layer.

[0098] In 1114, the first superconducting metal is deposited at a third ambient temperature that is lower than the melting point of the first superconducting metal and higher than the second ambient temperature, and a filling layer is formed to cover the adhesion layer. Thereby, the adhesion layer and the filling layer fill the opening of the second dielectric layer and form a second connection portion that is in conductive contact with the conductive layer under the second dielectric, and form a second superconducting metal layer that covers the second dielectric layer and the first connection portion.

[0099] In some implementations, the first ambient temperature and the second ambient temperature can be the same, for example, they can be 100°C to 300°C. The third ambient temperature is higher than the second ambient temperature, for example, it can be 450°C to 650°C.

[0100] In 1116, the third metal layer can optionally be planarized, which can be performed, for example, by CMP.

[0101] In 1118, the second and third metal layers can be patterned, thereby forming, for example, wiring.

[0102] After 1118, the method can be repeated, that is, other components of the superconducting integrated circuit can be formed. The method can end, for example, end until it is restarted to form a new superconducting integrated circuit. Of course, method 1100 can be included in a larger manufacturing method, there can be any number of preceding manufacturing operations before operation 1102, and there can be any number of subsequent manufacturing operations after operation 1118.

[0103] In some implementations, operation 1106 can be performed before operations 1112 and 1114. In some implementations, a part of the integrated circuit can be manufactured at a low temperature and operation 1106 can be used, and another part of the integrated circuit can be manufactured at a high temperature and operations 1112 and 1114 can be used. For example, if the components of the superconducting integrated circuit are temperature-sensitive during manufacturing, the higher the temperature, the two-step process of operations 1112 and 1114 can be used at a lower level of the superconducting integrated circuit, and the lower the temperature, the one-step process of operation 1106 can be used at a higher level where temperature-sensitive devices are formed.

[0104] Another example of a superconducting integrated circuit that can be combined with the methods described herein is described in U.S. Patent No. 9,768,371.

[0105] The methods, processes, or techniques described above can be implemented by a series of process-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the methods, processes, or techniques described above can be implemented with somewhat specialized devices, such as adiabatic quantum computers or quantum annealers, or systems that program or otherwise control the operation of adiabatic quantum computers or quantum annealers (e.g., computers that include at least one digital processor). The methods, processes, or techniques described above can include various operations, but as will be understood by those skilled in the art, in alternative examples, certain operations may be omitted and / or additional operations may be added. As will be understood by those skilled in the art, the illustrated order of operations is presented by way of example only and can be changed in alternative examples. Some of the exemplary operations or actions of the methods, processes, or techniques described above are performed repeatedly. Some of the operations of the methods, processes, or techniques described above can be performed during each iteration or after multiple iterations or at the end of all iterations.

[0106] The foregoing description of the exemplary implementations, including what is described in the abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Specific implementations and examples have been described herein for illustrative purposes, but as will be recognized by those skilled in the art, various equivalent modifications can be made without departing from the spirit and scope of this disclosure. The teachings of the various implementations provided herein are applicable not only to the exemplary quantum computing methods generally described above, but also to other quantum computing methods.

[0107] The various implementations described above can be combined to realize further implementations. All of the U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications assigned to the assignee of the present invention, which are referenced herein and / or listed in the application data sheet, are hereby incorporated by reference in their entirety, including but not limited to U.S. Patent No. 9,768,371, entitled "SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS", filed on September 19, 2017, and U.S. Patent Application No. 63 / 042,865, entitled "SYSTEMS AND METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS", filed on June 23, 2020.

[0108] These and other modifications to the implementations can be made in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific implementations disclosed herein and in the claims, but rather should be construed to include all possible implementations, together with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A method of forming a superconducting integrated circuit for a quantum processor, comprising: depositing a first superconducting metal to form a first superconducting metal layer covering at least a portion of a substrate, the first superconducting metal layer including an upper surface having a first region; depositing a dielectric layer to cover the first region of the first superconducting metal layer; patterning the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and to form an opening having side surfaces defined by the dielectric layer and a bottom surface defined by the at least a portion of the exposed first region of the first superconducting metal layer; depositing a second superconducting metal in the form of a continuous thin layer at an ambient temperature lower than the melting point of the second superconducting metal, whereby the second superconducting metal reflows to fill the opening and form a connection in conductive contact with at least a portion of the first region of the first superconducting metal layer, and to form a second superconducting metal layer covering the dielectric layer and the connection; A method comprising the above steps.

2. The method according to claim 1, further comprising depositing an adhesive layer along at least the side surfaces of the opening before depositing the second superconducting metal.

3. The method according to claim 1, further comprising planarizing the first superconducting metal layer.

4. The method according to claim 1, further comprising planarizing the second superconducting metal layer.

5. The method according to claim 4, wherein planarizing the second superconducting metal layer includes chemical mechanical polishing (CMP).

6. The method according to claim 1, wherein patterning the dielectric layer to form an opening includes patterning the dielectric layer to form an opening having a dimension greater than 0.1 micron.

7. The method according to any one of claims 1 to 6, wherein depositing a second superconducting metal includes depositing aluminum.

8. The method according to claim 7, wherein depositing the second superconducting metal at an ambient temperature lower than the melting point of the second superconducting metal includes depositing at an ambient temperature lower than 650°C.

9. Depositing the second superconducting metal at an ambient temperature lower than the melting point of the second superconducting metal includes depositing at an ambient temperature of 100°C to 520°C, the method according to claim 8.

10. Depositing the second superconducting metal at an ambient temperature lower than the melting point of the second superconducting metal includes depositing a first portion at an ambient temperature of 100°C to 300°C and depositing a second portion at an ambient temperature of 450°C to 650°C, the method according to claim 7.

11. Depositing the second superconducting metal includes depositing aluminum by physical vapor deposition (PVD), the method according to claim 7.

12. Depositing the first superconducting metal includes depositing aluminum, the method according to claim 7.

13. Depositing the first superconducting metal includes depositing a first wiring layer, and Depositing the second superconducting metal includes depositing vias and a second wiring layer, the method according to claim 1.

14. After depositing the first superconducting metal layer, patterning the first superconducting metal layer to form additional openings, Depositing an additional dielectric layer to fill the additional openings, Depositing the dielectric layer to cover the first region of the first superconducting metal layer and the upper surface of the additional dielectric layer The method according to any one of claims 1 and 13, further comprising.

15. Before patterning the first superconducting metal layer, depositing a polishing stop layer on at least a portion of the first superconducting metal layer The method according to claim 14, further comprising, wherein patterning the first superconducting metal layer further comprises patterning the first superconducting metal layer and the polishing stop layer.

16. After depositing the additional dielectric layer to fill the additional openings, planarizing the additional dielectric layer so as to have an upper surface at the same height as the upper surface of the polishing stop layer, Removing the polishing stop layer The method according to claim 15, further comprising.

17. Depositing a second polishing stop layer on at least a portion of the second superconducting metal layer, Patterning the second polishing stop layer and the second superconducting metal layer to form a third opening, Depositing a third dielectric layer so as to fill the third opening The method according to claim 16, further comprising. **Claim 18** The method according to claim 1, further comprising depositing a superconducting barrier layer covering the second superconducting metal layer and patterning the second superconducting metal layer and the superconducting barrier layer.

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