Wafer-Level Package for Device

Abstract

According to one embodiment of the present invention, a wafer-level package (100) for a device is provided, the package (100) comprising a first substrate (102) and a second substrate (103), at least one insulating standoff structure (104) between the first substrate (102) and the second substrate (103), a bonding layer (108) on the at least one standoff structure (104), a first lateral electrical connection line (109) on a surface of the first substrate (102) and a second lateral electrical connection line (110) on a surface of the second substrate (103), and an electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) via the bonding layer (108) of the at least one standoff structure (104).

Description

Technical Field

[0001] The present invention relates to wafer-level packages for devices, particularly wafer-level packages for microelectromechanical systems (MEMS).

Background Art

[0002] Microelectromechanical systems (MEMS) are miniaturized mechanical and electromechanical elements such as devices and structures fabricated using microfabrication techniques. MEMS consist of components sized between 1 micrometer and 100 micrometers, and the size of MEMS devices generally ranges from approximately 20 micrometers to 1 millimeter.

[0003] Due to their small size, configuration, and extremely demanding manufacturing methods, MEMS devices are prone to electrical problems. For example, the formation of electrical interconnections by through-silicon vias (TSVs) is a complex and costly process.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Therefore, an improved structure and manufacturing method for wafer packaging are needed.

Means for Solving the Problems

[0005] The present invention is defined by the features of the independent claims. Some specific embodiments are defined in the dependent claims.

[0006] According to a first aspect of the present invention, a wafer-level package for a device is provided, the package comprising a first substrate and a second substrate, at least one insulating stand-off structure between the first substrate and the second substrate, a bonding layer on at least one stand-off structure, and a first lateral electrical connection line on the surface of the first substrate and a second lateral electrical connection line on the surface of the second substrate. An electrical connection is formed between the first lateral electrical connection line and the second lateral connection line via the bonding layer of at least one stand-off structure. The bonding layer includes a eutectic alloy.

[0007] According to a second aspect of the present invention, there is provided a method of forming a wafer-level package for a device, including fabricating a first lateral electrical connection line on the surface of a first substrate, fabricating a second lateral electrical connection line on the surface of a second substrate, fabricating at least one insulating stand-off structure over a portion of the first lateral electrical connection line, fabricating a first bonding material layer on the surface of at least one stand-off structure, and bonding the first bonding material layer to the second lateral electrical connection line to form a bonding layer on the stand-off structure, and generating an electrical connection between the first lateral electrical connection line and the second lateral connection line via the bonding layer of at least one stand-off structure. The bonding of the first bonding material layer to the second lateral electrical connection line is provided by eutectic bonding.

[0008] According to one embodiment, the package includes at least one groove in the first substrate.

[0009] According to one embodiment, an electrical connection is formed across at least one groove via the second lateral connection line.

[0010] According to one embodiment, an electrical connection is formed across at least one groove via a second bonding material layer.

[0011] According to one embodiment, the package comprises at least one hermetic structure, which includes a seal ring between a first substrate and a second substrate, a bonding layer on the surface of the second substrate, and a plurality of micro-rings within the seal ring that confine the molten metal of the bonding layer between the micro-rings.

[0012] The present invention provides considerable advantages. The present invention enables a simple and cost-effective method of providing an electrical interconnection between the electrodes and pads of a device, especially when the electrodes and pads are separated by deep grooves and / or cavities with deep grooves, or when the electrodes of the device have deep grooves inside the packaging and pads outside the packaging. The structure is automatically generated during the processing of the bonding structure. Therefore, no additional lithography or etching processes, which would otherwise make the manufacturing process more complex and costly, are required.

[0013] Embodiments of the present invention widen the process window in the bonding of substrates, especially in the eutectic bonding of substrates. Due to the exact height of the micro-rings, an exact gap is provided for the micro-rings, and no temperature and pressure non-uniformities are seen in this gap like vacancies.

Advantages of the Invention

[0014] Embodiments of the present invention suppress misalignment due to sliding between the bonded substrates due to local press-fitting and increased friction, thus improving the bonding quality.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2A

Figure 2C

Figure 3A

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Figure 4E

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Figure 6

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the context of this specification, the term "substrate" includes wafers such as MEMS device wafers and cap wafers.

[0017] In the context of this specification, the term "first structure" includes a first substrate such as a device wafer and a layer on the first substrate before bonding.

[0018] In the context of this specification, the term "second structure" includes a second substrate such as a cap wafer and a layer on the second substrate before bonding.

[0019] An object of at least some embodiments of the present invention is to provide a simple and cost-effective electrical interconnection between the electrodes and pads of a device, particularly for a microelectromechanical system (MEMS) device.

[0020] FIG. 1 illustrates a portion of a wafer level package 100 according to an embodiment. The package 100 includes a first substrate 102 and a second substrate 103, at least one insulating standoff structure 104 between the first substrate 102 and the second substrate 103, a bonding layer 108 on at least one standoff structure 104, and a first lateral electrical connection line 109 on the surface of the first substrate 102 and a second lateral electrical connection line 110 on the surface of the second substrate 103. An electrical connection is formed between the first lateral electrical connection line 109 and the second lateral connection line 110 through the bonding layer 108 of at least one standoff structure 104. This enables electrical interconnection between the electrodes and pads of the device, especially when the electrodes and pads are separated by deep grooves and / or cavities with deep grooves, or when the electrodes of the device have deep grooves inside the packaging and pads outside the packaging. The structure is automatically generated during the processing of the bonding structure. Therefore, no additional lithography or etching process that would make the manufacturing process more complex and costly is required.

[0021] The bonding layer 108 includes a eutectic alloy. The eutectic alloy may include two or more metals. Suitable eutectic alloys include, for example, germanium-aluminum, gold-tin, gold-germanium, gold-silicon, gold-indium, or copper-tin alloys.

[0022] According to an embodiment, each of the at least one insulating standoff structure 104 has a height of less than 10 μm, such as less than 5 μm, for example 1 - 2 μm.

[0023] According to an embodiment, the thickness of the first lateral electrical connection line 109 is 0.2 - 5 μm, such as 0.5 - 1 μm.

[0024] According to an embodiment, the thickness of the first lateral electrical connection line 109 is smaller than the height of at least one insulating standoff structure 104.

[0025] According to an embodiment, the thickness of the bonding layer 108 is less than 5 μm, such as 0.5 - 2 μm.

[0026] According to one embodiment, the first substrate 102 comprises a passivation layer 111 on the surface of the first substrate 102, and / or the second substrate 103 comprises a passivation layer 112 on the surface of the second substrate 103. The passivation layer may include, for example, silicon dioxide (SiO2), aluminum oxide (Al2O3), or aluminum nitride (AlN). The passivation layer prevents short circuits of elements of the package or package device by preventing electrical contact between the substrate elements.

[0027] In one embodiment, the first substrate 102 and the second substrate 103 include silicon or ceramic. Silicon is a very reliable substrate material because it can have a very long service life with very little fatigue and no breakage. In single crystal form, silicon has virtually no hysteresis, and thus there is almost no energy dissipation. Suitable ceramic substrates are, for example, silicon nitride, aluminum nitride, titanium nitride, or silicon carbide. Aluminum nitride in the wurtzite structure exhibits pyroelectric and piezoelectric properties, which enables the production of sensors, for example, with sensitivity to vertical and shear forces. Titanium nitride exhibits high conductivity and a high modulus of elasticity.

[0028] According to one embodiment, the first lateral electrical connection line 109 and the second electrical connection line 110 include a metal such as molybdenum, aluminum, or copper. These metals enable a good and reliable electrical connection in the lateral electrical connection line between the device inside the package and the electrical circuit outside the package.

[0029] According to one embodiment, the insulating standoff structure 104 includes a dielectric material such as a ceramic material. The standoff structure may include, for example, silicon dioxide (SiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (Si3N4), or silicon carbide (SiC). These materials provide a good wetting surface and good electrical insulation for the bonding layer 108.

[0030] In one embodiment, packages 100, 200 include at least one groove 113, 205, 213 in a first substrate 102, 202. And an electrical connection is formed between a first lateral electrical connection line 109, 209 and a second lateral connection line 110, 210 through a bonding layer 108 of at least one stand-off structure 104, 214, 215, 216, 217, and also across at least one groove 113, 205, 213 through the second lateral connection line. This enables a simple and cost-effective structure that provides electrical interconnection of devices separated by the grooves.

[0031] According to one embodiment, the wafer-level package 200 includes a cavity 224 in a second substrate 203.

[0032] According to one embodiment, package 200 includes a getter 225 on the surface of cavity 224. The getter 225 can be used to generate and maintain a vacuum. The getter can be a thin-film getter. The getter absorbs some or all of the gases expected to be released into the cavity, such as water vapor, oxygen, carbon monoxide, carbon dioxide, nitrogen, hydrogen, and / or other gases. The getter includes metals that easily absorb gases. For example, the getter can include at least one of the following, namely titanium, aluminum, zirconium, boron, cobalt, calcium, strontium, or thorium.

[0033] In one embodiment, the wafer-level package 200 includes at least one hermetic structure 219. The hermetic structure 219 can include a seal ring 221 between the first substrate 202 and the second substrate 203, a bonding layer 222 on the surface of the second substrate, and a plurality of micro-rings 223 within the seal ring that confine the molten metal of the bonding layer between the micro-rings.

[0034] Detailed information about the seal ring and other related structures is presented in Finnish Patent Application No. 20205075, which is incorporated herein by reference.

[0035] The micro-ring of the hermetic structure 219 widens the process window in the bonding of the substrates, especially in the eutectic bonding of the substrates. Also, due to the exact height of the micro-ring, an exact gap is provided in the micro-ring, and in this gap, non-uniformity of temperature and pressure is not seen like a void. The hermetic structure suppresses the misalignment due to sliding between the bonded substrates due to local press-fitting and increased friction, thus improving the bonding quality.

[0036] The seal ring 221 may include a dielectric material or a ceramic material, for example, silicon dioxide (SiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (Si3N4), or silicon carbide (SiC).

[0037] The bonding layer 222 may include a eutectic alloy. The eutectic alloy may include two or more metals. Suitable eutectic alloys include, for example, germanium-aluminum, gold-tin, gold-germanium, gold-silicon, gold-indium, or copper-tin alloys.

[0038] Next, the structure of the wafer package for the device is considered in more detail by way of an embodiment.

[0039] Figures 2A through 2C illustrate that the package 200 includes four stand-off structures 214, 215, 216, 217 between the first substrate 202 and the second substrate 203. The package includes a bonding layer 208 on the stand-off structures 214, 215, 216, 217. The first lateral electrical connection line 209 is on the surface of the first substrate 202, and the second lateral electrical connection line 210 is on the surface of the second substrate 203.

[0040] Figures 2A through 2C illustrate that package 200 includes at least one groove 205, 213 in first substrate 202. The package may include groove 205 between insulating standoff structures 214, 215 and groove 213 between insulating standoff structures 216, 217. An electrical connection is formed between first lateral electrical connection line 209 and second lateral connection line 210 through bonding layer 208 of standoff structures 214, 215 and through second lateral electrical connection line 210 that crosses groove 205, and also through second lateral electrical connection line 210 that crosses groove 213 together with bonding layer 208 of standoff structures 216, 217.

[0041] Figures 2A through 2C illustrate that package 200 includes groove 213 having cavity 226.

[0042] Figure 2B illustrates that an electrical signal can pass from first electrical lateral connection line 209 to second lateral electrical connection line 210 through bonding layer 208 of standoff structure 215 and through second lateral electrical connection line 210 that crosses groove 205 between standoff structures 214, 215. In each case, an electrical signal can pass from second lateral electrical connection line 210 to first lateral electrical connection line 209 through bonding layer 208 of standoff structure 214.

[0043] Figure 2C illustrates that an electrical signal can pass from first lateral electrical connection line to second lateral electrical connection line through the bonding layer of standoff structure 216 and through second lateral electrical connection line 210 that crosses groove 213 between standoff structures 216, 217. In each case, an electrical signal can pass from second lateral electrical connection line 210 to first lateral electrical connection line 209 through bonding layer 208 of standoff structure 217.

[0044] Furthermore, Figure 2A illustrates that wafer level package 200 includes cavity 224 in second substrate 203. Additionally, package 200 includes getter 225 on the surface of cavity 224.

[0045] Figures 2A through 2C illustrate that the wafer level package 200 includes a hermetic structure 219. The hermetic structure 219 can surround the cavity 224.

[0046] According to one embodiment, a method for forming wafer level packages 100, 200 for devices is provided. The method includes fabricating first lateral electrical connection lines 109, 209 on the surface of a first substrate 102, 202; fabricating second lateral electrical connection lines 110, 210 on the surface of a second substrate 103, 203; fabricating at least one insulating standoff structure 104, 214, 215, 216, 217 across a portion of the first lateral electrical connection lines 109, 209; fabricating a first bonding material layer 106, 206 on the surface of the at least one standoff structure 104, 214, 215, 216, 217; bonding the first bonding material layer 106, 206 to the second lateral electrical connection lines 110, 210 to generate a bonding layer 108, 208 on the standoff structure 104, 214, 215, 216, 217; and generating an electrical connection between the first lateral electrical connection lines 109, 209 and the second lateral connection lines 110, 210 through the bonding layer 108, 208 of the at least one standoff structure 104, 214, 215, 216, 217. This enables a simple and cost-effective approach for providing electrical interconnections for devices.

[0047] The bonding of the first bonding material layer 106, 206 to the second lateral electrical connection lines 110, 210 is provided by eutectic bonding. First, the temperature can be raised to a value lower than the eutectic temperature of the eutectic alloy. Then, the temperature can be maintained constant for a short time to achieve uniform heating of both the first substrate and the second substrate. Thereafter, the temperature can be raised to a temperature above the eutectic point. Finally, the structure can be cooled to a temperature below the eutectic temperature.

[0048] Eutectic bonding does not require the use of a high constant force during bonding. Since the eutectic bonding process passes through a liquid phase, compared to direct wafer bonding methods, eutectic bonding is less susceptible to surface flatness irregularities, scratches, and particles.

[0049] According to one embodiment, the second lateral electrical connection lines 110, 210 comprise second bonding material layers 107, 207 on the surfaces of the second lateral electrical connection lines 110, 210. Therefore, the first bonding material layers 106, 206 can be bonded to the second bonding material layers 107, 207 to generate bonding layers 108, 208.

[0050] According to one embodiment, this method includes fabricating a passivation layer 111, 211 on the surface of the first substrate 102, 202 and / or fabricating a passivation layer 112, 212 on the surface of the second substrate 103, 203. The passivation layers 111, 112 can be grown by thermal oxidation in which the layer is exposed to oxygen and / or vapor to grow a thin surface layer on the layer.

[0051] According to one embodiment, this method includes fabricating at least one groove 113, 205, 213 in the first substrate 102, 202. This method may include fabricating a groove 205 between insulating standoff structures 214, 215 and fabricating a groove 213 between insulating standoff structures 216, 217. The groove can be formed, for example, by silicon wet or dry etching.

[0052] This method may include forming a cavity 224 in the second substrate 203. The cavity can be formed, for example, by silicon wet or dry etching.

[0053] Furthermore, this method may include forming a getter 225 in the cavity 224 of the second substrate 203. The getter 225 can be formed by a getter deposition process. For example, the getter can be deposited by sputtering, resistive evaporation, E-beam evaporation, or other suitable deposition techniques.

[0054] In one embodiment, the method includes fabricating at least one hermetic structure 219 across a portion of the first lateral electrical connection line 209. First, a seal ring 221 of the hermetic structure 219 is formed across a portion of the first lateral electrical connection line 209. Then, a first bonding material layer 206 is formed on the surface of the seal ring 221. Thereafter, a second bonding material layer 207 is formed on the surface of the second substrate 203. Finally, the first bonding material layer is bonded to the second bonding material layer to generate a bonding layer 208.

[0055] The layer of at least one hermetic structure 219 can be formed simultaneously with the layer of at least one insulating standoff structure 104, 214 - 217. For example, while the insulating standoff structures 104, 214 - 217 are being formed, the seal ring 221 of the hermetic structure 219 can be formed. Thus, the first bonding material layer 206 and the second bonding material layer 207 of the hermetic structure and the insulating standoff structure can be formed simultaneously.

[0056] Next, a method for forming a wafer package for a device is considered in more detail by way of an example embodiment.

[0057] Figures 3A through 3F illustrate a method of manufacturing a first structure according to several embodiments. First, a first substrate 202 for preparing a MEMS structure is obtained. This structure, as shown in Figure 3A, comprises two silicon layers that are joined together and surround a cavity inside. Then, a passivation layer 211 is provided on the first substrate 202 (Figure 3B). A first lateral electrical connection line 209 is deposited on the passivation layer 211 (Figure 3C). Thereafter, at least one insulating stand-off structure 214, 215, 216, 217 is deposited on the first lateral electrical connection line 209. Furthermore, at least one sealing structure 219 may also be deposited on the first lateral electrical connection line 209 (Figure 3D). And, as shown in Figure 3E, a first bonding material layer 206 is deposited on the surface of at least one stand-off structure 214, 215, 216, 217 and / or at least one sealing structure 219. Finally, for example, by silicon wet or dry etching, grooves 205, 213 and a MEMS device 218 are formed in the first substrate 202.

[0058] Figures 4A through 4E illustrate a method of manufacturing a second structure according to several embodiments. First, a passivation layer 212 is provided on a second substrate 203 (Figure 4A). Then, a second lateral electrical connection line 210 and a second bonding material layer 207 are deposited on the passivation layer 212 (Figure 4B). As shown in Figure 4C, for example, by plasma cleaning, wet chemical etching, or dry chemical etching, the passivation layer 212 can be partially removed. Thereafter, for example, by silicon wet or dry etching, a cavity 224 can be formed in the second substrate 203 (Figure 4D). Finally, and optionally, as shown in Figure 4E, a getter 225 can be deposited on the surface of the cavity 224.

[0059] The deposition of the layers of the wafer-level packages 100, 200, such as the first bonding material layers 106, 206 and the second bonding material layers 107, 207, can be performed by a deposition process. The deposition process can include, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0060] FIG. 5 illustrates an alternative embodiment for forming a wafer level package. The first substrate 302 includes a passivation layer 311 on the surface of the first substrate. In addition, the first substrate 302 includes a hermetic structure 319 and a first lateral connection line 309 on the surface of the first substrate. The hermetic structure 319 includes a seal ring 321 and a first bonding material layer 306 on the surface of the seal ring. The second substrate 303 includes a standoff structure 304. The standoff structure 304 includes a second bonding material layer 307 on the surface of the standoff structure. A groove 313 is formed in the first substrate between the hermetic structure and the standoff structure 304.

[0061] A wafer level package is formed by bonding the first bonding material layer 306 on the seal ring 321 to the second bonding material layer 307 to form a bonding layer. And an electrical connection is formed through at least one groove 313 via the second bonding material layer 307.

[0062] FIG. 6 illustrates an alternative embodiment for a wafer level package. The first substrate 402 includes a standoff structure 404. The first bonding material layer 406 is partially provided on the surface of the standoff structure 404 and on the first substrate 402. The second substrate 403 includes a second lateral electrical connection line 410 and a hermetic structure 419. The hermetic structure 419 includes a seal ring 421. The second bonding material layer 407 is partially provided on the surface of the seal ring and on the surface of the second lateral electrical connection line 410. The first substrate may further include a passivation layer 411 on the surface of the first substrate, and the second substrate may further include a passivation layer 412 on the surface of the second substrate. A groove 413 is provided in the first substrate between the standoff structure 404 and the hermetic structure 419.

[0063] The wafer level package is formed by bonding the first bonding material layer 406 and the second bonding material layer 407. And an electrical connection is formed across the groove via the second lateral electrical connection line 410.

[0064] According to some embodiments, the hermetic structure is for a MEMS device. However, the hermetic structure can be used in other devices such as automotive devices, e.g., rider components and tire pressure sensors, RF components, e.g., switches, filters, inductors, antennas, passive optical elements, e.g., silicon waveguides and modulators, microspectrometers, and plasmonic devices.

[0065] It is to be understood that the embodiments of the invention disclosed herein are not limited to the specific structures, processes, steps, or materials disclosed herein, but extend to equivalents thereof that would be recognized by those skilled in the art. It should also be understood that the terms employed herein are used only for the purpose of describing particular embodiments and are not intended to be limiting.

[0066] References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment.

[0067] As used herein, a plurality of articles, structural elements, components, and / or materials may be presented in a common list for convenience. However, these lists should not be construed as though each member of the list is individually identified as a separate and unique member. Thus, unless the contrary is indicated, each individual member of such a list should not be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group. In addition, various embodiments and examples of the invention may be referred to herein along with alternatives for the various components thereof. It is understood that such embodiments, examples, and alternatives are not to be construed as de facto equivalents of one another, but rather as separate and distinct representative examples of the invention.

[0068] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details such as examples of length, width, shape, etc. are provided to provide a complete understanding of the embodiments of the invention. However, those skilled in the art will recognize that the invention may be practiced without one or more of the specific details, or in combination with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the aspects of the invention.

[0069] The above examples illustrate the principles of the invention in one or more specific applications, but it will be apparent to those skilled in the art that various modifications can be made in the details of form, use, and implementation without the exercise of inventive faculty and without departing from the principles and concepts of the invention. Accordingly, the invention is not intended to be limited except as defined by the claims presented below.

[0070] The verbs "to comprise" and "to include" are used in this document as open limitations that do not require the exclusion of the presence of features not described, nor do they require the presence of features not described. The features described in the dependent claims are freely combinable with each other unless it is expressly stated otherwise. Furthermore, it should be understood that the use of "a" or "an" throughout this document, i.e., the singular form, does not exclude the plural.

Description of Reference Numerals

[0071] 100, 200 Wafer-Level Package 102, 202, 302, 402 First Substrate 103, 203, 303, 403 Second Substrate 104, 304, 404 Stand-Off Structure 106, 206, 306, 406 First Bonding Material Layer 107, 207, 307, 407 Second Bonding Material Layer 108, 208 Bonding Layer 109, 209, 309 First horizontal electrical connection line 110, 210, 410 Second horizontal electrical connection line 111, 112, 211, 212, 311, 411, 412 Inactivation layer 113, 205, 213, 313, 413 Groove portion 214~217 Stand-off structure 218 MEMS device 219, 319, 419 Sealing structure 221, 321, 421 Seal ring 222 Bonding layer 223 Microring 224, 226 Cavity 225 Getter

Claims

1. A wafer-level package (100) for a device, comprising: a first substrate (102) and a second substrate (103); at least one insulating stand-off structure (104) between the first substrate (102) and the second substrate (103); a bonding layer (108) on the at least one insulating stand-off structure (104); a first lateral electrical connection line (109) on the surface of the first substrate (102) and a second lateral electrical connection line (110) on the surface of the second substrate (103); wherein an electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) through the bonding layer (108) of the at least one stand-off structure (104), and the bonding layer (108) comprises a eutectic alloy. The wafer-level package (100).

2. The wafer-level package (100) according to claim 1, wherein each of the at least one insulating stand-off structure (104) has a height of less than 10 μm, such as less than 5 μm, for example 1 - 2 μm.

3. The wafer-level package (100) according to any one of the preceding claims, wherein the thickness of the first lateral electrical connection line (109) is 0.2 - 5 μm, such as 0.5 - 1 μm.

4. The wafer-level package (100) according to any one of the preceding claims, wherein the thickness of the first lateral electrical connection line (109) is smaller than the height of the at least one insulating stand-off structure (104).

5. The wafer-level package (100) according to any one of the preceding claims, wherein the thickness of the bonding layer (108) is less than 5 μm, such as 0.5 - 2 μm.

6. The wafer-level package (100) according to any one of the preceding claims, wherein the first substrate (102) comprises a passivation layer (111) on the surface of the first substrate (102), and / or the second substrate (103) comprises a passivation layer (112) on the surface of the second substrate (103).

7. The wafer-level package (100, 200) according to any one of the preceding claims, wherein the package (100, 200) comprises at least one groove (113, 205, 213) in the first substrate (102, 202).

8. ​ The wafer-level package (100, 200) according to claim 7, wherein an electrical connection is formed through the at least one groove portion (113, 205, 213) via the second horizontal connection line (110, 210).

9. The wafer-level package (100, 200) according to claim 7, wherein an electrical connection is formed through the at least one groove portion (313) via the second bonding material layer (307).

10. The package (200) comprises at least one hermetic structure (219), and the hermetic structure (219) a seal ring (221) between the first substrate (202) and the second substrate (203), a bonding layer (222) on the surface of the second substrate, a plurality of micro-rings (223) in the seal ring that confine the molten metal of the bonding layer between the micro-rings, comprising the wafer-level package (200) according to any one of the preceding claims.

11. The wafer-level package (100) according to any one of the preceding claims, wherein the package (100) is for a MEMS device.

12. A method for forming a wafer-level package (200) for a device, comprising: fabricating a first horizontal electrical connection line (209) on the surface of a first substrate (202); fabricating a second horizontal electrical connection line (210) on the surface of a second substrate (203); fabricating at least one insulating standoff structure (214) over a portion of the first horizontal electrical connection line (209); fabricating a first bonding material layer (206) on the surface of the at least one standoff structure (214); bonding the first bonding material layer (206) to the second horizontal electrical connection line (210) to generate a bonding layer (208) on the standoff structure (214), and generating an electrical connection between the first horizontal electrical connection line (209) and the second horizontal connection line (210) through the bonding layer (208) of the at least one standoff structure (214); including the bonding between the first bonding material layer (206) and the second horizontal electrical connection line (210) is provided by a eutectic bond, method.

13. The method according to claim 12, wherein each of the at least one insulating standoff structure (104) has a height of less than 10 μm, such as less than 5 μm, for example 1 - 2 μm.

14. The method according to any one of preceding claims 12 to 13, wherein the thickness of the first horizontal electrical connection line (109) is 0.2 to 5 μm, such as 0.5 to 1 μm.

15. The method according to any one of preceding claims 12 to 14, wherein the thickness of the first horizontal electrical connection line (109) is smaller than the height of the at least one insulating stand-off structure (104).

16. The method according to any one of preceding claims 12 to 15, wherein the thickness of the bonding layer (108) is less than 5 μm, such as 0.5 to 2 μm.

17. The method according to any one of preceding claims 12 to 16, comprising fabricating a passivation layer (211) on the surface of the first substrate (202) and / or fabricating a passivation layer (212) on the surface of the second substrate (203).

18. The method according to any one of preceding claims 12 to 17, comprising fabricating a second bonding material layer (207) on the surface of the second horizontal electrical connection line (210).

19. The method according to any one of preceding claims 12 to 18, comprising fabricating at least one groove (205, 213) in the first substrate (202).

20. The method according to any one of preceding claims 12 to 19, comprising fabricating at least one sealing structure (219) over a portion of the first horizontal electrical connection line (209).

21. The method according to any one of preceding claims 12 to 20, wherein the wafer-level package (200) is for a MEMS device.

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