Imaging Device and Electronic Apparatus

Abstract

To provide an imaging device with excellent imaging performance.SOLUTION: A region where a first layer, a second layer, and a third layer overlap with each other is provided. Each of the first layer and the second layer includes a transistor. The third layer includes a photoelectric conversion element. An off current of the transistor formed in the first layer is smaller than that of the transistor formed in the second layer. Field effect mobility of the transistor formed in the second layer is larger than that of the transistor formed in the first layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device using an oxide semiconductor.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification includes, as an example, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, driving methods thereof, or manufacturing methods thereof. can be cited as an example.

[0003] Note that in this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of a semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device.

Background Art

[0004] Techniques for forming transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. As semiconductor materials applicable to transistors, silicon-based semiconductors are widely known, but oxide semiconductors are attracting attention as other materials.

[0005] For example, zinc oxide or an In-Ga-Zn-based oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors are disclosed (see Patent Document 1 and Patent Document 2).

[0006] Further, in Patent Document 3, a transistor having an extremely low off-current with an oxide semiconductor is used for a part of a pixel circuit, and a transistor having silicon capable of fabricating a CMOS (Complementary Metal Oxide Semiconductor) circuit is used for a peripheral circuit to disclose an imaging device having a configuration.

[0007] Further, in Patent Document 4, an imaging device having a configuration in which a transistor having silicon, a transistor having an oxide semiconductor, and a photodiode having a crystalline silicon layer are stacked is disclosed has been.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0009] The characteristics required for individual transistors may differ even within the same circuit. For example the amplification transistor of a pixel of an image sensor preferably has high on-current characteristics. Also, the transfer transistor connected to the photodiode has low off-current characteristics and ​​This is preferable. That is, in order to form an imaging device with excellent performance, it is desirable to fabricate transistors so as to have the required characteristics.

[0010] Therefore, in one aspect of the present invention, an object is to provide an imaging device with excellent imaging performance. One object is to provide an imaging device having transistors formed of different materials. Or, one object is to provide an imaging device in which transistors formed of different materials are stacked. Or, one object is to provide an imaging device suitable for high-speed operation. Or, one object is to provide an imaging device with high resolution. Or, one object is to provide an imaging device with high integration density. Or, one object is to provide an imaging device with low power consumption. Or, one object is to provide an imaging device capable of imaging under low illumination. Or, one object is to provide an imaging device with a wide dynamic range. Or, one object is to provide an imaging device usable in a wide temperature range. Or, one object is to provide an imaging device with a high aperture ratio. Or, one object is to provide an imaging device with high reliability. Or, one object is to provide a novel imaging device or the like.

[0011] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention is not required to solve all of these problems. Note that other problems will become apparent from the description of the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other problems from the descriptions such as the surface and claims.

Means for Solving the Problems

[0012] One aspect of the present invention relates to an imaging device having a transistor formed using an oxide semiconductor. .

[0013] One aspect of the present invention is an imaging device having a first layer, a second layer, and a third layer, wherein the first layer, the second layer, and the third layer each have a region overlapping with each other, and the first layer has a first transistor and a second transistor, the second layer has a third transistor and a fourth transistor, the first to fourth transistors have an oxide semiconductor in the active layer, the third layer has a photoelectric conversion element, one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the second transistor is electrically connected to the gate of the third transistor, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, one of the electrodes of the photoelectric conversion element is electrically connected to the other of the source or drain of the first transistor, and the off-currents of the first and second transistors are smaller than those of the third and fourth transistors, and the field-effect mobilities of the third and fourth transistors are larger than those of the first and second transistors. An imaging device is characterized by this.

[0014] In the above aspect, the first layer, the second layer, and the third layer are, in the height direction, the first layer, the A configuration in which layers are arranged in the order of the second layer and the third layer, or in the order of the second layer, the first layer, and the third layer It can be configured to be arranged in the height direction.

[0015] Another aspect of the present invention is an imaging device having a stacked body including a first layer, a second layer, a third layer, and a fourth layer, wherein the first layer, the second layer, the third layer, and the fourth layer each have an overlapping region with each other, the first layer has a photoelectric conversion element, the second layer has a first transistor and a second transistor, the third layer has a third transistor and a fourth transistor, the fourth layer has a fifth transistor, the first transistor to the fourth transistor have an oxide semiconductor in the active layer, the fifth transistor has silicon in the active region or the active layer, the first transistor to the fourth transistor constitute a first circuit, the fifth transistor constitutes a second circuit, one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the second transistor is electrically connected to the gate of the third transistor, one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor, one of the electrodes of the photoelectric conversion element is electrically connected to the other of the source or drain of the first transistor, the off-currents of the first transistor and the second transistor are smaller than those of the third transistor and the fourth transistor, and the field-effect mobilities of the third transistor and the fourth transistor are larger than those of the first transistor and the second transistor. The imaging device is characterized by this.

[0016] ​​​​ Another aspect of the present invention includes a first layer, a second layer, a third layer, and a fourth layer An imaging device having a laminated body, wherein the first layer, the second layer, the third layer, and the fourth layer Each has an overlapping region with each other, the first layer has a photoelectric conversion element, and the second layer has a first First transistor and a second transistor, the third layer has a third transistor, A fourth transistor and a fifth transistor, the fourth layer has a sixth transistor The first transistor to the fifth transistor have an oxide semiconductor in the active layer, and the first Sixth transistor has silicon in the active region or the active layer, and the first transistor to the Fourth transistor constitutes a first circuit, and the fifth transistor and the sixth transistor Constitute a second circuit, and one of the source or drain of the first transistor is the second One of the source or drain of the transistor is electrically connected, and one of the source or drain of the second transistor One of the source or drain of the transistor is electrically connected to the gate of the third transistor, and the third One of the source or drain of the transistor is electrically connected to one of the source or drain of the fourth transistor One electrode of the photoelectric conversion element is electrically connected to the other of the source or drain of the first transistor And the off-current of the first transistor and the second transistor is the third transistor, the fourth transistor, and the fifth transistor Smaller than the transistor, and the field-effect mobility of the third transistor, the fourth transistor, and the fifth transistor Is larger than that of the first transistor and the second transistor, and is an imaging device characterized by this

[0017] ​​In the aspect having the first to fourth layers, the first layer, the second layer, the third layer, and the fourth layer may be arranged in the height direction in the order of the first layer, the second layer, the third layer, and the fourth layer, or may be arranged in the order of the first layer, the third layer, the second layer, and the fourth layer. That is possible.

[0018] Also, one of the source or drain of the first transistor may be configured to be electrically connected to one electrode of the capacitive element. That is possible.

[0019] Also, the oxide semiconductor preferably contains In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0020] Also, in the photoelectric conversion element, selenium or a compound containing selenium can be used for the photoelectric conversion layer. That is possible.

Advantages of the Invention

[0021] Therefore, in one aspect of the present invention, an imaging device with excellent imaging performance can be provided. Or, an imaging device having transistors formed of different materials can be provided. Or, an imaging device in which transistors formed of different materials are stacked can be provided. Or, an imaging device suitable for high-speed operation can be provided. Or, an imaging device with high resolution can be provided. Or, an imaging device with high integration can be provided. Or, an imaging device with low power consumption can be provided. Or, an imaging device capable of imaging under low illuminance can be provided. Or, an imaging device with a wide dynamic range can be provided. Or, an imaging device that can be used in a wide temperature range can be provided. That is possible. can be provided. Or, an imaging device with a high aperture ratio can be provided. Or , a highly reliable imaging device can be provided. Or, a novel imaging device or the like can be provided . Or, a novel semiconductor device or the like can be provided.

[0022] Note that one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention may, in some cases or depending on the situation, have effects other than these. Or, for example, one aspect of the present invention may, in some cases or depending on the situation, not have these effects.

Brief Description of the Drawings

[0023]

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Mode for Carrying Out the Invention

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description content of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description may be omitted. In addition, the matching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it means both when X and Y are electrically connected and when X and Y are functionally connected. When it is clearly stated that X and Y are connected in this specification or the like, it includes both the case where X and Y are electrically connected and the case where X and Y are functionally connected. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description may be omitted. In addition, the matching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings. In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description may be omitted. In addition, the matching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it means both when X and Y are electrically connected and when X and Y are functionally connected. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it means both when X and Y are electrically connected and when X and Y are functionally connected.

[0025] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it means both when X and Y are electrically connected and when X and Y are functionally connected. For example, in this specification and the like, when it is explicitly described that X and Y are connected, it means both when X and Y are electrically connected and when X and Y are functionally connected. It is assumed that the combination and the case where X and Y are directly connected are those disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or a text. In addition, those other than the connection relationship shown in the figure or the text are also regarded as those described in the figure or the text. That is.

[0026] Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0027] As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitor element, an inductor, a resistor element, a diode , a display element, a light-emitting element, a load, etc.) that enables an electrical connection between X and Y is not connected between X and Y. In other words, it is a case where X and Y are connected without an element (for example, a switch, a transistor, a capacitor element, an inductor, a resistor element, a diode, a display element, a light-emitting element, a load, etc.) that enables an electrical connection between X and Y. That is, it is a case where X and Y are connected without passing through an element (for example, a switch, a transistor, a capacitor element, an inductor, a resistor element, a diode, a display element, a light-emitting element, a load, etc.) that enables an electrical connection between X and Y.

[0028] As an example of the case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitor element, an inductor, a resistor element, a diode , a display element, a light-emitting element, a load, etc.) that enable an electrical connection between X and Y can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not. Or, the switch has a function of selecting and switching a path through which current flows. Note that when X and Y are electrically connected, X and Y... This shall include the case where it is directly connected to Y.

[0029] As an example of the case where X and Y are functionally connected, a circuit that enables the functional connection between X and Y (for example, a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.) , a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., such as an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected with one or more between X and Y. Note that, as an example, even if there is another circuit between X and Y, when the signal output from X is transmitted to Y, X and Y shall be considered to be functionally connected. Note that when X and Y are functionally connected, it shall include the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0030] Note that when it is explicitly described that X and Y are electrically connected, the cases where X and Y are electrically connected (that is, when connected with another element or another circuit sandwiched between X and Y) and the cases where X and Y are functionally connected (that is, when functionally connected with another circuit sandwiched between X and Y) and the case where X and Y are directly connected (that is, when connected without another element or another circuit sandwiched between X and Y) shall be those disclosed in this specification, etc. That is, being electrically connected, as explicitly stated When it is described only as being connected, if it is described as such in a certain context Assume that the same content is disclosed in this specification or the like.

[0031] For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without passing through) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without passing through) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y." Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." For example, when the source (or the first terminal, etc.) of a transistor is electrically connected to X via (or without passing through) Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via (or without passing through) Z2, or when the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, another part of Z1 is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. to a part of Z2, and another part of Z2 is directly connected to Y, it can be expressed as follows. It can be expressed as follows. It can be done as follows.

[0032] For example, "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y." The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order. Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." 1 of the terminals, etc.), the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order. Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y." Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." 1 of the terminals, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order. Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order. Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." The drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order. Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." It can be expressed as follows. Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." For example, "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y." Or, "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." Or, "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, Y are electrically connected in this order." The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ) can be expressed as "Y is provided in this connection order." Similar to these examples By using the same expression method to define the connection order in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope.

[0033] Or, as another expression method, for example, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is the path between the source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal, etc.) via the transistor. The first connection path is the path via Z1, and the drain of the transistor (or the second terminal, etc.) is electrically connected to Y via at least a third connection path. The third connection path does not have the second connection path, and the third connection path is the path via Z2." It can be expressed like this. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 through at least a first connection path. The first connection path does not have a second connection path The second connection path has a connection path via the transistor. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 through at least a third connection path. The third connection path does not have the second connection path." It can be expressed like this. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least a first connection path. The first connection path does not have a second connection path The second connection path has a connection path via the transistor. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path." It can be expressed like this. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least a first connection path. The first connection path does not have a second connection path The second connection path has a connection path via the transistor. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path." It can be expressed like this. Or, "The source of the transistor (or the first terminal, etc.) is electrically connected to X via Z1 by at least a first connection path. The first connection path does not have a second connection path The second connection path has a connection path via the transistor. The drain of the transistor (or the second terminal, etc.) is electrically connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path." It can be expressed is also electrically connected to X via Z1 by means of a first electrical path, and the first electrical path does not have a second electrical path, and the second electrical path is from the source (or the first terminal, etc.) of the transistor to the drain (or the second terminal, etc.) of the transistor is an electrical path, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via Z2 by means of at least a third electrical path, and the third electrical path does not have a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal, etc.) of the transistor to the source (or the first terminal, etc.) of the transistor. It can be expressed as "". Using an expression method similar to these examples, by defining the connection path in the circuit configuration , it is possible to distinguish between the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) and determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X , Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Even when components that are independent on the circuit diagram are shown as being electrically connected to each other, there may be a case where one component has the functions of a plurality of components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both a component having the function of the wiring and the function of the electrode. Therefore, the electrical connection in this specification means such a case where one conductive film has the functions of a plurality of components.

[0034] Note that these expression methods are just examples and are not limited to these expression methods. Here, X , Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0035] Note that even when components that are independent on the circuit diagram are shown as being electrically connected to each other, there may be a case where one component has the functions of a plurality of components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both a component having the function of the wiring and the function of the electrode. Therefore, the electrical connection in this specification means such a case where one conductive film has the functions of a plurality of components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both a component having the function of the wiring and the function of the electrode. Therefore, the electrical connection in this specification means such a case where one conductive film has the functions of a plurality of components. electrically connected herein means such a case where one conductive film has the functions of a plurality of components. The combination is also included in that category.

[0036] Note that the terms "film" and "layer" can, in some cases or depending on the situation, be interchanged with each other. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer".

[0037] (Embodiment 1) In this embodiment, an imaging device, which is one aspect of the present invention,

[0038] will be described with reference to the drawings. FIG. 1(A) is a cross-sectional view showing the pixel configuration of an imaging

[0039] device according to one aspect of the present invention, and FIG. 1(B) shows an example of a cross-section of the region where the circuit 91 shown is formed. The imaging device includes a layer 1100 having transistors 51, 52, etc., a layer

[0040] 1200 having transistors 53, 54, etc., and a layer 1300 having a photoelectric conversion element 60.

[0041] In FIG. 1(A), a photodiode formed on a silicon substrate 40 is illustrated as the photoelectric conversion element 60, but other configured photoelectric conversion elements described later may also be used. Layers 1100, 1200, and 1300 can be arranged in the order of layers 1100, 1200, In addition, some of the above layers may not be included.

[0042] In the circuit 91, one of the source electrode and the drain electrode of the transistor 51 is a photoelectric conversion The source electrode or drain electrode of the transistor 51 is electrically connected to one of the electrodes of the switching element 60. The other drain electrode is electrically connected to the gate electrode of the transistor 53. The other of the source electrode or drain electrode of the transistor 51 is connected to the source electrode or drain electrode of the transistor 52. The source electrode or drain electrode of the transistor 53 is electrically connected to the One of the gate electrodes is electrically connected to one of the source electrode or drain electrode of the transistor 54. 1A and 1B show a source electrode or a drain electrode of a transistor 51. The other electrode of the capacitor 59 is electrically connected to one electrode of the capacitor 59. The terminal 59 may be omitted. Here is an example.

[0043] In this embodiment, each wiring, each electrode, and each conductor 81 are illustrated as individual elements. However, when they are electrically connected, they may be provided as the same element. In addition, the gate electrode, source electrode, or drain electrode of a transistor may be a conductor. The form in which the gate electrodes and sources of transistors are connected to the wirings via 81 is an example. In some cases, the drain electrode or the drain electrode functions as a wiring. In some cases, some of the wirings shown on the surface may not be provided, or wirings, transistors, etc. other than those mentioned above may be provided. It may be included in each layer.

[0044] On each element, an insulating layer 41 or 42 having a function as a protective film, an interlayer insulating film, or a flattening film is formed. For example, the insulating layers 41 to 44 are made of a silicon oxide film, an oxide film, or the like. An inorganic insulating film such as a silicon nitride film can be used. Alternatively, an acrylic resin, a polysilicon film, or the like can be used. An organic insulating film such as an imide resin may be used. , CMP (Chemical Mechanical Polishing) if necessary. It is preferable to perform a flattening treatment by a flattening method such as a flattening method.

[0045] One of the wiring 71 and the wiring 73 can function as a power line and the other as an output line. The wiring 72 can function as a power supply line. The wiring 77 can function as a power supply line (low potential). The wiring 74, 75, and 76 control the on / off of the transistors. The wiring 74 can function as a connection wiring. do.

[0046] The transistor 51 controls the potential of the charge storage section (FD) in response to the output of the photoelectric conversion element 60. The transistor 52 can function as a transfer transistor to transfer the charge It can function as a reset transistor that initializes the potential of the storage section (FD). The transistor 53 is an amplifier transistor that outputs an electric potential corresponding to the electric potential of the charge storage section (FD). The transistor 54 can function as a selection transistor for selecting a pixel. It can be made to function as such.

[0047] Note that in FIG. 1A, each transistor has a back gate. However, as shown in FIG. 42(A), a configuration without a back gate is also possible. As shown in FIG. 42(B), it may be in a form having a back gate only for some transistors, for example, transistor 51. The back gate may be electrically connected to the front gate of the opposing transistor. Alternatively, a fixed potential different from the front gate may be supplied to the back gate. Note that the form regarding the presence or absence of the back gate can also be applied to the forms of other imaging devices described in this embodiment. For transistors 51 to 54, a transistor (hereinafter referred to as an OS transistor) having an active layer formed of an oxide semiconductor can be used. Since the OS transistor has extremely low off-current characteristics, the dynamic range of imaging can be expanded. In the circuit configuration shown in FIG. 1(B), when the intensity of light incident on the photoelectric conversion element 60 is high, the potential of the charge storage unit (FD) becomes low. For example, due to the low off-current characteristics of transistor 53, even when the gate potential (the potential of the charge storage unit (FD)) is extremely low, a current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be widened. In addition, due to the low off-current characteristics of transistors 51 and 52, the period during which charges can be held in the charge storage unit (FD) can be made extremely long. Therefore, a global shutter method in which the charge storage operation is performed simultaneously for all pixels can be applied without complicating the circuit configuration and the operation method. Therefore, even if the subject is a moving object, an image with little distortion can be obtained. The form regarding the presence or absence of the back gate can also be applied to the forms of other imaging devices described in this embodiment.

[0048] For transistors 51 to 54, a transistor (hereinafter referred to as an OS transistor) having an active layer formed of an oxide semiconductor can be used.

[0049] Since the OS transistor has extremely low off-current characteristics, the dynamic range of imaging can be expanded. In the circuit configuration shown in FIG. 1(B), when the intensity of light incident on the photoelectric conversion element 60 is high, the potential of the charge storage unit (FD) becomes low. For example, due to the low off-current characteristics of transistor 53, even when the gate potential (the potential of the charge storage unit (FD)) is extremely low, a current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be widened. In the circuit configuration shown in FIG. 1(B), when the intensity of light incident on the photoelectric conversion element 60 is high, the potential of the charge storage unit (FD) becomes low. For example, when the intensity of the light incident on the photoelectric conversion element 60 is high, the potential of the charge storage unit (FD) becomes low. For example, due to the low off-current characteristics of transistor 53, even when the gate potential (the potential of the charge storage unit (FD)) is extremely low, a current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be widened. Therefore, the range of illuminance that can be detected, that is, the dynamic range can be widened.

[0050] In addition, due to the low off-current characteristics of transistors 51 and 52, the period during which charges can be held in the charge storage unit (FD) can be made extremely long. Therefore, a global shutter method in which the charge storage operation is performed simultaneously for all pixels can be applied without complicating the circuit configuration and the operation method. Therefore, a global shutter method in which the charge storage operation is performed simultaneously for all pixels can be applied without complicating the circuit configuration and the operation method. Therefore, even if the subject is a moving object, an image with little distortion can be obtained. ​​​Can be easily obtained.

[0051] In addition, since the OS transistor has a smaller temperature dependence of electrical characteristic variations than a transistor using silicon in the channel region (hereinafter referred to as Si transistor), it can be used in an extremely wide temperature range. Therefore, an imaging device and a semiconductor device having the OS transistor are also suitable for mounting on automobiles, airplanes, spacecraft, etc.

[0052] In addition, since the OS transistor has a characteristic of higher drain breakdown voltage than the Si transistor, a highly reliable imaging device can be obtained.

[0053] Here, in order to further widen the dynamic range of the imaging device, it is preferable to use transistors with even higher on-currents for transistor 53 and the transistor 54 that forms the current path. Also, in order to further lengthen the period during which charge can be held in the charge storage section (FD), it is preferable to use transistors with even lower off-currents for transistor 51 and transistor 52.

[0054] That is, it is preferable to fabricate transistor 51 and transistor 52, and transistor 53 and transistor 54 so as to have more optimal electrical characteristics.

[0055] Therefore, in one aspect of the present invention, as shown in FIG. 1(A), an arrangement is provided in which a region where a layer 1100 having transistor 51 and transistor 52 overlaps with a layer 1200 having transistor 53 and transistor 54 is provided, and the transistors are fabricated separately.

[0056] Generally, a transistor has electrical characteristics having both a low off-current and a high on-current. However, there is a trade-off between the off-current and the on-current, and generally the off-current A transistor with a low on-state current also has a low on-state current, and a transistor with a high on-state current also has a high off-state current. The off-state current is the current flowing between the source and drain when the transistor is in a non-conducting state. The on-current is the current that flows between the source and the This is the current that flows between the drains.

[0057] That is, in one embodiment of the present invention, the transistor 51 and the transistor The transistor 52 has a lower off-state current than the transistor 53 and the transistor 54 in the layer 1200. The transistor 53 and the transistor 54 in the layer 1200 have low electrical characteristics. The transistor 54 is different from the transistors 51 and 52 in the layer 1100. The structure has electrical characteristics such that the on-state current is high.

[0058] To manufacture a transistor with a low off-state current, for example, the atomic ratio of the oxide semiconductor in the active layer is However, the band gap is relatively large, such as In:Ga:Zn=1:1:1 or 1:3:2. It is preferable to use Ga-Zn oxide. A stacked structure of oxide semiconductors having a ratio of 1:3:2 may be used. The 1:3:2 oxide semiconductor on the pole side may be replaced with gallium oxide. It is preferable to make the oxide semiconductor film thinner, which is the same as changing the gate electrode thickness. It is preferable to make the insulating film relatively thick.

[0059] To fabricate a transistor with a high on-state current, for example, the atomic ratio of the oxide semiconductor in the active layer is It is preferable to use an In-Ga-Zn oxide having a relatively small band gap such as In:Ga:Zn = 3:1:2, 2:1:3, 4:1:4.1. Also, these oxide semiconductors may be formed into a stacked structure sandwiched between oxide semiconductors such as In:Ga:Zn = 1:3:2. In addition, oxide semiconductors such as zinc oxide and In-Sn-Zn oxide may be used. Also, it is preferable to increase the film thickness of the oxide semiconductor, which is equivalent to changing the channel width. In addition, it is preferable to make the film thickness of the gate insulating film relatively thin.

[0060] Summarizing the above, as a relative condition, the active layers of the transistors 51 and 52 included in the layer 1100 preferably have a larger band gap than the active layers of the transistors 53 and 54 included in the layer 1200.

[0061] Also, as a relative condition, the film thickness of the active layers of the transistors 51 and 52 included in the layer 1100 is preferably thinner than the film thickness of the active layers of the transistors 53 and 54 included in the layer 1200.

[0062] Also, as a relative condition, the film thickness of the gate insulating films of the transistors 51 and 52 included in the layer 1100 is preferably thicker than the film thickness of the gate insulating films of the transistors 53 and 54 included in the layer 1200.

[0063] By adopting such a configuration, an imaging device with excellent imaging performance can be formed.

[0064] Also, the imaging device according to one aspect of the present invention can have the configuration shown in Fig. 2(A).

[0065] ​​​​​​​The imaging device shown in Fig. 2(A) includes a layer 110 having transistors 51, 52, etc. 0, a layer 1200 having transistors 53, 54, etc., and a layer 1300 having a photoelectric conversion element 60 and is provided with a layer 1400 having transistors 55, 56, etc. provided on a silicon substrate 40. Each of the above transistors and the photoelectric conversion element 60 is configured to have an electrical connection with each wiring via a conductor 81 embedded in an insulating layer.

[0066] In Fig. 2(A), as an example of the photoelectric conversion element 60 provided in the layer 1300, an element using selenium as a photoelectric conversion layer 61 is illustrated, but a photodiode formed on the silicon substrate shown in Fig. 1(A) can also be used.

[0067] The photoelectric conversion element 60 using a selenium-based material for the photoelectric conversion layer 61 has a characteristic of high external quantum efficiency for visible light. In this photoelectric conversion element, it can be made into a highly sensitive optical sensor with a large amplification of electrons with respect to the amount of incident light by avalanche multiplication. That is, by using a selenium-based material for the photoelectric conversion layer 61, a sufficient photocurrent can be obtained even when the pixel area is reduced. Moreover, since the photoelectric conversion element PD using a selenium-based material has high photosensitivity, it can be said that it is also suitable for imaging in a low-illumination environment. In addition, the selenium-based material has the advantage that the photoelectric conversion layer 61 can be easily made thin because of its high light absorption coefficient.

[0068] As the selenium-based material, amorphous selenium or crystalline selenium can be used. Crystalline selenium can be obtained, for example, by heat-treating after forming amorphous selenium into a film. Note that by making the crystal grain size of crystalline selenium smaller than the pixel pitch, the variation in characteristics for each pixel can be reduced.​​​​​​​​ It can be reduced. Also, crystalline selenium has characteristics of higher spectral sensitivity and light absorption coefficient with respect to visible light than amorphous selenium.

[0069] Although the photoelectric conversion layer 61 is shown as a single layer, gallium oxide or cerium oxide etc. may be provided as a hole injection blocking layer on the light receiving surface side of the selenium-based material, and nickel oxide or antimony sulfide etc. may be provided as an electron injection blocking layer on the electrode 66 side.

[0070] Also, the photoelectric conversion layer 61 may be a layer containing a compound of copper, indium, and selenium (CIS). Or, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, a photoelectric conversion element capable of utilizing avalanche multiplication can be formed in the same manner as a single layer of selenium.

[0071] The photoelectric conversion element 60 using a selenium-based material can be configured to have a photoelectric conversion layer 61 between an electrode 66 formed of a metal material etc. and a transparent conductive layer 62. Also, CIS and CIGS are p-type semiconductors, and cadmium sulfide or zinc sulfide etc. of an n-type semiconductor may be provided in contact therewith to form a junction.

[0072] In order to generate an avalanche phenomenon, it is preferable to apply a relatively high voltage (for example, 10 V or more) to the photoelectric conversion element. Since the OS transistor has characteristics of higher drain breakdown voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor with a high drain breakdown voltage and a photoelectric conversion element having a selenium-based material as a photoelectric conversion layer, a highly sensitive and highly reliable imaging device can be obtained. ​​​​​​​​​​​​​It is possible.

[0073] In FIG. 2(A), the photoelectric conversion layer 61 and the translucent conductive layer 62 are not separated between pixel circuits, but it may be configured to be separated between circuits as shown in FIG. 3(A). Also, in the region without the electrode 66 between pixels, a partition wall 67 is provided with an insulator to prevent cracks from entering the photoelectric conversion layer 6 1 and the translucent conductive layer 62, but it may be configured not to provide the partition wall 67 as shown in FIG. 3(B). Also, as shown in FIGS. 3(C) and (D), the translucent conductive layer 62 and the wiring 77 may be in direct contact.

[0074] Also, the electrode 66, the wiring 77, etc. may be multilayered. For example, as shown in FIG. 41(A), the electrode 66 can be made into two layers of conductive layers 66a and 66b, and the wiring 77 can be made into two layers of conductive layers 77a and 77b. In the configuration of FIG. 41(A), for example, 66a and 77a are formed by selecting a low-resistance metal or the like, and 66b and 77b are formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 61. With such a configuration, the electrical characteristics of the photoelectric conversion element can be improved. Also, some metals may cause electrolytic corrosion when contacting the translucent conductive layer 62. Even when such a metal is used for the conductive layer 77a, electrolytic corrosion can be prevented by passing through the conductive layer 77b.

[0075] For the conductive layer 66b and the conductive layer 77b, for example, molybdenum, tungsten, etc. can be used. For the conductive layer 66a and the conductive layer 77a, for example, aluminum, titanium, or a laminate such as sandwiching aluminum with titanium can be used.

[0076] Also, the insulating layer 41 may have a multi-layer structure. For example, as shown in FIG. 41(B), , when the insulating layer 41 has an insulating layer 41a and an insulating layer 41b, and the etching rate of the insulating layer 41a and the insulating layer 41 b is different, the conductor 81 will have a step. Similarly, when other insulating layers used for the interlayer insulating film or the planarization film are multi-layered, the conductor 81 will also have a step . Here, an example where the insulating layer 41 has two layers is shown, but the insulating layer 4 1 and other insulating layers may have a structure of three or more layers.

[0077] In addition, for the photoelectric conversion element 60, a pin type diode element using an amorphous silicon film, a microcrystalline silicon film, etc. may be used.

[0078] For example, FIG. 4 shows an example in which a pin-type thin film photodiode is used for the photoelectric conversion element 60. The photodiode has a structure in which an n-type semiconductor layer 65, an i-type semiconductor layer 64, and a p-type semiconductor layer 63 are laminated in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 64. In addition, for the p-type semiconductor layer 63 and the n-type semiconductor layer 65, amorphous silicon or microcrystalline silicon containing dopants for imparting their respective conductivity types can be used . A photodiode using amorphous silicon as the photoelectric conversion layer has high sensitivity in the wavelength region of visible light and is easy to detect weak visible light. In the photoelectric conversion element 60 shown in FIG. 4, the n-type semiconductor layer 65 acting as a cathode has an electrical connection with an electrode 66 having an electrical connection with the transistor 51.

[0079] Also, the p-type semiconductor layer 63 acting as an anode has an electrical connection with the wiring 77 via the conductor 81 . .

[0080] In the circuit 91, the connection form between the anode and cathode of the photoelectric conversion element 60 and the electrode layer and wiring may be opposite to that shown in FIG. 1(B).

[0081] In any case, it is preferable to form the photoelectric conversion element 60 such that the p-type semiconductor layer 63 becomes the light-receiving surface. By using the p-type semiconductor layer 63 as the light-receiving surface, the output current of the photoelectric conversion element 60 can be increased.

[0082] The configuration of the photoelectric conversion element 60 having the form of a pin-type thin-film photodiode, and the connection form of the photoelectric conversion element 60 and the wiring may be the examples shown in FIGS. 5(A), (B), (C), (D), (E), (F). Note that the configuration of the photoelectric conversion element 60 and the connection form between the photoelectric conversion element 60 and the wiring are not limited to these, and other forms may be used.

[0083] FIG. 5(A) shows a configuration in which a translucent conductive layer 62 in contact with the p-type semiconductor layer 63 of the photoelectric conversion element 60 is provided. The translucent conductive layer 62 acts as an electrode and can increase the output current of the photoelectric conversion element 60.

[0084] For the translucent conductive layer 62, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, or graphene etc. can be used. Also, the translucent conductive layer 62 is not limited to a single layer and may be a laminate of different films.

[0085] FIG. 5(B) shows a configuration in which the p-type semiconductor layer 63 of the photoelectric conversion element 60 and the wiring 78 have a direct electrical connection. ​​​​

[0086] Figure 5(C) shows a configuration in which a transparent conductive layer 62 in contact with the p-type semiconductor layer 63 of the photoelectric conversion element 60 is provided, and the wiring 78 and the transparent conductive layer 62 have an electrical connection. Figure 5(D) shows a configuration in which an opening through which the p-type semiconductor layer 63 is exposed is provided in the insulating layer covering the photoelectric conversion element 60, and the transparent conductive layer 62 covering the opening and the wiring 78 have an electrical connection.

[0087] Figure 5(E) shows a configuration in which a conductor 81 penetrating the photoelectric conversion element 60 is provided. In this configuration, the wiring 77 is electrically connected to the p-type semiconductor layer 63 via the conductor 81. In the drawing, the wiring 77 and the electrode 66 appear to be conducting through the n-type semiconductor layer 65. However, since the lateral resistance of the n-type semiconductor layer 65 is high, if an appropriate interval is provided between the wiring 77 and the above electrode, the resistance between the two becomes extremely high. Therefore, the photoelectric conversion element 60 can have diode characteristics without the anode and cathode being short-circuited. Note that there may be a plurality of conductors 81 electrically connected to the p-type semiconductor layer 63. Figure 5(F) shows a configuration in which a transparent conductive layer 62 in contact with the p-type semiconductor layer 63 is provided for the photoelectric conversion element 60 of Figure 5(E). Figure 5(D), Figure 5(E), and Figure 5(F) have the advantage that a wide light-receiving area can be ensured because the light-receiving region and the wiring do not overlap in the photoelectric conversion element 60 shown.

[0088] Figure 5(E) shows a configuration in which a conductor 81 penetrating the photoelectric conversion element 60 is provided. In this configuration, the wiring 77 is electrically connected to the p-type semiconductor layer 63 via the conductor 81. In the drawing, the wiring 77 and the electrode 66 appear to be conducting through the n-type semiconductor layer 65. However, since the lateral resistance of the n-type semiconductor layer 65 is high, if an appropriate interval is provided between the wiring 77 and the above electrode, the resistance between the two becomes extremely high. Therefore, the photoelectric conversion element 60 can have diode characteristics without the anode and cathode being short-circuited. Note that there may be a plurality of conductors 81 electrically connected to the p-type semiconductor layer 63. Figure 5(F) shows a configuration in which a transparent conductive layer 62 in contact with the p-type semiconductor layer 63 is provided for the photoelectric conversion element 60 of Figure 5(E). Figure 5(D), Figure 5(E), and Figure 5(F) have the advantage that a wide light-receiving area can be ensured because the light-receiving region and the wiring do not overlap in the photoelectric conversion element 60 shown. Figure 5(E) shows a configuration in which a conductor 81 penetrating the photoelectric conversion element 60 is provided. In this configuration, the wiring 77 is electrically connected to the p-type semiconductor layer 63 via the conductor 81. In the drawing, the wiring 77 and the electrode 66 appear to be conducting through the n-type semiconductor layer 65. However, since the lateral resistance of the n-type semiconductor layer 65 is high, if an appropriate interval is provided between the wiring 77 and the above electrode, the resistance between the two becomes extremely high. Therefore, the photoelectric conversion element 60 can have diode characteristics without the anode and cathode being short-circuited. Note that there may be a plurality of conductors 81 electrically connected to the p-type semiconductor layer 63. Figure 5(F) shows a configuration in which a transparent conductive layer 62 in contact with the p-type semiconductor layer 63 is provided for the photoelectric conversion element 60 of Figure 5(E). Figure 5(D), Figure 5(E), and Figure 5(F) have the advantage that a wide light-receiving area can be ensured because the light-receiving region and the wiring do not overlap in the photoelectric conversion element 60 shown. Figure 5(E) shows a configuration in which a conductor 81 penetrating the photoelectric conversion element 60 is provided. In this configuration, the wiring 77 is electrically connected to the p-type semiconductor layer 63 via the conductor 81. In the drawing, the wiring 77 and the electrode 66 appear to be conducting through the n-type semiconductor layer 65. However, since the lateral resistance of the n-type semiconductor layer 65 is high, if an appropriate interval is provided between the wiring 77 and the above electrode, the resistance between the two becomes extremely high. Therefore, the photoelectric conversion element 60 can have diode characteristics without the anode and cathode being short-circuited. Note that there may be a plurality of conductors 81 electrically connected to the p-type semiconductor layer 63. Figure 5(F) shows a configuration in which a transparent conductive layer 62 in contact with the p-type semiconductor layer 63 is provided for the photoelectric conversion element 60 of Figure 5(E).

[0089] Figure 5(F) shows a configuration in which a transparent conductive layer 62 in contact with the p-type semiconductor layer 63 is provided for the photoelectric conversion element 60 of Figure 5(E). Figure 5(D), Figure 5(E), and Figure 5(F) have the advantage that a wide light-receiving area can be ensured because the light-receiving region and the wiring do not overlap in the photoelectric conversion element 60 shown.

[0090] In the photoelectric conversion element 60 shown in Figure 5(D), Figure 5(E), and Figure 5(F), since the light-receiving region and the wiring do not overlap, there is an advantage that a wide light-receiving area can be ensured. Figure 5(D), Figure 5(E), and Figure 5(F) have the advantage that a wide light-receiving area can be ensured because the light-receiving region and the wiring do not overlap in the photoelectric conversion element 60 shown.

[0091] The photoelectric conversion element 60 formed using the above-mentioned selenium-based material or amorphous silicon is formed by film formation. It is manufactured using general semiconductor manufacturing processes such as the process of lithography and etching. In addition, selenium-based materials have high resistance, and as shown in Figure 2(A), The transfer layer 61 may be configured not to separate the circuits. The imaging device can be manufactured at a high yield and low cost. In the case of forming a photodiode having the photoelectric conversion layer 61, a polishing process and a bonding process are required. Such highly difficult processes are required.

[0092] In the imaging device shown in FIG. 2(A) and FIG. 4, a silicon substrate 40 has an active region. A layer 1400 in which the transistors 55 and 56 are provided is formed on the layers 1100 to 1104. It can be configured so as to overlap with the pixel circuit formed in 300.

[0093] The circuit formed on the silicon substrate 40 has a function of reading out the signal output from the pixel circuit and a function of detecting the signal. For example, the circuit 9 shown in FIG. The transistor 55 (n- The gates of transistors 52 (p-ch type) and 53 (p-ch type) are electrically connected. Either the source or drain of one transistor is connected to the source or drain of the other transistor. The source or drain of both transistors is electrically connected to one of the drains. The other of the inputs is electrically connected to a different wiring.

[0094] The silicon substrate 40 is not limited to a bulk silicon substrate, but may be a germanium or silicon gel substrate. Magnesium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, Substrates made of gallium nitride or organic semiconductors can also be used.

[0095] Also, as shown in Fig. 2(C), transistors 55 and 56 may be transistors having an active layer 58 of a silicon thin film. Further, the active layer 58 may be made of polycrystalline silicon or single-crystalline silicon of SOI (Silicon on Insulator). This is possible.

[0096] Here, as shown in Fig. 1(A), Fig. 2(A), Fig. 4, etc., between the region where a transistor having an oxide semiconductor is formed and the region where an Si transistor (Si photodiode in Fig. 1) is formed an insulating layer 80 is provided. For example, hydrogen in the insulating layer provided near the active regions of transistors 55 and 56

[0097] terminates the dangling bonds of silicon. Therefore, the hydrogen has the effect of improving the reliability of transistors 55 and 56. On the other hand, hydrogen in the insulating layer provided near the oxide semiconductor layer which is the active layer such as transistor 5 3 becomes one of the factors for generating carriers in the oxide semiconductor. Therefore, the hydrogen may be a factor for reducing the reliability of transistors 53 etc. Therefore, when laminating one layer having a transistor using a silicon-based semiconductor material and the other layer having a transistor using an oxide semiconductor it is preferable to provide an insulating layer 80 having a function of preventing the diffusion of hydrogen between them. By confining hydrogen in one layer with the insulating layer 80, transistor 55 ​​​​and the reliability of the transistor 56 can be improved. Also, the diffusion of hydrogen from one layer to the other layer is suppressed, so that the reliability of the transistor 53 and the like can also be improved .

[0098] As the insulating layer 80, for example, aluminum oxide, aluminum oxynitride, gallium oxide , gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide , hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used

[0099] In addition, in the configuration shown in FIGS. 2(A) and 4, the circuit formed on the silicon substrate 40 (for example, a driving circuit), the transistor 51, etc., and the photoelectric conversion element 60 can be formed so as to overlap each other , so that the integration degree of the pixels can be increased. That is, the resolution of the imaging device can be increased. For example, it is suitable for use in imaging devices with a pixel count of 4K2K, 8K4K, or 16K8K, etc .

[0100] Also, the imaging devices shown in FIGS. 2(A) and 4 are configured not to provide a photoelectric conversion element on the silicon substrate 40 . Therefore, an optical path for the photoelectric conversion element 60 can be secured without being affected by various transistors, wirings, etc., and a pixel with a high aperture ratio can be formed .

[0101] In addition, the imaging devices shown in FIGS. 2(A) and 4 can be arranged in the order of layer 1300, layer 1100, layer 1200, layer 1400 in the height direction as shown in FIGS. 2(A), 4, and 8(C) . Also, as shown in FIG. 8(D), they can be arranged in the order of layer 1300, layer 120 0, layer 1100, layer 1400 in the height direction. Also, layers other than the above can be arranged in the order of layer 1300, layer 120 0, layer 1100, layer 1400 in the height direction as shown in FIG. 8(D). Also, layers other than the above can be arranged in the order of layer 1300, layer 120 It may be included in the stacked structure. Also, there may be cases where some of the above layers are not included.

[0102] In addition, the imaging device according to one aspect of the present invention can have the configuration shown in FIG. 6.

[0103] The imaging device shown in FIG. 6 is a modified example of the imaging device shown in FIG. 2(A), and illustrates an example of configuring a CMOS inverter with an OS transistor and a Si transistor.

[0104] Here, the transistor 56, which is a Si transistor provided in the layer 1400, is of p-ch type and the transistor 55, which is an OS transistor provided in the layer 1500, is of n-ch type. By providing only p -ch type transistors on the silicon substrate 40, processes such as well formation and n-type impurity layer formation can be omitted.

[0105] The transistor 55 provided in the layer 1500 preferably has a high on-current, and the same configuration as the transistor provided in the layer 1200 can be used.

[0106] Note that the imaging device shown in FIG. 6 shows an example in which selenium is used for the photoelectric conversion element 60, but a configuration using a pin-type thin-film photodiode may be employed in the same manner as in FIG. 4.

[0107] In addition, as shown in FIGS. 6 and 8(E), the imaging device shown in FIG. 6 can be arranged in the order of layer 13 00, layer 1100, layer 1200, layer 1500, layer 1400 in the height direction. Also, as shown in FIG. 8(F), it can be arranged in the order of layer 1300, layer 1200, layer 1100, layer 1500, layer 1400 in the height direction. Also, there may be cases where layers other than the above are included in the stacked structure. Also, there may be cases where some of the above layers are not included.

[0108] An imaging device according to one embodiment of the present invention can have a structure shown in FIG.

[0109] The imaging device shown in FIG. 7 includes an OS transistor and a Si transistor, similar to the imaging device shown in FIG. This is an example of constructing a CMOS inverter using transistors. Transistor 55 is formed on layer 1200. 6 in that layer 1500 is omitted.

[0110] In the imaging device shown in FIG. 7, the transistor 55 is a transistor formed in the layer 1200. The transistor 53 and the transistor 54 can be fabricated in the same process. The manufacturing process of the device can be simplified.

[0111] The transistor 55 provided in the layer 1200 is a transistor 53 and a transistor 5 As with 4, it is formed as a transistor with a high on-state current, so it is used in CMOS inverter circuits. It has sufficient properties to be a component of the

[0112] The imaging device shown in FIG. 7 includes layers 1300, 1310, 1320, 1330, 1340, 1350, 1360, 1370, 1380, 1390, 1391, 1392, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1 The layers 1100, 1200, and 1400 can be arranged in this order. As shown in FIG. 1, in the height direction, the layers are stacked in the order of layer 1300, layer 1200, layer 1100, and layer 1400. In addition, layers other than those described above may be included in the laminate structure. , some of the above layers may not be included.

[0113] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. For example, any one of the transistors 51 to 54 It can also be configured with transistors having silicon or the like in one or more active regions or active layers. Further, both the transistor 55 and the transistor 56 can be configured with transistors having an oxide semiconductor layer in the active layer.

[0114] The imaging device according to one aspect of the present invention has a stacked structure for one circuit, and since the transistors and the like included in the circuit have an overlapping region with each other, the imaging device can be miniaturized. Further, a circuit having functions such as a function of reading out a signal output from the pixel circuit and a process of converting the signal can be configured to have an overlapping region with the pixel circuit, and further, miniaturization of the imaging device can be promoted.

[0115] FIG. 9(A) is a cross-sectional view of an example of a form in which a color filter or the like is added to the imaging device described in FIGS. 1 to 8. The cross-sectional view shows a part of a region having pixel circuits for three pixels. An insulating layer 2500 is formed on the layer 1300 on which the photoelectric conversion element 60 is formed. As the insulating layer 2500, a silicon oxide film having high translucency to visible light or the like can be used. Further, a configuration in which a silicon nitride film is laminated as a passivation film may be adopted. Further, a configuration in which a dielectric film such as hafnium oxide is laminated as an antireflection film may be adopted.

[0116] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 has a function of preventing color mixing of light passing through the upper color filter. The light-shielding layer 2510 can be configured by laminating a metal layer such as aluminum or tungsten or a dielectric film having a function as the metal layer and an antireflection film.

[0117] ​​​​​​​​​​An organic resin layer 2520 is provided as a planarization film on the insulating layer 2500 and the light-shielding layer 2510. This can be the configuration. Further, a color filter 2530 is formed for each pixel. For example, , to color filters 2530a, 2530b, and 2530 c, colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned, and a color image can be obtained.

[0118] On the color filters 2530a, 2530b, and 2530c a microlens array 2540 is provided. Therefore, light passing through the individual lenses of the microlens array 2540 passes through the color filter directly below and irradiates the photoelectric conversion element. Note that, as shown in FIG. 9(B), a configuration without the microlens array 254 0 can also be adopted. In this case, an insulating layer 2560 having light-transmitting properties or the like can be provided on the color filter.

[0119] Also, as shown in FIG. 9(C), an optical conversion layer 2550 may be used instead of the color filters 2530a, 2530b and 2530c. By adopting such a configuration, an imaging device that can obtain images in various wavelength regions can be achieved. Also, the imaging device shown in FIG. 9(C) can have a configuration without the microlens array 2540, similar to the configuration of FIG. 9(B).

[0120] For example, if a filter that blocks light having a wavelength equal to or less than that of visible light is used for the optical conversion layer 2550, an infrared imaging device can be achieved. Also, if a filter that blocks light having a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 2550 If a filter is used, an infrared imaging device can be obtained. Also, an optical conversion layer 2550 If a filter that blocks light with a wavelength equal to or longer than that of visible light is used, an ultraviolet imaging device can be obtained .

[0121] Also, if a scintillator is used for the optical conversion layer 2550, an imaging device can be obtained that is used for an X-ray imaging device or the like and can obtain an image visualizing the intensity of radiation When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by a phenomenon called photoluminescence. Then, the image data is acquired by detecting the light with the photoelectric conversion element 60. Also, an imaging device having such a configuration may be used for a radiation detector or the like

[0122] A scintillator is made of a substance that emits visible light or ultraviolet light by absorbing the energy when irradiated with radiation such as X-rays or gamma rays, or a material containing such a substance. For example, materials such as Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc., or those dispersed in resins or ceramics can be used

[0123] In addition, in the photoelectric conversion element 60 using a selenium-based material, since radiation such as X-rays can be directly converted into charges, a configuration that does not require a scintillator can also be adopted

[0124] Also, if the region other than the layer 1300 shown in FIGS. 9(A), (B), and (C) is made into the layer 1600, the combination with the configuration of the imaging device shown in FIGS. 1 to 8 can be as shown in FIGS. 10(A) to 10(F) . ​​​​​​​

[0125] Specifically, the configuration of the imaging device shown in FIG. 10(A) is as shown in FIG. 43. Also, the configuration shown in FIG. 1 0(C) is as shown in FIG. 44.

[0126] Also, the imaging device may be curved as shown in FIGS. 11(A1) and 11(B1). FIG. 11(A1) shows a state in which the imaging device is curved in the direction of the two-dot chain line X1-X2 in the figure. FIG. 11(A2) is a cross-sectional view of the portion indicated by the two-dot chain line X1-X2 in FIG. 11(A1). FIG. 11(A3) is a cross-sectional view of the portion indicated by the two-dot chain line Y1-Y2 in FIG. 11(A1).

[0127] FIG. 11(B1) shows a state in which the imaging device is curved in the direction of the two-dot chain line X3-X4 in the figure and also curved in the direction of the two-dot chain line Y3-Y4 in the figure. FIG. 11(B2) is a cross-sectional view of the portion indicated by the two-dot chain line X3-X4 in FIG. 11(B1). FIG. 11(B3) is a cross-sectional view of the portion indicated by the two-dot chain line Y3-Y4 in FIG. 11(B1).

[0128] By curving the imaging device, curvature of field and spherical aberration can be reduced. Therefore, it is possible to facilitate the optical design of lenses and the like used in combination with the imaging device. For example, since the number of lens elements for aberration correction can be reduced, miniaturization and weight reduction of semiconductor devices and the like using the imaging device can be facilitated. Also, the quality of the captured image can be improved.

[0129] Note that in this embodiment, one aspect of the present invention has been described. Or, in other embodiments, one aspect of the present invention is described. However, one aspect of the present invention is not limited to these. For example, although an example in which the present invention is applied to an imaging device has been shown as one embodiment of the present invention, One aspect of the present invention is not limited to this. The present invention may be applied to a device other than an imaging device. The present invention may be applied to a semiconductor device.

[0130] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0131] (Embodiment 2) In this embodiment, the pixel circuit described in the first embodiment will be described.

[0132] FIG. 12A shows the details of the pixel circuit (circuit 91) and the connection with each wiring shown in FIG. 1B. The circuit shown in FIG. 12A includes a photoelectric conversion element 60, a transistor 51, and a transistor The circuit includes a transistor 52, a transistor 53, and a transistor .

[0133] The anode of the photoelectric conversion element 60 is connected to the wiring 316, and the cathode is connected to the solenoid of the transistor 51. The other of the source or drain of the transistor 51 is connected to The transistor is connected to the charge storage section (FD) and the gate is connected to the wiring 312 (TX). One of the source and drain of the transistor 52 is connected to the charge storage section (FD), and the source or The other of the drains is connected to a wiring 317, and the gate is connected to a wiring 311 (RS). One of the source and drain of the transistor 53 is connected to the wiring 314 (GND). The other of the source and drain is connected to the source or drain of transistor 54. The gate of the transistor 54 is connected to the charge storage section (FD). The other side is connected to wiring 315 (OUT), and the gate is connected to wiring 313 (SE). All the above connections shall be electrical connections.

[0134] Note that potentials such as GND, VSS, and VDD may be supplied to wiring 314. Here, potential and voltage are relative. Therefore, the magnitude of the potential of GND is not necessarily 0 volts.

[0135] The photoelectric conversion element 60 is a light-receiving element and has a function of generating a current corresponding to the light incident on the pixel circuit. The transistor 51 has a function of controlling the charge accumulation in the charge accumulation section (FD) by the photoelectric conversion element 60. The transistor 52 has a function of resetting the potential of the charge accumulation section (FD). The transistor 53 has a function of outputting a signal corresponding to the potential of the charge accumulation section (FD). The transistor 54 has a function of controlling the selection of the pixel circuit during reading.

[0136] Note that the charge accumulation section (FD) is a charge holding node and holds charges that change according to the amount of light received by the photoelectric conversion element 60.

[0137] Note that the transistor 53 and the transistor 54 may be connected in series between the wiring 315 and the wiring 314. Therefore, they may be arranged in the order of wiring 314, transistor 53, transistor 54, wiring 315, or in the order of wiring 314, transistor 54, transistor 53, wiring 315.

[0138] The wiring 311 (RS) has a function as a signal line for controlling the transistor 52. ​​​​​。The wiring 312 (TX) functions as a signal line for controlling the transistor 51. The wiring 313 (SE) functions as a signal line for controlling the transistor 54. The wiring 314 (GND) functions as a signal line for setting a reference potential (e.g., GND). The wiring 315 (OUT) functions as a signal line for reading out the signal output from the transistor 53. The wiring 316 functions as a signal line for outputting charges from the charge accumulation section (FD) via the photoelectric conversion element 60, and is a low potential line in the circuit of FIG. 12(A). Also, the wiring 317 functions as a signal line for resetting the potential of the charge accumulation section (FD), and is a high potential line in the circuit of FIG. 12(A).

[0139] Here, the relationship with the wiring shown in FIG. 1(B) is as follows. The wiring 76 corresponds to the wiring 311 (RS ). The wiring 75 corresponds to the wiring 312 (TX). The wiring 74 corresponds to the wiring 313 (SE ). The wiring 71 corresponds to the wiring 314 (GND). The wiring 73 corresponds to the wiring 315 (O UT). The wiring 77 corresponds to the wiring 316. The wiring 72 corresponds to the wiring 317. .

[0140] Also, the pixel circuit according to one aspect of the present invention may have a configuration shown in FIG. 12(B). The circuit shown in FIG. 12( B) has the same components as the circuit shown in FIG. 12(A), but is different in that the anode of the photoelectric conversion element 6 0 is electrically connected to either the source or the drain of the transistor 52, and the cathode of the photoelectric conversion element 60 is electrically connected to the wiring 316. In this case, the wiring 316 is a signal line for supplying charges to the charge accumulation section (FD) via the photoelectric conversion element 60. ​It has a function as such and becomes a high potential line in the circuit of Fig. 12(B). Also, wiring 317 becomes a low potential line.

[0141] Next, the configurations of the elements shown in Figs. 12(A) and (B) will be described.

[0142] For the photoelectric conversion element 60, as described in the first embodiment, an element composed of a selenium-based material and a conductive layer, or an element in which a pin-type junction is formed by a silicon layer can be used. It is possible to use an element in which a pin-type junction is formed by a silicon layer. .

[0143] Transistors 51, 52, 53, and 54 can be formed using silicon semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single-crystalline silicon. However, it is preferable to form them using transistors with an oxide semiconductor. A transistor with a channel formation region formed of an oxide semiconductor has a characteristic of extremely low off-current. Silicon semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single-crystalline silicon can be used to form them. However, it is preferable to form them using transistors with an oxide semiconductor. A transistor with a channel formation region formed of an oxide semiconductor has a characteristic of extremely low off-current. In particular, if the leakage current of transistors 51 and 52 connected to the charge storage section (FD) is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD). In particular, if the leakage current of transistors 51 and 52 connected to the charge storage section (FD) is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD). In particular, if the leakage current of transistors 51 and 52 connected to the charge storage section (FD) is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD).

[0144] In particular, for transistors 51 and 52 connected to the charge storage section (FD), if the leakage current is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD). In particular, for transistors 51 and 52 connected to the charge storage section (FD), if the leakage current is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD). In particular, for transistors 51 and 52 connected to the charge storage section (FD), if the leakage current is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD). In particular, for transistors 51 and 52 connected to the charge storage section (FD), if the leakage current is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD). In particular, for transistors 51 and 52 connected to the charge storage section (FD), if the leakage current is large, the time during which the charges accumulated in the charge storage section (FD) can be held will be insufficient. Therefore, by using transistors with an oxide semiconductor for at least these two transistors, it is possible to prevent the outflow of unnecessary charges from the charge storage section (FD).

[0145] Also, in transistors 53 and 54, if the leakage current is large, unnecessary charges will be output to wiring 314 or wiring 315. Therefore, it is preferable to use transistors with a channel formation region formed of an oxide semiconductor for these transistors. Also, in transistors 53 and 54, if the leakage current is large, unnecessary charges will be output to wiring 314 or wiring 315. Therefore, it is preferable to use transistors with a channel formation region formed of an oxide semiconductor for these transistors. Also, in transistors 53 and 54, if the leakage current is large, unnecessary charges will be output to wiring 314 or wiring 315. Therefore, it is preferable to use transistors with a channel formation region formed of an oxide semiconductor for these transistors. .

[0146] An example of the operation of the circuit in FIG. 12(A) will be described with reference to the timing chart in FIG. 13(A). He explains.

[0147] In FIG. 13A, for the sake of simplicity, the potential of each wiring is given as a signal that changes between two values. However, since each potential is an analog signal, in practice it is not limited to binary values ​​and can be expressed in various ways depending on the situation. In addition, the signal 701 shown in the figure is the potential of the wiring 311 (RS), and the signal 702 is the potential of the wiring The potential of the line 312 (TX), the signal 703 is the potential of the wiring 313 (SE), and the signal 704 is the charge storage potential. The potential of the integrated circuit (FD), the signal 705, corresponds to the potential of the wiring 315 (OUT). The potential of the wiring 316 is always "Low", and the potential of the wiring 317 is always "High".

[0148] At time A, the potential of the wiring 311 (signal 701) is set to “High” and the potential of the wiring 312 ( When the signal 702) is set to "High", the potential of the charge storage section (FD) (signal 704) The potential of the wiring 317 is initialized to “High” and the reset operation is started. The potential of 15 (signal 705) is precharged to "High".

[0149] At time B, when the potential of the wiring 311 (signal 701) is set to “Low”, a reset operation is performed. At this point, a reverse bias is applied to the photoelectric conversion element 60. As a result, the potential of the charge storage section (FD) (signal 704) begins to decrease due to the reverse current. When the photoelectric conversion element 60 is irradiated with light, the reverse current increases. The rate at which the potential (signal 704) of the charge storage unit (FD) drops varies depending on the amount of light. According to the amount of light irradiated on the electric conversion element 60, the channel resistance between the source and drain of the transistor 53 changes. The channel resistance changes.

[0150] At time C, when the potential of the wiring 312 (signal 702) is set to "Low", the accumulation operation ends. Then, the potential of the charge accumulation unit (FD) (signal 704) becomes constant. Here, the potential is determined by the amount of charge generated by the photoelectric conversion element 60 during the accumulation operation. That is, it changes according to the amount of light irradiated on the photoelectric conversion element. Moreover, since the transistors 51 and 52 are configured with transistors having an extremely low off-current with a channel formation region formed in the oxide semiconductor layer, the potential of the charge accumulation unit (FD) can be kept constant until the subsequent selection operation (read operation) is performed. Also, since the transistors 51 and 52 are configured with transistors having an extremely low off-current with a channel formation region formed in the oxide semiconductor layer, the potential of the charge accumulation unit (FD) can be kept constant until the subsequent selection operation (read operation) is performed. is configured with transistors having an extremely low off-current with a channel formation region formed in the oxide semiconductor layer, the potential of the charge accumulation unit (FD) can be kept constant until the subsequent selection operation (read operation) is performed. is configured with transistors having an extremely low off-current with a channel formation region formed in the oxide semiconductor layer, the potential of the charge accumulation unit (FD) can be kept constant until the subsequent selection operation (read operation) is performed. is possible.

[0151] When the potential of the wiring 312 (signal 702) is set to "Low", the potential of the charge accumulation unit (FD) may change due to the parasitic capacitance between the wiring 312 and the charge accumulation unit (FD). If the amount of change in the potential is large, the amount of charge generated by the photoelectric conversion element 60 during the accumulation operation cannot be accurately obtained. To reduce the amount of change in the potential, measures such as reducing the gate-source (or gate-drain) capacitance of the transistor 51, increasing the gate capacitance of the transistor 53, and providing a holding capacitance in the charge accumulation unit (FD) are effective. In this embodiment, it is assumed that the change in the potential can be ignored by these measures. If the amount of change in the potential is large, the amount of charge generated by the photoelectric conversion element 60 during the accumulation operation cannot be accurately obtained. To reduce the amount of change in the potential, measures such as reducing the gate-source (or gate-drain) capacitance of the transistor 51, increasing the gate capacitance of the transistor 53, and providing a holding capacitance in the charge accumulation unit (FD) are effective. In this embodiment, it is assumed that the change in the potential can be ignored by these measures. If the amount of change in the potential is large, the amount of charge generated by the photoelectric conversion element 60 during the accumulation operation cannot be accurately obtained. To reduce the amount of change in the potential, measures such as reducing the gate-source (or gate-drain) capacitance of the transistor 51, increasing the gate capacitance of the transistor 53, and providing a holding capacitance in the charge accumulation unit (FD) are effective. In this embodiment, it is assumed that the change in the potential can be ignored by these measures. 53 to increase the gate capacitance, and to provide a holding capacitance in the charge accumulation unit (FD) are effective. In this embodiment, it is assumed that the change in the potential can be ignored by these measures. In this embodiment, it is assumed that the change in the potential can be ignored by these measures. is ignored.

[0152] At time D, when the potential of the wiring 313 (signal 703) is set to "High", the transistor 54 conducts and the selection operation starts, and the wiring 314 and the wiring 315 are connected through the transistor 53 and the transistor. conducts and the selection operation starts, and the wiring 314 and the wiring 315 are connected through the transistor 53 and the transistor. It conducts through the switch 54. Then, the potential (signal 705) of the wiring 315 decreases to some extent. Note that the pre-charge of the wiring 315 should be completed before time D. Here, the speed at which the potential (signal 705) of the wiring 315 decreases depends on the current between the source and drain of the transistor 53. That is, it changes according to the amount of light irradiating the photoelectric conversion element 60 during the accumulation operation.

[0153] At time E, when the potential (signal 703) of the wiring 313 is set to "Low", the transistor 54 is cut off and the selection operation ends, and the potential (signal 705) of the wiring 315 becomes a constant value. Here, the constant value changes according to the amount of light that irradiated the photoelectric conversion element 60. Therefore, by acquiring the potential of the wiring 315, it is possible to know the amount of light that irradiated the photoelectric

[0154] conversion element 60 during the accumulation operation. More specifically, when the light irradiating the photoelectric conversion element 60 is strong, the potential of the charge storage section (FD), that is, the gate voltage of the transistor 53 decreases. Therefore, the current flowing between the source and drain of the transistor 54 becomes small, and the potential (signal 705) of the wiring 315 decreases slowly.

[0155] Therefore, a relatively high potential can be read from the wiring 315. Conversely, when the light irradiating the photoelectric conversion element 60 is weak, the potential of the charge storage section (FD), that is, the gate voltage of the transistor 54 becomes high. Therefore, the current flowing between the source and drain of the transistor

[0156] Next, the timing chart shown in FIG. 13(B) is used to explain an example of the operation of the circuit in FIG. 12(B). Note that the potential of wiring 316 is always "High", and the potential of wiring 317 is always "Low". ”Low”.

[0157] At time A, when the potential of wiring 311 (signal 701) is set to "High" and the potential of wiring 312 ( signal 702) is set to "High", the potential of the charge storage section (FD) (signal 704) is initialized to the potential of wiring 317 ("Low"), and the reset operation is started. Note that the potential of wiring 31 5 (signal 705) is pre-charged to "High".

[0158] At time B, when the potential of wiring 311 (signal 701) is set to "Low", the reset operation ends and the accumulation operation is started. Here, since a reverse bias is applied to the photoelectric conversion element 60, the potential of the charge storage section (FD) (signal 704) begins to rise due to the reverse current. .

[0159] The operations after time C can be referred to the description of the timing chart in FIG. 13(A). At time E, by acquiring the potential of wiring 315, it is possible to know the amount of light irradiated to the photoelectric conversion element 60 during the accumulation operation.

[0160] Note that the pixel circuit shown in FIG. 12(A) may be configured such that transistors 52 to 54 are shared among a plurality of pixels as shown in FIG. 17. FIG. 17 illustrates a configuration in which transistors 52 to 54 are shared among a plurality of pixels in the vertical direction. However, transistors 52 to 57 may be shared among a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. FIG. 17 illustrates a configuration in which transistors 52 to 54 are shared among a plurality of pixels in the vertical direction. However, transistors 52 to 57 may be shared among a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. Although FIG. 17 illustrates a configuration in which transistors 52 to 54 are shared among a plurality of pixels in the vertical direction, transistors 52 to 57 may be shared among a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. Although FIG. 17 illustrates a configuration in which transistors 52 to 54 are shared among a plurality of pixels in the vertical direction, transistors 52 to 57 may be shared among a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. ​By adopting such a configuration, the number of transistors per pixel can be reduced. In FIG. 17, transistors 52 to 54 are shared by four pixels, but it may be two pixels, three pixels, or five or more pixels. Also, the same configuration can be adopted for the pixel circuit shown in FIG. 1 2(B).

[0161] Also, the pixel circuit according to one aspect of the present invention may have the configuration shown in FIGS. 14(A) and (B).

[0162] The circuit shown in FIG. 14(A) has a configuration in which transistors 52, wiring 316, and wiring 317 are omitted from the configuration of the circuit shown in FIG. 12(A), and wiring 311 (RS) is electrically connected to the anode of the photoelectric conversion element 60. Other configurations are the same as those of the circuit shown in FIG. 12(A). .

[0163] The circuit shown in FIG. 14(B) has the same components as the circuit shown in FIG. 14(A), but is different in that the anode of the photoelectric conversion element 60 is electrically connected to one of the source or drain of transistor 51, and the cathode of the photoelectric conversion element 60 is electrically connected to wiring 311 (RS). .

[0164] Similar to the circuit of FIG. 12(A), the circuit of FIG. 14(A) can be operated at the timing chart shown in FIG. 13(A).

[0165] At time A, when the potential of wiring 311 (signal 701) is set to "High" and the potential of wiring 312 ( signal 702) is set to "High", a forward bias is applied to the photoelectric conversion element 60, and the potential of the charge storage section (FD) (signal 704) becomes "High". That is, the charge storage section ​​The potential of (FD) is initialized to the potential (“High”) of wiring 311 (RS), and it enters the reset state. The above is the start of the reset operation. Note that the potential of wiring 315 (signal 705) is pre-charged to “High”. This is the start of the reset operation. At time B, when the potential of wiring 311 (signal 701) is set to “Low”, the reset operation ends and the accumulation operation starts. Here, since a reverse bias is applied to the photoelectric conversion element 60, the potential of the charge storage section (FD) (signal 704) starts to decrease due to the reverse current.

[0166] At time B, when the potential of wiring 311 (signal 701) is set to “Low”, the reset operation ends and the accumulation operation starts. Here, since a reverse bias is applied to the photoelectric conversion element 60, the potential of the charge storage section (FD) (signal 704) starts to decrease due to the reverse current.

[0167] The operations after time C can be referred to the circuit operation description in Fig. 12(A). At time E, by acquiring the potential of wiring 315, the amount of light irradiated on the photoelectric conversion element 60 during the accumulation operation can be known.

[0168] The circuit in Fig. 14(B) can be operated according to the timing chart shown in Fig. 13(C).

[0169] At time A, when the potential of wiring 311 (signal 701) is set to “Low” and the potential of wiring 312 (signal 702) is set to “High”, a forward bias is applied to the photoelectric conversion element 60, and the potential of the charge storage section (FD) (signal 704) becomes the reset state of “Low”. The above is the start of the reset operation. Note that the potential of wiring 315 (signal 705) is pre-charged to “High”.

[0170] At time B, when the potential of wiring 311 (signal 701) is set to “High”, the reset operation ends and the accumulation operation starts. Here, a reverse bias is applied to the photoelectric conversion element 60. ​​​​​​​​​​​​Therefore, due to the reverse current, the potential (signal 704) of the charge storage section (FD) begins to rise. and.

[0171] The operations after time C can be referred to the description of the circuit operations in FIG. 12(A). At time E, by obtaining the potential of the wiring 315, it is possible to know the amount of light irradiated to the photoelectric conversion element 60 during the accumulation operation. and. of light.

[0172] Note that the pixel circuit shown in FIG. 14(A) may be configured such that the transistors 53 and 54 are shared by a plurality of pixels as shown in FIG. 18. FIG. 18 illustrates a configuration in which the transistors 53 and 54 are shared by a plurality of pixels in the vertical direction. However, the transistors 53 and 54 may be shared by a plurality of pixels in the horizontal direction or in both the horizontal and vertical directions. In FIG. 18, a form in which the transistors 53 and 54 are shared by four pixels is illustrated, but it may be two pixels, three pixels, or five or more pixels. Also, the pixel circuit shown in FIG. 14(B) can have a similar configuration. and. or. and. Note that FIG. 18 illustrates a form in which the transistors 53 and 54 are shared by four pixels, but it may be two pixels, three pixels, or five or more pixels. Also, the pixel circuit shown in FIG. 14(B) can have a similar configuration. and. In the pixel circuit shown in FIG. 14(B), a similar configuration can be adopted.

[0173] Also, in FIGS. 12(A), (B) and FIGS. 14(A), (B), examples in the case where the transistor 51 is provided are shown. However, one aspect of the present invention is not limited thereto. As shown in FIGS. 15(A), (B), it is also possible to omit the transistor 51. and. As shown in FIGS. 15(A), (B), it is also possible to omit the transistor 51.

[0174] Also, the transistors used in the pixel circuit may be configured such that back gates are provided for the transistors 51, 53, and 54 as shown in FIG. 16(A) or FIG. 16(B). FIG. 16(A) shows a configuration in which a fixed potential is applied to the back gate. and. and. The threshold voltage can be controlled. Also, FIG. 16(B) shows a configuration in which the same potential as the front gate is applied to the back gate, and the on-current can be increased. In FIG. 1 6(A), an example of a configuration in which the back gate is electrically connected to the wiring 314 (GND) is illustrated, but it may be electrically connected to another wiring to which a fixed potential is supplied. In FIG. 1 6(A) and (B), examples of circuits in which a back gate is provided for the transistors in the circuit shown in FIG. 14(A) are shown, but the same configuration can also be applied to the circuits shown in FIGS. 12(A) and (B), FIG. 14(B), FIGS. 15(A) and ( B). Also, for the transistors included in one circuit, a configuration in which the same potential as the front gate is applied to the back gate, a configuration in which a fixed potential is applied to the back gate, or a configuration in which no back gate is provided can be arbitrarily combined as required.

[0175] Note that the pixel circuit shown in FIG. 16(A) may be in a form in which the transistors 53 and 54 are shared by a plurality of pixels as shown in FIG. 19. Also, the pixel circuit shown in FIG. 16(B) may be in a form in which the transistors 53 and 54 are shared by a plurality of pixels as shown in FIG. 20.

[0176] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0177] (Embodiment 3) In this embodiment, an example of a method for driving a pixel circuit will be described.

[0178] As described in Embodiment 2, the operation of the pixel circuit includes a reset operation, an accumulation operation, and a selection ​​It is a repetition of the selection operation. As an imaging method for controlling the entire pixel matrix, a global shutter method and a rolling shutter method are known.

[0179] FIG. 21(A) is a timing chart in the global shutter method. Note that FIG. 21(A) shows an imaging device having a plurality of pixel circuits in a matrix, and the circuit of FIG. 12(A) is provided in the pixel circuit. Taking this as an example, the operation of the pixel circuits from the first row to the nth row (n is a natural number of 3 or more) is described. Note that the following operation description can also be applied to the circuits shown in FIGS. 12(B), 14(A), (B), and FIGS. 15(A), (B).

[0180] In FIG. 12(A), signals 501, 502, and 503 are signals input to wiring 311(RS) connected to the pixel circuits of the first row, the second row, and the nth row. Also, signals 504, 505, and 506 are signals input to wiring 312(TX) connected to the pixel circuits of the first row, the second row, and the nth row. Also, signals 507, 508 and 509 are signals input to wiring 313( SE) connected to the pixel circuits of the first row, the second row, and the nth row.

[0181] Also, period 510 is the period required for one imaging. Also, period 511 is the period during which the pixel circuits of each row are simultaneously performing a reset operation. Also, period 520 is the period during which the pixel circuits of each row are simultaneously performing an accumulation operation. Note that the selection operation is sequentially performed in the pixel circuits of each row. As an example, period 531 is the period during which the pixel circuit of the first row is performing a selection operation. In this way, in the global shutter method, the reset operation is performed almost simultaneously in all pixel circuits. After that, the accumulation operation is performed almost simultaneously in all pixel circuits, and the readout operation is sequentially performed for each row. It is read out.

[0182] That is, in the global shutter method, the accumulation operation is performed almost simultaneously in all pixel circuits. Therefore, the simultaneity of imaging in the pixel circuits of each row is ensured. Therefore, even if the subject is a moving object, an image with little distortion can be obtained.

[0183] On the other hand, FIG. 21(B) is a timing chart when the rolling shutter method is used. Note that signals 501 to 509 can be referred to for the description of FIG. 21(A). Period 6 10 is the period required for one imaging. Also, period 611, period 612, and period 613 are the reset periods of the first row, the second row, and the nth row, respectively. Also, period 621, period 622, and period 623 are the accumulation operation periods of the first row, the second row, and the nth row, respectively. Also, period 631 is the period during which the pixel circuit of the first row is performing the selection operation. Thus, in the rolling shutter method, the accumulation operation is not performed simultaneously in all pixel circuits but is sequentially performed for each row. Therefore, the simultaneity of imaging in the pixel circuits of each row is not ensured. Therefore, since the imaging timings are different between the first row and the last row, when the moving object is the subject, an image with a large distortion is obtained. In order to realize the global shutter method, it is necessary to keep the potential of the charge accumulation part (FD) for a long time until the signal readout from each pixel is sequentially completed. The potential of the charge accumulation part (FD) can be realized by using a transistor with an extremely low off-current in which the channel formation region is formed of an oxide semiconductor in a transistor such as transistor 51. On the other hand, transistor 51

[0184] To realize the global shutter method, it is necessary to keep the potential of the charge accumulation section (FD) for a long time until the signal readout from each pixel is sequentially completed. The long-term holding of the potential of the charge accumulation section (FD) can be realized by using a transistor with an extremely low off-current in which the channel formation region is formed of an oxide semiconductor in a transistor such as transistor 51. The long-term holding of the potential of the charge accumulation section (FD) can be achieved by using a transistor with an extremely low off-current in which the channel formation region is formed of an oxide semiconductor in a transistor such as transistor 51. One way is to use a transistor with an extremely low off-current in which the channel formation region is formed of an oxide semiconductor in a transistor such as transistor 51. When a transistor having a channel formation region formed of silicon or the like is applied to the like, the off current is high, so that the potential of the charge storage part (FD) cannot be held for a long time, and the global shutter method becomes difficult to use.

[0185] As described above, by using a transistor having a channel formation region formed of an oxide semiconductor in the pixel circuit, the global shutter method can be easily realized.

[0186] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0187] (Embodiment 4) In this embodiment, a transistor having an oxide semiconductor that can be used in one aspect of the present invention will be described with reference to the drawings. Note that in the drawings of this embodiment, for clarity, some elements are shown enlarged, reduced, or omitted.

[0188] FIGS. 22(A) and (B) are a top view and a cross-sectional view of a transistor 101 according to one aspect of the present invention. FIG. 22(A) is a top view, and a cross-section in the direction of the dashed-dotted line B1 - B2 shown in FIG. 22(A) corresponds to FIG. 22(B). Also, a cross-section in the direction of the dashed-dotted line B3 - B4 shown in FIG. 22(A) corresponds to FIG. 28(A). Also, the direction of the dashed-dotted line B1 - B2 is referred to as the channel length direction, and the direction of the dashed-dotted line B 3 - B4 is referred to as the channel width direction.

[0189] The transistor 101 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 140 and a conductive layer 150 electrically connected to the oxide semiconductor layer 130, and an insulating layer 1 in contact with the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150 60, a conductive layer 170 in contact with the insulating layer 160, and the conductive layer 140, the conductive layer 150, the insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175 , and has. Further, a function as a planarization film may be added to the insulating layer 180 as necessary .

[0190] Here, the conductive layer 140 can function as a source electrode layer, the conductive layer 150 can function as a drain electrode layer, and the insulating layer 160 can function as a gate insulating film, and the conductive layer 170 can function as a gate electrode layer, respectively.

[0191] Also, the region 231 shown in FIG. 22(B) can function as a source region, the region 232 can function as a drain region, and the region 2 33 can function as a channel formation region. The regions 231 and 232 are in contact with the conductive layer 140 and the conductive layer 150, respectively. If a conductive material that easily binds to oxygen is used as the conductive layer 140 and the conductive layer 150, the regions 231 and 232 can be made to have low resistance .

[0192] Specifically, when the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150, oxygen deficiency occurs in the oxide semiconductor layer 130, and due to the interaction between the oxygen deficiency and hydrogen remaining in or diffusing from the outside into the oxide semiconductor layer 130, the regions 231 and 232 become low-resistance n-type.

[0193] Note that the functions of "source" and "drain" of a transistor may be interchanged when different polarities of transistors are employed, or when the direction of current changes in a circuit operation. Therefore, in this specification, the terms "source" and "drain" may be interchanged . be able to be used. Also, the "electrode layer" can also be referred to as "wiring".

[0194] In addition, although an example in which the conductive layer 170 is formed of two layers, i.e., the conductive layer 171 and the conductive layer 172, is illustrated it may be a single layer or a laminate of three or more layers. This configuration can also be applied to other transistors described in this embodiment .

[0195] In addition, although an example in which the conductive layers 140 and 150 are formed as single layers is illustrated, they may be a laminate of two or more layers. This configuration can also be applied to other transistors described in this embodiment .

[0196] Also, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 23(A) and (B). FIG. 23(A) is a top view of the transistor 102, and a cross section taken along the dashed-dotted line C1-C2 direction shown in FIG. 23(A) corresponds to FIG. 23(B). Further, a cross section taken along the dashed-dotted line C3-C4 direction shown in FIG. 23(A) corresponds to FIG. 28(B). Also, the dashed-dotted line C1-C2 direction is referred to as the channel length direction, and the dashed-dotted line C3-C4 direction is referred to as the channel width direction. FIG. 23(A) is a top view of the transistor 102, and a cross section taken along the dashed-dotted line C1-C2 direction shown in FIG. 23(A) corresponds to FIG. 23(B). Also, a cross section taken along the dashed-dotted line C3-C4 direction shown in FIG. 23(A) corresponds to FIG. 28(B). Also, the dashed-dotted line C1-C2 direction is referred to as the channel length direction, and the dashed-dotted line C3-C4 direction is referred to as the channel width direction.

[0197] The transistor 102 has the same configuration as the transistor 101, except that the ends of the insulating layer 160 acting as a gate insulating film and the ends of the conductive layer 170 acting as a gate electrode layer do not coincide. The structure of the transistor 102 is such that the conductive layers 140 and 150 are widely covered with the insulating layer 160, so that the resistance between the conductive layers 140 and 150 and the conductive layer 170 is high, and it has a feature of low gate leakage current.

[0198] ​​​​​​​Transistors 101 and 102 have a top gate structure having a region where the conductive layer 170 overlaps with the conductive layer 140 and the conductive layer 150. The width in the channel length direction of the region is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, it is easy to form a transistor with a high on-current. The transistor according to an aspect of the present invention may also have a configuration shown in FIGS. 24(A) and (B). FIG. 24(A) is a top view of the transistor 103, and a cross section taken along the one-dot chain line D1-D2 direction shown in FIG. 24(A) corresponds to FIG. 24(B). Also, a cross section taken along the one-dot chain line D3-D4 direction shown in FIG. 24(A) corresponds to FIG. 28(A). Also, the one-dot chain line D1-D2 direction is referred to as the channel length direction, and the one-dot chain line D3-D4 direction is referred to as the channel width direction. The transistor 103 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 140 and a conductive layer 150 that are electrically connected to the oxide semiconductor layer 130 through an opening provided in the insulating layer 175 and the insulating layer 180. Further, if necessary, it may have an insulating layer (planarization film) and the like in contact with the insulating layer 180, the conductive layer 140, and the conductive layer 150. Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is

[0199]

[0200]

[0201] The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0202] In addition, a region 231 shown in FIG. 24(B) is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. If an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0203] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0204] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 25A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 25(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 28(A). The direction of the dashed dotted line E3-E4 is referred to as the channel width direction.

[0205] In the transistor 104, the conductive layer 140 and the conductive layer 150 cover edges of the oxide semiconductor layer. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 104.

[0206] In addition, the regions 331 and 334 shown in FIG. 25(B) are source regions, and the regions 332 and Region 335 is a drain region, and region 333 can function as a channel formation region. .

[0207] Regions 331 and 332 can be made to have low resistance in the same way as regions 231 and 232 in transistor 101. It is possible to reduce the resistance.

[0208] Also, regions 334 and 335 can be made to have low resistance in the same way as regions 231 and 232 in transistor 103. Note that when the lengths of regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, there may be cases where regions 334 and 335 are not made to have low resistance. When the lengths of regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, there may be cases where regions 334 and 335 are not made to have low resistance. When the lengths of regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, there may be cases where regions 334 and 335 are not made to have low resistance. When the lengths of regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, there may be cases where regions 334 and 335 are not made to have low resistance. When the lengths of regions 334 and 335 in the channel length direction are 100 nm or less, preferably 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Therefore, there may be cases where regions 334 and 335 are not made to have low resistance.

[0209] Transistors 103 and 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layers 140 and 150. A self-aligned transistor has an extremely small parasitic capacitance between the gate electrode layer, the source electrode layer, and the drain electrode layer, and is therefore suitable for high-speed operation applications. Transistors 103 and 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layers 140 and 150. A self-aligned transistor has an extremely small parasitic capacitance between the gate electrode layer, the source electrode layer, and the drain electrode layer, and is therefore suitable for high-speed operation applications. Transistors 103 and 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layers 140 and 150. A self-aligned transistor has an extremely small parasitic capacitance between the gate electrode layer, the source electrode layer, and the drain electrode layer, and is therefore suitable for high-speed operation applications. Transistors 103 and 104 have a self-aligned structure in which the conductive layer 170 does not overlap with the conductive layers 140 and 150. A self-aligned transistor has an extremely small parasitic capacitance between the gate electrode layer, the source electrode layer, and the drain electrode layer, and is therefore suitable for high-speed operation applications.

[0210] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 26(A) and (B). FIG. 26(A) is a top view of transistor 105, and the cross section in the direction of the dashed line F1 - F2 shown in FIG. 26(A) corresponds to FIG. 26(B). Also, the cross section in the direction of the dashed line F3 - F4 shown in FIG. 26(A) corresponds to FIG. 28(A). Also, the direction of the dashed line F1 - F2 is referred to as the channel length direction, and the direction of the dashed line F3 - F4 is referred to as the channel width direction. FIG. 26(A) is a top view of transistor 105, and the cross section in the direction of the dashed line F1 - F2 shown in FIG. 26(A) corresponds to FIG. 26(B). Also, the cross section in the direction of the dashed line F3 - F4 shown in FIG. 26(A) corresponds to FIG. 28(A). Also, the direction of the dashed line F1 - F2 is referred to as the channel length direction, and the direction of the dashed line F3 - F4 is referred to as the channel width direction. FIG. 26(A) is a top view of transistor 105, and the cross section in the direction of the dashed line F1 - F2 shown in FIG. 26(A) corresponds to FIG. 26(B). Also, the cross section in the direction of the dashed line F3 - F4 shown in FIG. 26(A) corresponds to FIG. 28(A). Also, the direction of the dashed line F1 - F2 is referred to as the channel length direction, and the direction of the dashed line F3 - F4 is referred to as the channel width direction. FIG. 26(A) is a top view of transistor 105, and the cross section in the direction of the dashed line F1 - F2 shown in FIG. 26(A) corresponds to FIG. 26(B). Also, the cross section in the direction of the dashed line F3 - F4 shown in FIG. 26(A) corresponds to FIG. 28(A). Also, the direction of the dashed line F1 - F2 is referred to as the channel length direction, and the direction of the dashed line F3 - F4 is referred to as the channel width direction. FIG. 26(A) is a top view of transistor 105, and the cross section in the direction of the dashed line F1 - F2 shown in FIG. 26(A) corresponds to FIG. 26(B). Also, the cross section in the direction of the dashed line F3 - F4 shown in FIG. 26(A) corresponds to FIG. 28(A). Also, the direction of the dashed line F1 - F2 is referred to as the channel length direction, and the direction of the dashed line F3 - F4 is referred to as the channel width direction.

[0211] Transistor 105 includes an insulating layer 120 in contact with a substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 respectively through openings provided in the insulating layer 175 and the insulating layer 180. Further, it may have an insulating layer or the like in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152 as necessary.

[0212] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and are not in contact with the side surfaces.

[0213] Transistor 105 has the same configuration as transistor 101 except that it has the conductive layer 141 and the conductive layer 151, has openings provided in the insulating layer 175 and the insulating layer 180, and has a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 respectively through the openings. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can function as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 152) can function as a drain electrode layer.

[0214] Further, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 27(A) and (B). ​​​​​Yes. FIG. 27(A) is a top view of the transistor 106, and the dashed-dotted line G shown in FIG. 27(A) The cross-section in the G1-G2 direction corresponds to FIG. 27(B). Also, the dashed-dotted line G3 shown in FIG. 27(A) - The cross-section in the G4 direction corresponds to FIG. 28(A). Also, the direction of the dashed-dotted line G1-G2 is defined as the channel length direction, and the direction of the dashed-dotted line G3-G4 is defined as the channel width direction.

[0215] The transistor 106 includes an insulating layer 120 in contact with the substrate 115, an oxide semiconductor layer 130 in contact with the insulating layer 120, a conductive layer 141 and a conductive layer 151 electrically connected to the oxide semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, a conductive layer 170 in contact with the insulating layer 160, an insulating layer 175 in contact with the insulating layer 120, the oxide semiconductor layer 130, the conductive layer 141, the conductive layer 151, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 142 and a conductive layer 152 that are electrically connected to the conductive layer 141 and the conductive layer 151 respectively through openings provided in the insulating layer 175 and the insulating layer 180. Also, if necessary, it may have an insulating layer (planarization film ) in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 152, etc.

[0216] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and are not in contact with the side surfaces in a non-contact configuration.

[0217] The transistor 106 has the same configuration as the transistor 103 except for having the conductive layer 141 and the conductive layer 151. The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can act as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 15 2) can act as a drain electrode layer. - The conductive layer 140 (the conductive layer 141 and the conductive layer 142) can act as a source electrode layer, and the conductive layer 150 (the conductive layer 151 and the conductive layer 15 2) can act as a drain electrode layer.

[0218] In the structures of transistor 105 and transistor 106, since conductive layer 140 and conductive layer 1 50 are not in contact with insulating layer 120, oxygen in insulating layer 120 is less likely to be taken away by conductive layer 140 and conductive layer 150, and the supply of oxygen from insulating layer 120 into oxide semiconductor layer 130 can be facilitated.

[0219] Note that impurities for forming oxygen deficiencies and increasing the conductivity may be added to regions 231 and 232 in transistor 103, regions 334 and 335 in transistor 104 and transistor 106. As impurities for forming oxygen deficiencies in the oxide semiconductor layer, for example, one or more selected from phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon can be used. As a method for adding the impurities, a plasma treatment method, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. When the above elements are added to the oxide semiconductor layer as impurity elements, the bonds between the metal elements and oxygen in the oxide semiconductor layer are broken, and oxygen deficiencies are formed. Due to the interaction between the oxygen deficiencies contained in the oxide semiconductor layer and hydrogen remaining or added later in the oxide semiconductor layer,

[0220] the conductivity of the oxide semiconductor layer can be increased.

[0221] Note that when hydrogen is added to an oxide semiconductor in which oxygen deficiencies are formed by the addition of impurity elements, ​​​​​Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. Here, the oxide semiconductor that has been made a conductor can be used as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0222] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0223] In addition, the transistor of one embodiment of the present invention can be formed as shown in FIG. 28(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows the on-current to be increased and the threshold voltage to be controlled. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive semiconductor layer 130. It may be shorter than the width.

[0224] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To set 73 to the same potential, for example, as shown in FIG. 28(D), the conductive layer 170 and the conductive layer 1 73 may be electrically connected via a contact hole.

[0225] Further, in the transistors 101 to 106 in FIGS. 22 to 27, although an example in which the oxide semiconductor layer 130 is a single layer is illustrated, the oxide semiconductor layer 130 may be laminated. The oxide semiconductor layers 130 of the transistors 101 to 106 can be replaced with the oxide semiconductor layers 130 shown in FIG. 30( (B), (C) or FIG. 30(D), (E).

[0226] FIG. 30(A) is a top view of the oxide semiconductor layer 130, and FIGS. 30(B), (C) are cross-sectional views of the oxide semiconductor layer 130 having a two-layer structure. Further, FIGS. 30(D), (E) are cross-sectional views of the oxide semiconductor layer 130 having a three-layer structure.

[0227] For the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, oxide semiconductor layers having different compositions or the like can be used respectively.

[0228] Further, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 31(A), (B). FIG. 31(A) is a top view of the transistor 107, and a cross-section in the direction of the dashed-dotted line H 1-H2 shown in FIG. 31(A) corresponds to FIG. 31(B). Further, a cross-section in the direction of the dashed-dotted line H3 -H4 shown in FIG. 31(A) corresponds to FIG. 37(A). Further, the direction of the dashed-dotted line H1-H2 is referred to as the channel length direction, and the direction of the dashed-dotted line H3-H4 is referred to as the channel width direction.

[0229] The transistor 107 includes an insulating layer 120 in contact with the substrate 115 and an oxide in contact with the insulating layer 120. ​​​​A stack composed of a semiconductor layer 130a and an oxide semiconductor layer 130b, and conductive layers 140 and 150 that are electrically connected to the stack, an oxide semiconductor layer 130c that contacts the stack, the conductive layers 140 and 15 0, an insulating layer 160 that contacts the oxide semiconductor layer 130c, and a conductive layer 170 that contacts the insulating layer 160, an insulating layer 175 that contacts the conductive layers 140, 150, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, and an insulating layer 180 that contacts the insulating layer 175. Further, a function as a planarization film may be added to the insulating layer 180 as needed.

[0230] The transistor 107 has the same configuration as the transistor 101, except that the oxide semiconductor layer 130 is two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in regions 231 and 232, the oxide semiconductor layer 130 is three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 140 and 150 and the insulating layer 160.

[0231] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 32(A) and (B). FIG. 32(A) is a top view of the transistor 108, and the cross section in the one-dot chain line I1-I2 direction shown in FIG. 32(A) corresponds to FIG. 32(B). Further, the cross section in the one-dot chain line I3-I4 direction shown in FIG. 32(A) corresponds to FIG. 37(B). Also, the one-dot chain line I1-I2 direction may be referred to as the channel length direction, and the one-dot chain line I3-I4 direction may be referred to as the channel width direction.

[0232] Transistor 108 is different from transistor 107 in that the ends of the insulating layer 160 and the oxide semiconductor layer 130c do not coincide with the ends of the conductive layer 17 0.

[0233] Further, the transistor according to one aspect of the present invention may have a configuration shown in FIGS. 33(A) and (B). FIG. 33(A) is a top view of transistor 109, and the cross section in the dash-dotted line J 1-J2 direction shown in FIG. 33(A) corresponds to FIG. 33(B). Also, the cross section in the dash-dotted line J3 -J4 direction shown in FIG. 33(A) corresponds to FIG. 37(A). Further, the dash-dotted line J1-J2 direction is referred to as the channel length direction, and the dash-dotted line J3-J4 direction is referred to as the channel width direction.

[0234] Transistor 109 includes an insulating layer 120 in contact with the substrate 115, a stack composed of an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, an oxide semiconductor layer 130c in contact with the stack, an insulating layer 160 in contact with the oxide semiconductor layer 130c, a conductive layer 170 in contact with the insulating layer 16 0, an insulating layer 175 covering the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and a conductive layer 14 0 and a conductive layer 150 that are electrically connected to the stack through an opening provided in the insulating layer 175 and the insulating layer 180. Further, if necessary, it may have an insulating layer 180, a conductive layer 140, and an insulating layer (planarization film) in contact with the conductive layer 150, etc. In transistor 109, the oxide semiconductor layer 130 is two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in regions 231 and 232, and the oxide semiconductor layer 130 is three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide

[0235] in region 233. semiconductor layer 130c) at a point where the oxide semiconductor layer 130 is three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as the transistor 103, except that it is the oxide semiconductor layer 130c).

[0236] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 34(A) and (B). FIG. 34(A) is a top view of the transistor 110, and the cross section in the dash-dotted line K1-K2 direction shown in FIG. 34(A) corresponds to FIG. 34(B). Also, the cross section in the dash-dotted line K3-K4 direction shown in FIG. 34(A) corresponds to FIG. 37(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. FIG. 34(A) is a top view of the transistor 110, and the cross section in the dash-dotted line K1-K2 direction shown in FIG. 34(A) corresponds to FIG. 34(B). Also, the cross section in the dash-dotted line K3-K4 direction shown in FIG. 34(A) corresponds to FIG. 37(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. FIG. 34(A) is a top view of the transistor 110, and the cross section in the dash-dotted line K1-K2 direction shown in FIG. 34(A) corresponds to FIG. 34(B). Also, the cross section in the dash-dotted line K3-K4 direction shown in FIG. 34(A) corresponds to FIG. 37(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction. FIG. 34(A) is a top view of the transistor 110, and the cross section in the dash-dotted line K1-K2 direction shown in FIG. 34(A) corresponds to FIG. 34(B). Also, the cross section in the dash-dotted line K3-K4 direction shown in FIG. 34(A) corresponds to FIG. 37(A). Further, the dash-dotted line K1-K2 direction is referred to as the channel length direction, and the dash-dotted line K3-K4 direction is referred to as the channel width direction.

[0237] The transistor 110 has the same configuration as the transistor 104, except that the oxide semiconductor layer 130 is a two-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, and the oxide semiconductor layer 130 is a three-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233. The transistor 110 has the same configuration as the transistor 104, except that the oxide semiconductor layer 130 is a two-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, and the oxide semiconductor layer 130 is a three-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233. The transistor 110 has the same configuration as the transistor 104, except that the oxide semiconductor layer 130 is a two-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, and the oxide semiconductor layer 130 is a three-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233. The transistor 110 has the same configuration as the transistor 104, except that the oxide semiconductor layer 130 is a two-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, and the oxide semiconductor layer 130 is a three-layer (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233.

[0238] Also, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 35(A) and (B). FIG. 35(A) is a top view of the transistor 111, and the cross section in the dash-dotted line L1-L2 direction shown in FIG. 35(A) corresponds to FIG. 35(B). Also, the cross section in the dash-dotted line L3-L4 direction shown in FIG. 35(A) corresponds to FIG. 37(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. FIG. 35(A) is a top view of the transistor 111, and the cross section in the dash-dotted line L1-L2 direction shown in FIG. 35(A) corresponds to FIG. 35(B). Also, the cross section in the dash-dotted line L3-L4 direction shown in FIG. 35(A) corresponds to FIG. 37(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. FIG. 35(A) is a top view of the transistor 111, and the cross section in the dash-dotted line L1-L2 direction shown in FIG. 35(A) corresponds to FIG. 35(B). Also, the cross section in the dash-dotted line L3-L4 direction shown in FIG. 35(A) corresponds to FIG. 37(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction. FIG. 35(A) is a top view of the transistor 111, and the cross section in the dash-dotted line L1-L2 direction shown in FIG. 35(A) corresponds to FIG. 35(B). Also, the cross section in the dash-dotted line L3-L4 direction shown in FIG. 35(A) corresponds to FIG. 37(A). Further, the dash-dotted line L1-L2 direction is referred to as the channel length direction, and the dash-dotted line L3-L4 direction is referred to as the channel width direction.

[0239] The transistor 111 includes an insulating layer 120 in contact with the substrate 115, a stack including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, and is electrically connected to the stack. The transistor 111 includes an insulating layer 120 in contact with the substrate 115, a stack including an oxide semiconductor layer 130a and an oxide semiconductor layer 130b in contact with the insulating layer 120, and is electrically connected to the stack. The conductive layers 141 and 151 to be connected, and the oxide semiconductor layer 130c in contact with the laminate, the conductive layer 141, and the conductive layer 15 1, the insulating layer 160 in contact with the oxide semiconductor layer 130c, and the conductive layer 170 in contact with the insulating layer 160, and the insulating layer 175 in contact with the laminate, the conductive layer 141, the conductive layer 151, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170, and the insulating layer 180 in contact with the insulating layer 175, and the conductive layers 142 and 152 that are electrically connected to the conductive layers 141 and 151, respectively, through the openings provided in the insulating layer 175 and the insulating layer 180. Also, if necessary, an insulating layer (planarization film) or the like in contact with the insulating layer 180, the conductive layer 142, and the conductive layer 1 52 may be provided. The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160.

[0240] In addition, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 36(A) and (B). FIG. 36(A) is a top view of the transistor 112, and the cross-section in the dash-dotted line M1-M2 direction shown in FIG. 36(A) corresponds to FIG. 36(B). Also, the cross-section in the dash-dotted line M3-M4 direction shown in FIG. 36(A) corresponds to FIG. 37(A). Further, the dash-dotted line M1-M2 direction is referred to as the channel length direction, and the dash-dotted line M3-M4 direction is referred to as the channel width direction. The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160. The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160. The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160. The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160. The transistor 111 has the same configuration as the transistor 105, except that the oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b) in the regions 231 and 232, the oxide semiconductor layer 130 is a three-layer structure (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c) in the region 233, and a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between the conductive layers 141 and 151 and the insulating layer 160.

[0241] In addition, the transistor according to one aspect of the present invention may have the configuration shown in FIGS. 36(A) and (B). FIG. 36(A) is a top view of the transistor 112, and the cross-section in the dash-dotted line M1-M2 direction shown in FIG. 36(A) corresponds to FIG. 36(B). Also, the cross-section in the dash-dotted line M3-M4 direction shown in FIG. 36(A) corresponds to FIG. 37(A). Further, the dash-dotted line M1-M2 direction is referred to as the channel length direction, and the dash-dotted line M3-M4 direction is referred to as the channel width direction. FIG. 36(A) is a top view of the transistor 112, and the cross-section in the dash-dotted line M1-M2 direction shown in FIG. 36(A) corresponds to FIG. 36(B). Also, the cross-section in the dash-dotted line M3-M4 direction shown in FIG. 36(A) corresponds to FIG. 37(A). Further, the dash-dotted line M1-M2 direction is referred to as the channel length direction, and the dash-dotted line M3-M4 direction is referred to as the channel width direction. FIG. 36(A) is a top view of the transistor 112, and the cross-section in the dash-dotted line M1-M2 direction shown in FIG. 36(A) corresponds to FIG. 36(B). Also, the cross-section in the dash-dotted line M3-M4 direction shown in FIG. 36(A) corresponds to FIG. 37(A). Further, the dash-dotted line M1-M2 direction is referred to as the channel length direction, and the dash-dotted line M3-M4 direction is referred to as the channel width direction. FIG. 36(A) is a top view of the transistor 112, and the cross-section in the dash-dotted line M1-M2 direction shown in FIG. 36(A) corresponds to FIG. 36(B). Also, the cross-section in the dash-dotted line M3-M4 direction shown in FIG. 36(A) corresponds to FIG. 37(A). Further, the dash-dotted line M1-M2 direction is referred to as the channel length direction, and the dash-dotted line M3-M4 direction is referred to as the channel width direction. FIG. 36(A) is a top view of the transistor 112, and the cross-section in the dash-dotted line M1-M2 direction shown in FIG. 36(A) corresponds to FIG. 36(B). Also, the cross-section in the dash-dotted line M3-M4 direction shown in FIG. 36(A) corresponds to FIG. 37(A). Further, the dash-dotted line M1-M2 direction is referred to as the channel length direction, and the dash-dotted line M3-M4 direction is referred to as the channel width direction.

[0242] The transistor 112 is in regions 331, 332, 334, and 335 The oxide semiconductor layer 130 is two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b) In terms of this point, and except that in region 333 the oxide semiconductor layer 130 is three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c), it has the same configuration as the transistor 106.

[0243] Also, a transistor according to one aspect of the present invention may include a conductive layer 173 between the oxide semiconductor layer 130 and the substrate 115, as in the cross-sectional views in the channel length direction shown in FIGS. 38(A), (B), (C), (D), (E), (F), and the cross-sectional views in the channel width direction shown in FIGS. 37(C), (D). Using this conductive layer as a second gate electrode layer (back gate) makes it possible to further increase the on-current and control the threshold voltage. In the cross-sectional views shown in FIGS. 38(A), (B), (C), (D), (E), (F), the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Furthermore, the width of the conductive layer 173 may be shorter than the width of the conductive layer 1 70.

[0244] Also, the conductive layer 140 (source electrode layer) and the conductive layer 150 (drain electrode layer) in a transistor according to one aspect of the present invention may be formed such that the widths (W ) of the conductive layer 140 and the conductive layer 150 are longer than the width (W ) of the oxide semiconductor layer, as in the top views shown in FIGS. 39(A), (B) (showing only the oxide semiconductor layer 1 O S 30, the conductive layer 140, and the conductive layer 150). SD They may also be formed shorter. W OS ≧WSD (W SD is W OS as follows), the gate electric field is likely to be applied to the entire oxide semiconductor layer 130, and the electrical characteristics of the transistor can be improved.

[0245] In the transistors (transistors 101 to 112) according to one aspect of the present invention, in any configuration, the conductive layer 170 serving as the gate electrode layer electrically surrounds the channel width direction of the oxide semiconductor layer 130 via the insulating layer 160, and the on-current is increased. Such a transistor structure is called a surrounded channel (s-channel) structure.

[0246] Also, in a transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, and in a transistor having the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c by appropriately selecting two or three materials constituting the oxide semiconductor layer 130, current can flow through the oxide semiconductor layer 130b. When current flows through the oxide semiconductor layer 130b, it is less affected by interface scattering, and a high on-current can be obtained. When the oxide semiconductor layer 130b is thickened, the on-current can be improved. For example, the film thickness of the oxide semiconductor layer 130b may be set to 100 nm to 200 nm. is also good.

[0247] By using the transistor having the above configuration, good electrical characteristics can be imparted to the semiconductor device.

[0248] The configuration shown in the present embodiment can be used in appropriate combination with the configuration shown in other embodiments. ​​It is possible.

[0249] (Embodiment 5) In this embodiment, the components of the transistor shown in Embodiment 4 will be described in detail. It can be.

[0250] For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. - For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. - For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased. For the substrate 115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate whose surface is subjected to insulation treatment, etc. can be used. Alternatively, a silicon substrate on which transistors and photodiodes are formed, and a substrate on which an insulating layer, wiring, a conductor having a function as a contact plug, etc. are formed can be used. When forming a p-ch type transistor on a silicon substrate, it is preferable to use a silicon substrate having an n-type conductivity type. Alternatively, an SOI substrate having an n-type or i-type silicon layer may be used. When the transistor provided on the silicon substrate is a p-ch type, the plane orientation of the plane on which the transistor is formed is preferably the (110) plane. By forming a p-ch type transistor on the (110) plane, the mobility can be increased.

[0251] The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115, and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115, and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115, and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115, and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115, and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115, and can also play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 19 atoms / cm 3Use the above-described film. Also, when the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 also has a function as an interlayer insulating film. In that case, it is preferable to perform a planarization process such as CMP so that the surface becomes flat.

[0252] For example, the insulating layer 120 may be formed of an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, a nitride insulating film such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride, or a mixed material thereof. Further, a laminate of the above materials may be used.

[0253] In this embodiment, mainly, the case where the oxide semiconductor layer 130 included in the transistor has a three-layer structure in which the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side will be described in detail.

[0254] When the oxide semiconductor layer 130 is a single layer, a layer corresponding to the oxide semiconductor layer 13 0b shown in this embodiment may be used.

[0255] When the oxide semiconductor layer 130 is a two-layer structure, a laminate in which a layer corresponding to the oxide semiconductor layer 13 0a and a layer corresponding to the oxide semiconductor layer 130b shown in this embodiment are stacked in this order from the insulating layer 120 side may be used. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b may be interchanged.

[0256] ​​​​​In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0257] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0258] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum of the oxide semiconductor layer 13 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0259] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0260] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. It becomes difficult to form. Since the interface level may form a channel, the threshold voltage of the transistor may vary. Therefore, by providing the oxide semiconductor layer 130a, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, the reliability of the transistor can be improved. Also, since the oxide semiconductor layer 130c is composed of including one or more metal elements constituting the oxide semiconductor layer 130b, carrier scattering is less likely to occur at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c compared to the interface when the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact. Therefore, by providing the oxide semiconductor layer 130c, the field-effect mobility of the transistor can be increased. Moreover, the reliability of the transistor can be improved.

[0261] For the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, materials containing, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at an atomic ratio higher than that of the oxide semiconductor layer 130b can be used. Specifically, the atomic ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since the aforementioned elements strongly bond with oxygen, they have a function of suppressing the occurrence of oxygen deficiency in the oxide semiconductor layer. That is, it can be said that the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are less likely to have oxygen deficiency than the oxide semiconductor layer 130b. In addition, the oxide semiconductors that can be used as the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c should contain at least In or Zn. The interface level may form a channel, so the threshold voltage of the transistor may vary. Therefore, by providing the oxide semiconductor layer 130a, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. Moreover, the reliability of the transistor can be improved.

[0262] For the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, materials containing, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at an atomic ratio higher than that of the oxide semiconductor layer 130b can be used. Specifically, the atomic ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since the aforementioned elements strongly bond with oxygen, they have a function of suppressing the occurrence of oxygen deficiency in the oxide semiconductor layer. That is, it can be said that the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are less likely to have oxygen deficiency than the oxide semiconductor layer 130b. Moreover, the oxide semiconductors that can be used as the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c should contain at least In or Zn. The interface level may form a channel, so the threshold voltage of the transistor may vary. Therefore, by providing the oxide semiconductor layer 130a, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0263] For the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c, materials containing, for example, Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at an atomic ratio higher than that of the oxide semiconductor layer 130b can be used. Specifically, the atomic ratio is set to 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. It is preferable. Or, it is preferable to contain both In and Zn. Also, when using the oxide semiconductor in order to reduce the variation in the electrical characteristics of the transistors used together with them, it is preferable to contain a stabilizer.

[0264] Examples of the stabilizer include Ga, Sn, Hf, Al, or Zr, etc. Also, other stabilizers include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0265] For example, as the oxide semiconductor, indium oxide, tin oxide, gallium oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide can be used.

[0266] Here, for example, the In-Ga-Zn oxide means an oxide containing In, Ga, and Zn as main components. Also, it is acceptable if it contains metal elements other than In, Ga, and Zn. In this specification, a film composed of an In-Ga-Zn oxide is also called an IGZO film.

[0267] Also, a material represented by InMO3(ZnO) (m > 0 and m is not an integer) may be used. Here, M represents one or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Also, a material represented by In2SnO5(ZnO) (n > 0 and n is an integer) may be used. m (m > 0 and m is not an integer) may be used. Here, M represents one or a plurality of metal elements selected from Ga, Y, Zr, La, Ce, or Nd. Also, a material represented by In2SnO5(ZnO) (n > 0 and n is an integer) may be used. n (n > 0 and n is an integer) may be used.

[0268] When the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are In-M-Zn oxides containing at least indium, zinc, and M (a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), if the oxide semiconductor layer 130a is In:M:Zn = x1:y1:z1 [atomic ratio], the oxide semiconductor layer 130b is In:M:Zn = x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Zn = x3:y3:z3 [atomic ratio], it is preferable that y1 / x1 and y3 / x3 are larger than y2 / x2. y1 / x1 and y3 / x3 are 1.5 times or more, preferably 2 times or more, more preferably 3 times or more than y2 / x2. At this time, in the oxide semiconductor layer 130b, when y2 is equal to or more than x2, the electrical characteristics of the transistor can be stabilized. However, when y2 becomes 3 times or more of x2, the field-effect mobility of the transistor ​​​​​​​​​​​​​Since it will decrease, it is preferable that y2 is less than three times x2.

[0269] In the case of excluding Zn and O from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c the atomic ratio of In and M is preferably less than 50 atomic% for In and 50 atomic% or more for M, more preferably less than 25 atomic% for In and 7 5 atomic% or more for M. Further, excluding Zn and O from the oxide semiconductor layer 130b the atomic ratio of In and M is preferably 25 atomic% or more for In and 75 at omic% or less for M, more preferably 34 atomic% or more for In and 66 atomi c% or less.

[0270] Also, the oxide semiconductor layer 130b may have a higher indium content than the oxide semiconductor layer 130a and the oxide semiconductor layer 130 c. In an oxide semiconductor, mainly the s orbitals of heavy metals contribute to carrier conduction. By increasing the content rate of In, more s orbitals overlap. Therefore, an oxide having a composition with more In than M has a higher mobility than an oxide having a composition with In equal to or less than M. Therefore, by using an oxide with a high indium content for the oxide semiconductor layer 130b, a transistor with high field-effect mobility can be realized.

[0271] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 0 nm or less, more preferably 5 nm or more and 25 nm or less. Also, the oxide semiconductor layer 1 30b has a thickness of 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less, more preferably 15 nm or more and 100 nm or less. Also, the oxide semiconductor layer 130c The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, more preferably 3 nm or more and 15 nm or less. Also, the oxide semiconductor layer 130b is preferably thicker than the oxide semiconductor layer 1 30a.

[0272] In order to impart stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor layer and make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less than 1 ×10 17 / cm 3 , preferably less than 1×10 15 / cm 3 , more preferably less than 1×10 13 / cm 3 .

[0273] Also, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Also, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the layers of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c and at the interfaces thereof. .

[0274] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the silicon concentration estimated by SIMS (Secondary Ion Mass Spectrometry) analysis is 1×10 19 atoms / cm3 less than, preferably 5×10 18 atoms / cm 3 less than , more preferably 1×10 18 atoms / cm 3 is controlled to have a region less than Also, the hydrogen concentration is 2×10 20 atoms / cm 3 or less, preferably 5×10 1 9 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, further preferably 5×10 18 atoms / cm 3 is controlled to have a region less than or equal to Also, the nitrogen concentration is 5×10 19 atoms / cm 3 less than, preferably 5×10 18 at oms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, further preferably 5×10 17 atoms / cm 3 is controlled to have a region less than or equal to

[0275] Also, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced In order not to reduce the crystallinity of the oxide semiconductor layer, for example, the silicon concentration is 1×1 0 19 atoms / cm 3 less than, preferably 5×10 18 atoms / cm 3 less than, further preferably 1×10 18 atoms / cm 3 is controlled to have a region less than Also, the carbon concentration is 1×10 19 atoms / cm3 Less than 5 x 10 18 ato ms / cm 3 less than 1×10 18 atoms / cm 3 The area where Control to have.

[0276] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0277] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating film like a gate insulating film is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel is separated from the gate insulating film. .

[0278] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0279] In the band structures of the oxide semiconductor layers 130a, 130b, and 130c, the energy at the lower end of the conduction band changes continuously. This can also be understood from the fact that the compositions of the oxide semiconductor layers 130a, 130b, and 130c are similar, making it easy for oxygen to diffuse into each other. Therefore, although the oxide semiconductor layers 130a, 130b, and 130c are a laminate of layers with different compositions, they can be said to be physically continuous. In the drawings, the respective interfaces of the laminate are represented by dotted lines. The oxide semiconductor layer 130, which is laminated with a common main component, is fabricated not simply by laminating each layer but by forming a continuous junction (specifically, a U-shaped well structure (U Shape Well) in which the energy at the lower end of the conduction band changes continuously between the layers). That is, the laminate structure is formed such that there are no impurities that form defect energy levels such as trap centers or recombination centers at the interfaces of the respective layers. If impurities are mixed between the laminated oxide semiconductor layers, the continuity of the energy band is lost, and carriers are trapped or recombined at the interfaces and disappear. For example, for the oxide semiconductor layers 130a and 130c, In-Ga-Zn oxides such as In:Ga:Zn = 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1: 9:6 (atomic ratio) can be used. Also, for the oxide semiconductor layer 130b, In-Ga-Zn oxides such as In:Ga:Zn = 1:1:1, 2:1:3, 5:5:6, or 3:1:2 (atomic ratio) can be used.

[0280] The oxide semiconductor layers 130a, 130b, and 130c are a laminate of layers with different compositions, but they can be said to be physically continuous. In the drawings, the respective interfaces of the laminate are represented by dotted lines. The oxide semiconductor layer 130, which is laminated with a common main component, is fabricated not simply by laminating each layer but by forming a continuous junction (specifically, a U-shaped well structure (U Shape Well) in which the energy at the lower end of the conduction band changes continuously between the layers). That is, the laminate structure is formed such that there are no impurities that form defect energy levels such as trap centers or recombination centers at the interfaces of the respective layers. If impurities are mixed between the laminated oxide semiconductor layers, the continuity of the energy band is lost, and carriers are trapped or recombined at the interfaces and disappear. For example, for the oxide semiconductor layers 130a and 130c, In-Ga-Zn oxides such as In:Ga:Zn = 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1: 9:6 (atomic ratio) can be used. Also, for the oxide semiconductor layer 130b, In-Ga-Zn oxides such as In:Ga:Zn = 1:1:1, 2:1:3, 5:5:6, or 3:1:2 (atomic ratio) can be used.

[0281] 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio), etc. of In-Ga-Zn oxides can be used. Also, for the oxide semiconductor layer 130b, In-Ga-Zn oxides such as In:Ga:Zn = 1:1:1, 2:1:3, 5:5:6, or 3:1:2 (atomic ratio), etc. of In-Ga-Zn oxides can be used. For example, for the oxide semiconductor layers 130a and 130c, In-Ga-Zn oxides such as In:Ga:Zn = 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1: When the above oxides are used as sputtering targets for film formation, the oxide semiconductor film formed is The atomic ratio of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c must be They will not necessarily be identical, and there will be a difference of about ±20%.

[0282] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well. In the transistor using the semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. In addition, the oxide semiconductor layer 130 has a conduction band minimum that changes continuously. The channel formed in this way can also be called a U-shaped well. can also be called a buried channel.

[0283] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0284] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0285] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable to include a crystal part. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor. Also, the crystal oriented along the c-axis is resistant to distortion and can improve the reliability of a semiconductor device using a flexible substrate. For the conductive layer 140 acting as a source electrode layer and the conductive layer 150 acting as a drain electrode layer, for example, a single layer or a laminate of a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and an alloy of the metal material can be used. Typically, it is more preferable to use W with a high melting point, such as Ti which easily binds to oxygen and those with a relatively high subsequent process temperature. Also, a laminate of an alloy such as low-resistance Cu or Cu-Mn and the above material may be used. In the transistors 105, 106, 111, and 112, for example, W can be used for the conductive layer 141 and the conductive layer 151, and a laminate film of Ti and Al can be used for the conductive layer 142 and the conductive layer 152.

[0286] The above materials have the property of extracting oxygen from the oxide semiconductor film. Therefore, in a part of the region of the oxide semiconductor layer in contact with the above materials, oxygen in the oxide semiconductor film desorbs, forming oxygen vacancies. The hydrogen slightly contained in the film combines with the oxygen vacancies, significantly n-type doping the region. Therefore, the n-type doped region can act as a source or a drain of the transistor. When using W for the conductive layer 140 and the conductive layer 150, nitrogen doping can also be performed. It is preferable to use a single layer or a laminate of a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and an alloy of the metal material. Typically, it is more preferable to use W with a high melting point, such as Ti which easily binds to oxygen and those with a relatively high subsequent process temperature. Also, a laminate of an alloy such as low-resistance Cu or Cu-Mn and the above material may be used. In the transistors 105, 106, 111, and 112, for example, W can be used for the conductive layer 141 and the conductive layer 151, and a laminate film of Ti and Al can be used for the conductive layer 142 and the conductive layer 152. For the conductive layer 140 and the conductive layer 150, for example, a single layer or a laminate of a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and an alloy of the metal material can be used. Typically, it is more preferable to use W with a high melting point, such as Ti which easily binds to oxygen and those with a relatively high subsequent process temperature. Also, a laminate of an alloy such as low-resistance Cu or Cu-Mn and the above material may be used.

[0287] The above materials have the property of extracting oxygen from the oxide semiconductor film. Therefore, in a part of the region of the oxide semiconductor layer in contact with the above materials, oxygen in the oxide semiconductor film desorbs, forming oxygen vacancies. The hydrogen slightly contained in the film combines with the oxygen vacancies, significantly n-type doping the region. Therefore, the n-type doped region can act as a source or a drain of the transistor. When using W for the conductive layer 140 and the conductive layer 150, nitrogen doping can also be performed. It is preferable to include a crystal part. In particular, by using a crystal oriented along the c-axis, stable electrical characteristics can be imparted to the transistor.

[0288] Also, the crystal oriented along the c-axis is resistant to distortion and can improve the reliability of a semiconductor device using a flexible substrate. By doping with nitrogen, the oxygen-pulling property can be moderately weakened, resulting in n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding to the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the For the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0289] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. etc. may be contained as impurities.

[0290] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0291] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. Therefore, the thickness of the insulating layer 160 can be made larger than that of the case where silicon oxide is used. Therefore, the leakage current due to the tunnel current can be reduced. A transistor with a small current can be realized. Furthermore, hafnium oxide having a crystal structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with a small off-current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited thereto.

[0292] In addition, it is preferable to use a film with a small nitrogen oxide emission amount for the insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130. When an insulating layer with a large nitrogen oxide emission amount is in contact with an oxide semiconductor, the density of energy levels due to nitrogen oxides may increase. For the insulating layer 120 and the insulating layer 160, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film with a small nitrogen oxide emission amount can be used. When an insulating layer with a large nitrogen oxide emission amount is in contact with an oxide semiconductor, the density of energy levels due to nitrogen oxides may increase. For the insulating layer 120 and the insulating layer 160, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film with a small nitrogen oxide emission amount can be used. For the insulating layer 120 and the insulating layer 160, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film with a small nitrogen oxide emission amount can be used.

[0293] A silicon oxynitride film with a small nitrogen oxide emission amount is a film in which the ammonia emission amount is larger than the nitrogen oxide emission amount in the TDS method. Typically, the ammonia emission amount is 1×10 18 18 pieces / cm 3 or more and 5×10 19 pieces / cm 3 or less. The ammonia emission amount is the emission amount obtained by heat treatment at a film surface temperature of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. by heat treatment at a film surface temperature of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower.

[0294] By using the above oxide insulating layer as the insulating layer 120 and the insulating layer 160, it is possible to reduce the shift of the threshold voltage of the transistor and reduce the variation in the electrical characteristics of the transistor. By using the above oxide insulating layer as the insulating layer 120 and the insulating layer 160, it is possible to reduce the shift of the threshold voltage of the transistor and reduce the variation in the electrical characteristics of the transistor. in the electrical characteristics of the transistor can be reduced.

[0295] As the conductive layer 170 acting as the gate electrode layer, for example, conductive films such as Al, Ti, Cr, Co, Ni , Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W can be used. Also, alloys of the above materials or conductive nitrides of the above materials may be used. Also, a laminate of a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials may be used. Typically, a laminate of tungsten, a laminate of tungsten and titanium nitride, a laminate of tungsten and tantalum nitride, etc. can be used. Also, low-resistance Cu or an alloy such as Cu-Mn, or a laminate of the above materials and an alloy such as Cu or Cu-Mn may be used. In this embodiment, the conductive layer 170 is formed by using tantalum nitride for the conductive layer 171 and tungsten for the conductive layer 172.

[0296] As the insulating layer 175, a silicon nitride film containing hydrogen, an aluminum nitride film, or the like can be used. In the transistors 103, 104, 106, 109, 110, and 112 shown in Embodiment 4, by using an insulating film containing hydrogen as the insulating layer 175, a part of the oxide semiconductor layer can be made n-type. Also, the nitride insulating film also acts as a blocking film for moisture and the like, and can improve the reliability of the transistor.

[0297] Also, an aluminum oxide film can be used as the insulating layer 175. In particular, in the transistors 101, 102, 105, 107, 108, and 111 shown in Embodiment 4, an aluminum oxide film is used for the insulating layer 175. ​​​​​​​​​It is preferable to use an aluminum film. The aluminum oxide film has a high blocking effect that prevents the film from permeating both impurities such as hydrogen and moisture , and oxygen. Therefore, the aluminum oxide film can prevent impurities such as hydrogen and moisture from mixing into the oxide semiconductor layer 130 during and after the manufacturing process of the transistor, prevent oxygen from being released from the oxide semiconductor layer, and prevent unnecessary release of oxygen from the insulating layer 1 . It is suitable to be used as a protective film having the effect of preventing oxygen from being released from 20. In addition, the oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer . . . .

[0298] Also, it is preferable that an insulating layer 180 is formed on the insulating layer 175. The insulating layer may use an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide, and tantalum oxide. Further, the insulating layer may be a laminate of the above materials. . .

[0299] Here, it is preferable that the insulating layer 180 has more oxygen than the stoichiometric composition, similar to the insulating layer 120. Since the oxygen released from the insulating layer 180 can be diffused through the insulating layer 160 into the channel formation region of the oxide semiconductor layer 130, oxygen can fill the oxygen deficiency formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained. . . .

[0300] To highly integrate a semiconductor device, miniaturization of the transistor is essential. On the other hand, it is known that the electrical characteristics of the transistor deteriorate due to miniaturization of the transistor. Especially, the channel width . When it is miniaturized, the on-current decreases.

[0301] In the transistors 107 to 112 according to one embodiment of the present invention, an oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b in which a channel is formed, and the channel forming layer and the gate insulating film are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel forming layer and the gate insulating film can be suppressed, and the on-current of the transistor can be increased.

[0302] Further, in the transistor according to one embodiment of the present invention, as described above, a gate electrode layer (conductive layer 170) is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 130. Therefore, in addition to the gate electric field from the direction perpendicular to the upper surface with respect to the oxide semiconductor layer 130, a gate electric field from the direction perpendicular to the side surface is applied. That is, a gate electric field is applied to the entire channel forming layer, and the effective channel width is expanded. Therefore, the on-current can be further increased.

[0303] Further, in the transistor in which the oxide semiconductor layer 130 according to one embodiment of the present invention has two or three layers, by forming the oxide semiconductor layer 130b in which a channel is formed on the oxide semiconductor layer 130a, it has the effect of making it difficult to form interface levels. Further, in the transistor in which the oxide semiconductor layer 130 according to one embodiment of the present invention has three layers, by making the oxide semiconductor layer 130b the layer located in the middle of the three-layer structure, it also has the effect of eliminating the influence of impurity mixing from above and below. Therefore, in addition to the improvement of the on-current of the transistor described above, stabilization of the threshold voltage and reduction of the S value (subthreshold value) can be achieved. Therefore, the gate ​ The current when the voltage VG is 0 V can be reduced, and the power consumption can be decreased. Also , since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved . Also, the transistor according to one aspect of the present invention is suitable for forming a highly integrated semiconductor device because deterioration of electrical characteristics due to miniaturization can be suppressed .

[0304] Note that various films such as the metal film, semiconductor film, and inorganic insulating film described in this embodiment can typically be formed by sputtering or plasma CVD, but other methods, for example, thermal CVD, may be used. Examples of thermal CVD include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Atomic Layer Deposition). rganic Chemical Vapor Deposition) and ALD (A tomic Layer Deposition).

[0305] Since thermal CVD is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage .

[0306] Also, in thermal CVD, the source gas and the oxidant are simultaneously introduced into the chamber, the chamber is set to atmospheric pressure or reduced pressure, and they are reacted near or on the substrate to be deposited on the substrate to form a film . Alternatively, film formation may be performed

[0307] In ALD, the chamber is set to atmospheric pressure or reduced pressure, the source gas for reaction is introduced into the chamber and reacted, and this is repeated to form a film. An inert gas (argon or nitrogen, etc.) may be introduced as a carrier gas together with the source gas . For example, two or more types of source gases may be supplied to the chamber in sequence. At that time, the plurality of types of source gases do not mix . . After the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Or, instead of introducing the inert gas, the first source gas may be discharged by evacuation and then the second source gas may be introduced. The first source gas adsorbs and reacts on the surface of the substrate to form the first layer, and then the second source gas introduced later adsorbs and reacts, and the second layer is laminated on the first layer to form a thin film. By repeating a plurality of times while controlling this gas introduction sequence until a desired thickness is achieved, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions of gas introduction, precise film thickness adjustment is possible, which is suitable for fabricating fine FETs.

[0308] Thermal CVD methods such as MOCVD and ALD can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. It is not limited to these combinations, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. For example, when forming a hafnium oxide film by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor such as hafnium alkoxide, tetrakis(dimethylamido)hafnium (TDMAH, Hf[N(CH3)2]4), or tetrakis(ethylmethylamido)hafnium

[0309] is used. (Hf[N(CH3)2]4) or tetrakis(ethylmethylamido)hafnium (Hf[N(CH3)2]4) or tetrakis(ethylmethylamido)hafnium )A raw material gas obtained by vaporizing hafnium amide such as hafnium, and two types of gases, ozone ( O3), are used as the oxidizing agent.

[0310] For example, when forming an aluminum oxide film using a film forming apparatus that utilizes ALD, a liquid containing a solvent and an aluminum precursor (such as trimethylaluminum (TMA, Al(CH3)3 )) is vaporized to obtain a raw material gas, and two types of gases, H2O as the oxidizing agent, are used. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There are others.

[0311] For example, when forming a silicon oxide film using a film forming apparatus that utilizes ALD, hexachloro disilane is adsorbed on the film-forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed substance.

[0312] For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially introduced to form an initial tungsten film, and then WF6 gas and H 2 gas are sequentially introduced to form a tungsten film. Instead of B2H6 gas, SiH4 gas may be used.

[0313] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially introduced to form an In-O layer and then Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further then Zn(CH3)2 gas and O3 gas are sequentially introduced to form a ZnO layer. Note that this The order of these layers is not limited to this example. Using these gases, a mixed compound layer such as an In-Ga-O layer, an In-Zn -O layer, or a Ga-Zn-O layer may be formed. Note that instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. The structure shown in this embodiment can be used in appropriate combination with the structure shown in other embodiments.

[0314]

[0315] (Embodiment 6) Hereinafter, the structure of an oxide semiconductor film that can be used in one aspect of the present invention will be described.

[0316] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0317] In this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

[0318] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crys talline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film , a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0319] First, the CAAC-OS film will be described.

[0320] The CAAC-OS film is one of the oxide semiconductor films having a plurality of c-axis oriented crystal parts.

[0321] By using a transmission electron microscope (TEM: Transmission Electron Micro scope), a plurality of crystal parts can be confirmed by observing a composite analysis image of a bright-field image and a diffraction pattern of the CAAC-OS film ( Also referred to as a high-resolution TEM image.). On the other hand, even with a high-resolution TEM image, it is not possible to confirm a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary). Therefore, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries.

[0322] When observing a high-resolution TEM image of a cross section of the CAAC-OS film from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film, and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film.

[0323] On the other hand, when observing a high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0324] When performing a structural analysis on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, in the analysis of the CAAC-OS film having a crystal of InGaZnO4 by the out-of-plane method, a peak appears at a diffraction angle (2θ) near 31°. ​ may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal Therefore, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface

[0325] In addition, in the analysis of the CAAC-OS film having an InGaZnO4 crystal by the out-of-plane method in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36° The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals without c-axis orientation The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°

[0326] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, transition metal elements, etc. In particular, elements with a stronger binding force to oxygen than the metal elements constituting the oxide semiconductor film, such as silicon will disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film, resulting in a decrease in crystallinity Heavy metals such as iron and nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and result in a decrease in crystallinity. In addition, impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources

[0327] In addition, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiency in the oxide semiconductor film will become a carrier trap or capture hydrogen​​​​ may serve as a carrier generation source.

[0328] A state in which the impurity concentration is low and the density of defect levels is low (with few oxygen deficiencies) is referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have electrical characteristics ( also referred to as normally-on.) in which the threshold voltage becomes negative. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier traps of the oxide semiconductor film takes a long time to be released and may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0329] Also, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0330] Next, the microcrystalline oxide semiconductor film will be described.

[0331] In a high-resolution TEM image, the microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where distinct crystal parts cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film have a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. This is often the case. In particular, fine particles in the range of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less An oxide semiconductor film having nanocrystals (nc: nanocrystal) that are crystals is referred to as an nc -OS (nanocrystalline Oxide Semiconductor) film. Also, in a high-resolution TEM image, for example, grain boundaries may not be clearly identified in the nc-OS film.

[0332] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the out-of-plane method analysis. Also, when performing electron diffraction (also referred to as limited-field electron diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing nano-beam electron diffraction on the nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. Also, when performing nano-beam electron diffraction on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Also, when performing nano-beam electron diffraction on the nc-OS film, a plurality of spots may be observed within the ring-shaped region.

[0333] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However, the nc-OS film does not show regularity in crystal orientation between different crystal parts. Therefore, the nc-O S film has a higher density of defect levels than the CAAC-OS film.

[0334] Next, the amorphous oxide semiconductor film will be described.

[0335] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal parts. An oxide semiconductor film having an amorphous state like quartz is an example. The amorphous oxide semiconductor film cannot confirm crystal parts in a high-resolution TEM image.

[0336] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the analysis by the out-of-p

[0337] lane method. Also, when performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. When performing electron diffraction on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when performing nano-beam electron diffraction on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. observed.

[0338] Note that the oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (a-like OS: amorphous-like Oxide Semi conductor) film. conductor) film.

[0339] Void (also referred to as void) may be observed in the a-like OS film in a high-resolution TEM image. In addition, in a high-resolution TEM image, there are regions where the crystalline part can be clearly confirmed and regions where the crystalline part cannot be confirmed. The a-like OS film may crystallize and crystal growth may be observed by a small amount of electron irradiation to the extent observable by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization by a small amount of electron irradiation to the extent observable by TEM is hardly observed.

[0340] Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO4 has a layered structure and has two Ga-Zn-O layers between In-O layers. The unit cell of the crystal of InGaZnO4 has three In-O layers and six Ga-Zn-O layers, and a total of nine layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, where the distance between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe corresponds to the a-b plane of the crystal of InGaZnO4.

[0341] Note that the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[0342] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments. ​ (Embodiment 7)

[0343] The imaging device according to one aspect of the present invention and the semiconductor device including the imaging device can be used in display devices, personal computers, and image playback devices equipped with a recording medium (typically a device having a function of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, as electronic devices in which the imaging device according to one aspect of the present invention and the semiconductor device including the imaging device can be used, there are mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 40. personal computers, and image playback devices equipped with a recording medium (typically a device having a function of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying its image). l Versatile Disc and the like, and can display the image. play). In addition, as electronic devices in which the imaging device according to one aspect of the present invention and the semiconductor device including the imaging device can be used, there are mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, digital still cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs) cash dispensers, vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 40. cash dispensers, vending machines, and the like. Specific examples of these electronic devices are shown in FIG. 40.

[0344] FIG. 40(A) is a portable game machine, which has a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, a camera 909, and the like. Note that the portable game machine shown in FIG. 40(A) has two display units 903 and a display unit 904, but the number of display units of the portable game machine is not limited to this. The imaging device according to one aspect of the present invention can be used in the camera 909. to this. The imaging device according to one aspect of the present invention can be used in the camera 909.

[0345] FIG. 40(B) is a portable data terminal, which has a housing 911, a display unit 912, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. The imaging device according to one aspect of the present invention can be used in the camera 919.

[0346] Figure 40(C) is a digital camera, which has a housing 921, a shutter button 922, a microphone 9 23, a light emitting part 927, a lens 925, etc. An imaging device according to one aspect of the present invention can be provided at the position that becomes the focus of the lens 925.

[0347] Figure 40(D) is a wristwatch type information terminal, which has a housing 931, a display part 932, a list band 9 33, a camera 939, etc. The display part 932 may be a touch panel. The imaging device according to one aspect of the present invention can be used in the camera 939.

[0348] Figure 40(E) is a video camera, which has a first housing 941, a second housing 942, a display part 943, operation keys 944, a lens 945, a connection part 946, etc. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display part 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by the connection part 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The video on the display part 943 may be switched according to the angle between the first housing 941 and the second housing 94 2 at the connection part 946. An imaging device according to one aspect of the present invention can be provided at the position that becomes the focus of the lens 945.

[0349] Figure 40(F) is a mobile phone, which has a display part 952, a microphone 957, a speaker 954, a camera 959, input / output terminals 956, operation buttons 955, etc. on the housing 951. The imaging device according to one aspect of the present invention can be used in the camera 959. ​​​

[0350] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. 。

Description of Reference Numerals

[0351] 40 Silicon substrate 41 Insulating layer 41a Insulating layer 41b Insulating layer 44 Insulating layer 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 57 Transistor 58 Active layer 59 Capacitor element 60 Photoelectric conversion element 61 Photoelectric conversion layer 62 Transparent conductive layer 63 Semiconductor layer 64 Semiconductor layer 65 Semiconductor layer 66 Electrode 66a Conductive layer 66b Conductive layer 67 Partition wall 71 Wiring 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 77 Wiring 77a Conductive layer 77b Conductive layer 78 Wiring 80 Insulating layer 81 Conductor 91 Circuit 92 Circuit 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 115 Substrate 120 Insulating Layer 130 Oxide Semiconductor Layer 130a Oxide Semiconductor Layer 130b Oxide Semiconductor Layer 130c Oxide Semiconductor Layer 140 Conductive Layer 141 Conductive Layer 142 Conductive Layer 150 Conductive Layer 151 Conductive Layer 152 Conductive Layer 160 Insulating Layer 170 Conductive Layer 171 Conductive Layer 172 Conductive Layer 173 Conductive Layer 175 Insulating Layer 180 Insulating Layer 231 Region 232 Region 233 Region 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 317 Wiring 331 Region 332 Region 333 Region 334 Region 335 Region 501 Signal 502 Signal 503 Signal 504 Signal 505 Signal 506 Signal 507 Signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 613 period 621 period 622 period 623 period 631 period 701 signal 702 signal 703 signal 704 signal 705 signal 901 housing 902 housing 903 display unit 904 display unit 905 microphone 906 speaker 907 operation key 908 stylus 909 camera 911 housing 912 display unit 919 camera 921 housing 922 shutter button 923 microphone 925 lens 927 light emitting unit 931 housing 932 display unit 933 list band 939 camera 941 housing 942 housing 943 display unit 944 operation key 945 lens 946 connection part 951 housing 952 display unit 954 speaker 955 button 956 input / output terminal 957 Microphone 959 Camera 1100 Layer 1200 Layer 1300 Layer 1400 Layer 1500 Layer 1600 Layer 2500 Insulating Layer 2510 Light-Shielding Layer 2520 Organic Resin Layer 2530 Color Filter 2530a Color Filter 2530b Color Filter 2530c Color Filter 2540 Microlens Array 2550 Optical Conversion Layer 2560 Insulating Layer

Claims

1. A signal processing circuit having a first transistor with an active region on a silicon substrate, an anode wiring, a second transistor, a third transistor, a first plug, a second plug, a third plug, a conductive layer, a photodiode, an insulating layer, a metal layer, a color filter, and a microlens array, which are disposed on the light-receiving surface side of the first transistor, wherein the microlens array is disposed on the light-receiving surface side of the color filter, the insulating layer is provided on the light-receiving surface side of the first plug and covers at least a part of the side surface of the photodiode, the photodiode has an anode on the light-receiving surface side, the anode of the photodiode is disposed on the light-receiving surface side of the second transistor, the third transistor, and the first plug, the anode of the photodiode is electrically connected to the anode wiring via the first plug, the metal layer is disposed on the light-receiving surface side of the anode of the photodiode and overlaps with the first plug, the second transistor is a transfer transistor, the third transistor is an amplification transistor, the film thickness of the gate insulating film of the second transistor is larger than the film thickness of the gate insulating film of the third transistor, the source or drain of the second transistor is electrically connected to the gate of the third transistor via the second plug, the conductive layer, and the third plug, The imaging device, wherein the insulating layer is a silicon oxide film or a silicon oxynitride film.

2. A signal processing circuit having a first transistor with an active region on a silicon substrate, an anode wiring, a second transistor, a third transistor, a first plug, a second plug, a third plug, a conductive layer, a photodiode, an insulating layer, a metal layer, a color filter, and a microlens array, which are disposed on the light-receiving surface side of the first transistor, wherein the microlens array is disposed on the light-receiving surface side of the color filter, the insulating layer is provided on the light-receiving surface side of the first plug and covers at least a part of the side surface of the photodiode, the photodiode has an anode on the light-receiving surface side, the anode of the photodiode is disposed on the light-receiving surface side of the second transistor, the third transistor, and the first plug, The anode of the photodiode is electrically connected to the anode wiring via the first plug. The metal layer is disposed on the light-receiving surface side of the anode of the photodiode and overlaps with the first plug. The second transistor is a transfer transistor. The third transistor is an amplification transistor. The film thickness of the gate insulating film of the second transistor is larger than the film thickness of the gate insulating film of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the third transistor via the second plug, the conductive layer, and the third plug. The insulating layer is a silicon oxide film or a silicon oxynitride film. The metal layer has tungsten, an imaging device. A signal processing circuit having a first transistor having an active region on a silicon substrate; An anode wiring, a second transistor, a third transistor, a first plug, a second plug, a third plug, a conductive layer, a photodiode, an insulating layer, a metal layer, a color filter, and a microlens array disposed on the light-receiving surface side of the first transistor; The microlens array is disposed on the light-receiving surface side of the color filter. The insulating layer is provided on the light-receiving surface side of the first plug and covers at least a part of the side surface of the photodiode. The photodiode has an anode on the light-receiving surface side. The anode of the photodiode is disposed on the light-receiving surface side of the second transistor, the third transistor, and the first plug. The anode of the photodiode is electrically connected to the anode wiring via the first plug. The metal layer is disposed on the light-receiving surface side of the anode of the photodiode and overlaps with the first plug. The second transistor is a reset transistor. The third transistor is an amplification transistor. The film thickness of the gate insulating film of the second transistor is larger than the film thickness of the gate insulating film of the third transistor. The source or drain of the second transistor is electrically connected to the gate of the third transistor via the second plug, the conductive layer, and the third plug. The insulating layer is a silicon oxide film or a silicon oxynitride film, an imaging device. ​ ​ A signal processing circuit having a first transistor with an active region on a silicon substrate, an anode wiring, a second transistor, a third transistor, a first plug, a second plug, a third plug, a conductive layer, a photodiode, an insulating layer, a metal layer, a color filter, and a microlens array, which are arranged on the light-receiving surface side of the first transistor, the microlens array is arranged on the light-receiving surface side of the color filter, the insulating layer is provided on the light-receiving surface side of the first plug and covers at least a part of the side surface of the photodiode, the photodiode has an anode on the light-receiving surface side, the anode of the photodiode is arranged on the light-receiving surface side of the second transistor, the third transistor, and the first plug, the anode of the photodiode is electrically connected to the anode wiring through the first plug, the metal layer is arranged on the light-receiving surface side of the anode of the photodiode and overlaps with the first plug, the second transistor is a reset transistor, the third transistor is an amplification transistor, the film thickness of the gate insulating film of the second transistor is larger than the film thickness of the gate insulating film of the third transistor, the source or drain of the second transistor is electrically connected to the gate of the third transistor through the second plug, the conductive layer, and the third plug, the insulating layer is a silicon oxide film or a silicon oxynitride film, the metal layer has tungsten, an imaging device.

5. In any one of Claims 1 to 4, having a capacitive element, the gate of the third transistor is electrically connected to one electrode of the capacitive element, an imaging device.

6. An imaging device according to any one of Claims 1 to 5, an electronic device having a display unit.

Images