Quantum computer with error reduction of elongation coefficient enabled

Abstract

Techniques related to error mitigation for quantum computers are provided. For example, one or more embodiments described herein may include a system that may include a memory capable of storing computer-executable components. The system may also include a processor operatively coupled to the memory and capable of executing the computer-executable components stored in the memory. The computer-executable components may include an error mitigation component that interpolates gate parameters associated with a target stretch factor from a reference model, the reference model including reference gate parameters for a quantum gate calibrated with a plurality of reference stretch factors.

Description

Technical Field

[0001] The disclosure of the subject matter relates to the use of stretch factors for performing error mitigation in quantum computing, and more particularly to interpolating quantum gate parameters associated with a target stretch factor from a reference model calibrated with a plurality of reference stretch factors.

Background Art

[0002] Quantum computers produce noise that degrades the accuracy of quantum operations. Error mitigation techniques can account for the noise and improve the results of quantum computers. In conventional error mitigation techniques, quantum operations are executed several times on a quantum circuit. In one or more of the executions of the quantum operation, the duration of the gates included in the quantum circuit can be stretched by a specific factor known as a stretch factor. Stretching the gate duration can introduce additional noise into the execution of the quantum operation. Thereby, the quantum computer can generate a plurality of result data sets, each of which includes an amount of each noise affected by the adopted stretch factor. Next, the error-mitigated result can be extrapolated from the plurality of result data sets. However, for each stretch factor utilized in the execution of the quantum operation, a new gate parameter is defined and must be calibrated. Calibrating the gate parameters for each stretch factor requires the scientist to access the hardware of the quantum computer and can be significantly time-consuming. Therefore, conventional error mitigation techniques are limited by calibration requirements.

[0003] Other conventional error reduction techniques are implemented by replacing all two-qubit quantum gates in a quantum circuit with multiple copies of themselves. For example, each two-qubit gate in a quantum circuit can be replaced with an odd number of two-qubit gates. However, these techniques may ignore single-qubit gates and may be inappropriate for long stretch factors that may correspond to quantum circuits approaching coherence limits. Additionally, a further constraint on conventional error reduction techniques is that two sequential applications of a two-qubit gate must create an identity operation. SUMMARY OF THE INVENTION

[0004] The following presents a summary to enable a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements nor to precisely delineate the scope of particular embodiments or the scope of the claims. The sole purpose of this summary is to present concepts in a simplified form as a prelude to a more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, or computer program product, or a combination thereof, that can facilitate error reduction of the stretch factor of a quantum operation is described.

[0005] According to one embodiment, a system is provided. The system can include a memory capable of storing computer-executable components. The system can also include a processor operably coupled to the memory and capable of executing the computer-executable components stored in the memory. The computer-executable components can include an error reduction component capable of interpolating gate parameters associated with a target stretch factor from a reference model, where the reference model can include reference gate parameters of quantum gates calibrated at a plurality of reference stretch factors. An advantage of such a system can be that the reference model can be employed to reduce calibration overhead.

[0006] In some examples, the system can include a model component capable of defining a plurality of reference stretch factors by determining the number of reference stretch factors within a stretch factor interval based on at least one of a per-gate error determination and a gate parameter determination. An advantage of such a system can be that the reference model can include reference stretch factors associated with a dynamic range of calibration of quantum gates.

[0007] According to an embodiment, a system is provided. The system can include a memory capable of storing computer-executable components. The system can also include a processor operably coupled to the memory and capable of executing the computer-executable components stored in the memory. The computer-executable components can include a recommendation component capable of identifying a stretch factor for error reduction of a quantum circuit based on the number of gates and the number of qubits of the quantum circuit. An advantage of such a system can be that the system can be an available choice of a stretch factor predicted to be most efficient in facilitating Richardson error mitigation.

[0008] In some examples, the recommended component can compare the number of gates and qubits of a quantum circuit with a reference table that includes a range of scaling factors associated with a defined combination of the number of gates and qubits. The advantage of such a system can be a recommendation of a scaling factor based on past executions of similar quantum circuits.

[0009] According to an embodiment, a computer-implemented method is provided. The computer-implemented method can include interpolating gate parameters associated with a target scaling factor from a reference model by a system operably coupled to a processor, where the reference model includes reference gate parameters of quantum gates calibrated at a plurality of reference scaling factors. The advantage of such a computer-implemented method can be a determination of gate parameters for a target scaling factor without calibrating the quantum gates at the target scaling factor.

[0010] In some examples, the computer-implemented method can include determining, by the system, the number of reference scaling factors included within a scaling factor interval based on at least one of a determination of an error per gate and a determination of a gate parameter. The advantage of such a computer-implemented method can be a generation of a reference model highly calibrated with reference scaling factors associated with an increase in changes in the operation of the quantum gates.

[0011] According to another embodiment, a computer-implemented method is provided. The computer-implemented method can include recommending, by a system operably coupled to a processor, a scaling factor for error mitigation of a quantum circuit based on the number of gates and qubits of the quantum circuit. The advantage of such a method can be the usability for a user to effectively execute an error mitigation protocol using a desired scaling factor.

[0012] In some examples, the computer-implemented method can further include the system performing a randomized benchmarking operation to determine a maximum extension factor associated with a set of quantum gates. The computer-implemented method can also further include the system monitoring the usability of one or more quantum gates from the set of quantum gates. The advantage of such a method is that the extension factor can be adjusted, or recommended, or both, to match the capabilities of the quantum hardware (e.g., the recent operating capabilities of the quantum gates).

[0013] According to an embodiment, a computer program product for error mitigation of a quantum computer is provided. The computer program product can include a computer-readable storage medium having program instructions embodied therein. The program instructions are executable by a processor and can cause the processor to generate a range of extension factors associated with quantum gates at a plurality of reference extension factors. The program instructions can also cause the processor to receive an extension factor from the range of extension factors. Further, the program instructions can cause the processor to interpolate gate parameters associated with the extension factor based on the plurality of reference extension factors. The advantage of such a computer program product can be a reduction in the calibration overhead of the quantum computer.

[0014] In some examples, the program instructions can further cause the processor to identify a recommended extension factor from the range of extension factors based on the number of gates and the number of qubits of a quantum circuit including the quantum gates. The advantage of such a computer program product can be an improvement in the applicability of error mitigation.

[0015] This patent file or application file includes at least one drawing created in color. Copies of this patent or patent application publication that include color drawings are provided by the United States Patent and Trademark Office upon request and payment of the required fees.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0017] The following detailed description is merely exemplary in nature and is not intended to limit the embodiments, or the application or uses of the embodiments, either in whole or in part. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding "Background" or "Summary of the Invention" sections, or the "Detailed Description of the Invention" section.

[0018] Here, one or more embodiments will be described with reference to the drawings, and throughout the drawings, like reference numerals are used to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various instances.

[0019] Assuming the problems associated with other implementations of error mitigation in quantum computing, the present disclosure can be implemented to produce solutions to one or more of these problems by interpolating quantum gate parameters from one or more reference models calibrated with respect to a reference stretch factor. One or more embodiments described herein can advantageously perform error mitigation with respect to the intervals of the stretch factor with a minimal calibration overhead. The various embodiments described herein can enable the adoption of one or more desired stretch factors from a specific range characterized by a plurality of reference stretch factors.

[0020] The various embodiments of the present invention can be directed to a computer processing system, a computer-implemented method, an apparatus, or a computer program product, or a combination thereof, that facilitates efficient, effective, and autonomous calibration of stretched pulses and interpolation of gate parameters (e.g., without direct human guidance). For example, one or more embodiments described herein can calibrate a plurality of quantum gates with respect to a reference stretch factor and generate a reference model. Further, the various embodiments can interpolate gate parameters with respect to a desired stretch factor from the reference model. Further, one or more embodiments described herein can recommend one or more stretch factors for use in a particular quantum circuit. Further, one or more embodiments can adjust one or more selected stretch factors to enhance compatibility with the hardware of a particular quantum computer.

[0021] A computer processing system, a computer-implemented method, an apparatus, or a computer program product, or a combination thereof, is inherently highly technical and not abstract and employs hardware or software or both to solve problems (e.g., error mitigation in quantum computing) that cannot be performed as a series of mental activities by a human. For example, one or more individuals cannot generate a reference model for interpolation of stretch factors and error mitigation.

[0022] Also, one or more embodiments described herein can constitute a technical improvement beyond conventional error reduction by interpolating quantum gate parameters from one or more reference models calibrated with a plurality of reference extension coefficients. Further, various embodiments described herein can show a technical improvement beyond conventional error reduction techniques by recommending the extension coefficients to be adopted based on the characteristics of a specific quantum circuit, or the hardware of a specific quantum computer, or both. Further, various embodiments described herein can show a technical improvement beyond conventional error reduction techniques by enabling the selection of one or more extension coefficients within a specific range while minimizing calibration overhead.

[0023] Furthermore, one or more embodiments described herein can have practical applications by reducing errors in one or more quantum operations. For example, various embodiments described herein can interpolate quantum gate parameters from a reference model, thereby enabling the selection of one or more desirable extension coefficients from a specific range without being hindered by the limitations associated with calibrating quantum gates. Further, one or more embodiments described herein can control the recommended components to analyze a specific quantum circuit, or generate one or more recommended extension coefficients adopted for error reduction, or both. Thereby, one or more embodiments can enable a user to adopt an extension coefficient that is suitable for a desired quantum circuit.

[0024] FIG. 1 shows a block diagram of an exemplary non-limiting system 100 that can facilitate error mitigation in quantum computing. Repetition of the description of similar elements employed in other embodiments described herein is omitted for brevity. Aspects of the systems (e.g., system 100, etc.), apparatus, or processes in various embodiments of the present invention can comprise one or more machine-executable components embodied within one or more machines (e.g., embodied within one or more computer-readable media associated with one or more machines). Such components, when executed by one or more machines (e.g., a computer, a computing device, or a virtual machine, or a combination thereof, etc.), can cause the machine to perform the described operations.

[0025] As shown in FIG. 1, system 100 can comprise one or more servers 102, one or more networks 104, an input device 106, or a quantum computer 108, or a combination thereof. Server 102 can comprise an error mitigation component 110. Error mitigation component 110 can further comprise a communication component 112 or a model component 114, or both. Also, server 102 can comprise at least one memory 116 or can be otherwise associated with at least one memory 116. Server 102 can further comprise a system bus 118 that can couple to various components such as, but not limited to, error mitigation component 110 and associated components, memory 116, or processor 120, or a combination thereof. Although server 102 is shown in FIG. 1, in other embodiments, multiple devices of various types can be associated with or can comprise the features shown in FIG. 1. Further, server 102 can communicate with one or more cloud computing environments.

[0026] One or more networks 104 can include, but are not limited to, wired and wireless networks including cellular networks, wide area networks (WANs) (e.g., the Internet) or local area networks (LANs). For example, server 102 can communicate with one or more input devices 106 and / or quantum computer 108 (and vice versa) using substantially any desired wired or wireless technology, including but not limited to, for example, cellular, WAN, wireless fidelity (Wi-Fi), Wi-Max, WLAN, or Bluetooth technology, or combinations thereof. Further, in the illustrated embodiment, error reduction component 110 can be provided on one or more servers 102, but it should be understood that the architecture of system 100 is not so limited. For example, error reduction component 110 or one or more components of error reduction component 110 can be present on another computer device, such as another server device, or client device, or combinations thereof.

[0027] One or more input devices 106 can include, but are not limited to, one or more computerized devices such as a personal computer, a desktop computer, a laptop computer, a mobile phone (e.g., a smartphone), a computerized tablet (e.g., having a processor), a smart watch, a keyboard, a touch screen, or a mouse, or a combination thereof. One or more input devices 106 can be employed to input one or more quantum circuits or target extension coefficients or both into system 100, thereby sharing the aforementioned data with server 102 (e.g., via a direct connection, or via one or more networks 104, or both). For example, one or more input devices 106 can transmit data to communication component 112 (e.g., via a direct connection, or via one or more networks 104, or both). Further, one or more input devices 106 can include one or more displays capable of presenting to a user one or more outputs generated by system 100. For example, one or more displays can include, but are not limited to, a cathode ray tube display (CRT), a light-emitting diode display (LED), an electroluminescent display (ELD), a plasma display panel (PDP), a liquid crystal display (LCD), or an organic light-emitting diode display (OLED), or a combination thereof.

[0028] In various embodiments, one or more input devices 106 or one or more networks 104 or both can be employed to input one or more settings or commands or both into the system 100. For example, in the various embodiments described herein, one or more input devices 106 can be employed to operate, or manipulate, or perform both the server 102 or associated components or both. Further, one or more input devices 106 can be employed to display one or more outputs (such as, for example, displays, data, or visualizations, or combinations thereof) generated by the server 102 or associated components or both. Further, in one or more embodiments, one or more input devices 106 can be included within, or operably coupled to, a cloud computing environment or both.

[0029] In various embodiments, one or more quantum computers 108 can comprise quantum hardware devices that can utilize the laws of quantum mechanics (such as, for example, superposition or quantum entanglement or both) to facilitate computational processing (while, for example, meeting DiVincenzo's criteria). In one or more embodiments, one or more quantum computers 108 can comprise a quantum data plane, a control processor plane, a control and measurement plane, or qubit technology, or combinations thereof.

[0030] In one or more embodiments, the quantum data plane can include one or more quantum circuits comprising physical qubits, a structure for fixing the positions of the qubits, or support circuitry, or a combination thereof. The support circuitry can, for example, facilitate the measurement of the state of a qubit or execute a gate operation on a qubit (e.g., in the case of a gate-based system), or both. In some embodiments, the support circuitry can comprise a wired network that can enable multiple qubits to communicate information with each other. Further, the wired network can facilitate the transmission of control signals via direct electrical connections or electromagnetic radiation (e.g., optical signals, microwave signals, or low-frequency signals, or a combination thereof), or both. For example, the support circuitry can comprise one or more superconducting resonators operatively coupled to one or more qubits. As described herein, the term "superconducting" can characterize materials that exhibit superconducting properties below a superconducting critical temperature, such as aluminum (e.g., a superconducting critical temperature of 1.2 Kelvin) or niobium (e.g., a superconducting critical temperature of 9.3 Kelvin). Further, those skilled in the art will recognize that other superconducting materials (e.g., hydride superconductors such as lithium hydride / magnesium hydride alloys) can be used in the various embodiments described herein.

[0031] In one or more embodiments, the control processor plane can identify, or trigger, or perform both, a Hamiltonian sequence of the operation or measurement or both of the quantum gates, and this sequence executes a program (provided, for example, by a host processor such as server 102, or one or more input devices 106, or both) to implement a quantum algorithm. For example, the control processor plane can convert the compiled code into commands for the control and measurement planes. In one or more embodiments, the control processor plane can further execute one or more quantum error correction algorithms.

[0032] In one or more embodiments, the control and measurement plane can convert a digital signal generated by the control processor plane that can define the quantum operation to be executed into an analog control signal for performing an operation on one or more qubits in the quantum data plane. Also, the control and measurement plane can convert one or more analog measurement outputs of the qubits in the data plane into classical binary data that can be shared with other components of the system 100 (e.g., via the control processor plane, with, for example, an error mitigation component 110, etc.).

[0033] One of ordinary skill in the art will recognize that various qubit technologies can provide the basis for one or more qubits of one or more quantum computers 108. Two exemplary qubit technologies can include trapped ion qubits or superconducting qubits or both. For example, if the quantum computer 108 utilizes trapped ion qubits, the quantum data plane can include a plurality of ions that function as qubits, and one or more traps that help hold the ions in specific positions. Further, the control and measurement plane can include a laser source or microwave source directed at one or more of the ions to affect the quantum state of the ions, lasers for cooling the ions or enabling measurement of the ions or both, or one or more photon detectors for measuring the state of the ions, or a combination thereof. In another case, a superconducting qubit (e.g., such as a superconducting quantum interference device (SQUID)) can be a lithographically defined electronic circuit that can be cooled to millikelvin temperatures to exhibit quantized energy levels (e.g., due to quantized states of electron charge or magnetic flux). The superconducting qubit can be based on Josephson junctions, such as a transmon qubit. Also, the superconducting qubit can be adapted to microwave control electronics and can be used with gate-based techniques or integrated cryogenic control. Further exemplary qubit technologies can include, but are not limited to, photonic qubits, quantum dot qubits, gate-based neutral atom qubits, semiconductor qubits (e.g., optically gated or electrically gated), or topological qubits, or a combination thereof.

[0034] In various embodiments, one or more quantum computers 108 can comprise one or more quantum gates 122. The one or more quantum gates 122 can operably couple a plurality of qubits of the one or more quantum computers 108. The one or more quantum computers 108 can execute one or more quantum operations by controlling one or more of the quantum gates 122 according to one or more particular quantum circuits. In various embodiments, the one or more quantum gates 122 can be any type of quantum gate 122 where the pulse implementing the gate can be stretched. Exemplary types of gates that can be included within the one or more quantum gates 122 can include, but are not limited to, cross resonance gates, single qubit gates, or multi qubit gates, or combinations thereof.

[0035] In one or more embodiments, the communication component 112 can receive one or more Hamiltonians, quantum circuits, or target stretch factors, or combinations thereof, from one or more input devices 106 (e.g., via a direct electrical connection, or via one or more networks 104, or both) and share that data with various associated components of the error mitigation component 110. Further, the communication component 112 can facilitate sharing of data between the error mitigation component 110 and the one or more quantum computers 108 (e.g., via a direct electrical connection, or via one or more networks 104, or both), or vice versa, or both.

[0036] A time - dependent drive Hamiltonian can be characterized by Equation 1 below. K(t)=Σ α J α (t)P α (1) Here, "Σ α " can represent the sum over index alpha, and "Jα " can represent the time - dependent strength of the interaction associated with "P α ". Further, "P α " is an N - qubit Pauli operator affected by the time - invariant noise "λ", and after evolution under the scaled drive " j " during the time "c

Number

[0037] In various embodiments, model component 114 can reduce calibration overhead associated with implementing various stretch factors by generating one or more reference models, from which gate parameters for a target stretch factor can be interpolated. For example, one or more reference models generated by model component 114 can relate the quantum gate parameters of one or more quantum computers 108 to their effects in unitary time evolution. In various embodiments, model component 114 can generate one or more reference models based on analytical considerations, empirical measurements, or both. Exemplary gate parameters that can be interpolated from one or more reference models can include, but are not limited to, the amplitude of a cross resonance pulse, the phase of a cross resonance pulse, a derivative removal by adiabatic gate (DRAG) value (e.g., the DRAG coefficient of a single qubit pulse), or the amplitude of a single qubit pulse, or a combination thereof.

[0038] For example, the amplitude “Ω” of a cross resonance pulse of duration “T” can be related to a ZX rotation characterized by (e.g., θ ZX = ω ZX characterized by T) by a cubic model according to Equation 2 below.

[0039]

Equation

[0040] One or more reference models can include a plurality of reference stretch factors (cj ∈[c min , c max , it is possible to consider continuous intervals of the elongation coefficient (characterized by). In various embodiments, each of the quantum gates 122 of one or more quantum computers 108 can be calibrated with respect to each of the reference elongation coefficients. Further, the calibrated gate parameters can be plotted against the reference elongation coefficients within one or more reference models. Thereby, the model component 114 can employ one or more empirical fits to the plotted data to characterize the relationship between the parameter values and the reference elongation coefficients for each of the quantum gates 122 of one or more quantum computers 108.

[0041] FIG. 2 shows a diagram of an exemplary non-limiting graph 200 representing various empirical fits that can be employed by the model component 114 to generate one or more reference models that characterize the relationship between the gate parameters and the elongation coefficient, according to one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the model component 114 can fit the amplitude parameter of a particular quantum gate 122 to the calibrated reference elongation coefficient data. Further, as shown in graph 200, the model component 114 of a particular quantum gate 122 can use polynomial fits or piecewise linear fits or both to fit the angle parameter or the differential parameter or both of a particular quantum gate 122 to the calibrated reference elongation coefficient data. The reference model illustrated by graph 200 can account for calibrations for elongation coefficient intervals within the range of 1 - 2.

[0042] As shown in FIG. 2, line 202 can represent the calibration of the first stretch factor performed on quantum gate 122 (e.g., a cross resonance gate). Line 204 can represent the calibration of the subsequent second stretch factor performed on quantum gate 122. Line 206 can represent a piecewise linear fit using parameters resulting from the calibration of the first stretch factor. Line 208 can represent a piecewise linear fit using parameters resulting from the calibration of the second stretch factor. Line 210 can represent a polynomial fit using parameters resulting from the calibration of the first stretch factor. Line 212 can represent a polynomial fit using parameters resulting from the calibration of the second stretch factor. In various embodiments, θ (e.g., inversely proportional to time) ZX = ω ZX The sensitivity of the fit of the amplitude parameter using ZX = ω ZX T can be lower than the fit for other gate parameters such as the phase parameter or the DRAG parameter or both.

[0043] In various embodiments, model component 114 can determine the stretch factor intervals associated with each quantum gate based on one or more operating characteristics of the quantum gates 122 of one or more quantum computers 108. For example, model component 114 can determine the stretch factor intervals such that a minimal amount of calibration overhead is required while still generating quantum gates 122 for error mitigation (e.g., Richardson error mitigation). For example, model component 114 can determine the number of stretch factors that function as the reference stretch factor for a quantum gate 122, or which stretch factors function as changes in the error value or parameter value or both for each Clifford of a particular quantum gate 122 based on the reference stretch factor.

[0044] For example, the model component 114 can define the number or value or both of the reference elongation coefficients included within the elongation coefficient interval based on the determination of the error per gate (e.g., the error per Clifford). For example, the number of reference elongation coefficients included within the elongation coefficient interval can increase with the number of changes in the determination of the error per gate (e.g., the error per Clifford) within the elongation coefficient interval. In another example, the model component 114 can define the number or value or both of the reference elongation coefficients included within the elongation coefficient interval based on the gate parameters. For example, the number of reference elongation coefficients included within the elongation coefficient interval can increase with the number of changes in the determination of the gate parameters within the elongation coefficient interval.

[0045] Figures 3A - B illustrate exemplary non - limiting graphs 300 and / or 302 that can be generated by model component 114 to characterize one or more operating characteristics of one or more quantum gates 122 and identify a reference stretch factor, in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In one or more embodiments, graph 300 and / or 302 can be generated by model component 114 based on one or more analytical considerations (e.g., in accordance with Equation 2) regarding the quantum gates 122 of one or more quantum computers 108. As shown in Figure 3A, exemplary graph 300 can consider the amplitude of the cross - resonance pulse (e.g., referred to as "amp_CR" in Figure 3A) as a target gate parameter for reference modeling. As shown in Figure 3B, model component 114 can generate exemplary graph 302 by first estimating how the error value per Clifford changes as a function of the stretch factor value. For example, model component 114 can perform an initial estimate where the error per Clifford is determined for a set of stretch factors that are typically linearly spaced within a stretch factor interval. Next, model component 114 can select a reference stretch factor based on the amount of change between the error values per Clifford.

[0046] Within regions A of the exemplary graphs 300, 302, a change in the amount of gate parameters or per Clifford error values, or both, greater than within region B can occur for a particular quantum gate 122. For example, the difference between gate parameter values or per Clifford error values, or both, from one reference point to another within region A can be greater than the difference between gate parameter values or per Clifford error values, or both, from one reference to another within region B. For example, the slope of the empirical fit characterizing the change in amplitude or per Clifford error values, or both, within region A can be greater than that of region B.

[0047] In various embodiments, the model component 114 can define the number of reference stretch coefficients included within region A to be greater than the number of reference stretch coefficients included within region B. For example, as shown in FIG. 3A, the model component 114 can identify five reference stretch coefficients corresponding to region A and three reference stretch coefficients corresponding to region B. In another case, as shown in FIG. 3B, the model component 114 can identify four reference stretch coefficients corresponding to region A and two reference stretch coefficients corresponding to region B. Thereby, the density of the reference stretch coefficients associated with region A can be greater than the density of the reference stretch coefficients associated with region B.

[0048] In one or more embodiments, the error reduction component 110 can share the reference elongation coefficient value determined by the model component 114 with one or more data scientists via one or more input devices 106. Thereby, the data scientist can calibrate the quantum gates 122 of one or more quantum computers 108 with respect to the reference elongation coefficient. As a result of the calibration, reference gate parameters associated with the reference elongation coefficient can be determined. For example, the reference gate parameters of a particular quantum gate can be the gate parameters that achieve the reference elongation coefficient according to the calibration. Further, one or more of the input devices 106 can be used to input the reference gate parameters into the system 100 and share the reference gate parameters with the error reduction component 110. According to various embodiments described herein, the model component 114 can plot the reference gate parameters against the reference elongation coefficient and generate one or more reference models using empirical fitting (e.g., piecewise linear fitting, polynomial fitting).

[0049] In one or more embodiments, the error reduction component 110 can share the reference elongation coefficient value determined by the model component 114 with one or more input devices 106 or quantum computers 108 or both, to facilitate automated calibration of one or more quantum gates 122. For example, the calibration can execute multiple calibration routines that execute the operations of one or more quantum computers 108 to determine the values of the gate parameters of the associated pulses. Each calibration routine can also return the accuracy associated with the gate parameters of the associated pulse being calibrated. Thereby, the automated calibration can determine whether to execute the next calibration routine or whether the last calibration routine needs to be repeated.

[0050] FIG. 4 shows a diagram of an exemplary non-limiting system 100 that further includes a gate resource component 402, a tracking component 404, or an adjustment component 406, or a combination thereof, in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the gate resource component 402 can define one or more operating capabilities of one or more quantum gates 122 of the quantum computer 108. Also, the tracking component 404 can track the operating capabilities defined by the gate resource component 402 to identify whether one or more changes have occurred. Further, the adjustment component 406 can change one or more target extension factors to correspond to the operating capabilities defined by the gate resource component 402 and tracked by the tracking component 404.

[0051] One or more quantum gates 122 (e.g., cross resonance gates) of the quantum computer 108 can have different gate lengths and gate errors and can be initially optimized. Accordingly, the maximum extension factor that can be employed for each quantum gate can vary. For example, the first quantum gate 122 of the quantum computer 108 can succeed in employing a maximum extension factor of 2, while the second quantum gate 122 of the quantum computer 108 can fail with an extension factor of 2.

[0052] In various embodiments, the gate resource component 402 can generate one or more gate resource tables 408. For example, each quantum gate 122 of one or more quantum computers 108 can be represented within one or more gate resource tables 408. Further, the gate resource component 402 can add to the gate resource table 408 the minimum stretch factor and the maximum stretch factor that can be employed with each quantum gate 122. For example, one or more gate resource tables 408 can represent each quantum gate 122 by each identifier (e.g., title or number or both), and can list the minimum stretch factor value and the maximum stretch factor value associated with each quantum gate 122. In various embodiments, the number, location, or composition of the quantum gates 122, or a combination thereof, can be input into the system 100 via one or more input devices 106 by one or more data scientists or one or more computer programs or both who are proficient in the quantum computer 108. In some embodiments, the gate resource component 402 can retrieve from one or more quantum computers 108 data that defines the number, location, or composition of the quantum gates 122, or a combination thereof. In one or more embodiments, the quantum gates 122 can be identified, for example, by name and stretch factor (e.g., the stretch factor can be incorporated into the name of the quantum gate 122). For example, exemplary names of quantum gates 122 can include, but are not limited to, CNOT_1.00 (e.g., the stretch factor is 1.00), CNOT_1.50 (e.g., the stretch factor is 1.50), or CNOT_2.00 (e.g., the stretch factor is 2.00), or a combination thereof. In various embodiments, one or more gate resource tables 408 can be stored within one or more memories 116. In one or more embodiments, one or more gate resource tables 408 can be stored in a computer architecture external to the server 102.In some embodiments, one or more quantum gates 122 can be further grouped into a set known as a family within one or more gate resource tables 408 based on one or more functions within one or more quantum computers 108 or their proximity to each other or both.

[0053] The minimum stretch factor and / or the maximum stretch factor associated with the quantum gate 122 can be calculated by the gate resource component 402 based on one or more analytical considerations and / or one or more measurement results or both. For example, in various embodiments, one or more input devices 106 can be employed to input the hardware characteristics of the quantum gate 122 into the system 100. Exemplary hardware characteristics can include, but are not limited to, the material composition of the quantum gate 122, the connectivity of the quantum gate 122, the length of the quantum gate 122, the fidelity of the quantum gate 122, or fluctuations in the fidelity of the quantum gate 122, or combinations thereof. For example, the maximum stretch factor for a particular quantum gate 122 can define a stretch factor value beyond which the quantum gate 122 becomes too unstable to be used or too many errors occur and it becomes unusable. Based on the hardware characteristics, the gate resource component 402 can calculate the minimum stretch factor and / or the maximum stretch factor or both that can be employed with the quantum gate according to a numerical model of the quantum system based on the hardware characteristics of one or more quantum computers 108. In another example, the quantum gate 122 can be operated using a plurality of increasing stretch factors to identify the minimum stretch factor value and / or the maximum stretch factor value or both at which normal operation can be achieved, and one or more quantum computers 108 can share the identified minimum stretch factor and / or the maximum stretch factor or both (e.g., via one or more networks 104) with the gate resource component 402.

[0054] In various embodiments, one or more quantum gates 122 may be susceptible to variations in operation. As a result of the variations, the maximum stretch factor that can be employed by the quantum gates 122 may change over time. The tracking component 404 can track the operating state of one or more quantum gates 122 to ensure that the maximum stretch factor reflected in one or more gate resource tables 408 is up-to-date. For example, the tracking component 404 can execute one or more randomized benchmarking protocols to evaluate the capabilities of the hardware of the quantum computer 108 by estimating the average error rate measured during the execution of a sequence of random quantum gate operations. For example, the randomized benchmarking can be based on uniformly random Clifford operations. Further, quantum process tomography (QPT) and / or quantum gate set tomography (GST) can be performed (e.g., by the tracking component 404) to determine the maximum stretch factor value (e.g., based on the fidelity of the quantum gates 122). When a randomized benchmarking protocol is employed, a plurality of sequences of Clifford gates including "m" Clifford gates can be created. In any particular sequence of Clifford gates of length m, one to m - 1 Clifford gates can be randomly selected from the Clifford group. The last Clifford gate can be selected such that the sequence of m Clifford gates creates an identity operation. The average value of the measurement results at each length m can be determined to create a curve representing the qubit population as a function of m. Further, the gate fidelity can be extracted from this curve using empirical fitting.

[0055] In one or more embodiments, the tracking component 404 can periodically perform a randomized benchmarking protocol to verify the maximum extension factor included in one or more gate resource tables 408. For example, the tracking component 404 can perform a randomized benchmarking protocol according to one or more schedules. For example, the tracking component 404 can perform a randomized benchmarking protocol daily, at intervals of several days (e.g., every two days), weekly, or at another desired time interval. Further, the schedule of the randomized benchmarking performed by the tracking component 404 can vary between quantum gates 122. For example, the quantum gate associated with the highest maximum extension factor can be the gate most susceptible to gate fluctuations, and thus can be the subject of more frequent randomized benchmarking by the tracking component 404 than the quantum gate associated with a lower maximum extension factor. For example, the quantum gate associated with the highest maximum extension factor can be the subject of daily randomized benchmarking by the tracking component 404, while the quantum gate associated with the lowest maximum extension factor can be the subject of weekly randomized benchmarking by the tracking component 404. In various embodiments, the schedule of the randomized benchmarking performed by the tracking component 404 can vary based on the amount of maintenance overhead assigned to the system 100 or the quantum computer 108 or both.

[0056] In one or more embodiments, the adjustment component 406 can determine whether one or more target extension factors should be changed to match the capabilities of the available quantum gates 122, by referring to one or more gate resource tables 408 (e.g., generated by the gate resource component 402, updated by the tracking component 404, or both). For example, one or more input devices 106 can be used to define one or more quantum circuits to be executed during one or more quantum operations by one or more quantum computers 108. One or more input devices 106 can also be used to define one or more target extension factors utilized during an error mitigation protocol, if error mitigation is employed to improve the results of a quantum operation.

[0057] The adjustment component 406 can analyze the received quantum circuit (e.g., received via one or more networks 104 or communication components 112 or both), and identify which quantum gates 122 from one or more quantum computers 108 are operating during the quantum operation. For example, the adjustment component 406 can associate the quantum gates 122 of the quantum computer 108 with a particular quantum circuit based on the qubit connectivity established by the quantum gates and defined by the quantum circuit. In another example, each quantum gate 122 of a particular quantum circuit must be executed by one or more quantum computers 108. If a particular quantum circuit includes a quantum gate 122 that is not natively supported by the quantum computer 108, the quantum gate 122 can be decomposed into quantum gates 122 that are natively supported. For example, if a particular quantum circuit defines a quantum gate 122 that is not supported by one or more quantum computers 108 due to limited qubit connectivity, a swap gate (e.g., decomposed into gates supported by the quantum computer 108) can be inserted into the quantum circuit by the adjustment component 406. Thereby, the adjustment component 406 can identify the quantum gates 122 associated with the quantum operation, and with reference to one or more gate resource tables 408, identify the range of acceptable (e.g., limited by a maximum stretch factor) stretch factors that can be utilized with the associated quantum gates 122. If one or more target stretch factors provided via the input device 106 are within the range of acceptable stretch factors, the error mitigation component 110 can proceed with the implementation of one or more error mitigation protocols described herein using the particular target stretch factors. If one or more stretch factors provided via the input device 106 are outside the range of acceptable stretch factors, the adjustment component 406 can change the value of the target stretch factor to one or more values within the acceptable range.For example, the adjustment component 406 can change the value of one or more target extension coefficients to a value within an acceptable range that is closest to the initially provided value. In another case, the adjustment component 406 can change the value of one or more target extension coefficients to a value within the center of the acceptable range.

[0058] In various embodiments, one or more extension coefficients within the acceptable range may still be unusable. Unusable extension coefficients within the acceptable range may be indicated in performance benchmarks such as error values per high Clifford. For example, an exemplary acceptable range of extension coefficients can be from 1.0 to 3.0. However, extension coefficients from 2.1 to 2.3 may be unusable due to insufficient fidelity (e.g., one or more calibration protocols may have been invalid for these extension coefficients). The adjustment component 406 can ensure that the target extension coefficient is not within the range of 2.1 to 2.3.

[0059] Furthermore, the adjustment component 406 can change the target extension coefficient to satisfy one or more hardware constraints. For example, the hardware of some quantum computers 108 can only read pulses that contain a defined number of multiples of samples (e.g., only pulses that are multiples of 16 samples). The adjustment component 406 can choose to change the target extension coefficient such that the pulse is a multiple of the defined number for the hardware of the quantum computer 108. For example, if the defined number is 16 and a pulse using an extension coefficient of 2.1 contains 168 samples, the adjustment component 406 can choose to use a target extension coefficient of 2 such that the pulse contains (a multiple of 16) 160 samples.

[0060] To illustrate non-limiting embodiments of how the gate resource component 402, the tracking component 404, or the adjustment component 406, or combinations thereof, can operate in cooperation, the following exemplary use cases are considered. The quantum gates 122 of one or more quantum computers 108 may first be optimized such that in one or more error reduction protocols, an elongation factor in the range of 1.0 or more to 2.0 or less can be normally employed. The gate resource component 402 can store a range of acceptable elongation factors (e.g., 1.0 to 2.0) in one or more gate resource tables 408 in relation to the unique identifiers of the quantum gates 122. After the initial optimization, one or more operational variations may occur in the quantum gates 122, and the range of acceptable elongation factors may narrow to a new range of 1.0 or more to 1.8 or less. For example, the qubit coherence times T1 and T2 may vary in one or more quantum computers 108, which may adversely affect the quantum gates 122 that employ large elongation factors. During the randomized benchmarking protocol executed by the tracking component 404 according to one or more defined schedules, the tracking component 404 can identify the narrowed range and, accordingly, update one or more gate resource tables 408. Before the execution of a quantum operation that utilizes the quantum gates 122 by one or more quantum computers 108, the adjustment component 406 can compare one or more target elongation factors provided in relation to the quantum operation with the acceptable range of elongation factors (e.g., 1.0 to 1.8) stored in one or more gate reference tables 408. If the target elongation factor is greater than 1.8, the adjustment component 406 can change the value of the target elongation factor to 1.8 to match the capabilities of the quantum gates 122.

[0061] FIG. 5 shows a diagram of an exemplary non - limiting system 100 that further includes an interpolation component 502, in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the interpolation component 502 is configured to determine, based on one or more reference models generated by the model component 114, one or more quantum - gate parameters that can achieve a target stretch factor for a particular quantum gate 122 (e.g., provided by one or more input devices 106 or modified by the adjustment component 406 or both).

[0062] In one or more embodiments, the interpolation component 502 can interpolate the gate parameters of the target stretch factor based on nearby reference - gate parameters calibrated with respect to a reference stretch factor. As described herein, the one or more reference models generated by the model component 114 can plot a reference stretch factor against reference - gate parameters (e.g., determined by one or more calibration protocols) and can include an empirical fit to the plotted data. The interpolation component 502 can further interpolate the gate parameters from the empirical fit with respect to one or more target stretch factors. Thereby, the interpolation component 502 can interpolate the gate parameters from the reference model for stretch factors that would not otherwise be calibrated (e.g., non - reference stretch factors).

[0063] FIG. 6 shows an exemplary non-limiting reference model 600 that can represent interpolation of gate parameters to be performed by interpolation component 502, according to one or more embodiments described herein. Repetition of the description of similar elements employed in other embodiments described herein is omitted for brevity. According to various embodiments described herein, an exemplary reference model 600 can be generated by model component 114.

[0064] As shown in FIG. 6, the exemplary reference model 600 plots four reference stretch coefficients represented by the gate parameter "p" (e.g., the amplitude of the cross resonance pulse) for (e.g., " i ", "

Number

Number

Number

Number

[0065] Accordingly, the interpolation component 502 can interpolate the gate parameters associated with the target elongation coefficient by identifying the position of the target elongation coefficient on the adapted model and referring to the gate parameter values corresponding to that position. For example, the position of the target elongation coefficient "

Number

Number

[0066] FIG. 7 shows a diagram of an exemplary non-limiting system 100 that further includes an execution component 702 in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the execution component 702 can execute one or more quantum operations on one or more quantum computers 108 using one or more gate parameters interpolated from one or more reference models.

[0067] In one or more embodiments, one or more input devices 106 may be used to define one or more quantum circuits executed on one or more quantum computers 108 to perform quantum operations. Further, one or more input devices 106 may be used to define one or more target extension factors utilized in one or more error mitigation protocols with respect to the quantum operations. The interpolation component 502 can interpolate one or more gate parameters to achieve the target extension factors from one or more reference models. The execution component 702 can execute the quantum circuit on one or more quantum computers 108 using the one or more interpolated gate parameters.

[0068] For example, the execution component 702 can execute the quantum circuit multiple times on one or more quantum computers 108 to generate result data. The execution component 702 can utilize each interpolated gate parameter in each execution. Thus, each execution of the quantum circuit on one or more quantum computers 108 can generate result data associated with each extension factor, thereby incorporating each noise amount. In various embodiments, the execution component 702 can transmit one or more execution commands to one or more quantum computers 108 via one or more networks 104. For example, the execution component 702 can generate one or more digital signals that define the quantum circuit to be executed by the quantum computer 108, or the gate parameter values used by the quantum computer 108 during execution, or both.

[0069] FIG. 8 shows a diagram of an exemplary non-limiting system 100 further comprising a mitigation component 802. Repetition of the description of similar elements employed in other embodiments described herein is omitted for brevity. In various embodiments, the mitigation component 802 can implement one or more error mitigation protocols to remove noise from the resulting data. The error mitigation protocol implemented by the mitigation component 802 can identify noise based on the differences between the resulting data generated by different executions of the quantum circuit when affected by varying stretch factors. In one or more embodiments, the mitigation component 802 can generate a noise-reduced result by extrapolating the resulting data obtained by the execution component 702 to the zero-order noise limit using Richardson error mitigation or another extrapolation method.

[0070] FIG. 9 shows an exemplary non-limiting graph depicting the effectiveness of one or more error reduction protocols implemented by a mitigation component 802, in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. The graph of FIG. 9 shows a hydrogen molecule dissociation energy curve with reduced Richardson error that may be generated by an error mitigation component 110. For example, the reduced result data shown in FIG. 9 can be considered a set of result data executed on a cloud computing-based quantum computer 108 using target stretch factors 1.00, 1.50, and 2.00. For example, the gate parameters of one or more quantum computers 108 for a target stretch factor were obtained by an interpolation component 502 by interpolating parameters from reference stretch factors 1.0, 1.26, 1.58, and 2.00. The results shown in FIG. 9 indicate that the error-reduced result data (e.g., indicated by triangles) is closer to the ideal result data (e.g., indicated by stars) than the execution performed at a stretch factor of 1.0.

[0071] FIG. 10 shows an exemplary non-limiting mode of operation 1000 that can facilitate one or more error mitigation protocols executed by an error mitigation component 110 in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. The mode of operation 1000 can illustrate an exemplary non-limiting path of communication between an error mitigation component 110 (and related components of the error mitigation component 110, for example), one or more input devices 106, or one or more quantum computers 108, or a combination thereof. In various embodiments, the communication and / or transfer of data shown in FIG. 10 can be performed via one or more networks 104, such as a cloud computing environment. For example, system 100 can use a cloud computing environment to control one or more quantum computers 108.

[0072] At 1002, a gate resource component 402 can share an extension factor interval with one or more of the input devices 106. The extension factor interval can be a range of extension factors from which one or more target extension factors for implementing one or more error mitigation protocols described herein can be selected. In one or more embodiments, a minimum extension factor value (``c min '') and a maximum extension factor (``c max '') associated with one or both of the quantum gates 122 or a family of quantum gates 122 can be used to define, for example, a range such as ``[c min ,c maxAn elongation coefficient interval (characterized as ") can be defined. For example, the gate resource component 402 can analyze one or more gate resource tables 408 with respect to one or more quantum gates 122 or a family of quantum gates 122 or both that can be used to perform quantum operations. The gate resource component 402 can use, as the smallest minimum elongation coefficient value associated with one or more quantum gates 122 or a family of quantum gates 122 or both (e.g., defined in one or more gate resource tables 408), the minimum elongation coefficient value of the interval ("c min "). Also, the gate resource component 302 can use, as the largest maximum elongation coefficient value associated with one or more quantum gates 122 or a family of quantum gates 122 or both (e.g., defined in one or more gate resource tables 408), the maximum elongation coefficient value of the interval ("c max "). Thereby, the elongation coefficient interval can characterize the widest range of acceptable elongation coefficients associated with one or more quantum gates 122 or a family of quantum gates 122 or both that can be used in the operation.

[0073] According to one or more embodiments described herein, one or more input devices 106 can be used to select one or more elongation coefficient values from the elongation coefficient interval as one or more target elongation coefficients for error reduction. For example, one or more input devices 106 can be used to select a plurality of elongation coefficient values from within the elongation coefficient interval to function as target elongation coefficients. At 1004, one or more input devices 106 can share the selected target elongation coefficients with the error reduction component 110 to facilitate the execution of one or more quantum operations. Further, at 1004, one or more input devices 106 can be used to define one or more quantum circuits that can be executed using the target elongation coefficients selected for performing the quantum operations.

[0074] In various embodiments, the adjustment component 406 can analyze a selected target extension factor or one or more specific quantum circuits or both. As described herein, the adjustment component 406 can identify the associated quantum gates 122 of one or more quantum computers 108 for the execution of one or more specific quantum circuits. For example, if one or more quantum computers 108 comprise a plurality of quantum gates 122, the adjustment component 406 can identify the quantum gates 122 that are available for an operation (e.g., quantum gates 122 that are not currently performing another quantum operation or are in a state for an operation or both). Further, the adjustment component 406 can identify one or more quantum gates 122 that satisfy the connectivity of the qubits defined by one or more quantum circuits as the quantum gates 122 associated with a particular quantum operation. For example, one or more specific quantum circuits can define the number of qubits coupled by the quantum gates 122 or the type of coupling (e.g., including logical conditions) indicated by the quantum gates 122 or both, and one or more of the associated quantum gates 122 identified by the adjustment component 406 can satisfy the definition of the quantum circuit. Further, in one or more embodiments, the adjustment component 406 can further compare one or more target extension factors with one or more updated (e.g., updated by the tracking component 404) capabilities of one or more of the associated quantum gates 122.

[0075] If one or more target stretch factors are outside the updated acceptable range of stretch factors for one or more associated quantum gates 122, the adjustment component 406 can change the values of the one or more target stretch factors so that they are within the acceptable range of stretch factors. For example, the adjustment component 406 can add to or subtract from the one or more target stretch factor values the minimum amount needed to move the target stretch factor values within the acceptable range. At 1006, the adjustment component 406 can share the one or more (e.g., changed or unchanged) target stretch factors with the interpolation component 502.

[0076] In various embodiments, the interpolation component 502 can determine the parameters of one or more quantum gates 122 that can achieve one or more target stretch factors. For example, the interpolation component 502 can use one or more reference models (e.g., generated by the model component 114) to interpolate the parameters of one or more quantum gates 122 from one or more empirical fits. Thereby, the interpolation component 502 can interpolate the parameters of one or more quantum gates 122 from a model calibrated with a plurality of reference stretch factors. Interpolating one or more quantum gate parameters 122 from a calibrated reference model advantageously enables the interpolation component 502 to determine the parameters of one or more quantum gates 122 without calibrating one or more quantum computers 108 for a particular target stretch factor. At 1008, the interpolation component 502 can share the parameters of the one or more interpolated quantum gates 122 with the execution component 702.

[0077] In some embodiments, the interpolation component 502 may be provided within one or more input devices 106. For example, at 1002, the model component 114 can further share one or more interpolation functions with one or more input devices 106. For example, the model component 114 can generate one or more interpolation functions based on one or more reference models. One or more interpolation functions can characterize the empirical fitting performed by the model component 114. Thereby, one or more interpolation functions can output the parameters of one or more quantum gates 122 based on one or more target scaling factor inputs. For example, the empirical fitting of one or more reference models can characterize the relationship between the gate parameters and the scaling factors, which can be represented as one or more interpolation functions (e.g., observed by calibrating one or more reference scaling factors).

[0078] In one or more embodiments, the execution component 702 can generate one or more execution schedules based on one or more specific quantum circuits, one or more target scaling factors, or the parameters of one or more interpolated quantum gates 122, or a combination thereof. One or more execution schedules can characterize the quantum circuit as a plurality of circuits each associated with a respective target scaling factor. For example, if two quantum circuits and three target scaling factors are defined by one or more input devices 106, the execution component 702 can generate an execution schedule that includes six respective quantum circuits (e.g., variations based on three scaling factors for each quantum circuit). At 1010, the execution component 702 can send one or more command signals to one or more quantum computers 108 to execute a specific quantum operation. For example, one or more command signals can characterize one or more execution schedules and the parameters of the associated interpolated quantum gates 122 to be executed by one or more quantum computers 108.

[0079] One or more quantum computers 108 can execute one or more quantum operations based on a command signal and generate a set of result data. For example, one or more quantum computers 108 can use the parameters of the associated interpolated quantum gates 122 to execute one or more specific quantum circuits according to one or more execution schedules and thereby according to one or more target extension factors. In various embodiments, one or more quantum computers 108 can generate each result data set for each execution of a quantum circuit. For example, if the execution schedule includes the execution of six quantum circuits (e.g., two quantum circuits each including three changes corresponding to three target extension factors as described above), one or more quantum computers 108 can generate the result data associated with each of the six executions. Further, the result data of all six quantum circuit executions can constitute a set of result data associated with a specific quantum operation.

[0080] In one or more embodiments, the result data set can include a label specifying the context of data generation. For example, the label can describe the quantum circuit, the target extension factor, or the parameters of the quantum gate 122, or a combination thereof, executed by one or more quantum computers 108 to achieve the associated result data. For example, if the set of result data includes six data sets, each data set can include a label (e.g., a header entry) that describes the quantum circuit, the target extension factor, or the parameters of the quantum gate 122, or a combination thereof, that achieved the result data included in the data set. 1012, one or more quantum computers 108 can share the set of result data of a specific quantum operation with one or more reduction components 802.

[0081] In various embodiments, the mitigation component 802 can implement one or more error mitigation protocols, such as the Richardson error mitigation protocol, and extrapolate a set of result data to the zero-noise limit. For example, the mitigation component 802 can analyze the labels of the data sets to identify which data sets are associated with changes in the same quantum circuit and which target extension coefficients are associated with each change. For example, the various data sets within the set of result data can characterize a particular quantum circuit with varying amounts of noise based on the various target extension coefficients employed. Thereby, the mitigation component 802 can use Richardson error mitigation techniques to extrapolate a result with reduced error from the set of result data. At 1014, the mitigation component 802 can share the result data with reduced error with one or more input devices 106.

[0082] FIG. 11 shows a diagram of an exemplary non-limiting system 100 further comprising a recommendation component 1102 in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. In various embodiments, the recommendation component 1102 can generate one or more recommended extension coefficients for selection as target extension coefficients via one or more input devices 106.

[0083] In one or more embodiments, the recommended component 1102 can generate one or more recommended scaling factors based on the number of quantum gates 122 of a particular quantum circuit (e.g., the total number of quantum gates 122, or the number of quantum gates 122 by type of gate (such as the number of single - qubit gates, or two - qubit gates, or both), or both) or the number of qubits or both. For example, as the number of quantum gates 122 or qubits or both in a quantum circuit increases, the maximum scaling factor recommended for the execution of the quantum circuit can decrease. For example, adopting a large scaling factor value in a quantum circuit that includes a large number of quantum gates 122 or qubits or both (e.g., a quantum circuit with a high circuit depth) can introduce a overwhelming amount of noise into the resulting data, thereby hindering error - mitigation protocols. For example, if the fidelity of the gates within a quantum circuit falls below a particular threshold (e.g., 50%), the quantum circuit can be considered too deep to be executed by one or more quantum computers 108. The recommended component 1102 can analyze one or more particular quantum circuits (defined, e.g., via one or more input devices 106) and determine an optimal set of scaling factors that can maximize, or otherwise improve, the effectiveness of one or more error - mitigation protocols, or both. For example, the recommended component 1102 can analyze one or more particular quantum circuits (defined, e.g., via one or more input devices 106) and determine an optimal set of scaling factors that can achieve a desirable distribution of noise within a set of result data of a quantum operation.

[0084] In various embodiments, the recommended component 1102 can be calibrated, or trained, or both, via a plurality of benchmark quantum operations executed on one or more quantum computers 108. For example, the quantum operations can be executed multiple times on one or more quantum computers 108 using a particular scaling factor, and the number of quantum gates 122, or the number of qubits, or both, can vary with each execution (e.g., thereby changing the depth of the quantum circuit). For example, for a plurality of reference scaling factors, all-to-all connectivity quantum alternating operator ansatz (QAOA) can be executed (e.g., on one or more quantum computers 108, or on a simulator, or both) using a plurality of different circuit depths "p" and a plurality of different qubit numbers "N". A set of resulting data achieved by the execution can define a range of acceptable scaling factors recommended for a particular quantum circuit profile (p, N). For example, the acceptable scaling factor can be a scaling factor that achieves a Hellinger distance below a defined threshold.

[0085] Furthermore, the recommended component 1102 can generate one or more recommended tables 1104, add data to one or more recommended tables 1104, or perform both, based on the execution of one or more benchmark quantum operations. As shown in FIG. 11, one or more recommended tables 1104 can be stored, for example, in one or more memories 116. For example, one or more recommended tables 1104 can specify a plurality of quantum circuit profiles (p,N) (e.g., a plurality of quantum circuits having various combinations of the number of gates or qubits or both, thereby having various circuit depths). The recommended component 1102 can add to one or more recommended tables 1104 a range of acceptable scaling factors associated with each quantum circuit profile (p,N).

[0086] The recommended component 1102 can compare one or more specific quantum circuits (e.g., provided via one or more input devices 106) with the quantum circuit profiles of one or more recommended tables 1104. If one or more quantum circuits have the same circuit depth (e.g., the same combination of the number of gates and qubits) as the quantum circuit profiles of one or more recommended tables 1104, the recommended component 1102 can identify the associated range of acceptable scaling factors as the recommended range of scaling factors. If one or more specific quantum circuits have a different circuit depth (e.g., a different combination of the number of gates and qubits) from the quantum circuit profiles, the recommended component 1102 can identify the range of acceptable scaling factors associated with the most closely matching quantum circuit profile (e.g., the quantum circuit profile having the smallest deviation in the combination of the number of quantum gates 122 or qubits or both from one or more specific quantum circuits).

[0087] In various embodiments, the recommended component 1102 can share the range of recommended elongation factors with one or more input devices 106 for the selection of one or more target elongation factors (e.g., when one or more input devices 106 can be used to select a target elongation factor from the range of recommended elongation factors). In one or more embodiments, the recommended component 1102 can select one or more elongation factors as the recommended target elongation factors from the associated range of acceptable elongation factors (e.g., the recommended target elongation factors can be linearly spaced between a value of 1.0 and the maximum elongation factor associated with a particular quantum gate 122). Further, the recommended component 1102 can share one or more recommended elongation factors with one or more input devices 106 for approval via one or more input devices 106.

[0088] In one or more embodiments, the recommended component 1102 can perform one or more discovery techniques to determine one or more recommended elongation factors. For example, the recommended component 1102 can generate one or more recommended target elongation factors based on counting the number of single qubit quantum gates 122 or two qubit quantum gates 122 or both defined by a particular quantum circuit, along with the error rate observed for the quantum gate 122 during calibration at one or more reference elongation factors.

[0089] FIG. 12 shows an exemplary non-limiting mode of operation 1200 that can facilitate one or more error reduction protocols executed by the error reduction component 110 in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity. The mode of operation 1200 can illustrate an exemplary non-limiting path of communication between the error reduction component 110 (and, for example, associated components of the error reduction component 110), one or more input devices 106, or one or more quantum computers 108, or combinations thereof. In various embodiments, the communication and / or transfer of data shown in FIG. 12 can be performed via one or more networks 104, such as a cloud computing environment. For example, the system 100 can use a cloud computing environment to control one or more quantum computers 108.

[0090] Compared to the mode of operation 1000, the mode of operation 1200 incorporates a recommended component 1102. For example, one or more input devices 106 can be used to define one or more quantum circuits for performing one or more quantum operations on one or more quantum computers 108. At 1202, one or more input devices 106 can share one or more specific quantum circuits with the recommended component 1102. The recommended component 1102 can generate one or more recommendations, including but not limited to, a plurality of recommended scaling factors, or a range of recommended scaling factors, or combinations thereof. For example, the recommended component 1102 can compare one or more specific quantum circuits with one or more quantum circuit profiles stored in one or more recommendation tables 1004 in accordance with various embodiments described herein.

[0091] At 1204, the recommended component 1102 can share one or more recommendations with one or more input devices 106 for approval or selection or both. For example, one or more input devices 106 can be used to approve one or more recommended stretch factors as target stretch factors to be utilized in one or more error reduction protocols according to the various embodiments described herein. In another example, one or more input devices 106 can be used to select one or more target stretch factors from a recommended range of stretch factors.

[0092] Thereafter, the mode of operation 1200 can perform steps 1006 - 1014 described herein with reference to the mode of operation 1000. For example, one or more input devices 106 can share one or more target stretch factors (which can include, for example, an approved recommended stretch factor, a stretch factor selected from a recommended range, or a defined stretch factor unrelated to one or more recommendations generated by the recommended component 1102, or a combination thereof) with the adjustment component 406 to facilitate the adaptation of one or more quantum gates 122 of a quantum computer 108 that executes one or more quantum operations. Thereafter, one or more specific quantum circuits can be executed using the target stretch factor on one or more quantum computers 108 according to the various embodiments described herein. Further, the result data generated by the execution on the quantum computer 108 can be subject to one or more error reduction protocols such as Richardson error reduction.

[0093] FIG. 13 shows a flowchart of an exemplary non - limiting computer - implemented method 1300 that can facilitate performing one or more quantum operations on one or more quantum computers 108 using error mitigation, in accordance with one or more embodiments described herein. Repeated descriptions of similar elements employed in other embodiments described herein are omitted for brevity.

[0094] At 1302, the computer - implemented method 1300 can include generating one or more reference models that can include reference gate parameters of one or more quantum gates 122 calibrated with a plurality of reference extension coefficients (e.g., by model component 114) by a system 100 operably coupled to a processor 120. At 1304, the computer - implemented method 1300 can include receiving, by the system 100 (e.g., by error mitigation component 110), one or more quantum circuits. For example, one or more input devices 106 can be used to define one or more quantum circuits that can define how one or more quantum operations are to be performed on the quantum computer 108 (e.g., the number of qubits used, the number of quantum gates 122 used, the connectivity of the qubits or quantum gates 122 or both, the types of quantum gates 122 used, measurement operations, qubit reset operations, or the number of times each quantum circuit is repeated to collect statistical values, or combinations thereof, etc.).

[0095] At 1306, the computer-implemented method 1300 can include the system 100 recommending one or more scaling factors for quantum error mitigation based on, for example, the number of gates or qubits or both of a quantum circuit (e.g., by the recommended component 1102). For example, the recommended component 1102 can identify one or more recommended scaling factors or intervals of recommended scaling factors or both that can be employed in a quantum circuit based at least on the circuit depth of the quantum circuit, according to various embodiments described herein. Further, the recommended scaling factors can be shared with one or more input devices 106 for selection or approval or both. At 1308, the computer-implemented method 1300 can include the system 100 receiving one or more target scaling factors that can be employed in a quantum circuit to facilitate one or more error mitigation protocols (e.g., by the error mitigation component 110). For example, one or more input devices 106 can be used to select one or more target scaling factors from a range of recommended scaling factors, to define one or more target scaling factors not recommended, or a combination thereof, for selecting one or more of the recommended scaling factors as target scaling factors.

[0096] At 1310, the computer-implemented method 1300 can include adjusting, by the system 100 (e.g., by the adjustment component 406), one or more target stretch factors to match one or more capabilities of one or more quantum gates 122 of a quantum circuit. For example, one or more target stretch factor values can be changed based on one or more variations in the operating capabilities of one or more quantum gates 122 according to various embodiments described herein. At 1312, the computer-implemented method 1300 can include interpolating, by the system 100 (e.g., by the interpolation component 502), parameters of one or more quantum gates 122 from one or more reference models with respect to one or more target stretch factors. At 1314, the computer-implemented method 1300 can include generating result data by executing, by the system 100 (e.g., by the execution component 702), one or more quantum operations on one or more quantum computers 108 according to one or more particular quantum circuits, target stretch factors, or interpolated gate parameters, or combinations thereof. For example, the execution component 702 can generate one or more execution schedules to generate a set of result data associated with the execution of a quantum circuit with an amount of noise that varies due to varying target stretch factors according to various embodiments described herein. At 1316, the computer-implemented method 1300 can include generating an error-reduced result by extrapolating, by the system 100 (e.g., by the reduction component 802), the result data to the zero-th noise limit. For example, the reduction component 802 can implement a Richardson error reduction protocol according to various embodiments described herein.

[0097] The present disclosure includes a detailed description of cloud computing, but the implementations of the content shown herein should be understood not to be limited to cloud computing environments. Embodiments of the present invention can be implemented in combination with any other type of computing environment that is currently known or will be developed in the future.

[0098] Cloud computing is a service - delivery model that enables convenient on - demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services), and these resources can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0099] The characteristics are as follows.

[0100] On - demand self - service: Cloud consumers can unilaterally provision computing capabilities such as server time and network storage automatically as needed, without the need for human interaction with a service provider.

[0101] Broad network access: Cloud capabilities are available over a network and can be accessed using standard mechanisms, facilitating use by heterogeneous thin - client or thick - client platforms (e.g., mobile phones, laptops, and PDAs).

[0102] Resource Pool: The provider's computing resources are pooled and provided to multiple users using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated according to requests. There is a sense of location independence, and users usually neither manage nor know about the exact location of the resources provided. However, at a higher level of abstraction, it may be possible to specify a location (e.g., country, state, or data center).

[0103] Rapid Adaptability: The cloud's capabilities can be provisioned quickly, flexibly, and in some cases automatically, scale out rapidly, be released quickly, and scale in rapidly. The capabilities available for provisioning often appear to users as if they can purchase any amount at any time without limit.

[0104] Measured Service: The cloud system automatically controls and optimizes resource usage at an abstract level suitable for the type of service (e.g., storage, processing, bandwidth, and active user accounts) by leveraging metering capabilities. The usage of resources can be monitored, controlled, and reported, providing transparency to both the provider and the user of the services utilized.

[0105] The service model is as follows.

[0106] SaaS (Software as a Service): The capabilities provided to users are the use of the provider's applications running on cloud infrastructure. Those applications can be accessed from various client devices via a thin-client interface such as a web browser (e.g., web-based email). Users do not manage or control the underlying cloud infrastructure, which includes the network, servers, operating system, storage, or individual application functionality, except for making limited user-specific application configurations.

[0107] PaaS (Platform as a Service): The capabilities provided to users are to deploy the applications created or acquired by the users, which are created using programming languages and tools supported by the provider, onto the cloud infrastructure. Users do not manage or control the underlying cloud infrastructure, which includes the network, servers, operating system, or storage, but can control the deployed applications and, in some cases, the configuration of the application hosting environment.

[0108] IaaS (Infrastructure as a Service): The capabilities provided to users are the provisioning of processing, storage, network, and other basic computing resources, and users can deploy and run any software that can include an operating system and applications. Users do not manage or control the underlying cloud infrastructure, but can control the operating system, storage, and deployed applications, and in some cases, can exercise limited control over selected network components (e.g., host firewall).

[0109] The deployment model is as follows.

[0110] Private cloud: This cloud infrastructure is operated only for an organization. It can be managed by this organization or a third party and can exist on-premises or off-premises.

[0111] Community cloud: This cloud infrastructure is shared by multiple organizations and supports a specific community that shares concerns (e.g., mission, security requirements, policies, and compliance considerations). It can be managed by these organizations or a third party and can exist on-premises or off-premises.

[0112] Public cloud: This cloud infrastructure is available for general users or large industry groups and is owned by an organization that sells cloud services.

[0113] Hybrid cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that are combined with each other while leaving their unique entities intact by means of standardized technologies or proprietary technologies (e.g., cloud bursting for load balancing between clouds) that enable the migration of data and applications.

[0114] The cloud computing environment is a service-oriented environment that emphasizes statelessness, loose coupling, modularity, and semantic interoperability. At the center of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0115] Referring now to FIG. 14, an exemplary cloud computing environment 1400 is shown. As illustrated, cloud computing environment 1400 includes one or more cloud computing nodes 1402 with which local computing devices used by cloud consumers (e.g., personal digital assistant (PDA) or cellular phone 1404, desktop computer 1406, laptop computer 1408, or automotive computer system 1410, or a combination thereof, etc.) can communicate. The nodes 1402 may communicate with one another. The nodes 1402 may be physically or virtually grouped in one or more networks into private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described hereinabove (not shown). Thereby, cloud computing environment 1400 can provide an infrastructure, platform, or SaaS, or a combination thereof, for which cloud consumers need not maintain resources on local computing devices. The types of computing devices 1404 - 1410 shown in FIG. 14 are only intended to be exemplary, and it is understood that the computing nodes 1402 and cloud computing environment 1400 can communicate with any type of computer control device via any type of network or network addressable connection (e.g., connection using a web browser) or both.

[0116] Referring now to FIG. 15, a set of functional abstraction layers provided by the cloud computing environment 1400 (FIG. 14) is shown. Repeated descriptions of similar elements used in other embodiments described herein are omitted for brevity. It should be understood in advance that the components, layers, and functions shown in FIG. 15 are for illustrative purposes only and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided.

[0117] The hardware and software layer 1502 includes hardware components and software components. Examples of hardware components include mainframe 1504, RISC (Reduced Instruction Set Computer) architecture-based server 1506, server 1508, blade server 1510, storage device 1512, and network and network components 1514. In some embodiments, the software components include network application server software 1513 and database software 1518.

[0118] The virtualization layer 1520 comprises an abstract layer that can provide virtual entities such as virtual server 1522, virtual storage 1524, virtual network 1526 including a virtual private network, virtual applications and operating systems 1528, and virtual clients 1530.

[0119] To give an example, the management layer 1532 can provide the functions described below. Resource provisioning 1534 dynamically procures computing resources and other resources used to execute tasks within a cloud computing environment. Measurement and pricing 1536 performs cost tracking when resources are utilized within a cloud computing environment, and creates and sends invoices for the use of those resources. To give an example, those resources may include application software licenses. Security performs ID verification of cloud users and tasks, and protects data and other resources. The user portal 1538 provides access to the cloud computing environment to users and system administrators. Service level management 1540 allocates and manages cloud computing resources so as to meet the required service levels. Service Level Agreement (SLA) planning and execution 1542 makes advance preparations for and procures cloud computing resources for which future demands are expected, in accordance with the SLA.

[0120] The workload layer 1544 shows examples of functions available in a cloud computing environment. Examples of workloads and functions that may be provided from this layer include mapping and navigation 1546, software development and life cycle management 1548, delivery of virtual classroom education 1550, data analysis processing 1552, transaction processing 1554, and quantum computing 1556. Various embodiments of the present invention can control one or more quantum computers 108, execute one or more error mitigation protocols, or both, using the cloud computing environment described with reference to FIGS. 14 and 15, in accordance with the various embodiments described herein.

[0121] The present invention may be a system, a method, or a computer program product, or a combination thereof, at any possible technical detail level of integration. The computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to execute aspects of the present invention. The computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of the computer-readable storage medium includes a portable floppy (R) disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or a flash memory, a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy (R) disk, a punched card, or a mechanically encoded device such as a raised structure in a groove in which instructions are recorded, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted via a wire.

[0122] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). This network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transfers them for storage on a computer-readable storage medium within each computing / processing device.

[0123] Computer-readable program instructions for carrying out the operations of the present invention may be source code or object code written in any combination of one or more programming languages, including assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages such as Smalltalk(R), C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially executed on the user's computer as a stand-alone software package, partially executed on the user's computer and a remote computer respectively, or executed entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to carry out aspects of the present invention, an electronic circuit, including for example a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions for customizing the electronic circuit by utilizing the state information of the computer-readable program instructions.

[0124] Aspects of the invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0125] These computer-readable program instructions are provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer-readable program instructions may be stored in a computer-readable storage medium that includes instructions for causing a computer, programmable data processing apparatus, or other device to function in a particular manner such that the storage medium includes an article of manufacture including instructions for implementing the aspects of the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0126] The computer-readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0127] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, depending upon the functionality involved, or may sometimes be executed in the reverse order. It should also be noted that each block of the block diagrams or flowchart diagrams, or combinations of blocks in the block diagrams or flowchart diagrams or both, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or a combination of dedicated hardware and computer instructions.

[0128] To provide additional context for the various embodiments described herein, FIG. 16 and the following description are intended to illustrate an exemplary computing environment 1600 in which the various embodiments described herein may be implemented. Embodiments have been described above in the general context of computer-executable instructions that may be executed on one or more computers, but one of ordinary skill in the art will recognize that embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or both.

[0129] Typically, a program module includes routines, programs, components, data structures, etc. that perform a particular task or implement a particular abstract data type. Further, those skilled in the art will understand that the method of the present invention can be practiced using other computer system configurations including single-processor computer systems or multi-processor computer systems, minicomputers, mainframe computers, stand-alone Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, handheld computing devices, microprocessor-based consumer electronics or programmable consumer electronics, etc., each of which may be operably coupled to one or more associated devices.

[0130] The embodiments shown herein can also be practiced within a distributed computing environment where certain tasks are performed by remote processing devices linked through a communication network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components can be executed from memory that can include or consist of one or more distributed memory units. As used herein, the terms “memory” and “memory unit” are interchangeable. Further, one or more embodiments described herein can execute the code of computer-executable components in a distributed manner, for example, by binding or cooperating with multiple processors that execute code from one or more distributed memory units. As used herein, the term “memory” can include a single memory or memory unit at one location, or multiple memories or memory units at one or more locations.

[0131] A computing device can generally include various media that can include a computer-readable storage medium, a machine-readable storage medium, or a communication medium, or a combination thereof, and as used herein, the following two terms are used differently from each other. A computer-readable storage medium or a machine-readable storage medium can be any usable storage medium that can be accessed by a computer, and includes both volatile and non-volatile media, removable and non-removable media. By way of example, a computer-readable storage medium or a machine-readable storage medium can be implemented in connection with any method or technology for storing information such as computer-readable instructions or machine-readable instructions, program modules, structured data or unstructured data, but is not limited thereto.

[0132] A computer-readable storage medium can include, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technologies, compact disc read only memory (CD-ROM), digital versatile disc (DVD), Blu-ray disc (BD) or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, semiconductor drives or other semiconductor storage devices, or other tangible media or non-transitory media or both that can be used to store desired information. In this regard, the terms "tangible" or "non-transitory" as used herein, when applied to storage, memory, or computer-readable media, are understood to exclude only transitory signals that propagate themselves as modifiers, and do not waive rights to all standard storage, memory, or computer-readable media that are not merely transitory signals that propagate themselves.

[0133] A computer-readable storage medium can be accessed by one or more local computing devices or remote computing devices via, for example, access requests, queries, or other data retrieval protocols, for various operations regarding the information stored by the medium.

[0134] A communication medium typically embodies computer-readable instructions, data structures, program modules, or other structured or unstructured data in a data signal such as a modulated data signal (e.g., a carrier wave or other transport mechanism) and includes any information delivery or transport medium. The term "modulated data signal" refers to a signal having one or more of the characteristics set or changed in such a manner as to encode information in one or more signals. By way of example, the communication medium includes, but is not limited to, wired media such as a wired network or direct wired connection, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0135] Referring again to FIG. 16, an exemplary environment 1600 for implementing various embodiments of the aspects described herein includes a computer 1602, which includes a processing unit 1604, a system memory 1606, and a system bus 1608. The system bus 1608 couples system components, including but not limited to the system memory 1606, to the processing unit 1604. The processing unit 1604 can be any of a variety of commercially available processors. Dual microprocessors and other multiprocessor architectures can also be employed as the processing unit 1604.

[0136] System bus 1608 can be any of several types of bus structures that can be further interconnected to a memory bus (with or without a memory controller), a peripheral bus, and a local bus, using any of various commercially available bus architectures. System memory 1606 includes ROM 1610 and RAM 1612. The basic input / output system (BIOS) can be stored in non-volatile memory such as ROM, erasable programmable read only memory (EPROM), EEPROM, etc., and the BIOS includes basic routines that help transfer information between elements within computer 1602 during startup and the like. RAM 1612 can also include high-speed RAM such as static RAM for caching data.

[0137] The computer 1602 further includes an internal hard disk drive (HDD) 1614 (e.g., EIDE, SATA), one or more external storage devices 1616 (e.g., magnetic floppy (R) disk drive (FDD), memory stick or flash drive reader, memory card reader, etc.), and an optical disk drive 1620 (e.g., a drive capable of reading or writing to CD-ROM disks, DVDs, BDs, etc.). Although the internal HDD 1614 is shown as being within the computer 1602, the internal HDD 1614 can also be configured to be used within an external suitable enclosure (not shown). Further, although not shown in the environment 1600, in addition to or instead of the HDD 1614, a solid state drive (SSD) can be used. The HDD 1614, the external storage device 1616, and the optical disk drive 1620 can each be connected to the system bus 1608 by an HDD interface 1624, an external storage interface 1626, and an optical drive interface 1628. The interface 1624 for the implementation of the external drive can include at least one or both of the Universal Serial Bus (USB) interface technology and the Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technology. Other external drive connection technologies are contemplated for the embodiments described herein.

[0138] Drives and associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. The drives and storage media of computer 1602 accommodate storage of any data in a suitable digital format. Although the description of the computer-readable storage media above refers to various storage devices, it should be understood by those skilled in the art that other types of storage media that can be read by a computer can also be used in the exemplary operating environment, whether currently existing or to be developed in the future, and further that any such storage media can contain computer-executable instructions for performing the methods described herein.

[0139] A plurality of program modules, including operating systems 1630, one or more application programs 1632, other program modules 1634, and program data 1636, can be stored in the drives and RAM 1612. All or part of an operating system, application, module, or data, or a combination thereof, can also be cached in RAM 1612. The systems and methods described herein can be implemented using various commercially available operating systems or combinations of operating systems.

[0140] Computer 1602 can optionally include emulation technology. For example, a hypervisor (not shown) or other medium can emulate the hardware environment of operating system 1630, and the emulated hardware can optionally be different from the hardware shown in FIG. 16. In such embodiments, operating system 1630 can include one of the virtual machines (VMs) hosted on computer 1602. Further, operating system 1630 can provide a runtime environment, such as the Java(R) runtime environment or the.NET framework, to application 1632. The runtime environment is a consistent execution environment that enables application 1632 to be executed on any operating system that includes the runtime environment. Similarly, operating system 1630 can support containers, application 1632 can be in the form of a container, and a container is a lightweight, stand-alone, executable software package that includes, for example, code for the application, a runtime, system tools, system libraries, and settings.

[0141] Furthermore, computer 1602 can be enabled using a security module, such as a trusted processing module (TPM). For example, using a TPM, a boot component hashes the next boot component in time, waits for the hash result to match a protected value, and then loads the next boot component. This process can be performed at any layer within the code execution stack of computer 1602, for example, at the application execution level or applied at the operating system (OS) kernel level, thereby enabling security at any level of code execution.

[0142] The user can input commands and information into computer 1602 via one or more wired / wireless input devices (such as pointing devices like keyboard 1638, touch screen 1640, and mouse 1642). Other input devices (not shown) can include a microphone, infrared (IR) remote control, radio frequency (RF) remote control, or other remote controls, joystick, virtual reality controller or virtual reality headset or both, game pad, touch pen, image input device (such as a camera), gesture sensor input device, vision movement sensor input device, emotion or face detection device, biometric input device (such as a fingerprint or iris scanner), etc. These and other input devices can often be connected to processing unit 1604 via an input device interface 1644 that can be coupled to system bus 1608, but can also be connected by other interfaces such as a parallel port, IEEE 1394 serial port, game port, USB port, IR interface, BLUETOOTH(R) interface, etc.

[0143] A monitor 1646 or other type of display device can also be connected to system bus 1608 via an interface such as video adapter 1648. In addition to monitor 1646, the computer typically includes other peripheral output devices (not shown) such as speakers, printers, etc.

[0144] Computer 1602 can operate within a network environment using logical connections to one or more remote computers, such as remote computer 1650, via wired communication, wireless communication, or both. Remote computer 1650 can be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer device, or other common network node, and typically includes many or all of the elements described in relation to computer 1602, but for the sake of brevity, only memory / storage device 1652 is shown. The logical connections shown in the figure include wired / wireless connections to a local area network (LAN) 1654 or a larger network (e.g., wide area network (WAN) 1656), or both. Such LAN and WAN network environments are common in offices and companies, facilitate enterprise-wide computer networks such as intranets, and all can be connected to a global communication network (e.g., the Internet).

[0145] When used within a LAN network environment, computer 1602 can be connected to local network 1654 via a wired, wireless, or both communication network interface or adapter 1658. Adapter 1658 can facilitate wired or wireless communication with LAN 1654, and LAN 1654 can also include a wireless access point (AP) arranged to communicate with adapter 1658 in wireless mode.

[0146] When used within a WAN network environment, computer 1602 can include a modem 1660 or can be connected to a communication server on WAN 1656 by other means for establishing communication, such as via the Internet. Modem 1660, which can be a wired or wireless device existing either internally or externally, can be connected to system bus 1608 via input device interface 1644. Program modules shown in relation to computer 1602 or portions thereof within the network environment can be stored in remote memory / storage device 1652. It will be understood that the network connections shown are examples and that other means of establishing communication links between computers can be used.

[0147] When used either within a LAN network environment or a WAN network environment, computer 1602 can access a cloud storage system or other network-based storage system in addition to or instead of external storage device 1616 as described above. Generally, the connection between computer 1602 and the cloud storage system can be established via LAN 1654 or WAN 1656, for example, by adapter 1658 or modem 1660 respectively. When connecting computer 1602 to an associated cloud storage system, external storage interface 1626 can manage the storage provided by the cloud storage system using adapter 1658 or modem 1660 or both, similar to other types of external storage. For example, external storage interface 1626 can be configured to provide access to the cloud storage source as if the cloud storage source were physically connected to computer 1602.

[0148] Computer 1602 can function to communicate with any wireless device or entity (e.g., a printer, scanner, desktop computer or portable computer or both, portable data assistant, communication satellite, any component or location of a device associated with a wirelessly detectable tag (e.g., a kiosk, newsstand, merchandise shelf, etc.), and a telephone) that is operably arranged in wireless communication. This communication can include wireless fidelity (Wi-Fi) and BLUETOOTH(R) wireless technologies. Thus, this communication can be in a pre-defined structure similar to a conventional network or simply be an ad hoc communication between at least two devices.

[0149] The foregoing content includes merely examples of a system, computer program product, and computer-implemented method. Of course, for the purpose of explaining the present disclosure, it is impossible to describe all possible combinations of components, products, or computer-implemented methods, or combinations thereof. However, those skilled in the art can recognize that many other combinations and permutations of the present disclosure are possible. Further, terms such as "including", "having", "possessing", etc., as used in the embodiments, claims, appendices, and drawings of the invention, are intended to be inclusive in the same manner as the term "comprising" is construed when used as a transitional term in the claims, i.e., as including the recited elements but not excluding other elements. The descriptions of the various embodiments are presented for purposes of illustration but are not intended to be exhaustive or limited to the disclosed embodiments. It will be apparent to those skilled in the art that many changes and modifications are possible without departing from the scope and spirit of the described embodiments. The terms used herein are selected in order to best explain the principles of the embodiments, the practical application, or a technical improvement over technologies found in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

Claims

1. A system comprising a memory storing computer-executable components, and a processor operably coupled to the memory and executing the computer-executable components stored in the memory, wherein the computer-executable components include an interpolation component that interpolates gate parameters associated with a target stretch factor from a reference model, and the reference model includes reference gate parameters of quantum gates calibrated with a plurality of reference stretch factors.

2. The system of claim 1, further comprising a model component that defines the plurality of reference stretch factors by determining the number of reference stretch factors within a stretch factor interval based on at least one of determination of per-gate errors and determination of gate parameters.

3. The system of claim 2, wherein the number of reference stretch factors included within the stretch factor interval increases with the number of changes in the determination of per-gate errors within the stretch factor interval.

4. The system of claim 3, wherein the number of reference stretch factors included within the stretch factor interval increases with the number of changes in the determination of gate parameters within the stretch factor interval.

5. An execution component that generates result data by performing a quantum operation on a quantum circuit using the interpolated gate parameters, the quantum circuit including the quantum gate, and a reduction component that generates a result with reduced error by extrapolating the result data to a zero-th noise limit, the system according to any one of claims 1 to 4.

6. The system according to any one of claims 1 to 5, further comprising a recommendation component that identifies the target stretch factor based on the number of gates and the number of qubits of a quantum circuit including the quantum gate.

7. A computer-implemented method including interpolating, by a system operably coupled to a processor, gate parameters associated with a target stretch factor from a reference model, the reference model including reference gate parameters of quantum gates calibrated with a plurality of reference stretch factors.

8.

7. A system comprising a memory storing computer-executable components, and a processor operably coupled to the memory and executing the computer-executable components stored in the memory, wherein the computer-executable components include an interpolation component that interpolates gate parameters associated with a target stretch factor from a reference model, and the reference model includes reference gate parameters of quantum gates calibrated with a plurality of reference stretch factors.

8. The computer-implemented method according to claim 7, further comprising determining, by the system, the number of reference elongation coefficients included within an elongation coefficient interval based on at least one of a determination of an error for each gate and a determination of gate parameters.

9. The computer-implemented method according to claim 8, wherein the number of reference elongation coefficients included within the elongation coefficient interval increases with the number of changes in the determination of the error for each gate within the elongation coefficient interval, and the number of reference elongation coefficients included within the elongation coefficient interval increases with the number of changes in the determination of the gate parameters within the elongation coefficient interval.

10. Generating result data by the system by performing a quantum operation on a quantum circuit using the interpolated gate parameters, the quantum circuit including the quantum gate, and The computer-implemented method according to any one of claims 7 to 9, further comprising generating, by the system, a result with reduced error by extrapolating the result data to the zero-point noise limit.

11. The computer-implemented method according to claim 10, further comprising identifying, by the system, the target elongation coefficient based on the number of gates and the number of qubits of the quantum circuit including the quantum gate.

12. A computer program for error reduction of a quantum computer, the computer program causing a computer to generate a range of elongation coefficients associated with a quantum gate with a plurality of reference elongation coefficients, receive an elongation coefficient from the range of elongation coefficients, and interpolate gate parameters associated with the elongation coefficient based on the plurality of reference elongation coefficients.

13. The computer program according to claim 12, further causing the computer to define the plurality of reference elongation coefficients by determining the number of reference elongation coefficients within an elongation coefficient interval based on at least one of a determination of an error for each gate and a determination of gate parameters.

14. The computer program according to any one of claims 12 or 13, further causing the computer to identify a recommended elongation coefficient from the range of elongation coefficients based on the number of gates and the number of qubits of the quantum circuit including the quantum gate.

15. The computer program according to claim 14, further causing comparison of the number of gates and the number of qubits of the quantum circuit with a reference table including a range of expansion coefficients associated with a combination of a defined number of gates and a number of qubits.

16. generating result data by performing a quantum operation on a quantum circuit including the quantum gate using the gate parameter; The computer program according to any one of claims 12 to 15, further causing generation of a result with reduced error by extrapolating the result data to the zero-th noise limit.

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