Adjustable quantum coupler facilitating quantum gates between qubits

Abstract

[0003] Devices and / or computer-implemented methods are provided for facilitating quantum gates between qubits using tunable couplers and capacitor devices. According to one embodiment, the quantum coupler device can include a tunable coupler coupled between like-polarity terminals of a first qubit and a second qubit, the tunable coupler configured to control a first coupling between the first qubit and the second qubit. The quantum coupler device can further include a capacitor device coupled to opposite-polarity terminals of the first qubit and the second qubit, the capacitor device configured to provide a second coupling that is opposite in sign to the first coupling.

Description

Technical Field

[0001] The present disclosure relates to a quantum coupler, and more particularly, to a quantum coupler that facilitates quantum gates between qubits (qubits).

Background Art

[0002] In large-scale quantum computing processors, nearest-neighbor qubits are coupled together to generate qubit-qubit interactions involved in the execution of quantum gates. When the interaction is always on, unwanted coherent rotations or coherent qubit errors or both occur on spectator qubits (e.g., adjacent qubits), resulting in gate errors during quantum computing. Such coherent rotations or coherent qubit errors or both limit the performance of qubits and currently impede the progress of quantum computing processors. The coupling between adjacent qubits is the main cause of coherent qubit errors, specifically ZZ errors.

[0003] In some prior arts, attempts have been made to eliminate such coherent rotations or coherent qubit errors (e.g., ZZ errors) or both by coupling an adjustable coupler to the qubits used to execute quantum gates. A problem with such prior arts is that the adjustable coupler is designed to operate at a resonance frequency above the resonance frequency of the qubit. In the case of a resonance frequency above the resonance frequency of the qubit, the ZZ turn-on becomes small and it becomes more difficult to achieve fast gates due to a wide range of detuning.

Summary of the Invention

[0004] To provide a basic understanding of one or more embodiments of the present invention, an overview is presented below. This overview is not intended to identify key elements or essential elements, nor to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, a system, device, computer-implemented method, or computer program product, or a combination thereof, will be described that uses an adjustable coupler and a capacitor device to facilitate quantum gates between qubits.

[0005] According to one embodiment, a quantum coupler device can include an adjustable coupler configured to be coupled between terminals of the same polarity of a first qubit and a second qubit and to control a first coupling between the first qubit and the second qubit. The quantum coupler device can further include a capacitor device configured to be coupled to terminals of opposite polarity of the first qubit and the second qubit and to provide a second coupling having an opposite sign with respect to the first coupling. The advantage of such a quantum coupler device is that such a quantum coupler device can improve the speed of quantum gates (e.g., shorten the time taken to complete an operation on a qubit).

[0006] In some embodiments, the adjustable coupler is configured to control a first coupling, and the capacitor device is configured to provide a second coupling to eliminate coherent rotation between a first qubit and a second qubit, thereby reducing quantum gate errors associated with at least one of the first qubit or the second qubit, speeding up quantum gates including the first qubit and the second qubit, improving the performance of a quantum processor comprising a quantum coupler device, or improving the fidelity of a quantum processor comprising a quantum coupler device. The advantage of such a quantum coupler device is that such a quantum coupler device turns off the coupling between the first qubit and the second qubit, thereby eliminating coherent rotation or coherent qubit errors or both in at least one of the first qubit or the second qubit or both that cause gate errors during quantum computing.

[0007] According to another embodiment, a computer-implemented method of quantum coupling can include providing an adjustable coupling between terminals of the same polarity of a first qubit and a second qubit by a system operably coupled to a processor. The computer-implemented method of quantum coupling can further include providing a capacitive coupling between terminals of opposite polarities of the first qubit and the second qubit by the system. The computer-implemented method of quantum coupling can further include adjusting a resonance frequency associated with the adjustable coupling by the system. When the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit, the capacitive coupling generates a coupling that cancels the adjustable coupling. The advantage of such a computer-implemented method of quantum coupling is that such a computer-implemented method of quantum coupling can be implemented to improve the speed of quantum gates (e.g., reduce the time taken to complete an operation on a qubit).

[0008] In some embodiments, when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit, the system eliminates coherent rotation in at least one of the first qubit or the second qubit based on a coupling that cancels the adjustable coupling, thereby reducing quantum gate errors associated with at least one of the first qubit or the second qubit, accelerating quantum gates including the first qubit and the second qubit, improving the performance of the quantum processor, or improving the fidelity of the quantum processor. The advantage of such a computer-implemented method of quantum coupling is that by implementing such a computer-implemented method of quantum coupling, the coupling between the first qubit and the second qubit is turned off, thereby eliminating coherent rotation or coherent qubit errors or both in at least one of the first qubit or the second qubit or both that cause gate errors during quantum computing.

[0009] According to another embodiment, the quantum coupler device can include an adjustable coupler coupled between the first qubit and the second qubit. The quantum coupler device can further include a capacitor device coupled between the first qubit and the second qubit. The capacitor device generates a coupling with a sign opposite to that of the coupling from the adjustable coupler based on the resonance frequency of the adjustable coupler being less than the resonance frequencies of both the first qubit and the second qubit. The advantage of such a quantum coupler device is that such a quantum coupler device can improve the speed of quantum gates (e.g., reduce the time taken to complete an operation on a qubit).

[0010] In some embodiments, the adjustable coupler is configured to control a first coupling, and the capacitor device provides a second coupling to eliminate coherent rotation between a first qubit and a second qubit, thereby reducing quantum gate errors associated with at least one of the first qubit or the second qubit, accelerating quantum gates including the first qubit and the second qubit, improving the performance of a quantum processor comprising the quantum coupler device, or improving the fidelity of a quantum processor comprising the quantum coupler device. The advantage of such a quantum coupler device is that such a quantum coupler device turns off the coupling between the first qubit and the second qubit, thereby eliminating coherent rotation or coherent qubit errors or both in the first qubit or the second qubit or both, which cause gate errors during quantum computing.

[0011] According to another embodiment, the device can comprise a first adjustable coupler coupled between terminals of the same polarity of the first qubit and the second qubit and configured to control a first coupling between the first qubit and the second qubit. The device can further comprise a first capacitor device coupled to terminals of opposite polarity of the first qubit and the second qubit and configured to provide a second coupling having an opposite sign with respect to the first coupling. The device can further comprise a second adjustable coupler coupled between terminals of the same polarity of the second qubit and the third qubit and configured to control a third coupling between the second qubit and the third qubit. The device can further comprise a second capacitor device coupled to terminals of opposite polarity of the second qubit and the third qubit and configured to provide a fourth coupling having an opposite sign with respect to the third coupling. An advantage of such a device is that such a device can improve the speed of quantum gates (e.g., reduce the time taken to complete an operation on a qubit).

[0012] In some embodiments, the first adjustable coupler or the second adjustable coupler is configured to control the first coupling or the third coupling, respectively, and the first capacitor device or the second capacitor device provides the second coupling or the fourth coupling, respectively, to eliminate coherent rotations between the first qubit and the second qubit or between the second qubit and the third qubit, thereby facilitating at least one of: reduction of quantum gate errors associated with at least one of the first qubit, the second qubit, or the third qubit; acceleration of quantum gates including the first qubit and the second qubit or the second qubit and the third qubit; improvement in the performance of a quantum processor comprising the device; or improvement in the fidelity of a quantum processor comprising the device. The advantage of such a device is that such a device turns off the coupling between the first qubit and the second qubit or between the second qubit and the third qubit, thereby eliminating coherent rotations or coherent qubit errors or both in the first qubit, the second qubit, or the third qubit or combinations thereof that cause gate errors during quantum computing.

[0013] According to another embodiment, a computer-implemented method can include providing, by a system operably coupled to a processor, a first adjustable coupling between terminals of the same polarity of a first qubit and a second qubit and a second adjustable coupling between terminals of the same polarity of a second qubit and a third qubit. The computer-implemented method can further include providing, by the system, a first capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit and a second capacitive coupling between terminals of opposite polarity of the second qubit and the third qubit. The computer-implemented method can further include adjusting, by the system, a first resonance frequency associated with the first adjustable coupling and a second resonance frequency associated with the second adjustable coupling. The first capacitive coupling includes a first coupling that cancels the first adjustable coupling when the first resonance frequency is less than a third resonance frequency of both the first qubit and the second qubit, and the second capacitive coupling includes a second coupling that cancels the second adjustable coupling when the second resonance frequency is less than a fourth resonance frequency of both the second qubit and the third qubit. An advantage of such a computer-implemented method is that such a computer-implemented method can be implemented to improve the speed of quantum gates (e.g., reduce the time taken to complete an operation on a qubit).

[0014] In some embodiments, the computer-implemented method further includes, by a system, eliminating coherent rotations in at least one of a first qubit, a second qubit, or a third qubit based on at least one of a first adjustable coupling or a second adjustable coupling, thereby facilitating at least one of a reduction of quantum gate errors associated with the first qubit, the second qubit, or the third qubit, an acceleration of quantum gates including the first qubit and the second qubit or the second qubit and the third qubit, an improvement in the performance of a quantum processor, or an improvement in the fidelity of a quantum processor. The advantage of such a computer-implemented method is that by implementing such a computer-implemented method, the coupling between the first qubit and the second qubit or the coupling between the second qubit and the third qubit can be turned off, thereby eliminating coherent rotations or coherent qubit errors or both in the first qubit, the second qubit, or the third qubit or a combination thereof that cause gate errors during quantum computing.

Brief Description of the Drawings

[0015]

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DETAILED DESCRIPTION OF THE INVENTION

[0016] The following detailed description is merely exemplary and is not intended to limit embodiments, or the application or use of embodiments, or both. Further, there is no intention to be bound by the explicit or implicit information presented in the foregoing sections of the technical field or the summary of the invention or the section of the mode for carrying out the invention.

[0017] Next, one or more embodiments will be described with reference to the drawings, and throughout, like reference numerals are used to refer to like elements. In the following description, numerous specific details are set forth for the purpose of providing a more thorough understanding of one or more embodiments. However, it will be apparent in various instances that one or more embodiments may be practiced without these specific details.

[0018] Quantum computing generally involves using quantum mechanical phenomena for the purpose of performing computing and information processing functions. Quantum computing can generally be seen as contrasting with classical computing, which uses transistors to perform operations on binary values. That is, a classical computer can perform operations on bit values that are either 0 or 1, while a quantum computer can perform operations on qubits (quantum bits) that include superpositions of both 0 and 1, entangle multiple qubits, and use interference.

[0019] Considering the above problems with the prior art, implementing the present disclosure results in a quantum coupler device comprising an adjustable coupler coupled between a first qubit and a second qubit, and a capacitor device coupled between the first qubit and the second qubit, which can facilitate a quantum gate (e.g., a controlled phase (C-phase) gate) between the first qubit and the second qubit, in the form of a device or a computer-implemented method or both, generating a solution to these problems, where the capacitor device generates a coupling opposite in sign to the coupling from the adjustable coupler based on the resonance frequency of the adjustable coupler being smaller than the resonance frequencies of both the first qubit and the second qubit. The advantage of such a device or a computer-implemented method or both is that implementing them can improve the speed of the quantum gate (e.g., shorten the time taken to complete an operation on the qubit).

[0020] In some embodiments, implementing the present disclosure results in a device or a computer-implemented method or both in the form of facilitating a quantum gate (e.g., a C-phase gate) between a first qubit and a second qubit using the above-described quantum coupler device, generating a solution to these problems, where the adjustable coupler is configured to control a first coupling, and the capacitor device is configured to provide a second coupling to eliminate coherent rotation between the first qubit and the second qubit. The advantage of such a device or a computer-implemented method or both is that implementing them can turn off the coupling between the first qubit and the second qubit, thereby eliminating coherent rotation or coherent qubit error or both in the first qubit or the second qubit or both that cause gate errors during quantum computing.

[0021] When an element is referred to as being "coupled" to another element, it can be understood to represent one or more of various types of couplings including, but not limited to, a communication coupling, an electrical coupling, an electromagnetic coupling, an operational coupling, an optical coupling, a physical coupling, a thermal coupling, or another type of coupling or a combination thereof. It should also be understood that the following terms referred to in this specification are defined as follows.

[0022] Quantum gate - Can represent an operation performed on a qubit.

[0023] C-phase - Can indicate a controlled phase gate. The Z rotation of one qubit is defined by the state of another qubit.

[0024] ZZ - Can indicate a state-dependent qubit interaction that can be used to form a C-phase gate.

[0025] Flux tunable - Can indicate a device whose frequency depends on the magnetic flux.

[0026] Transmon - A type of superconducting qubit where the charging energy Ec is much smaller than the Josephson energy Ej.

[0027] FIG. 1 shows a circuit diagram of an exemplary and non-limiting device 100 that can facilitate quantum gates between qubits using an adjustable coupler and a capacitor device according to one or more embodiments described herein. Device 100 can comprise a semiconductor device, a superconducting device, or both, that can be implemented within a quantum device. For example, device 100 can comprise an integrated semiconductor circuit, a superconducting circuit (e.g., a quantum circuit), or both, that can be implemented within a quantum device such as, for example, a quantum hardware, a quantum processor, a quantum computer, or another quantum device or combination thereof. Device 100 can comprise a semiconductor device, a superconducting device, or both, such as, for example, a quantum coupler device, an adjustable quantum coupler device, or both, that can be implemented within such a quantum device as defined above.

[0028] As illustrated by the exemplary embodiment shown in FIG. 1, device 100 can include an adjustable coupler 102 (shown as a coupler qubit in FIG. 1 and as coupler qubit 1 in FIG. 2) that can be coupled between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)) of a first qubit 106a (shown as Q1 in FIG. 1) and a second qubit 106b (shown as Q2 in FIG. 1). The adjustable coupler 102, illustrated in the exemplary embodiment shown in FIG. 1, can include a superconducting quantum interference device (SQUID) 118 (referred to herein as SQUID 118). In the exemplary embodiment shown in FIG. 1, SQUID 118 can include two Josephson junctions 120a, 120b (shown as Xs in FIG. 1, respectively) and a capacitor 122a. In various embodiments, SQUID 118 can be used to control the adjustability of adjustable coupler 102 as described herein (e.g., by applying a magnetic flux through SQUID 118). The first qubit 106a and the second qubit 106b, illustrated in the exemplary embodiment shown in FIG. 1, can each include a Josephson junction 120c and 120d (shown as Xs in FIG. 1, respectively) and capacitors 122b and 122c.

[0029] As illustrated by the exemplary embodiment shown in FIG. 1, the adjustable coupler 102 can be coupled between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)) of the first qubit 106a and the second qubit 106b via capacitive coupling visually represented as capacitor 108a and capacitor 108b, respectively, in FIG. 1. The adjustable coupler 102 can comprise an adjustable coupler including, but not limited to, a flux adjustable coupler, an adjustable coupler - qubit, a flux adjustable coupler - qubit, an adjustable qubit, an adjustable bus, a flux adjustable qubit - bus, or another adjustable coupler or combination thereof. The first qubit 106a or the second qubit 106b or both can include a qubit including, but not limited to, a fixed - frequency qubit, an adjustable qubit, a transmon - qubit, a fixed - frequency transmon - qubit, an adjustable transmon - qubit, or another qubit or combination thereof.

[0030] As illustrated by the exemplary embodiment shown in FIG. 1, device 100 can further include a capacitor device 110 (shown as a bypass capacitor in FIG. 1 and as bypass capacitor 1 in FIG. 2) that can be coupled to terminals 104a and 104c of opposite polarities (e.g., positive (+) and negative (-)) of the first qubit 106a and the second qubit 106b. As illustrated by the exemplary embodiment shown in FIG. 1, capacitor device 110 can include a first terminal 112a and a second terminal 112b that can cross-couple between the first qubit 106a and the second qubit 106b, and tunable coupler 102 can directly couple between the first qubit 106a and the second qubit 106b. For example, as illustrated in FIG. 1, the first terminal 112a of capacitor device 110 can be coupled to terminal 104a of the first qubit 106a, and the second terminal 112b of capacitor device 110 can be coupled to terminal 104c of the second qubit 106b. Capacitor device 110 can include a capacitor device including, but not limited to, a differential capacitor (e.g., a capacitor connecting opposite voltage paddles of a transmon qubit), a bypass capacitor, or another capacitor device or combination thereof.

[0031] Hereinafter, design rules regarding the capacitor device 110 or the second capacitor device 210 of the device 200 described later with reference to FIG. 2, which can be implemented according to one or more embodiments of the present disclosure described in this specification, or both will be described. In various embodiments, the adjustable coupler 102 or the second adjustable coupler 202 of the device 200 described later with reference to FIG. 2, or both, can approximate the exchange interaction (J) between the first qubit 106a and the second qubit 106b, or between the second qubit 106b and the third qubit 206 of the device 200 described later with reference to FIG. 2, or both, according to the following formula (1). It should be understood that in these embodiments, by adopting the formula (1) defined below, it is further understood that one or more design specifications of the capacitor device 110 of the device 100 or the second capacitor device 210 of the device 200, or both, can be estimated.

[0032] Formula (1)

Number

[0033] In some embodiments, the bypass capacitance associated with the capacitor device 110 or the second capacitor device 210 of the device 200 described below with reference to FIG. 2, or both, can be set to create a qubit-to-qubit coupling with a sign that is the opposite of J (e.g., via the computer 1012, the system memory 1016, the processing unit 1014, the AWG, the VNA, etc.) and a magnitude that is greater than or equal to the magnitude of J. For example, in these embodiments, the bypass capacitance associated with the capacitor device 110 or the second capacitor device 210 of the device 200 described below with reference to FIG. 2, or both, can be set based on the following device parameters (e.g., via the computer 1012, the system memory 1016, the processing unit 1014, the AWG, the VNA, etc.). 1,1 and a magnitude that is the opposite of J 1,1 and greater than or equal to the magnitude of J. For example, in these embodiments, the bypass capacitance associated with the capacitor device 110 or the second capacitor device 210 of the device 200 described below with reference to FIG. 2, or both, can be set based on the following device parameters (e.g., via the computer 1012, the system memory 1016, the processing unit 1014, the AWG, the VNA, etc.).

[0034] 1) The anharmonicities of qubits δ1 and δ2 (e.g., the anharmonicities δ1 and δ2 of the first qubit 106a and the second qubit 106b respectively, or the second qubit 106b and the third qubit 206 of the device 200 described below with reference to FIG. 2, or both)

[0035] 2) The couplings between the qubits and the adjustable couplers g1 and g2 (e.g., the couplings g1 and g2 between the first qubit 106a and the second qubit 106b respectively and the adjustable coupler 102, or between the second qubit 106b and the third qubit 206 respectively and the second adjustable coupler 202 of the device 200 described below with reference to FIG. 2, or both)

[0036] In various embodiments, the tunable coupler 102 may be configured to generate or control or both a first coupling 114 (e.g., a tunable coupling not shown in FIG. 1) between the first qubit 106a and the second qubit 106b. In various embodiments, the capacitor device 110 may be configured to generate or provide or both a second coupling 116 (e.g., a capacitive coupling not shown in FIG. 1) having an opposite sign with respect to the first coupling 114 between the first qubit 106a and the second qubit 106b, and the first coupling 114 may be generated or controlled or both by the tunable coupler 102 as described above. In these embodiments, the capacitor device 110 may be capable of generating or providing or both the second coupling 116 based on the resonant frequency of the tunable coupler 102 being less than the resonant frequencies of both the first qubit 106a and the second qubit 106b, as described below. For example, in these embodiments, the capacitor device 110 may be capable of generating or providing or both the second coupling 116 based on the resonant frequency of the tunable coupler 102 being less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b, and such resonant frequencies of the first qubit 106a and the second qubit 106b may be the same or different.

[0037] In an exemplary embodiment, although not shown in FIG. 1, the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof can be coupled to a pulse generator device that can be external to the device 100. For example, in one exemplary embodiment, the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof can be coupled to a pulse generator device including, but not limited to, an arbitrary waveform generator (AWG), a vector network analyzer (VNA), or another pulse generator device or a combination thereof that can transmit or receive or both transmit and receive pulses (e.g., microwave pulses) between the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof, and such a pulse generator device can be external to the device 100. In this exemplary embodiment, such a pulse generator device (e.g., AWG, VNA, etc.) can also be coupled to a computer (e.g., computer 1012 described below with reference to FIG. 10) having a memory (e.g., system memory 1016 described below with reference to FIG. 10) capable of storing instructions (e.g., software, routines, processing threads, etc.) and a processor (e.g., processing unit 1014 described below with reference to FIG. 10) capable of executing such instructions stored on the memory. In this exemplary embodiment, such a computer can be employed to operate or control or both operate and control such a pulse generator device (e.g., AWG, VNA, etc.) (e.g., via the processing unit 1014 executing instructions stored in the system memory 1016), whereby the pulse generator device can transmit or receive or both transmit and receive pulses (e.g., microwave pulses) between the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof.

[0038] Continuing with the above exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), adjustable coupler 102 can provide an adjustable coupling (e.g., first coupling 114) between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)) of first qubit 106a and second qubit 106b. In this exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), capacitor device 110 can provide a capacitive coupling (e.g., second coupling 116) between terminals 104a and 104c of opposite polarities (e.g., positive (+) and negative (-)) of first qubit 106a and second qubit 106b. In this exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), adjustable coupler 102 can further adjust the resonance frequency associated with the adjustable coupling (e.g., first coupling 114), and when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both first qubit 106a and second qubit 106b (e.g., less than the resonance frequency of first qubit 106a and less than the resonance frequency of second qubit 106b), the capacitive coupling (e.g., second coupling 116) generates a coupling that cancels the adjustable coupling.

[0039] Continuing with the above exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), device 100 can facilitate performing a quantum gate between the first qubit 106a and the second qubit 106b. For example, as will be described later with reference to FIG. 3, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), the adjustable coupler 102 can adjust the resonance frequency associated with an adjustable coupling (e.g., the first coupling 114) such that the resonance frequency approaches the resonance frequencies of the first qubit 106a and the second qubit 106b, increasing the ZZ.

[0040] In various embodiments, the adjustable coupler 102 may be configured to control the first coupling 114 (e.g., via computer 1012, system memory 1016, processing unit 1014, AWG, VNA, etc.), and the capacitor device 110 may provide a second coupling 116 (e.g., via computer 1012, system memory 1016, processing unit 1014, AWG, VNA, etc.) to eliminate coherent rotations or coherent qubit errors (e.g., ZZ errors) or both in the first qubit 106a, the second qubit 106b, or an adjacent qubit 106c (not shown in FIG. 1) or a combination thereof. In these embodiments, such an adjacent qubit 106c can include qubits that may be formed on the device 100 at a position adjacent to the first qubit 106a or the second qubit 106b or both. In these embodiments, as described above, based on receiving a pulse (e.g., a microwave pulse) from a pulse generator device (e.g., AWG, VNA, etc.) (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), the adjustable coupler 102 and the capacitor device 110 can separate the first qubit 106a from the second qubit 106b and / or separate the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b.In these embodiments, when the resonance frequency associated with the adjustable coupling (e.g., the resonance frequency associated with the adjustable coupler 102) is less than the resonance frequencies of both the first qubit 106a and the second qubit 106b (e.g., less than the resonance frequency of the first qubit 106a and less than the resonance frequency of the second qubit 106b), the adjustable coupler 102 and the capacitor device 110 can, based on (e.g., using) the capacitive coupling (e.g., the second coupling 116) that can cancel the adjustable coupling (e.g., the first coupling 114), separate the first qubit 106a from the second qubit 106b and / or separate the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b. In these embodiments, based on such separation of the first qubit 106a from the second qubit 106b and / or separation of the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b, the adjustable coupler 102 and the capacitor device 110 can thereby eliminate coherent rotation or coherent qubit error (e.g., ZZ error) or both in the first qubit 106a, the second qubit 106b, or the adjacent qubit 106c or a combination thereof. In these embodiments, based on such elimination of coherent rotation or coherent qubit error or both, the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof can thereby facilitate reduction of quantum gate error associated with the first qubit 106a, the second qubit 106b, or the adjacent qubit 106c or a combination thereof, speed up quantum gates including the first qubit 106a and the second qubit 106b, improve the performance of a quantum processor comprising the device 100 (which can comprise a quantum coupler device, for example), or improve the fidelity of such a quantum processor comprising the device 100, or a combination thereof.

[0041] FIG. 2 shows a circuit diagram of an exemplary and non - limiting device 200 that can facilitate quantum gates between qubits using an adjustable coupler and capacitor devices according to one or more embodiments described herein. Device 200 can include an exemplary and non - limiting alternative embodiment of device 100, and device 200 can include additional adjustable couplers and additional capacitor devices coupled to a second qubit 106b and further coupled to additional qubits. For the sake of brevity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0042] As illustrated by the exemplary embodiment shown in FIG. 2, device 200 can include a second adjustable coupler 202 (designated as coupler - qubit 2 in FIG. 2) that can be coupled between terminals 204a and 204b of the same polarity (e.g., positive (+) or negative (-)) of a second qubit 106b and a third qubit 206 (designated as Q3 in FIG. 2). The second adjustable coupler 202 illustrated in the exemplary embodiment shown in FIG. 2 can include a superconducting quantum interference device (SQUID) 220 (referred to herein as SQUID220). In the exemplary embodiment shown in FIG. 2, SQUID220 can include two Josephson junctions 222a, 222b (each designated as X in FIG. 2) and a capacitor 224a. In various embodiments, SQUID220 can be used to control the adjustability of the second adjustable coupler 202 as described herein (e.g., by applying a magnetic flux through SQUID220). The third qubit 206 illustrated in the exemplary embodiment shown in FIG. 2 can include a Josephson junction 222c (designated as X in FIG. 2) and a capacitor 224b.

[0043] As illustrated by the exemplary embodiment shown in FIG. 2, the adjustable coupler 202 can be coupled between terminals 204a and 204b of the same polarity (e.g., positive (+) or negative (-)) of the second qubit 106b and the third qubit 206 via capacitive coupling visually represented as capacitor 208a and capacitor 208b, respectively, in FIG. 2. The second adjustable coupler 202 can comprise an adjustable coupler including, but not limited to, a flux adjustable coupler, an adjustable coupler - qubit, a flux adjustable coupler - qubit, an adjustable qubit, an adjustable bus, a flux adjustable qubit - bus, or another adjustable coupler or combination thereof. The third qubit 206 can include a qubit including, but not limited to, a fixed - frequency qubit, an adjustable qubit, a transmon qubit, a fixed - frequency transmon qubit, an adjustable transmon qubit, or another qubit or combination thereof.

[0044] As illustrated by the exemplary embodiment shown in FIG. 2, device 200 can further include a second capacitor device 210 (designated as bypass capacitor 2 in FIG. 2) that can be coupled to terminals 204a and 204c of opposite polarities (e.g., positive (+) and negative (-)) of the second qubit 106b and the third qubit 206. As illustrated by the exemplary embodiment shown in FIG. 2, the second capacitor device 210 can include a first terminal 212a and a second terminal 212b that can cross-couple between the second qubit 106b and the third qubit 206, and the second adjustable coupler 202 can directly couple between the second qubit 106b and the third qubit 206. For example, as illustrated in FIG. 2, the first terminal 212a of the second capacitor device 210 can be coupled to the terminal 204a of the second qubit 106b, and the second terminal 212b of the second capacitor device 210 can be coupled to the terminal 204c of the third qubit 206. The second capacitor device 210 can include a capacitor device including, but not limited to, a differential capacitor (e.g., a capacitor connecting opposite voltage paddles of a transmon qubit), a bypass capacitor, or another capacitor device or a combination thereof.

[0045] In various embodiments, the second adjustable coupler 202 may be configured to generate or control or both generate and control a third coupling 214 (e.g., a second adjustable coupling not shown in FIG. 2) between the second qubit 106b and the third qubit 206. In various embodiments, the second capacitor device 210 is configured to generate or provide or both generate and provide a fourth coupling 216 (e.g., a second capacitive coupling not shown in FIG. 2) that is opposite in sign to the third coupling 214 between the second qubit 106b and the third qubit 206, and the third coupling 214 may be generated or controlled or both by the second adjustable coupler 202 as described above. In these embodiments, the second capacitor device 210 is capable of generating or providing or both generating and providing the fourth coupling 216 based on the resonant frequency of the first adjustable coupler 202 being less than the resonant frequency of the second qubit 106b or the third qubit 206 or both (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206) as described below.

[0046] In an exemplary embodiment, although not shown in FIG. 2, the device 200, the adjustable coupler 102, the capacitor device 110, the second adjustable coupler 202, or the second capacitor device 210 or a combination thereof can be external to the device 200 and can transmit or receive or both transmit and receive a pulse (e.g., a microwave pulse) between the device 200, the adjustable coupler 102, the capacitor device 110, the second adjustable coupler 202, or the second capacitor device 210 or a combination thereof, and can be coupled to a pulse generator device (e.g., an AWG, a VNA, etc.). In this exemplary embodiment, such a pulse generator device (e.g., an AWG, a VNA, etc.) can also be coupled to a computer (e.g., the computer 1012 described below with reference to FIG. 10) having a memory (e.g., the system memory 1016 described below with reference to FIG. 10) capable of storing instructions (e.g., software, routines, processing threads, etc.) and a processor (e.g., the processing unit 1014 described below with reference to FIG. 10) capable of executing such instructions stored on the memory. In this exemplary embodiment, such a computer can be employed to operate or control or both operate and control such a pulse generator device (e.g., an AWG, a VNA, etc.) (e.g., via the processing unit 1014 executing instructions stored in the system memory 1016), whereby the pulse generator device can transmit or receive or both transmit and receive a pulse (e.g., a microwave pulse) between the device 200, the adjustable coupler 102, the capacitor device 110, the second adjustable coupler 202, or the second capacitor device 210 or a combination thereof.

[0047] Continuing with the above exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), adjustable coupler 102 can provide an adjustable coupling (e.g., first coupling 114) between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)) of first qubit 106a and second qubit 106b, or second adjustable coupler 202 can provide a second adjustable coupling (e.g., third coupling 214) between terminals 204a and 204b of the same polarity (e.g., positive (+) or negative (-)) of second qubit 106b and third qubit 206, or both. In this exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), capacitor device 110 can provide a capacitive coupling (e.g., second coupling 116) between terminals 104a and 104c of opposite polarities (e.g., positive (+) and negative (-)) of first qubit 106a and second qubit 106b, or second capacitor device 210 can provide a second capacitive coupling (e.g., fourth coupling 216) between terminals 204a and 204c of opposite polarities (e.g., positive (+) and negative (-)) of second qubit 106b and third qubit 206, or both.In this exemplary embodiment, based on receiving a pulse from such a pulse generator device (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), adjustable coupler 102 can further adjust the resonance frequency associated with an adjustable coupling (e.g., first coupling 114), and when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit 106a and the second qubit 106b (e.g., less than the resonance frequency of the first qubit 106a and less than the resonance frequency of the second qubit 106b), capacitive coupling (e.g., second coupling 116) generates a coupling that cancels the adjustable coupling, or second adjustable coupler 202 can further adjust the resonance frequency associated with a second adjustable coupling (e.g., third coupling 214), and when the resonance frequency associated with the second adjustable coupling is less than the resonance frequencies of both the second qubit 106b and the third qubit 206 (e.g., less than the resonance frequency of the second qubit 106b and less than the resonance frequency of the third qubit 206), second capacitive coupling (e.g., fourth coupling 216) generates a coupling that cancels the second adjustable coupling, or both.

[0048] In various embodiments, the adjustable coupler 102 or the second adjustable coupler 202 may be configured to control the first coupling 114 or the third coupling 214, respectively (e.g., via computer 1012, system memory 1016, processing unit 1014, AWG, VNA, etc.), and the capacitor device 110 or the second capacitor device 210 may provide the second coupling 116 or the fourth coupling 216, respectively (e.g., via computer 1012, system memory 1016, processing unit 1014, AWG, VNA, etc.) to eliminate coherent rotations or coherent qubit errors (e.g., ZZ errors) or both in the first qubit 106a, the second qubit 106b, the third qubit 206, or an adjacent qubit 218 (not shown in FIG. 2) or a combination thereof. In these embodiments, such an adjacent qubit 218 may include qubits that may be formed on the device 200 at a position adjacent to the first qubit 106a, the second qubit 106b, or the third qubit 206 or a combination thereof.

[0049] In these embodiments, as described above, based on receiving a pulse (e.g., a microwave pulse) from a pulse generator device (e.g., AWG, VNA, etc.) (e.g., via computer 1012, system memory 1016, processing unit 1014, etc.), the adjustable coupler 102 and the capacitor device 110 can separate the first qubit 106a from the second qubit 106b and / or separate an adjacent qubit 218 from the first qubit 106a and / or the second qubit 106b. In these embodiments, as described above, based on receiving such a pulse from such a pulse generator device, the second adjustable coupler 202 and the second capacitor device 210 can separate the second qubit 106b from the third qubit 206 and / or separate an adjacent qubit 218 from the second qubit 106b and / or the third qubit 206.

[0050] In these embodiments, as described above, based on receiving such a pulse from such a pulse generator device, if the resonant frequency associated with the adjustable coupling (e.g., the resonant frequency associated with the adjustable coupler 102) is less than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b), the adjustable coupler 102 and the capacitor device 110 can, based on (e.g., using) the capacitive coupling (e.g., the second coupling 116) that can cancel the adjustable coupling (e.g., the first coupling 114), separate the first qubit 106a from the second qubit 106b and / or separate the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b. In these embodiments, as described above, based on receiving such a pulse from such a pulse generator device, if the resonant frequency associated with the second adjustable coupling (e.g., the resonant frequency associated with the second adjustable coupler 202) is less than the resonant frequencies of both the second qubit 106b and the third qubit 206 (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206), the second adjustable coupler 202 and the second capacitor device 210 can, based on (e.g., using) the second capacitive coupling (e.g., the fourth coupling 216) that can cancel the second adjustable coupling (e.g., the third coupling 214), separate the second qubit 106b from the third qubit 206 and / or separate the adjacent qubit 218 from the second qubit 106b and / or the third qubit 206.

[0051] In these embodiments, based on such separation of the first qubit 106a from the second qubit 106b, separation of the second qubit 106b from the third qubit 206, and / or separation of the adjacent qubits 218 from the second qubit 106b and / or the third qubit 206, the adjustable coupler 102 and the capacitor device 110, or the second adjustable coupler 202 and the second capacitor device 210, or both, thereby can eliminate coherent rotation or coherent qubit error (e.g., ZZ error) or both in the first qubit 106a, the second qubit 106b, the third qubit 206, or the adjacent qubits 218 or a combination thereof. In these embodiments, based on such elimination of coherent rotation or coherent qubit error or both in these embodiments, the device 200, the adjustable coupler 102, the capacitor device 110, the second adjustable coupler 202, or the second capacitor device 210 or a combination thereof thereby can facilitate reduction of quantum gate error associated with the first qubit 106a, the second qubit 106b, the third qubit 206, or the adjacent qubits 218 or a combination thereof, speeding up of quantum gates including the first qubit 106a and the second qubit 106b or the second qubit 106b and the third qubit 206, improvement of the performance of a quantum processor (which can include a quantum coupler device) comprising the device 200, or improvement of the fidelity of such a quantum processor comprising the device 200, or a combination thereof.

[0052] In an exemplary embodiment, during operation of device 200, to execute a quantum gate between the first qubit 106a and the second qubit 106b, the adjustable coupler 102 can be pulsed on, while the second adjustable coupler 202 remains off. Conversely, in this exemplary embodiment, during operation of device 200, to execute a quantum gate between the second qubit 106b and the third qubit 206, the second adjustable coupler 202 can be pulsed on, while the adjustable coupler 102 remains off. In one example, in a non-limiting alternative embodiment of device 200 that can include more qubits (e.g., four or more qubits, not shown), each pair of qubits between which a two-qubit quantum gate can be executed can have its own coupler-qubit (e.g., adjustable coupler 102 or second adjustable coupler 202) and bypass capacitor (e.g., capacitor device 110 or second capacitor device 210). In this exemplary and non-limiting alternative embodiment of device 200, one or more of the embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can be generalized (e.g., scaled) to correspond to a certain number (e.g., four or more) of qubits, or to various topologies (e.g., various superconducting circuit topologies), or both.

[0053] The manufacture of various embodiments of the present disclosure (e.g., devices 100, 200, etc.) described herein, illustrated in the figures, or both, can include a multi-step sequence of photolithography processing steps, chemical processing steps, or both, that facilitate the step-by-step creation of electronic-based systems, devices, components, or circuits, or combinations thereof, in semiconductor devices or superconducting devices (e.g., integrated circuits), or both. For example, various embodiments of the present disclosure (e.g., devices 100, 200, etc.) described herein, illustrated in the figures, or both, can be manufactured on a substrate (e.g., a silicon (Si) substrate, etc.) by employing techniques including, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive-tone photoresist, negative-tone photoresist, hybrid-tone photoresist, etc.), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), deposition techniques, sputtering techniques, plasma ashing techniques, heat treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, or another technique for manufacturing integrated circuits, or combinations thereof.

[0054] The various embodiments of the present disclosure (e.g., devices 100, 200, etc.) described in this specification, illustrated in the figures, or both, can be manufactured using various materials. For example, the various embodiments of the present disclosure (e.g., devices 100, 200, etc.) described in this specification, illustrated in the figures, or both, can be made using conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, non-conductive materials, or one or more other materials utilized using one or more of the above techniques for manufacturing integrated circuits, or combinations thereof, and can be manufactured using materials of one or more different material classes including but not limited to these.

[0055] FIG. 3 shows an exemplary and non-limiting graph 300 that can facilitate quantum gates between qubits using an adjustable coupler and capacitor device according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0056] Graph 300 can include result data obtained from implementing one or more embodiments of the present disclosure described herein. For example, graph 300 can include result data obtained from implementing device 100 according to one or more embodiments of the present disclosure described herein (e.g., computer-implemented method 500 or computer-implemented method 600 or both, described below with reference to FIGS. 5 and 6 respectively). In this example, as illustrated in FIG. 3, graph 300 can include a three-dimensional (3D) graph of result data obtained from implementing device 100, and this three-dimensional (3D) graph can be plotted as follows. The Y-axis (e.g., the vertical axis of graph 300) is qubit detuning represented in megahertz (MHz), the x-axis (e.g., the horizontal axis of graph 300) is the frequency of adjustable coupler 102 controlled by the magnetic flux passing through SQUID 118 of device 100 and can be represented in gigahertz (GHz) (displayed as the bus frequency in FIG. 3), and the Z-axis (e.g., the axis of graph 300 extending in and out of the page) is the ZZ interaction frequency represented by various gray shadings corresponding to frequencies in the range from 1 kHz to 1 MHz as indicated by the ZZ legend shown in FIG. 3.

[0057] In an exemplary embodiment, to create graph 300, the following parameters, namely Frequency of the first qubit 106a = 5 GHz, Frequency of the second qubit 106b = 5 GHz + detuning, Coupling between the first qubit 106a, the second qubit 106b, and adjustable coupler 102 = 60 megahertz MHz, and Direct coupling between the first qubit 106a and the second qubit 106b = -2 MHz are used to quantize device 100.

[0058] In an exemplary embodiment, to generate graph 300, device 100 can be quantized using the parameters defined above, and the frequency and detuning of tunable coupler 102 can vary. In this exemplary embodiment, based on such variations in the frequency and detuning of tunable coupler 102, the ZZ interaction between the first qubit 106a and the second qubit 106b can be calculated. In this exemplary embodiment, as illustrated by graph 300 shown in FIG. 3, region 302 near the frequency = 3.5 GHz of tunable coupler 102 is a place where the ZZ interaction is relatively small and can represent an operating point where tunable coupler 102 is off. In this exemplary embodiment, to form a two-qubit gate between the first qubit 106a and the second qubit 106b, the frequency of tunable coupler 102 can be increased to a relatively large value (e.g., 5 GHz). For example, in this exemplary embodiment, by applying a magnetic flux passing through SQUID 118 (e.g., by providing a pulse via computer 1012, system memory 1016, processing unit 1014, AWG, VNA, etc. as described above with reference to FIG. 1), the frequency of tunable coupler 102 can be controlled (e.g., increased, decreased, etc.).

[0059] An exemplary and non-limiting alternative embodiment of graph 300 can include a two-dimensional representation of a plane extending across the entire graph 300, such a plane can be defined along line 304 shown in FIG. 3. For example, graph 400, described below and illustrated in FIG. 4, can include such an exemplary and non-limiting alternative embodiment of graph 300, and graph 400 can include a two-dimensional side view of such a plane extending across the entire graph 300 that can be defined along line 304 shown in FIG. 3.

[0060] FIG. 4 shows exemplary and non-limiting information 400 that can facilitate a quantum gate between qubits using an adjustable coupler and a capacitor device, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0061] As described above, graph 400 can include an exemplary and non-limiting alternative embodiment of graph 300, and graph 400 can include a two-dimensional side view of a plane extending across the entire graph 300 that can be defined along line 304 shown in FIG. 3. As illustrated in the exemplary embodiment shown in FIG. 4, graph 400 shows the ZZ interaction strength between a first qubit 106a and a second qubit 106b for a given set of device parameters (e.g., the device parameters defined above with reference to FIG. 3). In this exemplary embodiment, such ZZ interaction strength values are plotted on the Y-axis (e.g., the vertical axis) of graph 400 and correspond to various flux pulse values of the adjustable coupler 102 (displayed as F bus (GHz)) plotted along the X-axis (e.g., the horizontal axis) of graph 400. In the exemplary embodiment shown in FIG. 4, graph 400 can have a corresponding time graph 402 that shows the duration of each flux pulse that can be applied to device 100 (e.g., adjustable coupler 102, capacitor device 110, etc.) when implementing the quantum gate sequence described below.

[0062] Quantum gate sequence

[0063] As described above with reference to FIG. 3, the device 100 can be implemented (e.g., quantized, simulated, etc.) by providing a pulse to the adjustable coupler 102 that can turn the ZZ interaction on and off, and the resulting data obtained from such implementation can be plotted as the graphs 300, graph 400, or the time graph 402 shown in FIGS. 3 and 4, or a combination thereof. In the exemplary embodiments of the graph 400 and the time graph 402 illustrated in FIG. 4, the first step of the quantum gate sequence (e.g., between the first qubit 106a and the second qubit 106b) is indicated by the number 1 in the graph 400 and the time graph 402. In this exemplary embodiment, at step 1 of such a quantum gate sequence, the frequency (e.g., resonance frequency) of the adjustable coupler 102 (which can be provided with an adjustable bus, for example) is such that the ZZ interaction is negligible (e.g., when the flux pulse is 3.75 GHz, the corresponding ZZ interaction strength is about 10 -5 MHz). In this exemplary embodiment, the second step of such a quantum gate sequence is indicated by the number 2 in the graph 400 and the time graph 402. In this exemplary embodiment, at step 2 of such a quantum gate sequence, the frequency (e.g., resonance frequency) of the adjustable coupler 102 can be adjusted by a flux pulse (e.g., 4.50 GHz) to turn on the ZZ interaction between the first qubit 106a and the second qubit 106b. In this exemplary embodiment, the third step of such a quantum gate sequence is indicated by the number 3 in the graph 400 and the time graph 402. In this exemplary embodiment, at step 3 of such a quantum gate sequence, after the flux pulse ends, the frequency (e.g., resonance frequency) of the adjustable coupler 102 is returned to the off position, and the ZZ interaction between the first qubit 106a and the second qubit 106b becomes negligible again.

[0064] Various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can be associated with various technologies. For example, various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can be associated with quantum computing technology, quantum gate technology, quantum coupler technology, quantum hardware technology or software technology or both, quantum circuit technology, superconducting circuit technology, machine learning technology, artificial intelligence technology, cloud computing technology, or other technologies or combinations thereof.

[0065] Various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can provide technical improvements to systems, devices, components, operation steps, or processing steps or combinations thereof related to the various technologies identified above. For example, various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can provide an adjustable coupling between terminals of the same polarity of a first qubit (e.g., first qubit 106a) and a second qubit (e.g., second qubit 106b), can provide a capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit, or can adjust the resonance frequency associated with the adjustable coupling, or can perform a combination thereof, and when the resonance frequency associated with the adjustable coupling is smaller than the resonance frequencies of both the first qubit and the second qubit, the capacitive coupling generates a coupling that cancels the adjustable coupling. In this example, based on such cancellation of the adjustable coupling (e.g., zero setting, offset, negate, etc.), various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can thereby eliminate coherent rotations or coherent qubit errors or both in the first qubit, the second qubit, or an adjacent qubit (e.g., adjacent qubit 106c) or a combination thereof that cause gate errors during quantum computing.In this example, various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) are based on such elimination of coherent rotations or coherent qubit errors or both in the first qubit, the second qubit, or adjacent qubits or combinations thereof, thereby facilitating reduction of quantum gate errors associated with the first qubit, the second qubit, or adjacent qubits or combinations thereof, acceleration of quantum gates including the first qubit and the second qubit, improvement in the performance of a quantum processor (e.g., a quantum processor including device 100 or device 200), or improvement in the fidelity of a quantum processor, or a combination thereof.

[0066] Various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can provide technical improvements to classical computing devices or quantum computing devices (e.g., quantum processors, quantum hardware, superconducting circuits, etc.) or both, which may be associated with one or more of the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.), or to processing units (e.g., a quantum processor including device 100 or device 200, processing unit 1014, etc.) associated with both. For example, as described above, by canceling (e.g., zeroing, offsetting, negating, etc.) adjustable couplings and eliminating coherent rotations or coherent qubit errors or both in a first qubit, a second qubit, or adjacent qubits or combinations thereof, one or more of the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can thereby facilitate a reduction in quantum gate errors associated with a first qubit, a second qubit, or adjacent qubits or combinations thereof, or an acceleration of quantum gates including the first qubit and the second qubit, or both. In this example, such a reduction in quantum gate errors or such an acceleration of quantum gates or both can facilitate an improvement in the performance of a quantum processor (e.g., a quantum processor including device 100 or device 200 and performing quantum gates), or an improvement in the fidelity of such a quantum processor, or both.

[0067] Based on the cancelation of adjustable couplings and the elimination of coherent rotations or coherent qubit errors or both in the first qubit, the second qubit, or adjacent qubits or combinations thereof as described above, the actual applications of the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) are to implement them in quantum devices (e.g., quantum processors, quantum computers, etc.) to provide one or more solutions (e.g., discovery problem-solving methods, etc.) to various problems covering complex ones (e.g., estimation problems, optimization problems, etc.) in various fields (e.g., finance, chemistry, medicine, etc.), which can be calculated more quickly and efficiently with improved fidelity. Based on the cancelation of adjustable couplings and the elimination of coherent rotations or coherent qubit errors or both in the first qubit, the second qubit, or adjacent qubits or combinations thereof as described above, one or more actual applications of the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) are, for example, to implement them in a quantum processor (e.g., a quantum processor comprising device 100 or device 200) to calculate one or more solutions (e.g., discovery problem-solving methods, etc.) to optimization problems in the fields of chemistry, medicine, or finance or combinations thereof, and such solutions can be used to design, for example, new compounds, new drugs, and / or new systems and / or methods for option pricing.

[0068] It should be understood that the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) provide new approaches brought about by relatively new quantum computing technologies. For example, the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) provide new approaches for eliminating unintentional coherent rotations or coherent qubit errors or both that occur in spectator qubits (e.g., the first qubit 106a, the second qubit 106b, or adjacent qubits 106c or combinations thereof) that result in gate errors during quantum computing. In this example, such new approaches for eliminating unintentional coherent rotations or coherent qubit errors or both can enable faster and more efficient quantum computing with improved fidelity using a quantum processor that includes one or more of the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.).

[0069] The various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can employ hardware or software to solve problems that are inherently highly technical, not abstract, and cannot be performed as a series of human intellectual acts. In some embodiments, one or more of the processes described herein can be performed by one or more dedicated computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, etc.) performing defined tasks related to the various technologies identified above. Newly arising problems can be solved by adopting the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) through the adoption of the above-described technological advancements, quantum computing systems, cloud computing systems, computer architectures, or another technology or combination thereof.

[0070] The various operations that can be performed by the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) are operations that exceed the capabilities of the human mind. Thus, it should be understood that the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can utilize various combinations of electrical components, mechanical components, and circuits that cannot be replicated or performed by humans even in the human mind. For example, the amount of data processed over a certain period of time by the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.), the speed at which such data is processed, or the type of data processed can be more, faster, or different compared to the amount, speed, or data type that a human mind can process over the same period of time.

[0071] According to some embodiments, the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can also operate overall for the purpose of performing one or more other functions while also performing the various operations described herein (e.g., being powered on overall, being executed overall, etc.). It should be understood that performing such multiple operations simultaneously exceeds the capabilities of the human mind. It should also be understood that the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can include information that cannot be manually obtained by an entity such as a human user. For example, the type, amount, or kind of information included in device 100 or device 200 or a combination thereof can be more complex than the information manually obtained by a human user.

[0072] FIG. 5 shows a flow diagram of an exemplary and non-limiting computer-implemented method 500 that can facilitate a quantum gate between qubits using an adjustable coupler and a capacitor device, according to one or more embodiments described herein. For simplicity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0073] At 502, computer-implemented method 500 can include providing an adjustable coupling (e.g., a first coupling 114) between terminals (e.g., between terminal 104a and terminal 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., a first qubit 106a and a second qubit 106b) by a system (e.g., a computer 1012 coupled operably to a processor (such as a processing unit 1014, etc.), coupled to an AWG or a VNA or both, and further coupled to a device 100, an adjustable coupler 102, or a capacitor device 110 or a combination thereof).

[0074] At 504, computer-implemented method 500 can include providing a capacitive coupling (e.g., a second coupling 116) between terminals (e.g., between terminal 104a and terminal 104c) of opposite polarities (e.g., positive (+) and negative (-)) of a first qubit and a second qubit by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to a device 100, an adjustable coupler 102, or a capacitor device 110 or a combination thereof).

[0075] In 506, computer-implemented method 500 can include adjusting a resonance frequency associated with an adjustable coupling by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), where the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both a first qubit and a second qubit (e.g., less than the resonance frequency of first qubit 106a and less than the resonance frequency of second qubit 106b), and where capacitive coupling generates a coupling that cancels the adjustable coupling.

[0076] FIG. 6 shows a flowchart of an exemplary and non-limiting computer-implemented method 600 that can facilitate a quantum gate between qubits using an adjustable coupler and a capacitor device, according to one or more embodiments described herein. For simplicity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0077] In 602, computer-implemented method 600 can include providing an adjustable coupling (e.g., first coupling 114) between terminals (e.g., between terminal 104a and terminal 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b) by a system (e.g., a system including a computer 1012 that can be coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof) operably coupled to a processor (e.g., processing unit 1014, etc.).

[0078] In 604, the computer-implemented method 600 can include providing capacitive coupling (e.g., the second coupling 116) between terminals (e.g., between terminal 104a and terminal 104c) of opposite polarities (e.g., positive (+) and negative (-)) of a first qubit and a second qubit by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof).

[0079] In 606, the computer-implemented method 600 can include adjusting a resonance frequency associated with an adjustable coupling by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), where when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit (e.g., less than the resonance frequency of the first qubit 106a and less than the resonance frequency of the second qubit 106b), the capacitive coupling generates a coupling that cancels the adjustable coupling.

[0080] In 608, the computer-implemented method 600 can include separating a first qubit from a second qubit based on a coupling that cancels an adjustable coupling when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit (e.g., less than the resonance frequency of the first qubit 106a and less than the resonance frequency of the second qubit 106b) by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof).

[0081] At 610, computer-implemented method 600, by a system (e.g., a computer 1012 coupled to an AWG or VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), when the resonant frequency associated with the adjustable coupling is less than the resonant frequencies of both the first qubit and the second qubit, eliminates coherent rotation in at least one of the first qubit or the second qubit based on a coupling that cancels the adjustable coupling, thereby facilitating at least one of: reduction of quantum gate errors associated with at least one of the first qubit or the second qubit, speeding up of quantum gates including the first qubit and the second qubit, improvement in the performance of a quantum processor (e.g., a quantum processor comprising device 100 which can include a quantum coupler device), or improvement in the fidelity of a quantum processor.

[0082] FIG. 7 shows a flowchart of an exemplary and non-limiting computer-implemented method 700 that can facilitate quantum gates between qubits using an adjustable coupler and a capacitor device, according to one or more embodiments described herein. For simplicity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0083] In 702, computer-implemented method 700 can include providing, by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof) operably coupled to a processor (e.g., processing unit 1014), a first adjustable coupling (e.g., first coupling 114) between terminals (e.g., between terminal 104a and terminal 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b), and a second adjustable coupling (e.g., third coupling 214) between terminals (e.g., between terminal 204a and terminal 204b) of the same polarity (e.g., positive (+) or negative (-)) of a second qubit and a third qubit (e.g., third qubit 206).

[0084] In 704, computer-implemented method 700 can include providing, by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), a first capacitive coupling (e.g., second coupling 116) between terminals (e.g., between terminal 104a and terminal 104c) of opposite polarities (e.g., positive (+) and negative (-)) of a first qubit and a second qubit, and a second capacitive coupling (e.g., fourth coupling 216) between terminals (e.g., between terminal 204a and terminal 204c) of opposite polarities (e.g., positive (+) and negative (-)) of a second qubit and a third qubit.

[0085] In 706, computer-implemented method 700 can include adjusting a first resonance frequency associated with a first adjustable coupling and a second resonance frequency associated with a second adjustable coupling by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), where the first capacitive coupling includes a first coupling that cancels the first adjustable coupling when the first resonance frequency is less than the third resonance frequency of both the first qubit and the second qubit (e.g., less than the resonance frequency of the first qubit 106a and less than the resonance frequency of the second qubit 106b), and the second capacitive coupling includes a second coupling that cancels the second adjustable coupling when the second resonance frequency is less than the fourth resonance frequency of both the second qubit and the third qubit (e.g., less than the resonance frequency of the second qubit 106b and less than the resonance frequency of the third qubit 206).

[0086] FIG. 8 shows a flow diagram of an exemplary and non-limiting computer-implemented method 800 that can facilitate quantum gates between qubits using an adjustable coupler and a capacitor device, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0087] At 802, the computer-implemented method 800 can include providing, by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof) operably coupled to a processor (e.g., processing unit 1014), a first adjustable coupling (e.g., first coupling 114) between terminals (e.g., between terminal 104a and terminal 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b), and a second adjustable coupling (e.g., third coupling 214) between terminals (e.g., between terminal 204a and terminal 204b) of the same polarity (e.g., positive (+) or negative (-)) of a second qubit and a third qubit (e.g., third qubit 206).

[0088] At 804, the computer-implemented method 800 can include providing, by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), a first capacitive coupling (e.g., second coupling 116) between terminals (e.g., between terminal 104a and terminal 104c) of opposite polarities (e.g., positive (+) and negative (-)) of a first qubit and a second qubit, and a second capacitive coupling (e.g., fourth coupling 216) between terminals (e.g., between terminal 204a and terminal 204c) of opposite polarities (e.g., positive (+) and negative (-)) of a second qubit and a third qubit.

[0089] At 806, the computer-implemented method 800 can include adjusting a first resonant frequency associated with a first adjustable coupling and a second resonant frequency associated with a second adjustable coupling by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), the first capacitive coupling including a first coupling that cancels the first adjustable coupling when the first resonant frequency is less than the third resonant frequency of both the first qubit and the second qubit (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b), and the second capacitive coupling including a second coupling that cancels the second adjustable coupling when the second resonant frequency is less than the fourth resonant frequency of both the second qubit and the third qubit (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206).

[0090] At 808, the computer-implemented method 800 can include performing at least one of separating the first qubit from the second qubit or separating the second qubit from the third qubit based on at least one of the first adjustable coupling or the second adjustable coupling by a system (e.g., a computer 1012 coupled to an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), at least one of the first qubit, the second qubit, or the third qubit including at least one of a fixed-frequency qubit, an adjustable qubit, a transmon qubit, a fixed-frequency transmon qubit, or an adjustable transmon qubit.

[0091] At 810, computer-implemented method 800 can include, by a system (e.g., a computer 1012 coupled to an AWG or VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof), eliminating coherent rotation in at least one of a first qubit, a second qubit, or a third qubit based on at least one of a first adjustable coupling or a second adjustable coupling, thereby facilitating at least one of: reduction of quantum gate errors associated with at least one of the first qubit, the second qubit, or the third qubit; speeding up of quantum gates including the first qubit and the second qubit or the second qubit and the third qubit; improvement in performance of a quantum processor (e.g., a quantum processor comprising device 200 that can include a quantum coupler device); or improvement in fidelity of a quantum processor.

[0092] FIG. 9 shows a flowchart of an exemplary and non-limiting computer-implemented method 900 that can facilitate quantum gates between qubits using an adjustable coupler and a capacitor device, according to one or more embodiments described herein. For simplicity, repeated descriptions of similar elements or processes or both used in each embodiment are omitted.

[0093] At 902, computer-implemented method 900 can include providing an adjustable coupling (e.g., first coupling 114) between terminals (e.g., between terminal 104a and terminal 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b) (e.g., via a system that can include a computer 1012 coupled to an AWG or VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof).

[0094] In 904, the computer-implemented method 900 can include providing capacitive coupling (e.g., the second coupling 116) between terminals (e.g., between terminal 104a and terminal 104c) of opposite polarities (e.g., positive (+) and negative (-)) of a first qubit and a second qubit (e.g., via a system including a computer 1012 coupled to, for example, an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof).

[0095] In 906, the computer-implemented method 900 can include adjusting a resonance frequency associated with an adjustable coupling (e.g., a resonance frequency associated with the first coupling 114 that can be generated or controlled or both by the adjustable coupler 102) (e.g., via a system including a computer 1012 coupled to, for example, an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof). For example, referring to the exemplary embodiments shown in FIGS. 1, 3, and 4, a magnetic flux that enables adjustment of the resonance frequency of the adjustable coupler 102 such that the resonance frequency of the adjustable coupler 102 is above, at, or below the resonance frequencies of both the first qubit 106a and the second qubit 106b (e.g., above, at, or below the resonance frequency of the first qubit 106a and above, at, or below the resonance frequency of the second qubit 106b) can be provided to the adjustable coupler 102 (e.g., via a system including a computer 1012 coupled to, for example, an AWG or a VNA or both, and further coupled to device 100, adjustable coupler 102, or capacitor device 110 or a combination thereof).

[0096] At 908, the computer-implemented method 900 can include determining whether the ZZ interaction between a first qubit and a second qubit is on (e.g., via a system including a computer 1012 coupled to, for example, an AWG or VNA or both, and further coupled to a device 100, an adjustable coupler 102, or a capacitor device 110 or a combination thereof). For example, referring to the above exemplary embodiments shown in FIGS. 1, 3, and 4, whether the resonant frequency associated with the adjustable coupler 102 is above or below the resonant frequencies of both the first qubit 106a and the second qubit 106b can correspond to the strength of the ZZ interaction between the first qubit 106a and the second qubit 106b (e.g., above - corresponding to when ZZ is on, below - corresponding to when ZZ is off). Thus, in these exemplary embodiments, the determination regarding whether the ZZ interaction is on can be performed using graph 300, graph 400, or time graph 402 or both. In these exemplary embodiments, when the resonant frequency of the adjustable coupler 102 is above the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., above the resonant frequency of the first qubit 106a and above the resonant frequency of the second qubit 106b), the capacitive coupling (e.g., the second coupling 116) does not cancel the adjustable coupling (e.g., the first coupling 114) (e.g., without zero setting, negating, offsetting, etc.), and by applying a flux pulse increased to the point where a quantum gate can be executed between the first qubit 106a and the second qubit 106b, the ZZ interaction between the first qubit 106a and the second qubit 106b can be increased (e.g., as illustrated by graph 400 in FIG. 4, for a 4.50 GHz flux pulse, the corresponding ZZ interaction strength is about 10 -0.5 MHz).

[0097] In 908, when it is determined that the ZZ interaction between the first qubit and the second qubit is on, in 910, the computer-implemented method 900 can include performing a quantum gate between the first qubit and the second qubit (e.g., via a system including a computer 1012 that can be coupled to, for example, an AWG or a VNA or both, and further coupled to the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof). For example, referring to the above exemplary embodiments shown in FIGS. 1, 3, and 4, when the resonant frequency of the adjustable coupler 102 is adjusted to a point that exceeds the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., exceeds the resonant frequency of the first qubit 106a and exceeds the resonant frequency of the second qubit 106b at a flux pulse of 4.50 GHz as illustrated by the graph 400 in FIG. 4), the corresponding strength of the ZZ interaction between the first qubit 106a and the second qubit 106b can enable the execution of a quantum gate between the first qubit 106a and the second qubit 106b.

[0098] At 912, the computer-implemented method 900 can include turning off the ZZ interaction between the first qubit and the second qubit by tuning the resonance frequency associated with an adjustable coupling (e.g., via a system including a computer 1012 that can be coupled to, for example, an AWG or a VNA or both, and further coupled to the device 100, the adjustable coupler 102, or the capacitor device 110 or a combination thereof). For example, in the exemplary embodiments shown in FIGS. 1, 3, and 4, when the resonance frequency of the adjustable coupler 102 is below the resonance frequencies of both the first qubit 106a and the second qubit 106b (e.g., below the resonance frequency of the first qubit 106a and below the resonance frequency of the second qubit 106b), the capacitive coupling (e.g., the second coupling 116) can cancel (e.g., zero, negate, offset, etc.) the adjustable coupling (e.g., the first coupling 114), and at that point, the ZZ interaction between the first qubit 106a and the second qubit 106b is negligible and thus substantially off (e.g., as illustrated by the graph 400 in FIG. 4, for a flux pulse of 3.75 GHz, the corresponding ZZ interaction strength is about 10 -5 MHz).

[0099] At 908, if it is determined that the ZZ interaction between the first qubit and the second qubit is not on, the computer-implemented method 900 can include returning to operation 906 and tuning the resonance frequency associated with the adjustable coupling. In various embodiments, operations 906 and 908 of the computer-implemented method 900 can be repeated until the ZZ interaction between the first qubit and the second qubit is on. In these embodiments, based on repeating operations 906 and 908 until the ZZ interaction between the first qubit and the second qubit is on, the computer-implemented method 900 can proceed to operations 910 and 912.

[0100] To provide context for various aspects of the disclosed subject matter, FIGS. 10 and the following description are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 10 shows a block diagram of an exemplary and non-limiting operating environment that can facilitate one or more embodiments described herein. For example, as described below, the operating environment 1000 can be used to implement the exemplary and non-limiting multi-step manufacturing sequences described above with reference to FIGS. 1 and 2 that can be performed to manufacture device 100 or device 200 or a combination thereof in accordance with one or more embodiments of the present disclosure described herein. In another example, as described below, the operating environment 1000 can be used to implement one or more of the exemplary and non-limiting computer-implemented methods 500, 600, 700, 800, or 900 or a combination thereof described above with reference to FIGS. 5-9. For the sake of brevity, repeated descriptions of similar elements or processes or both used in other embodiments described herein are omitted.

[0101] The exemplary and non-limiting multi-step manufacturing sequence described above with reference to FIGS. 1 and 2, which may be implemented to manufacture device 100 or device 200 or a combination thereof, may be implemented by a computing system (e.g., the operating environment 1000 illustrated in FIG. 10 and described below) or a computing device (e.g., the computer 1012 illustrated in FIG. 10 and described below) or both. In a non-limiting and exemplary embodiment, such a computing system (e.g., operating environment 1000) or such a computing device (e.g., computer 1012) or both may include one or more processors and one or more memory devices capable of storing executable instructions that, when executed by the one or more processors, can facilitate the execution of the exemplary and non-limiting multi-step manufacturing sequence described above with reference to FIGS. 1 and 2. By way of non-limiting example, the one or more processors may direct or control one or both of one or more systems or devices operable to perform the manufacture of semiconductor devices or superconducting devices or both, or both, to facilitate the execution of the exemplary and non-limiting multi-step manufacturing sequence described above with reference to FIGS. 1 and 2.

[0102] In another example, one or more of the exemplary and non-limiting computer-implemented methods 500, 600, 700, 800, or 900 described above with reference to FIGS. 5-9, or combinations thereof, can also be implemented (e.g., executed) by the operating environment 1000. By way of non-limiting example, one or more processors of such a computing device (e.g., computer 1012) can direct or control one or both of one or more systems or devices (e.g., AWG, VNA, etc.) or both operable to execute the operation or routine or both of such a computer-implemented method, or facilitate the execution of one or more of the exemplary and non-limiting computer-implemented methods 500, 600, 700, 800, or 900 described above with reference to FIGS. 5-9, or combinations thereof.

[0103] For simplicity of explanation, the computer-implemented methodologies are depicted and described as a series of acts. The innovative subject matter is not limited by the acts shown or the order of acts, e.g., the acts can occur in various orders or simultaneously or both, and can occur with other acts not presented or described herein. It should be understood and recognized that not all acts are required to implement the computer-implemented methodologies in accordance with the disclosed subject matter. Further, one of ordinary skill in the art will understand and recognize that, alternatively, the computer-implemented methodologies can be represented as a series of interrelated states via a state diagram or events. Further, it should be further understood that the computer-implemented methodologies disclosed herein and throughout can be stored on a manufacture article to facilitate the transfer and conveyance of such computer-implemented methodologies to a computer. As used herein, the term manufacture article is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0104] Referring to FIG. 10, a suitable operating environment 1000 for implementing various aspects of the present disclosure can also include a computer 1012. The computer 1012 can also include a processing unit 1014, a system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to the system memory 1016, to the processing unit 1014. The processing unit 1014 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures can also be employed as the processing unit 1014. The system bus 1018 can use any of a variety of available bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, or a local bus or a combination thereof, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0105] System memory 1016 can also include volatile memory 1020 and non-volatile memory 1022. A basic input / output system (BIOS) that contains basic routines for transferring information between elements within computer 1012 during startup and the like is stored in non-volatile memory 1022. Computer 1012 can also include removable / non-removable volatile / non-volatile computer storage media. FIG. 10 shows, for example, disk storage 1024. Disk storage 1024 can include devices such as, but not limited to, magnetic disk drives, floppy (R) disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 1024 can include the storage media separately or in combination with other storage media. To facilitate connection of disk storage 1024 to system bus 1018, typically a removable or non-removable interface such as interface 1026 is used. FIG. 10 also shows software that acts as an intermediary between the user and the basic computer resources described in the preferred operating environment 1000. Such software can include, for example, operating system 1028. Operating system 1028, which can be stored on disk storage 1024, acts to control and allocate the resources of computer 1012.

[0106] System application 1030 utilizes the management of resources by operating system 1028 via program modules 1032 and program data 1034 stored either in system memory 1016 or on disk storage 1024, for example. It should be understood that the present disclosure may be implemented using various operating systems or combinations of operating systems. A user inputs commands or information to computer 1012 via input device 1036. Input device 1036 includes, but is not limited to, pointing devices such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite receiving antenna, scanner, TV tuner card, digital camera, digital video camera, web camera, etc. These and other input devices are connected to processing unit 1014 via system bus 1018 through interface port 1038. Interface port 1038 includes, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output device 1040 uses some of the same type of ports as input device 1036. Thus, for example, a USB port can be used to provide input to computer 1012 and output information from computer 1012 to output device 1040. Output adapter 1042 is provided to indicate that among output devices 1040, there are some output devices 1040 such as monitors, speakers, and printers that require special adapters. Output adapter 1042 includes, by way of example and not limitation, video cards and sound cards that provide connection means between output device 1040 and system bus 1018. Note that other devices or systems of devices or both, such as remote computer 1044, provide both input and output functions.

[0107] Computer 1012 can operate in a networked environment using logical connections to one or more remote computers such as remote computer 1044. Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer device, or other common network node, and typically can include many or all of the elements described with respect to computer 1012. For simplicity, only memory storage device 1046 is shown along with remote computer 1044. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and physically connected via communication connection 1050. Network interface 1048 encompasses wired or wireless or both communication networks such as local area network (LAN), wide area network (WAN), and cellular network. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet(R), Token Ring, and the like. WAN technologies include circuit-switched networks such as point-to-point links, Integrated Services Digital Network (ISDN) and its variants, packet-switched networks, and Digital Subscriber Line (DSL), but are not limited thereto. Communication connection 1050 refers to the hardware / software used to connect network interface 1048 to system bus 1018. For clarity of explanation, communication connection 1050 is shown inside computer 1012, but can also be external to computer 1012. The hardware / software for connecting to network interface 1048 can include internal and external technologies such as modems including regular telephone grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet(R) cards for illustrative purposes only.

[0108] The present invention may be a system, method, apparatus, or computer program product, or a combination thereof, at any possible level of integration of technical details. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to implement aspects of the present invention. The computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing, but is not limited thereto. A non-exhaustive list of more specific examples of computer-readable storage media includes the following, namely, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy (R) disk, punch cards, or mechanically encoded devices such as raised structures within grooves in which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0109] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, a wireless network, or a combination thereof. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for carrying out operations of the present invention can be source code or object code written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages such as Smalltalk(R), C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer as a stand-alone software package, partly on the user's computer, partly on the user's computer and partly on a remote computer, or entirely on the computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).In some embodiments, to execute aspects of the present invention, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by personalizing the electronic circuit using state information of the computer-readable program instructions.

[0110] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, or other device to function in a particular manner, such that the storage medium containing instructions comprises an article of manufacture including instructions for implementing the function / act specified in one or more blocks of the flowchart and / or block diagram. The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0111] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of a module that includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions described in the blocks can be performed in an order different from that shown in the figures. For example, two blocks shown in succession can, in fact, be executed substantially simultaneously, depending on the functions involved, or, in some cases, the blocks can be executed in the reverse order. It should also be noted that each block of the block diagram or flowchart diagram, or both, and combinations of blocks in the block diagram or flowchart diagram, or both, can be implemented by a dedicated hardware-based system that performs the specified function or operation or a combination of dedicated hardware and computer instructions.

[0112] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on one or more computers, those skilled in the art will understand that the present disclosure may also be implemented in combination with other program modules. In general, program modules include routines, programs, components, data structures, etc. that perform specific tasks, implement specific abstract data types, or both. Also, those skilled in the art will understand that the computer-implemented methods of the present invention may be implemented in other computer system configurations including single-processor or multi-processor computer systems, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic devices, etc. The illustrated embodiments may be implemented in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. However, some embodiments, if not all embodiments of the present disclosure, may be implemented on a stand-alone computer. In a distributed computing environment, program modules may be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from a memory that may include or be composed of one or more distributed memory units. The terms "memory" and "memory unit" as used herein are interchangeable. Further, one or more embodiments described herein can execute the code of computer-executable components in a distributed manner, e.g., multiple processors can execute the code from one or more distributed memory units in combination or in cooperation. The term "memory" as used herein can include a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

[0113] As used in this application, the terms "component", "system", "platform", "interface", etc. can refer to, include, or both, computer-related entities having one or more specific functionalities, or entities related to computing machines. Entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer or a combination thereof. As an example, both an application running on a server and the server can be components. One or more components can be present within a process or an execution thread or both, and a component can be located on one computer or distributed between two or more computers or both. In another example, each component can be executed from various computer-readable media storing various data structures. A component can communicate through local or remote processes or both, according to signals such as one or more data packets (e.g., data from one component that interacts via signals with another component within a local system or a distributed system or with other systems via a network such as the Internet). As another example, a component can be a device having a specific functionality provided by an electrical or electronic circuit operating by a software or firmware application executed by a processor or by a mechanical part operating by such an electrical or electronic circuit. In such a case, the processor can be inside or outside the device and can execute at least a part of the software or firmware application.As yet another example, the component can be a device that provides a particular function via electronic components without mechanical parts, and the electronic components can include a processor or other means that execute software or firmware that at least partially provides the function of the electronic components. In one aspect, the component can emulate the electronic components, for example, via a virtual machine within a cloud computing system.

[0114] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or otherwise apparent from the context, "X employs A or B" is intended to mean any of the natural inclusive substitutions. That is, "X employs A or B" is satisfied in any of the above instances where X employs A, X employs B, or X employs both A and B. Further, the articles "a" and "an" as used in this specification and the appended drawings are generally to be construed to mean "one or more" unless otherwise specified or otherwise apparent from the context that the singular is intended. The terms "example" or "exemplary" or both as used in this specification are utilized as serving as an example, instance, or illustration. To avoid misunderstanding, the subject matter disclosed in this specification is not limited to such examples. Further, any aspect or design described in this specification as an "example" or "exemplary" or both should not be construed as necessarily preferred or advantageous as compared to other aspects or designs, nor does it mean excluding equivalent exemplary structures and techniques known to those skilled in the art.

[0115] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor, a single processor with software multithreading execution capabilities, a multi-core processor, a multi-core processor with software multithreading execution capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Further, a processor can refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Also, a processor can utilize nanoscale architectures such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates to optimize the spatial use or enhance the performance of user equipment. A processor can also be implemented as a combination of computing processing units. In the present disclosure, the terms "store", "storage", "data store", "data storage", "database", and substantially any other information storage component related to the operation and function of a component are used to refer to an entity embodied in a "memory component", "memory", or a component including a memory. It should be understood that the memory or memory component or both described herein can be either volatile memory or non-volatile memory, or can include both volatile memory and non-volatile memory.By way of example and not limitation, non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include, for example, RAM that can act as an external cache memory. By way of example and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), extended SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct rambus RAM (DRRAM), direct rambus dynamic RAM (DRDRAM), and rambus dynamic RAM (RDRAM). Further, the disclosed memory components of the systems or computer-implemented methods herein are not limited to including these, but are intended to include these and any other suitable types of memory.

[0116] What has been described above is only by way of example of systems and computer-implemented methods. Of course, it is not possible to describe all possible combinations of components or computer-implemented methods or both in order to explain the present disclosure, but those skilled in the art can understand that many further combinations and permutations of the present disclosure are possible. Further, to the extent that terms such as "comprising," "having," "owning," etc. are used in the detailed description, claims, accompanying documents, and drawings, such terms are intended to be inclusive in the same manner as when the term "including" is construed when used as a transitional term in the claims.

[0117] The description of various embodiments has been presented for illustrative purposes, but this description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, actual applications, or technological improvements over technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum coupler device, comprising: An adjustable coupler coupled between terminals of the same polarity of a first qubit and a second qubit and configured to control a first coupling between the first qubit and the second qubit; A capacitor device coupled to terminals of opposite polarities of the first qubit and the second qubit and configured to provide a second coupling having an opposite sign to the first coupling based on a resonance frequency of the adjustable coupler being smaller than resonance frequencies of both the first qubit and the second qubit, the quantum coupler device comprising the adjustable coupler and the capacitor device.

2. The quantum coupler device according to claim 1, wherein the adjustable coupler is configured to control the first coupling, and the capacitor device is configured to provide the second coupling to eliminate coherent rotation between the first qubit and the second qubit, thereby facilitating at least one of reduction of quantum gate errors associated with at least one of the first qubit or the second qubit, speeding up of a quantum gate including the first qubit and the second qubit, improvement of performance of a quantum processor comprising the quantum coupler device, or improvement of fidelity of the quantum processor comprising the quantum coupler device.

3. The quantum coupler device according to claim 1 or 2, wherein the adjustable coupler includes at least one of a flux-adjustable coupler, an adjustable coupler qubit, a flux-adjustable coupler qubit, an adjustable qubit, an adjustable bus, or a flux-adjustable qubit bus.

4. The quantum coupler device according to any one of claims 1 to 3, wherein at least one of the first qubit or the second qubit includes at least one of a fixed-frequency qubit, an adjustable qubit, a transmon qubit, a fixed-frequency transmon qubit, or an adjustable transmon qubit.

5. The quantum coupler device according to any one of claims 1 to 4, wherein the capacitor device includes at least one of a differential capacitor or a bypass capacitor. Claim 6. A system operably coupled to a processor, providing an adjustable coupling between terminals of the same polarity of a first qubit and a second qubit, the system providing a capacitive coupling between terminals of opposite polarities of the first qubit and the second qubit, the system including adjusting a resonance frequency associated with the adjustable coupling, wherein when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit, the capacitive coupling generates a coupling that cancels the adjustable coupling, a method. Claim 7 The method of claim 6, further including, when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit, separating the first qubit from the second qubit based on the coupling that cancels the adjustable coupling. Claim 8 The method of claim 6 or 7, further including, when the resonance frequency associated with the adjustable coupling is less than the resonance frequencies of both the first qubit and the second qubit, eliminating coherent rotation in at least one of the first qubit or the second qubit based on the coupling that cancels the adjustable coupling, thereby facilitating at least one of reducing quantum gate errors associated with at least one of the first qubit or the second qubit, speeding up quantum gates including the first qubit and the second qubit, improving the performance of a quantum processor, or improving the fidelity of the quantum processor. Claim 9 The method according to any one of claims 6 to 8, wherein at least one of the first qubit or the second qubit includes at least one of a fixed-frequency qubit, an adjustable qubit, a transmon qubit, a fixed-frequency transmon qubit, or an adjustable transmon qubit. Claim 10 A quantum coupler device, an adjustable coupler coupled between a first qubit and a second qubit, A quantum coupler device comprising a capacitor device coupled between the first qubit and the second qubit, wherein the capacitor device generates a coupling opposite in sign to the coupling from the adjustable coupler based on the resonance frequency of the adjustable coupler being less than the resonance frequencies of both the first qubit and the second qubit.

11. The quantum coupler device according to claim 10, wherein the capacitor device comprises a first terminal and a second terminal, the first terminal and the second terminal are cross-coupled between the first qubit and the second qubit, and the adjustable coupler is directly coupled between the first qubit and the second qubit.

12. The quantum coupler device according to claim 10 or 11, wherein the adjustable coupler is coupled between terminals of the same polarity of the first qubit and the second qubit, and the adjustable coupler is configured to control the coupling between the first qubit and the second qubit.

13. The adjustable coupler is coupled between terminals of the same polarity of the first qubit and the second qubit, the adjustable coupler is configured to control a first coupling between the first qubit and the second qubit, the capacitor device is coupled to terminals of opposite polarity of the first qubit and the second qubit, The quantum coupler device according to any one of claims 10 to 12, wherein the capacitor device is configured to provide a second coupling opposite in sign to the first coupling.

14. The adjustable coupler is configured to control the first coupling, and the capacitor device provides the second coupling to eliminate coherent rotation between the first qubit and the second qubit, thereby reducing quantum gate errors associated with at least one of the first qubit or the second qubit, accelerating quantum gates including the first qubit and the second qubit, improving the performance of a quantum processor comprising the quantum coupler device, or improving the fidelity of the quantum processor comprising the quantum coupler device, the quantum coupler device according to claim 13, configured to facilitate at least one of.

15. The adjustable coupler includes at least one of a flux adjustable coupler, an adjustable coupler qubit, a flux adjustable coupler qubit, an adjustable qubit, an adjustable bus, or a flux adjustable qubit bus, the quantum coupler device according to any one of claims 10 to 14.

16. At least one of the first qubit or the second qubit includes at least one of a fixed frequency qubit, an adjustable qubit, a transmon qubit, a fixed frequency transmon qubit, or an adjustable transmon qubit, the quantum coupler device according to any one of claims 10 to 15.

17. The capacitor device includes at least one of a differential capacitor or a bypass capacitor, the quantum coupler device according to any one of claims 10 to 16.

18. A device, A first adjustable coupler coupled between terminals of the same polarity of the first qubit and the second qubit and configured to control a first coupling between the first qubit and the second qubit; A first capacitor device coupled to terminals of opposite polarities of the first qubit and the second qubit and configured to provide a second coupling having an opposite sign to the first coupling based on the resonant frequency of the first adjustable coupler being less than the resonant frequencies of both the first qubit and the second qubit; A second adjustable coupler coupled between terminals of the same polarity of the second qubit and the third qubit and configured to control a third coupling between the second qubit and the third qubit; A second capacitor device coupled to terminals of opposite polarity of the second qubit and the third qubit and configured to provide a fourth coupling having an opposite sign to the third coupling; A device comprising the same. **Claim 19**: The device according to claim 18, wherein the second capacitor device provides the fourth coupling based on the resonance frequency of the second adjustable coupler being smaller than the resonance frequencies of both the second qubit and the third qubit. **Claim 20** The first adjustable coupler or the second adjustable coupler is configured to control the first coupling or the third coupling respectively, and the first capacitor device or the second capacitor device provides the second coupling or the fourth coupling respectively to eliminate coherent rotation between the first qubit and the second qubit or between the second qubit and the third qubit, thereby reducing quantum gate errors associated with at least one of the first qubit, the second qubit, or the third qubit, accelerating quantum gates including the first qubit and the second qubit or the second qubit and the third qubit, improving the performance of a quantum processor comprising the device, or improving the fidelity of the quantum processor comprising the device. The device according to claim 18 or 19, configured to facilitate at least one of the above. **Claim 21** At least one of the first adjustable coupler or the second adjustable coupler includes at least one of a flux adjustable coupler, an adjustable coupler qubit, a flux adjustable coupler qubit, an adjustable qubit, an adjustable bus, or a flux adjustable qubit bus. At least one of the first qubit, the second qubit, or the third qubit includes at least one of a fixed-frequency qubit, an adjustable qubit, a transmon qubit, a fixed-frequency transmon qubit, or an adjustable transmon qubit. The device according to any one of claims 18 to 20, wherein at least one of the first capacitor device or the second capacitor device includes at least one of a differential capacitor or a bypass capacitor. **Claim 22**: A system operably coupled to a processor provides a first adjustable coupling between terminals of the same polarity of a first qubit and a second qubit and a second adjustable coupling between terminals of the same polarity of the second qubit and a third qubit. The system provides a first capacitive coupling between terminals of opposite polarities of the first qubit and the second qubit and a second capacitive coupling between terminals of opposite polarities of the second qubit and the third qubit. The system includes adjusting a first resonance frequency associated with the first adjustable coupling and a second resonance frequency associated with the second adjustable coupling. The first capacitive coupling includes a first coupling that cancels the first adjustable coupling when the first resonance frequency is less than a third resonance frequency of both the first qubit and the second qubit. The second capacitive coupling includes a second coupling that cancels the second adjustable coupling when the second resonance frequency is less than a fourth resonance frequency of both the second qubit and the third qubit. **Claim 23** The system further includes performing at least one of separating the first qubit from the second qubit or separating the second qubit from the third qubit, respectively based on at least one of the first adjustable coupling or the second adjustable coupling, wherein at least one of the first qubit, the second qubit, or the third qubit includes at least one of a fixed-frequency qubit, an adjustable qubit, a transmon qubit, a fixed-frequency transmon qubit, or an adjustable transmon qubit. The method according to claim 22.

24. The system further includes eliminating coherent rotation in at least one of the first qubit, the second qubit, or the third qubit based on at least one of the first adjustable coupling or the second adjustable coupling, thereby facilitating at least one of reducing quantum gate errors associated with the first qubit, the second qubit, or the third qubit, accelerating quantum gates including the first qubit and the second qubit or the second qubit and the third qubit, improving the performance of the quantum processor, or improving the fidelity of the quantum processor. The method according to claim 22 or 23.

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